Bias control integrated circuit and radio frequency power amplifier module

Abstract

The invention relates to a bias control integrated circuit and a radio frequency power amplifier module. More specifically, the present invention relates to a bias control integrated circuit capable of simultaneously providing bias signals of different polarities and capable of being used in a time domain duplex (TDD) system. The bias control integrated circuit includes a plurality of identical bias circuits, each bias circuit including an input node for receiving a digital value and a DAC for converting the received digital value into an analog bias signal between a respective high voltage and a respective low voltage. The output of the DAC forms a first output node of the bias circuit. The bias circuit further includes a second output node and a switching unit connected to the first output node and the second output node, and the switching unit is configured to output the analog bias signal output by the DAC or a corresponding low voltage as a switched analog bias signal according to a switching signal at the second output node.

Description

Technical Field

[0001] The present invention relates to a bias control integrated circuit and a radio frequency (RF) power amplifier module. More specifically, the present invention relates to a bias control integrated circuit capable of simultaneously providing bias signals of different polarities and capable of being used in a time domain duplexing (TDD) system. The present invention also relates to a bias circuit used in the bias control integrated circuit and a radio frequency (RF) power amplifier module including the bias control integrated circuit. Background Art

[0002] Typically, the bias control integrated circuit includes a plurality of identical bias circuits integrated on a semiconductor die. Each bias circuit generates a separate bias signal to provide to an amplifier stage. For example, each bias circuit can be configured to generate a corresponding gate bias signal for a multi-stage amplifier including a plurality of field effect transistors.

[0003] The bias control integrated circuit may be part of a power amplifier module. Such a module includes a substrate on which the bias control integrated circuit is mounted together with one or more semiconductor dies on which the power transistors of the power amplifier are integrated.

[0004] Power amplifier modules are often designed to be used in various telecommunication scenarios. For example, a power amplifier module may be designed to operate in a time division duplex system, where the power amplifier module needs to be able to quickly switch between an on state and an off state. Additionally, these same power amplifier modules may be designed to also operate in frequency division multiplexing, where the power amplifier module may be in an on state for relatively long periods of time.

[0005] Recently, power amplifier modules using power transistors based on different semiconductor technologies have been developed. For example, power amplifier modules using both gallium nitride-based field effect transistors and silicon-based laterally diffused metal oxide semiconductor (LDMOS) transistors have been disclosed. In the following, such power amplifier modules are referred to as hybrid power amplifier modules.

[0006] Figure 1An example of a hybrid power amplifier module is schematically shown in FIG. Here, the power amplifier module 100 includes a substrate 10, on which a bias control integrated circuit (IC) 20, a first power amplifier 30 based on a first semiconductor technology, and a second power amplifier 40 based on a second semiconductor technology different from the first semiconductor technology are arranged. The power amplifiers 30, 40 are arranged as separate semiconductor dies mounted on the substrate 10. In the case where the semiconductor technology of the power amplifier (e.g., the power amplifier 30) is the same as the semiconductor technology of the bias control IC 20, the power amplifier and the bias control IC can be implemented as a single semiconductor die.

[0007] The power amplifier module 100 receives a radio frequency RF input signal RF_in and a signal D representing bias settings to be used for the power amplifiers 30, 40. The bias IC 20 comprises an arithmetic unit 21 which determines the input signal to be provided to the bias circuits 22, 23 as a function of the measured temperature T. Thus, variations in the performance of the power amplifiers 30, 40 with temperature, in particular the ambient temperature, can be compensated.

[0008] The bias circuits 22, 23 each provide a bias signal to the corresponding power amplifier 30, 40 according to the measured temperature T and the signal D. The last stage of the power amplifier module 100, i.e., the power amplifier 40, provides its output signal RF_output (RF_out) to the load ZL outside the power amplifier module 100. In addition, the power amplifiers 30, 40 are each provided with a separate power supply voltage Vdd1, Vdd2. For example, the power amplifiers 30, 40 can be implemented using field effect transistors. In this case, the power supply voltages Vdd1 and Vdd2 are used to bias the drain terminals of the field effect transistors, while the bias circuits 22, 23 bias the gate terminals. The power supply voltage is usually provided using a source outside the power amplifier module 100.

[0009] Hybrid power amplifier modules may require the bias control IC to output bias signals of different polarities. For example, GaN FETs require a gate voltage in the range of -10V to 0V, while SiLDMOS transistors require a gate voltage in the range of 0V to 5V. Currently known bias control ICs cannot meet this requirement and the requirement that the same bias control IC can be used for TDD applications.

[0010] Therefore, an object of the present invention is to provide a bias control integrated circuit that can simultaneously output bias signals of different polarities and can be used in a TDD system. Summary of the invention

[0011] According to the present invention, the object is achieved using a bias control integrated circuit for providing multiple bias signals as defined in claim 1. The bias control integrated circuit includes a semiconductor die on which a plurality of preferably identical bias circuits are integrated. Each bias circuit is capable of operating independently in one of a plurality of modes. The mode in which each bias circuit operates can be configured and / or set individually. In some embodiments, the mode in which each bias circuit operates can be switched. For example, the bias control integrated circuit may include a digital control register. In other embodiments, the mode in which each bias circuit operates is determined by the connection method of the bias circuit (e.g., using bonding wires).

[0012] According to the present invention, each bias circuit includes a reference high node, the voltage of which during operation is configured to be equal to a corresponding high voltage among a plurality of high voltages corresponding to a plurality of modes. Each bias circuit also includes a reference low node, the voltage of which during operation is configured to be equal to a corresponding low voltage among a plurality of low voltages corresponding to a plurality of modes.

[0013] For example, the bias control integrated circuit includes six bias circuits. The voltage at the reference high node and the voltage at the reference low node of a given bias circuit can be configured according to the following table.

[0014]

[0015] Each bias circuit also includes an input node for receiving a digital value. The digital value represents a bias signal to be provided by the bias circuit. A digital-to-analog converter (DAC) is provided in each bias circuit for converting the received digital value into an analog bias signal between a voltage at a reference high node and a voltage at a reference low node. The output of the DAC forms a first output node of the bias circuit.

[0016] Each bias circuit also includes a second output node and a switching unit, which is connected to the first output node and the second output node and is configured to output the analog bias signal output by the DAC or the corresponding low voltage as a switching analog bias signal at the second output node according to the switching signal.

[0017] The first output node can be used for applications where the switching time required to turn on and / or turn off the transistor of the power amplifier is not important and / or the transistor of the power amplifier does not need to be turned off during operation. The second output node can be used for applications where such switching time is important, such as for TDD applications. Additionally or alternatively, the switching unit can be configured to operate in a first mode and / or a second mode. In the first mode, the switching unit outputs an analog bias signal output by the DAC or a corresponding low voltage as a switching analog bias signal at the second output node according to the switching signal. In the second mode, the switching unit outputs the analog bias signal output by the DAC at the second output node.

[0018] The polarity of at least one high voltage may be different from the polarity of at least one other high voltage and / or the polarity of at least one low voltage may be different from the polarity of at least one other low voltage.

[0019] The switching unit of each bias circuit may include a first switching unit arranged between a first output node and a second output node of the bias circuit, a second switching unit arranged between the second output node and a reference node electrically connected to a reference low node, and a switching controller configured to control the first switching unit and the second switching unit according to a switching signal.

[0020] For example, the switching controller may be configured to control the first switching unit to provide a low-ohmic connection between the first output node and the second output node, and to control the second switching unit to provide a high-ohmic connection between the second output node and the reference node, in response to the switching signal having a first logic value. In addition, the switching controller may be configured to control the first switching unit to provide a high-ohmic connection between the first output node and the second output node, and to control the second switching unit to provide a low-ohmic connection between the second output node and the reference node, in response to the switching signal having a second logic value different from the first logic value. For example, the first logic value may represent a logical high value, and the second logic value may represent a logical low value. When the switching signal has the first logic value, the voltage at the second output node may be the same as the voltage at the first output node, and when the switching signal has the second logic value, the voltage at the second output node may be the same as the voltage at the reference node of the switching unit, which is generally equal to or substantially equal to the corresponding low voltage.

[0021] The present invention is not limited to any number of modes. However, the plurality of modes may include a first mode and a second mode. In the first mode, the voltage at the reference high node during operation is configured to be equal to a first high voltage, and the voltage at the reference low node during operation is configured to be equal to a first low voltage. In the second mode, the voltage at the reference high node during operation is configured to be equal to a second high voltage, and the voltage at the reference low node during operation is configured to be equal to a second low voltage. Using two different modes allows the bias control integrated circuit to be used to bias a hybrid power amplifier that uses two different semiconductor technologies to implement the power amplifier.

[0022] The reference high node and the reference low node of each bias circuit in the plurality of bias circuits can be formed by terminals. In order to operate a given bias circuit in a corresponding mode, the reference high node and the reference low node of the bias circuit can be configured to be connected to a high voltage power supply and a low voltage power supply, respectively, corresponding to the mode in which the bias circuit works or should work. The high voltage power supply and / or the low voltage power supply can be arranged outside the semiconductor die.

[0023] The terminal can be formed using a conductive patch or pad and / or the terminal can refer to a specific node in an electrical network. The patch or pad can be configured to be electrically connected to a substrate on which a bias control integrated circuit is mounted. For example, for a dual-mode bias control integrated circuit, the reference high node of the first bias circuit may include a pad and / or be formed by a pad, which is connected to a terminal on the substrate on which the bias control integrated circuit is mounted using a bonding wire, wherein the terminal provides a 5V voltage. The reference high node of the second bias circuit may include a pad and / or be formed by a pad, which is connected to a terminal on the substrate that provides a 10V voltage using a bonding wire.

[0024] Alternatively, the bias control integrated circuit may include a reference voltage setting unit configured to, according to a mode signal for a given bias circuit and intended to set the bias circuit to operate in a given mode among a plurality of modes, perform the following operations: setting a voltage at a reference high node of the bias circuit to a high voltage corresponding to the given mode among a plurality of high voltages, and setting a voltage at a reference low node of the bias circuit to a low voltage corresponding to the given mode among a plurality of low voltages.

[0025] The reference voltage setting unit can be connected to a power supply for all reference high voltages and reference low voltages. For example, the semiconductor die may include multiple common high nodes and multiple common low nodes, the voltages of the multiple common high nodes during operation are equal to multiple high voltages, and the voltages of the multiple common low nodes during operation are equal to multiple low voltages. The reference voltage setting unit can be connected to multiple common high nodes and multiple common low nodes. Multiple common high nodes can be configured to be electrically connected to a power supply of a high voltage, and / or multiple common low nodes can be configured to be electrically connected to a power supply of a low voltage. The power supply of the high voltage and / or the power supply of the low voltage can be arranged outside the semiconductor die.

[0026] The reference voltage setting unit may be configured to set each of the plurality of bias circuits to operate in a given mode of the plurality of modes according to a single mode signal indicating a desired mode of each bias circuit. For example, the mode signal provided to the reference voltage setting unit may be a digital signal. The mode signal may include bias information for one or all bias circuits.

[0027] Preferably, a single reference voltage setting unit is used to set the high voltage and the low voltage for each bias circuit. Alternatively, multiple reference voltage setting units can be used, for example each bias circuit includes one reference voltage setting unit. In the latter case, each bias circuit is connected to a common high node and a common low node. In addition, the use of a common high node and a common low node enables the use of a single connection to the low voltage source and the high voltage source without requiring each reference voltage setting unit to be individually connected.

[0028] The semiconductor die may include a controller configured to determine and provide a corresponding digital value for each bias circuit. Information about the desired bias level of a power amplifier or power transistor connected to the bias control integrated circuit may be stored in a memory inside the bias control integrated circuit, such as in a memory of the controller. The information may be, for example, various digital values ​​provided to each bias circuit. Alternatively, the controller may be configured to receive one or more input signals and determine the corresponding digital value based on the one or more input signals. In this case, the information based on which the digital value is generated comes from outside the bias control integrated circuit. In the latter case, it is preferred that the controller is configured to receive separate input signals for each bias circuit. However, these separate signals may be part of a common input signal.

[0029] The controller can be configured to generate corresponding digital values for each bias circuit based on the temperature measured by a temperature sensor and one or more input signals. The temperature sensor can be disposed on a semiconductor die. Alternatively, information about the temperature can be provided from one or more power amplifiers biased by a bias control integrated circuit. In a particular embodiment, each power amplifier or one or more power transistors of such a power amplifier each provide a corresponding temperature to the bias control integrated circuit. In such a case, the bias signal provided to the power amplifier or one or more of its power transistors can be determined individually by the controller based on one or more temperatures from the power amplifier or one or more of its power transistors.

[0030] The memory can include a look-up table that stores corresponding digital values for a plurality of temperatures and an arithmetic unit. The arithmetic unit is configured to calculate or determine the digital values to be output to each bias circuit based on the measured temperature and one or more digital values corresponding to the measured temperature of the values stored in the look-up table for one or more input signals.

[0031] An example of the look-up table is shown below. In this example, only entries for one bias circuit are provided.

[0032] The actual look-up table can include information for each bias circuit.

[0033] Input signal The measured temperature The digital value to be output Bias Circuit #1 Value #1 T1 Output value #1 Bias Circuit #1 Value #1 T2 Output value #2 Bias Circuit #1 Value #1 T3 Output #3 Bias Circuit #1 Value #2 T1 Output #4 Bias Circuit #1 Value #2 T2 Output value #5 Bias Circuit #1 Value #2 T3 Output value #6

[0034] If value #1 is provided to the controller and the arithmetic unit determines that the temperature is equal to T2, it will determine that output value #2 should be output to bias circuit #1. It is possible that the measured temperature does not exactly correspond to the stored temperature. To address this issue, the arithmetic unit can be configured to use interpolation to determine the digital values to be output to each bias circuit based on two or more digital values stored in the look-up table corresponding to temperatures above and below the measured temperature. Referring to the example above, if value #1 is provided to the controller and the measured temperature is equal to T4, where T1 < T4 < T2, the value to be output to bias circuit #1 is calculated or determined to be between output value #1 and output value #2. Preferably, the look-up table can store corresponding digital values for a plurality of temperatures for each bias circuit separately.

[0035] The controller can also be configured to output digital values to each bias circuit independent of the input signals. For example, the controller can be configured to ensure a fixed bias for the power amplifier or its power transistors. However, the actual values output to the bias circuits can be changed to account for temperature variations.

[0036] According to another aspect, the present invention provides a power amplifier module, including a plurality of power amplifiers, each power amplifier having one or more power transistors, the technology of the one or more power transistors being different from the technology of the power transistors of at least one other power amplifier in the plurality of power amplifiers. The power amplifier module also includes a bias control integrated circuit as described above, wherein each bias circuit is configured to provide an analog bias signal of the bias circuit or a switched analog bias signal of the bias circuit to a control input terminal of a corresponding power transistor of a power amplifier in the plurality of power amplifiers.

[0037] One or more bias circuits in the bias control integrated circuit configured to bias one or more power transistors of a given power amplifier of the plurality of power amplifiers are configured to operate in a different mode than one or more bias circuits in the bias control integrated circuit configured to bias one or more power transistors of a different power amplifier of the plurality of power amplifiers.

[0038] One or more power transistors of a power amplifier in the plurality of power amplifiers may be based on the same semiconductor material that is different from the semiconductor material on which one or more power transistors of a different power amplifier in the plurality of power amplifiers are based. These types of power amplifier modules are referred to as hybrid power amplifier modules. For example, one or more power transistors of a first power amplifier in the plurality of power amplifiers may be based on gallium nitride, such as each power transistor comprising a gallium nitride-based field effect transistor, and one or more power transistors of a second power amplifier in the plurality of power amplifiers may be based on silicon, such as each power transistor comprising a silicon laterally diffused metal oxide semiconductor transistor.

[0039] The power amplifier module may also include a first substrate, such as a laminated substrate, wherein one or more power transistors of each power amplifier are arranged to be mounted on one or more semiconductor dies on the first substrate. The first substrate may include one or more terminals for electrically connecting the power amplifier module to a second substrate on which the power amplifier module is mounted or to be mounted. As an example, the power amplifier module may be packaged as a land grid array (LGA) package or a leadless package such as a quad flat no-lead (QFN). The bias control integrated circuit and one or more semiconductor dies on which the power transistors of the power amplifier are implemented may be mounted to the first substrate using known die placement techniques (such as die bonding or flip chip bonding).

[0040] As long as a high voltage power supply and a low voltage power supply are arranged outside the semiconductor die of the bias control integrated circuit, one or more voltage generating units arranged on the first substrate can be used to implement an off-die power supply for high voltage and an off-die power supply for low voltage. Alternatively, the high voltage power supply and the low voltage power supply are arranged outside the power amplifier module. In the latter case, the power amplifier module may include a plurality of terminals configured to be connected to a high voltage power supply and a low voltage power supply outside the power amplifier module, wherein a reference high node and a reference low node of each bias circuit are electrically connected to corresponding terminals among the plurality of terminals of the power amplifier module.

[0041] According to another aspect, the present invention provides a bias circuit configured as a bias circuit of the above-mentioned bias control integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Next, the present invention will be described with reference to the accompanying drawings, in which the same reference numerals will be used to refer to the same or similar components, wherein:

[0043] Figure 1 A known power amplifier module is shown;

[0044] Figure 2 schematically shows a bias circuit according to the present invention;

[0045] Figure 3 Shows Figure 2 An implementation method of a bias circuit;

[0046] Figure 4 An embodiment of a bias control integrated circuit according to the present invention is shown;

[0047] Figure 5 A first embodiment of a power amplifier module according to the present invention is shown;

[0048] Figure 6 A second embodiment of a power amplifier module according to the present invention is shown;

[0049] Figure 7 A third embodiment of a power amplifier module according to the present invention is shown; and

[0050] Figure 8 A fourth embodiment of a power amplifier module according to the invention is shown. DETAILED DESCRIPTION

[0051] Figure 2 A bias circuit 200 according to the invention is schematically shown. The bias circuit 200 comprises an input node for receiving a digital value Sn. In the following, the node will be referred to using the reference numeral of the signal at the node. For example, the node Sn receives the digital value Sn.

[0052] The bias circuit 200 also includes a reference high node An and a reference low node Bn. The digital-to-analog converter DAC 210 converts the digital value Sn into an analog bias signal Vgn between a high voltage An and a low voltage Bn. In addition, the analog bias signal Vgn is provided at a node Vgn, which serves as a first output node of the bias circuit 200.

[0053] The bias circuit 200 further includes a switching unit 220 connected to the first output node Vgn and the second output node Vgn,s. The switching unit 220 is configured to output the analog bias signal Vgn or the low voltage Bn output by the DAC 210 as a switching analog bias signal at the second output node Vgn,s according to the switching signal TDD.

[0054] Figure 3 2 shows an implementation of the bias circuit 200. Therein, the DAC 210 is implemented using a main DAC 2101 and a buffer amplifier 2102. The main DAC 2101 is configured to convert a digital value Sn into an analog value, regardless of which bias circuit is used. The buffer amplifier 2102 is configured to buffer the analog signal provided by the main DAC 2101. If the analog value output by the main DAC 2101 is between a low voltage Bn and a high voltage An, the output of the buffer amplifier 2102 will be equal to the analog value output by the main DAC 2101. When the analog value output by the main DAC 2101 is lower than Bn, the buffer amplifier 2102 will output Bn, and when the analog value output by the main DAC 2101 is higher than An, the buffer amplifier 2102 will output An.

[0055] Alternatively, the main DAC 2101 may have a low reference voltage V_DAC_low and a high reference voltage V_DAC_high, between which the DAC 2101 outputs a voltage DAC_out. In this case, the DAC average voltage may be defined as DAC_avg=(V_DAC_high+V_DAC_low) / 2. Similarly, the buffer average voltage may be defined as BUF_avg=(An+Bn) / 2. In addition, the gain G of the buffer amplifier 2102 may be defined using G=(An-Bn) / (V_DAC_high-V_DAC_low). The buffer amplifier 2102 may be configured to output a voltage BUF_out equal to G×(DAC_out-DAC_avg)+BUF_avg. For example, when DAC_high=5, DAC_low=-3, An=10, and Bn=-2, G will be equal to 12 / 8, DAC_avg will be equal to 1, and BUF_avg will be equal to 4. In this case, BUF_out=BUF_avg+G×(DAC_out−DAC_avg)=4+12 / 8×(DAC_out−1) can be used to represent the output of the buffer amplifier 2102. It should be noted that the present invention does not exclude other mappings between the output voltage of the DAC 2101 and the output voltage of the buffer amplifier 2102.

[0056] The switching unit 220 includes a PMOS transistor Q1, the source of the transistor Q1 is connected to the first output node Vgn, the drain is connected to the second output node Vgn,s, and the gate is connected to the output terminal of the comparator 2201. The comparator 2201 serves as a switching controller. When the TDD signal is a logic high level, the comparator will output a logic high level, that is, a voltage equal to the reference voltage Vrefn. When the TDD signal is a logic low, the comparator 2201 will output Bn.

[0057] It should be noted that in some embodiments, Vrefn is derived from An and / or is equal to An. For example, the bias circuit 200 may include a unit for generating Vrefn based on An. In other embodiments, Vrefn is the same for each bias circuit 200. In this case, Vrefn can be generated external to the bias circuit 200 but on the bias control IC, or on a substrate on which the bias control IC is disposed.

[0058] The switching unit 220 further includes an NMOS transistor Q2 , a drain of the transistor Q2 being connected to the second output node Vgn,s, and a source of the transistor Q2 being connected to Bn.

[0059] When the TDD signal is at a logic high level, the voltage at the gate of Q1 is at a high level, and Q1 will be turned off. On the other hand, the voltage at the gate of Q2 is at a high level, and Q2 will be turned on. Therefore, the voltage at the second output node, i.e., the switching analog bias signal Vgn,s, will be equal to Bn.

[0060] When the TDD signal is at a logic low level, the voltage at the gate of Q1 is at a low level, and Q1 will be turned on. On the other hand, the level at the gate of Q2 is at a low level, and Q2 will be turned off. Therefore, the voltage at the second output node, i.e., Vgn,s, will be equal to Vgn.

[0061] Using TDD signaling, the bias signal at the second output node can be quickly switched between Vgn and Bn. Therefore, the signal from the second output node can be used as a bias signal in TDD applications.

[0062] Figure 4 An embodiment of a bias control integrated circuit IC 300 according to the present invention is shown. The bias control integrated circuit IC 300 comprises N (N=2) bias circuits, each bias circuit being configured as the bias circuit 200 and each bias circuit being preferably identical.

[0063] The bias control IC 300 includes a semiconductor die 301 on which the bias circuit 200 is integrated. Each bias circuit outputs two bias signals. For example, bias circuit 1 outputs signals Vg1 and Vg1,s, and bias circuit 2 outputs signals Vg2 and Vg2,s.

[0064] The bias control IC 200 also includes a controller 302, a temperature sensor T, a clock signal generator CLK, and an analog-to-digital converter ADC, which converts an analog signal from the temperature sensor T into a digital value and provides the signal to the controller 302 according to the clock signal. The controller 302 receives a data signal D, which indicates a bias signal to be provided by the bias circuit 200. The controller 302 determines two digital values ​​S1 and S2 to be provided to the two bias circuits 200 according to the data signal D and the digital signal provided by the ADC. This allows the bias control IC 300 to output a bias signal that depends on temperature, for example to compensate for changes in ambient temperature. In other embodiments, a fixed bias is used. In these embodiments, the data signal D is not provided and / or the controller 302 is not configured to receive such a signal. Then, the controller 302 determines the digital values ​​S1 and S2 based only on the measured temperature. A data interface can be provided to the programming controller 302 and / or a memory included in the programming controller 302 or a memory connected to the programming controller 302.

[0065] The bias control IC 300 is disposed on a substrate. In order to enable connection between the circuit on the substrate and the bias control IC 300, electrical connections are made. Figure 4 In FIG. 1 , these connections are indicated using bold lines 303, each of which represents one or more bond wires. In addition, circles indicate nodes, where nodes with similar reference numbers (eg, A1) are electrically connected, for example, using conductive traces.

[0066] The various nodes in the bias circuit 200 are connected, for example, using a standard routing scheme, to terminals of the bias control IC 300, each of which is configured to receive a voltage signal from an external source (e.g., a circuit on a substrate on which the bias control IC 300 is mounted or to be mounted). The following table shows how the externally generated high voltages Vh1 and Vh2, the externally generated low voltages Vl1 and Vl2, the data signal D, the signal TDD, and the output signals Vg1, Vg1,s, Vg2, and Vg2,s are connected to the nodes on the bias control IC 300. In addition, it is assumed that the reference voltage Vref1 is generated based on the voltage Vh1, and the reference voltage Vref2 is generated based on the voltage Vh2.

[0067]

[0068]

[0069] Figures 5 to 7 Different embodiments of the power amplifier module according to the present invention are shown. In different embodiments, the external voltages Vh1, Vl1, Vh2 and Vl2 are distributed to the two bias circuits 200 in different ways.

[0070] Figure 5 A power amplifier module 500 is shown. The power amplifier module 500 includes a substrate 501, on which a bias control IC 400, a first power amplifier 10, and a second power amplifier 20 are disposed. The first power amplifier 10 and the second power amplifier 20 are based on different semiconductor technologies. For example, the first power amplifier 10 may include a silicon-based LDMOS transistor, and the second power amplifier 20 may include a GaN-based FET.

[0071] The bias control IC 400 includes two bias circuits 200, which can be configured similarly to Figure 3 or Figure 4 The bias control IC 400 includes a temperature sensor that outputs an analog temperature signal to the controller 302. Although not described in detail, the bias control IC 400 may include the following: Figure 4 The ADC and clock generator described in .

[0072] The controller 302 includes an arithmetic unit 302A and a memory 302B. For each input value included in the input signal D and for each bias circuit, the memory 302B includes a plurality of values ​​to be output to each bias circuit according to the temperature. This allows the controller 302 to compensate for changes in ambient temperature.

[0073] Figure 5 A plurality of terminals 502 are shown, which are shaped as pads and are arranged on a side of the substrate 501 opposite to the side on which the bias control IC 400 is mounted on the substrate 501. The connection of the terminals 502 to the opposite side of the substrate 501 can use known through-hole technology. In addition, the bias control IC 400, the power amplifier 10 and the power amplifier 20 can be covered by a cured molding compound. In this way, an LGA type package is obtained. However, it should be noted that the present invention is equally applicable to other package types.

[0074] A plurality of pads 503 are provided on the side of the substrate 501 where the bias control IC 400 is provided. Another plurality of pads 404 are provided on the bias control IC 400. Some of these pads are used as reference high nodes or reference low nodes. One or more bonding wires 303 are used to connect the pads 503 and 404. It should be noted that Figure 5 , only one output node of each bias circuit 200 is shown as connected to the power amplifier 10, 20. In addition, the connection is schematically shown as a line connecting the amplifier to a pad on the substrate 501, which is connected to the bias control IC 400 using a bonding wire 303. Similarly, the RF input signal RF_in is provided to a pad on the back side of the substrate. Through a through hole, this signal is available on the other side of the substrate 501. There, it is routed to the input of the power amplifier 10. Again, this connection is schematically shown as a line.

[0075] The connections schematically shown above may actually include bond wires, solder bumps, or other means of electrically connecting the power amplifier 10, 20 to the substrate 501. The connections shown may include more than one connection to the substrate 501. For example, these connections may include through holes for making connections to the back side of the substrate 501, and may include conductive traces and one or more electrical components, such as surface mount devices (SMDs). They extend down to the terminals 502 on the back side of the module, so they also include through holes, traces, and many components.

[0076] exist Figure 5 In the embodiment of the present invention, each bias circuit 200 includes pads for receiving a high voltage and a low voltage. The same TDD signal is fed to each bias circuit, so each bias circuit does not require a separate pad for the signal.

[0077] As shown, the pads of the two bias circuits 200 are connected in different ways. For example, the lower bias circuit receives values ​​Vh2 and Vl2, while the upper bias circuit receives values ​​Vh1 and Vl1. In this embodiment, the mode in which the bias circuit operates, that is, which low voltage and high voltage are used, is determined by the physical connection using the bonding wire 303.

[0078] exist Figure 5 In some embodiments, the values ​​Vh1, Vh2, Vl1, and Vl2 are received from one or more sources external to the power amplifier module 500. Alternatively, Vh1, Vh2, Vl1, and Vl2 may be generated from other signals that may have been generated on the module 500 or the bias control IC 400, or may be generated from other signals that may not have been generated on the module 500 or the bias control IC 400. For example, the module 500 may receive voltages Va and Vb, where voltages Vh1 and Vh2 are generated based on voltage Va, and voltages Vl1 and Vl2 are generated based on Vb. In some embodiments, Va is equal to the larger of Vh1 and Vh2, and / or Vb is equal to the smaller of Vl1 and Vl2.

[0079] Figure 6 and Figure 7 Other embodiments of the power amplifier module according to the present invention are shown. Figure 6 In the embodiment, the power amplifier module 600 includes a reference voltage setting unit 405 as part of each bias circuit, which sets the high voltage and low voltage to be used in the bias circuit according to the mode signal. The mode signal can be generated by the controller 302. Alternatively, the mode signal is provided external to the power amplifier module 600. The mode signal indicates in which mode a given bias circuit should operate. Figure 6 As shown, the reference voltage setting unit 405 is electrically connected to a terminal 502 on a substrate 501 that receives various high voltages and low voltages.

[0080] exist Figure 6 In some embodiments, a separate and different mode signal m1, m2 is provided to each reference voltage setting unit 405. In other embodiments, the same mode signal is provided to each reference voltage setting unit 405. In the latter case, the mode signal should include settings for each bias circuit, and the reference voltage setting unit 405 should be configured to determine which part of the mode signal is intended for which bias circuit.

[0081] Figure 7An embodiment of a power amplifier module 700 in which such a shared mode signal m is used is shown. Also in this case, a single reference voltage setting unit 405 is used, which allocates a high voltage and a low voltage to be used by each bias circuit. Also, the reference voltage setting unit 405 may be connected to or include pads that form a common high node and a common low node and are connected to corresponding pads on the substrate 501 using bonding wires.

[0082] In the above embodiment, the voltages Vl1, Vl2, Vh1 and Vh2 are generated outside the power amplifier module. However, these voltages and other voltages (such as mode signals m1, m2, m) may alternatively be generated on the bias control IC or on the substrate 501. An example of this is shown in FIG. Figure 8 Shown in.

[0083] Figure 8 A power amplifier module 800 is shown in which signals Vl1, Vl2, Vh1 and Vh2 are generated by a voltage unit 405A based on externally supplied voltages Va and Vb. In addition, a mode signal m is provided from the outside.

[0084] The above content has explained the present invention using the detailed embodiments of the present invention. However, the present invention is not limited to these embodiments. On the contrary, various modifications are possible without departing from the scope of the present invention defined by the attached claims and their equivalents.

Claims

1. A bias control integrated circuit (300, 400) for providing a plurality of bias signals, the bias control integrated circuit comprising a semiconductor die (301) on which a plurality of bias circuits (200) are integrated, each bias circuit being capable of operating independently in one of a plurality of modes, wherein: Each bias circuit consists of: a reference high node (An, A1, A2), wherein a voltage of the reference high node during operation is configured to be equal to a corresponding high voltage among a plurality of high voltages corresponding to the plurality of modes; a reference low node (Bn, B1, B2), the voltage of the reference low node during operation being configured to be equal to a corresponding low voltage among a plurality of low voltages corresponding to the plurality of modes; An input node (Sn), the input node being configured to receive a digital value; a digital-to-analog converter DAC (210), the DAC being configured to convert the received digital value into an analog bias signal between a corresponding high voltage and a corresponding low voltage, wherein the output of the DAC forms a first output node (Vgn, Vg1) of the bias circuit; a second output node (Vgn,s, Vg1,s); and A switching unit (220) is connected to the first output node and the second output node and is configured to output the analog bias signal output by the DAC or the corresponding low voltage as a switching analog bias signal at the second output node according to a switching signal (TDD).

2. The bias control integrated circuit according to claim 1, wherein: The polarity of at least one high voltage is different from the polarity of at least one other high voltage, and / or wherein the polarity of at least one low voltage is different from the polarity of at least one other low voltage.

3. The bias control integrated circuit according to claim 1, wherein: The switching unit of each bias circuit includes: a first switching unit (Q1), the first switching unit being arranged between the first output node and the second output node of the bias circuit; a second switching unit (Q2) provided between the second output node and a reference node electrically connected to the reference low node; and a switching controller (2201), the switching controller being configured to control the first switching unit and the second switching unit according to the switching signal, The switching controller is configured to control the first switching unit to provide a low-ohmic connection between the first output node and the second output node, and control the second switching unit to provide a high-ohmic connection between the second output node and the reference node in response to the switching signal having a first logic value. The switching controller is configured to control the first switching unit to provide a high-ohmic connection between the first output node and the second output node, and to control the second switching unit to provide a low-ohmic connection between the second output node and the reference node in response to the switching signal having a second logic value different from the first logic value.

4. The bias control integrated circuit according to claim 1, wherein: The multiple modes include: a first mode in which the voltage at the reference high node is configured to be equal to a first high voltage during operation and the voltage at the reference low node is configured to be equal to a first low voltage during operation; and A second mode during which the voltage at the reference high node is configured to be equal to a second high voltage during operation and the voltage at the reference low node is configured to be equal to a second low voltage during operation.

5. The bias control integrated circuit according to claim 1, wherein: The reference high node and the reference low node of each bias circuit in the plurality of bias circuits are each formed by a terminal, and wherein, in order to operate a given bias circuit in a corresponding mode, the reference high node and the reference low node of the bias circuit are configured to be connected to a high voltage power supply and a low voltage power supply, respectively, corresponding to a mode in which the bias circuit works or should work, wherein the high voltage power supply and / or the low voltage power supply are preferably arranged outside the semiconductor die.

6. The bias control integrated circuit according to claim 1, comprising a reference voltage setting unit (405), the reference voltage setting unit (405) being configured to perform the following operations according to a mode signal for a given bias circuit and intended to set the bias circuit to operate in a given mode among the plurality of modes: setting the voltage at the reference high node of the bias circuit to a high voltage among the plurality of high voltages corresponding to the given mode; and The voltage at the reference low node of the bias circuit is set to a low voltage corresponding to the given mode among the plurality of low voltages.

7. The bias control integrated circuit according to claim 6, wherein: The semiconductor die comprises: a plurality of common high nodes, the voltages of the plurality of common high nodes during operation being equal to the plurality of high voltages; and a plurality of common low nodes, the voltages of the plurality of common low nodes during operation being equal to the plurality of low voltages, Wherein, the reference voltage setting unit is connected to the plurality of common high nodes and the plurality of common low nodes.

8. The bias control integrated circuit according to claim 7, wherein: A common high node among the plurality of common high nodes is configured to be electrically connected to a power source of the high voltage; and / or A common low node among the plurality of common low nodes is configured to be electrically connected to a power source of the low voltage, The high voltage power supply and / or the low voltage power supply are preferably arranged outside the semiconductor die. The reference voltage setting unit is configured to set each of the plurality of bias circuits to operate in a given mode among the plurality of modes according to a mode signal indicating a desired mode of each bias circuit.

9. The bias control integrated circuit according to claim 1, wherein: The semiconductor die includes a controller (302) configured to determine and provide a respective digital value for each bias circuit, wherein the controller is configured to receive one or more input signals and to determine the respective digital value based on the one or more input signals, and wherein the controller is configured to receive a separate input signal for each bias circuit.

10. The bias control integrated circuit according to claim 9, wherein: The controller is configured to generate the corresponding digital value for each bias circuit based on a temperature measured by a temperature sensor and the one or more input signals.

11. The bias control integrated circuit according to claim 10, wherein: The temperature sensor is disposed on the semiconductor die.

12. The bias control integrated circuit of claim 10, wherein: The controller comprises: a lookup table (302B) storing corresponding digital values ​​of a plurality of temperatures and a plurality of possible values ​​of the one or more input signals; and An arithmetic unit (302A) configured to calculate or determine the digital value to be output to each bias circuit based on the measured temperature and one or more digital values ​​stored in the lookup table corresponding to the values ​​of the one or more input signals and the measured temperature.

13. The bias control integrated circuit of claim 12, wherein: The arithmetic unit is configured to determine the digital value to be output to each bias circuit using interpolation based on two or more digital values ​​corresponding to temperatures above and below the measured temperature stored in the lookup table, wherein the lookup table stores corresponding digital values ​​for multiple temperatures of each bias circuit, respectively.

14. A radio frequency power amplifier module (500, 600, 700, 800), comprising: a plurality of power amplifiers (10, 20), each power amplifier having one or more power transistors of a different technology than a power transistor of at least one other power amplifier of the plurality of power amplifiers; The bias control integrated circuit (400) according to claim 1, wherein each bias circuit is configured to provide an analog bias signal of the bias circuit or a switched analog bias signal of the bias circuit to a control input terminal of a corresponding power transistor of a power amplifier of the plurality of power amplifiers, The one or more bias circuits in the bias control integrated circuit configured to bias one or more power transistors of a given power amplifier among the multiple power amplifiers are configured to operate in a mode different from the one or more bias circuits in the bias control integrated circuit configured to bias one or more power transistors of a different power amplifier among the multiple power amplifiers.

15. The power amplifier module according to claim 14, wherein: The same semiconductor material on which one or more power transistors of a power amplifier in the plurality of power amplifiers are based is different from the semiconductor material on which one or more power transistors of a different power amplifier in the plurality of power amplifiers are based, Among them, one or more power transistors of a first power amplifier among the multiple power amplifiers are based on gallium nitride, for example, each power transistor includes a gallium nitride-based field effect transistor, and one or more power transistors of a second power amplifier among the multiple power amplifiers are based on silicon, for example, each power transistor includes a silicon laterally diffused metal oxide semiconductor transistor.

16. The power amplifier module according to claim 14, further comprising a first substrate (501), such as a laminate substrate, wherein The one or more power transistors of each power amplifier are arranged as one or more semiconductor dies mounted on a first substrate, wherein the first substrate comprises one or more terminals for electrically connecting the power amplifier module to a second substrate, and the power amplifier module is mounted on the second substrate or is to be mounted on the second substrate, The power amplifier module is packaged as a land grid array (LGA) package, or a leadless package, such as a quad flat no-lead (QFN) package.

17. The power amplifier module according to claim 16, wherein: The reference high node and the reference low node of each bias circuit in the plurality of bias circuits are each formed by a terminal, and wherein, in order to operate a given bias circuit in a corresponding mode, the reference high node and the reference low node of the bias circuit are configured to be connected to a high voltage power supply and a low voltage power supply, respectively, corresponding to a mode in which the bias circuit works or should work, wherein the high voltage power supply and / or the low voltage power supply are preferably arranged outside the semiconductor die, wherein the off-die power supply for a high voltage among the plurality of high voltages and the off-die power supply for a low voltage among the plurality of low voltages are implemented using one or more voltage generating units arranged on the first substrate.

18. The power amplifier module according to claim 16, wherein: The reference high node and the reference low node of each of the plurality of bias circuits are each formed by a terminal, and wherein, in order to operate a given bias circuit in a corresponding mode, the reference high node and the reference low node of the bias circuit are configured to be respectively connected to a high voltage power supply and a low voltage power supply corresponding to a mode in which the bias circuit works or should work, wherein the high voltage power supply and / or the low voltage power supply are preferably arranged outside the semiconductor die, and the power amplifier module includes a plurality of terminals, and the plurality of terminals are configured to be connected to the high voltage power supply and the low voltage power supply outside the power amplifier module, wherein the reference high node and the reference low node of each bias circuit are electrically connected to corresponding terminals among the plurality of terminals of the power amplifier module.

19. A bias control integrated circuit comprising: A bias circuit (200) comprising: a reference high node (An), the voltage of the reference high node during operation being configured to be equal to a corresponding high voltage among a plurality of high voltages corresponding to a plurality of modes; a reference low node (Bn), a voltage of the reference low node during operation being configured to be equal to a corresponding low voltage among a plurality of low voltages corresponding to the plurality of modes; An input node (Sn), the input node being configured to receive a digital value; a digital-to-analog converter DAC (210) for converting a received digital value into an analog bias signal between a corresponding high voltage and a corresponding low voltage, wherein an output of the DAC forms a first output node (Vgn) of the bias circuit; a second output node (Vgn,s); and a switching unit (220) connected to the first output node and the second output node and configured to output the analog bias signal output by the DAC or the corresponding low voltage as a switching analog bias signal at the second output node according to a switching signal; and A reference voltage setting unit (405) is configured to perform the following operations according to a mode signal for a bias circuit and intended to set the bias circuit to operate in a given mode among the plurality of modes: setting the voltage at the reference high node of the bias circuit to a high voltage among the plurality of high voltages corresponding to the given mode, and setting the voltage at the reference low node of the bias circuit to a low voltage corresponding to the given mode among the plurality of low voltages, Therein, the polarity of at least one high voltage is different from the polarity of at least one other high voltage and / or the polarity of at least one low voltage is different from the polarity of at least one other low voltage.

20. A bias control integrated circuit, comprising: A bias circuit (200) comprising: a reference high node (An), the voltage of the reference high node during operation being configured to be equal to a corresponding high voltage among a plurality of high voltages corresponding to a plurality of modes; a reference low node (Bn), a voltage of the reference low node during operation being configured to be equal to a corresponding low voltage among a plurality of low voltages corresponding to the plurality of modes; An input node (Sn), the input node being configured to receive a digital value; a digital-to-analog converter DAC (210) for converting the received digital value into an analog bias signal between a corresponding high voltage and a corresponding low voltage, wherein an output of the DAC forms a first output node (Vgn) of the bias circuit; a second output node (Vgn,s); and a switching unit (220) connected to the first output node and the second output node and configured to output the analog bias signal output by the DAC or the corresponding low voltage as a switching analog bias signal at the second output node according to a switching signal, wherein a reference high node and a reference low node of the bias circuit are each formed by a terminal, and wherein in order to operate the bias circuit in a corresponding mode, the reference high node and the reference low node of the bias circuit are configured to be connected to a power supply of a high voltage and a power supply of a low voltage, respectively, corresponding to a mode in which the bias circuit operates or should operate; Therein, the polarity of at least one high voltage is different from the polarity of at least one other high voltage and / or the polarity of at least one low voltage is different from the polarity of at least one other low voltage.

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