A low-voltage operational amplifier for reducing system offset voltage

Abstract

The present invention relates to a low-voltage operational amplifier for reducing system offset voltage, comprising a folded cascode input module (101), a CLASS_AB output stage control circuit (102), and an output stage module (103). The low-voltage operational amplifier solves the problems of large system offset voltage, inaccurate output stage quiescent current control, and wasted dynamic power consumption in existing low-voltage CLASS_AB operational amplifiers, improves the output stage quiescent current error caused by the channel length modulation effect, and simultaneously improves the current matching of the first stage cascode tube by adding a second stage cascode tube, effectively reducing the input offset voltage of the operational amplifier system. When a large external source / sink current exists, the CLASS_AB output stage control circuit (102) is current-limited to limit the internal maximum power consumption, thereby reducing both heat generation and useless power consumption, thereby broadening the application of the CLASS_AB output stage operational amplifier in low-voltage, high-precision circuit systems.

Description

Technical Field

[0001] The invention relates to a low-voltage operational amplifier for reducing system offset voltage, belonging to the technical field of analog integrated circuits. Background Art

[0002] Common output stage circuits in op amps include Class-A, Class-B, and Class-AB. Class-AB is widely used due to its excellent performance when driving large capacitors and small resistors. Class-AB output stages operate between Class-A and Class-B circuits, overcoming the low efficiency of Class-A output stages while avoiding the crossover distortion of Class-B output stages. Therefore, Class-AB output stages offer the advantages of low distortion, high efficiency, and moderate power consumption, but their control structure is complex.

[0003] Theoretically, the output resistance of a MOS transistor in its saturation region is infinite. However, due to the channel length modulation effect, the output resistance is not constant but varies with the drain voltage. When channel length modulation is present in a matched MOS transistor, differences in drain potential can lead to errors in the mirrored current. This can cause mismatches within the op amp, making it difficult to accurately control the quiescent current in the op amp's output stage and causing output distortion.

[0004] In low voltage CLASS_AB output stage circuits, a feedback controlled bias circuit is often used to control the output tube of the op amp to determine the quiescent current of the op amp output stage. Figure 1 As shown, it mainly includes a rail-to-rail input stage circuit, a CLASS_AB control circuit, and an output stage circuit. The rail-to-rail input stage circuit can provide a large output swing and a high output impedance. The PMOS transistors M1 and M2 are input transistors, and the current source I1 provides bias for them; the NMOS transistors M3 and M4 are input transistors, and the current source I2 provides bias for them. The PMOS transistors M10 and M11 are the input pair transistors of the CLASS_AB bias circuit. The PMOS transistors M17, M18, M19, M8, and M20 are the minimum current selection circuit. The diode-connected NMOS transistor M8 provides bias for the NMOS transistor M11. Current source I5 flows through NMOS transistor M7, generating a bias voltage that provides bias for NMOS transistors M9 and M10. The output stage circuit includes PMOS transistor M22 and NMOS transistor M21. Capacitors C1 and C2 and resistors R1 and R2 form a Miller compensation structure to provide frequency compensation for the operational amplifier.

[0005] The accuracy of the output-stage circuit's quiescent current control is dependent on the matching between M20 and M21. Because M20 and M21 have different source-drain voltages (VDS) but the same VGS, channel length modulation (CLM) prevents M20 from accurately replicating M21's quiescent current. This results in a significant deviation between the theoretical quiescent current of output transistor M21 and the output current. When the op amp is operating dynamically, if a high current flows through output transistor M21, M20 proportionally samples M21's current, resulting in unnecessary power waste and increased chip heating.

[0006] On the other hand, channel length modulation will increase the offset voltage of the op amp system. Since the drain voltage of M9 is not equal to the drain voltage of M10 and not equal to the drain voltage of M11, the current flowing through M10 is not equal to the current flowing through M11, and the current flowing through M9 is not equal to the current flowing through M10 + the current flowing through M11, resulting in the drain voltage of M5 not being equal to the drain voltage of M6. In order to make the current flowing through M5 as close as possible to the current flowing through M6, an offset voltage will be generated at the input.

[0007] In the above-mentioned CLASS-AB output stage operational amplifier, a feedback-controlled bias circuit is used to control the quiescent current of the output stage. However, due to the channel length modulation effect and the fact that the drain voltage of the sampling tube M20 that samples the quiescent current of the output stage is not equal to the drain voltage of the output tube M21, the output stage current varies significantly. At the same time, the difference in the VDS voltage of the folded cascode tube increases the system offset voltage of the operational amplifier. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a low-voltage operational amplifier with reduced system offset voltage, solve the problems of large system offset voltage, inaccurate output stage quiescent current control, and wasteful dynamic power consumption in existing low-voltage CLASS_AB operational amplifiers, and broaden the application of CLASS_AB output stage operational amplifiers in low-voltage, high-precision circuit systems.

[0009] In order to solve the above-mentioned technical problems, the present invention adopts the following technical solution: the present invention designs a low-voltage operational amplifier for reducing system offset voltage, comprising a folded cascode input module, a CLASS_AB output stage control circuit, and an output stage module, wherein the signal output end of the folded cascode input module, the signal input end of the CLASS_AB output stage control circuit, and the signal input end of the output stage module are connected; the signal output end of the CLASS_AB output stage control circuit is connected to the feedback input end of the folded cascode input module, and the signal output end of the output stage module is connected to the feedback input end of the CLASS_AB output stage control circuit and the feedback input end of the folded cascode input module respectively.

[0010] The folded cascode input module performs amplification processing on the input signal received at its signal input end according to the signal received at its feedback input end, and generates a control signal to transmit to the CLASS_AB output stage control circuit and the output stage module respectively. The output stage module receives the control signal from the folded cascode input module and performs processing to obtain the output signal for output, and simultaneously transmits it to the feedback input end of the CLASS_AB output stage control circuit and the feedback input end of the folded cascode input module. The CLASS_AB output stage control circuit performs processing on the control signal received from the folded cascode input module according to the signal received at its feedback input end to obtain the result signal, and transmits it to the feedback input end of the folded cascode input module.

[0011] As a preferred technical solution of the present invention: the CLASS_AB output stage control circuit includes an NMOS transistor M8, an NMOS transistor M20, an NMOS transistor M33, an NMOS transistor M34, a PMOS transistor M17, a PMOS transistor M18, a PMOS transistor M19, a PMOS transistor M30, a PMOS transistor M31, a PMOS transistor M32, and a sixth current source I6; wherein the source of the PMOS transistor M30, the source of the PMOS transistor M31, and the source of the PMOS transistor M32 The sources are all connected to the external power supply VCC. The gate of the PMOS tube M30, the gate of the PMOS tube M31, the gate of the PMOS tube M32, the drain of the PMOS tube M30, and the positive electrode of the sixth current source I6 are connected. The negative electrode of the sixth current source I6 is grounded. The drain of the PMOS tube M31 is connected to the source of the PMOS tube M17. The drain of the PMOS tube M32 is connected to the source of the PMOS tube M18. The drain of the PMOS tube M17 is connected to the source of the PMOS tube M19. The gate of M19 constitutes the first signal input terminal of the CLASS_AB output stage control circuit. The drain of the PMOS transistor M19, the gate of the NMOS transistor M8, and the drain of the NMOS transistor M8 are connected, constituting the signal output terminal of the CLASS_AB output stage control circuit. The source of the NMOS transistor M8 is grounded. The gate of the PMOS transistor M17, the gate of the PMOS transistor M18, the drain of the PMOS transistor M18, the drain of the NMOS transistor M33, and the drain of the NMOS transistor M34 are connected. The gate of the NMOS transistor M33 constitutes the second signal input terminal of the CLASS_AB output stage control circuit. The source of the NMOS transistor M33, the source of the NMOS transistor M34, and the drain of the NMOS transistor M20 are connected. The gate of the NMOS transistor M20 constitutes the third signal input terminal of the CLASS_AB output stage control circuit. The source of the NMOS transistor M20 is grounded, and the gate of the NMOS transistor M34 constitutes the feedback input terminal of the CLASS_AB output stage control circuit.

[0012] As a preferred technical solution of the present invention: in the structure of the folded cascode input module, the positive electrode of the first current source I1 is connected to the external power supply VCC, the negative electrode of the first current source I1, the source electrode of the PMOS tube M1, and the source electrode of the PMOS tube M2 are connected, the gate electrode of the PMOS tube M2 is connected to the gate electrode of the NMOS tube M3 to form the first feedback input end of the folded cascode input module, which is used to connect the signal output end of the output stage module, the source electrode of the NMOS tube M3, the source electrode of the NMOS tube M4, and the positive electrode of the second current source I2 are connected, the negative electrode of the second current source I2 is grounded, the gate electrode of the PMOS tube M1 and the gate electrode of the NMOS tube M4 are connected to form the signal input end of the folded cascode input module, and the PMOS The source of the transistor M29 is connected to the external power supply VCC, the drain of the PMOS transistor M29, the source of the PMOS transistor M26, and the gate of the PMOS transistor M29 are connected, the gate of the PMOS transistor M26, the gate of the PMOS transistor M27, the gate of the PMOS transistor M28, the drain of the PMOS transistor M26, and the positive electrode of the third current source I3 are connected, the negative electrode of the third current source I3 is grounded, the positive electrode of the fourth current source I4 is connected to the external power supply VCC, the negative electrode of the fourth current source I4, the drain of the NMOS transistor M24, the gate of the NMOS transistor M24, and the gate of the NMOS transistor M25 are connected to form the second signal output end of the folded cascode input module, which is used to connect the second signal of the CLASS_AB output stage control circuit. The input end, the source of the NMOS transistor M24, the drain of the NMOS transistor M23, and the gate of the NMOS transistor M23 are connected, the source of the NMOS transistor M23 is grounded, the positive electrode of the fifth current source I5 is externally connected to the power supply VCC, the negative electrode of the fifth current source I5, the drain of the NMOS transistor M7, the gate of the NMOS transistor M7, the gate of the NMOS transistor M9, and the gate of the NMOS transistor M10 are connected, the source of the NMOS transistor M7 is grounded, the source of the PMOS transistor M15 and the source of the PMOS transistor M16 are both externally connected to the power supply VCC, the gate of the PMOS transistor M15 and the gate of the PMOS transistor M16 are connected and externally connected to the first bias voltage VB1, the drain of the PMOS transistor M15, the drain of the NMOS transistor M3, and the PMOS transistor M10 are connected. The sources of the S transistor M12 are connected, the drain of the PMOS transistor M16, the drain of the NMOS transistor M4, the source of the PMOS transistor M13, and the source of the PMOS transistor M14 are connected, the gates of the PMOS transistor M12, the gates of the PMOS transistor M13, and the gates of the PMOS transistor M14 are connected and externally connected to the second bias voltage VB2, the drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M27, the drain of the PMOS transistor M27, the drain of the NMOS transistor M9, the gate of the NMOS transistor M5, and the gate of the NMOS transistor M6 are connected, the source of the NMOS transistor M9, the drain of the PMOS transistor M2, and the drain of the NMOS transistor M5 are connected, and the source of the NMOS transistor M5 is grounded.The drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M25, forming the first signal output terminal of the folded cascode input module, which is used to connect to the first signal input terminal of the CLASS_AB output stage control circuit. The source of the NMOS transistor M25 is connected to the drain of the NMOS transistor M10, the drain of the PMOS transistor M14 is connected to the source of the PMOS transistor M28, and the drain of the PMOS transistor M28 is connected to the drain of the NMOS transistor M11, forming the third signal output terminal of the folded cascode input module, which is used to connect to the third signal input terminal of the CLASS_AB output stage control circuit. The gate of the NMOS transistor M11 forms the second feedback input terminal of the folded cascode input module, which is used to connect to the signal output terminal of the CLASS_AB output stage control circuit. The source of the NMOS transistor M10, the source of the NMOS transistor M11, the drain of the PMOS transistor M1, and the drain of the NMOS transistor M6 are connected, and the source of the NMOS transistor M6 is grounded.

[0013] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M14 is equal to that of the PMOS tube M13, and is half of the width-to-length ratio of the PMOS tube M12; the width-to-length ratio of the NMOS tube M10 is equal to that of the NMOS tube M11, and is half of the width-to-length ratio of the NMOS tube M9.

[0014] As a preferred technical solution of the present invention: the current generated by the first bias voltage VB1 acting on the PMOS tube M15 is K1 times the current set by the fourth current source I4, and the width-to-length ratio of the PMOS tube M27 is twice the width-to-length ratio of the PMOS tube M28.

[0015] As a preferred technical solution of the present invention, the width-to-length ratio of the PMOS tube M29 and the width-to-length ratio of the PMOS tube M26 are adjusted so that the drain voltage of the PMOS tube M13, the drain voltage of the PMOS tube M12, and the drain voltage of the PMOS tube M14 are equal; and the width-to-length ratio of the NMOS tube M23 and the width-to-length ratio of the NMOS tube M24 are adjusted so that the drain voltage of the PMOS tube M10 is equal to the drain voltage of the NMOS tube M11.

[0016] As a preferred technical solution of the present invention: the output stage module includes an NMOS tube M21, a PMOS tube M22, a Miller capacitor C1, a Miller capacitor C2, a zero adjustment resistor R1, and a zero adjustment resistor R2, wherein the source of the PMOS tube M22 is externally connected to the power supply VCC, the gate of the PMOS tube M22 is connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module, and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit, the other end of the Miller capacitor C1 is connected to one end of the zero adjustment resistor R1, the other end of the zero adjustment resistor R1 and the drain of the PMOS tube M22 are connected to the drain of the PMOS tube M22. The four ends of the zero-adjustment resistor R2, one end of the zero-adjustment resistor R2, and the drain of the NMOS transistor M21 are connected to form a signal output end of the output stage module. While the signal output end of the output stage module is outputting, it is respectively connected to the feedback input end of the CLASS_AB output stage control circuit and the feedback input end of the folded cascode input module. The other end of the zero-adjustment resistor R2 is connected to one end of the Miller capacitor C2, and the other end of the Miller capacitor C2 is connected to the gate of the NMOS transistor M21 to form a second signal input end of the output stage module, which is used to be connected to the third signal input end of the CLASS_AB output stage control circuit. The source of the NMOS transistor M21 is grounded.

[0017] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M19, the width-to-length ratio of the PMOS tube M17, and the width-to-length ratio of the PMOS tube M18 are consistent and are 1 / K3 times the width-to-length ratio of the PMOS tube M22; the width-to-length ratio of the NMOS tube M21 is K1 times the width-to-length ratio of the NMOS tube M20, and K3=K1.

[0018] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M31 and the width-to-length ratio of the PMOS tube M32 are both K2 times the width-to-length ratio of the PMOS tube M30.

[0019] The low-voltage operational amplifier for reducing system offset voltage described in the present invention has the following technical effects compared with the prior art by adopting the above technical solution:

[0020] The present invention designs a low-voltage operational amplifier for reducing system offset voltage, comprising a folded cascode input module, a CLASS_AB output stage control circuit, and an output stage module. The invention solves the problems of large system offset voltage, inaccurate output stage quiescent current control, and wasted dynamic power consumption in existing low-voltage CLASS_AB operational amplifiers, improves the output stage quiescent current error caused by the channel length modulation effect, and simultaneously improves the current matching of the first stage cascode by adding a second stage cascode transistor, effectively reducing the input offset voltage of the operational amplifier system. When a large external source or sink current exists, the CLASS_AB output stage control circuit is current limited to limit the internal maximum power consumption, thereby reducing both heat generation and useless power consumption, thereby broadening the application of the CLASS_AB output stage operational amplifier in low-voltage, high-precision circuit systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of an existing CLASS_AB output stage operational amplifier circuit;

[0022] Figure 2 It is a schematic diagram of the low-voltage CLASS_AB output stage control circuit designed by the present invention.

[0023] Among them, 101. Folded cascode input module, 102. CLASS_AB output stage control circuit, 103. Output stage module. DETAILED DESCRIPTION

[0024] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0025] The present invention designs a low voltage operational amplifier for reducing the system offset voltage, such as Figure 2 As shown, the design includes a folded cascode input module 101, a CLASS_AB output stage control circuit 102, and an output stage module 103, wherein the signal output end of the folded cascode input module 101, the signal input end of the CLASS_AB output stage control circuit 102, and the signal input end of the output stage module 103 are connected; the signal output end of the CLASS_AB output stage control circuit 102 is connected to the feedback input end of the folded cascode input module 101, and the signal output end of the output stage module 103 is connected to the feedback input end of the CLASS_AB output stage control circuit 102 and the feedback input end of the folded cascode input module 101 at the same time as the output.

[0026] The folded cascode input module 101 amplifies the input signal received at its signal input terminal according to the signal received at its feedback input terminal, generates a control signal and transmits it to the CLASS_AB output stage control circuit 102 and the output stage module 103 respectively. The output stage module 103 receives the control signal from the folded cascode input module 101 and processes it to obtain an output signal to drive an external load, and simultaneously transmits it to the feedback input terminal of the CLASS_AB output stage control circuit 102 and the feedback input terminal of the folded cascode input module 101. The CLASS_AB output stage control circuit 102 processes the control signal received from the folded cascode input module 101 according to the signal received at its feedback input terminal to obtain a result signal, and transmits it to the feedback input terminal of the folded cascode input module 101.

[0027] According to the above design, in actual application, the folded cascode input module 101, the CLASS_AB output stage control circuit 102, and the output stage module 103 are specifically designed, wherein, Figure 2As shown, the folded cascode input module 101 receives the feedback signal from the CLASS_AB output stage control circuit 102 and generates a bias voltage of the output transistor to control the output stage static current. The design includes NMOS transistor M8, NMOS transistor M20, NMOS transistor M33, NMOS transistor M34, PMOS transistor M17, PMOS transistor M18, PMOS transistor M19, PMOS transistor M30, PMOS transistor M31, PMOS transistor M32, and a sixth current source I6; wherein, PMOS transistor M3 The source of the PMOS tube M0, the source of the PMOS tube M31, and the source of the PMOS tube M32 are all connected to the external power supply VCC. The gate of the PMOS tube M30, the gate of the PMOS tube M31, the gate of the PMOS tube M32, the drain of the PMOS tube M30, and the positive electrode of the sixth current source I6 are connected. The negative electrode of the sixth current source I6 is grounded. The drain of the PMOS tube M31 is connected to the source of the PMOS tube M17. The drain of the PMOS tube M32 is connected to the source of the PMOS tube M18. The drain of the PMOS tube M17 is connected to the positive electrode of the PMOS tube M19. The source of the PMOS transistor M19 and the gate of the PMOS transistor M19 constitute the first signal input terminal of the CLASS_AB output stage control circuit 102. The drain of the PMOS transistor M19, the gate of the NMOS transistor M8, and the drain of the NMOS transistor M8 are connected to form the signal output terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS transistor M8 is grounded. The gate of the PMOS transistor M17, the gate of the PMOS transistor M18, the drain of the PMOS transistor M18, the drain of the NMOS transistor M33, and the drain of the NMOS transistor M34 are connected to each other. The drains of the five transistors are connected. The gate of the NMOS transistor M33 constitutes the second signal input terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS transistor M33, the source of the NMOS transistor M34, and the drain of the NMOS transistor M20 are connected. The gate of the NMOS transistor M20 constitutes the third signal input terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS transistor M20 is grounded, and the gate of the NMOS transistor M34 constitutes the feedback input terminal of the CLASS_AB output stage control circuit 102.

[0028] Based on the above specific design structure of the CLASS_AB output stage control circuit 102, the structure of the folded cascode input module 101 is further designed, such as Figure 2As shown, the positive electrode of the first current source I1 is connected to the external power supply VCC, the negative electrode of the first current source I1, the source of the PMOS transistor M1, and the source of the PMOS transistor M2 are connected, the gate of the PMOS transistor M2 is connected to the gate of the NMOS transistor M3 to form the first feedback input end of the folded cascode input module 101, which is used to connect to the signal output end of the output stage module 103, the source of the NMOS transistor M3, the source of the NMOS transistor M4, and the positive electrode of the second current source I2 are connected, the negative electrode of the second current source I2 is grounded, the gate of the PMOS transistor M1 and the gate of the NMOS transistor M4 are connected to form the signal input end of the folded cascode input module 101, and the source of the PMOS transistor M29 is connected to the external power supply VCC The drain of the PMOS transistor M29, the source of the PMOS transistor M26, and the gate of the PMOS transistor M29 are connected. The gate of the PMOS transistor M26, the gate of the PMOS transistor M27, the gate of the PMOS transistor M28, the drain of the PMOS transistor M26, and the positive electrode of the third current source I3 are connected. The negative electrode of the third current source I3 is grounded. The positive electrode of the fourth current source I4 is connected to the external power supply VCC. The negative electrode of the fourth current source I4, the drain of the NMOS transistor M24, the gate of the NMOS transistor M24, and the gate of the NMOS transistor M25 are connected to form the second signal output end of the folded cascode input module 101, which is used to connect to the second signal input end of the CLASS_AB output stage control circuit 102. The source of the MOS transistor M24, the drain of the NMOS transistor M23, and the gate of the NMOS transistor M23 are connected. The source of the NMOS transistor M23 is grounded. The positive electrode of the fifth current source I5 is externally connected to the power supply VCC. The negative electrode of the fifth current source I5, the drain of the NMOS transistor M7, the gate of the NMOS transistor M7, the gate of the NMOS transistor M9, and the gate of the NMOS transistor M10 are connected. The source of the NMOS transistor M7 is grounded. The source of the PMOS transistor M15 and the source of the PMOS transistor M16 are both externally connected to the power supply VCC. The gate of the PMOS transistor M15 and the gate of the PMOS transistor M16 are connected and externally connected to the first bias voltage VB1. The drain of the PMOS transistor M15, the drain of the NMOS transistor M3, and the PMOS transistor M10 are externally connected. The sources of the PMOS transistor M12 are connected, the drain of the PMOS transistor M16, the drain of the NMOS transistor M4, the source of the PMOS transistor M13, and the source of the PMOS transistor M14 are connected, the gates of the PMOS transistor M12, the gates of the PMOS transistor M13, and the gates of the PMOS transistor M14 are connected and externally connected to a second bias voltage VB2, the drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M27, the drain of the PMOS transistor M27, the drain of the NMOS transistor M9, the gate of the NMOS transistor M5, and the gate of the NMOS transistor M6 are connected, the source of the NMOS transistor M9, the drain of the PMOS transistor M2, and the drain of the NMOS transistor M5 are connected, and the source of the NMOS transistor M5 is grounded.The drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M25 to form the first signal output terminal of the folded cascode input module 101, which is used to connect to the first signal input terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS transistor M25 is connected to the drain of the NMOS transistor M10, the drain of the PMOS transistor M14 is connected to the source of the PMOS transistor M28, and the drain of the PMOS transistor M28 is connected to the drain of the NMOS transistor M11 to form the folded cascode input module. The third signal output terminal of block 101 is connected to the third signal input terminal of the CLASS_AB output stage control circuit 102. The gate of NMOS transistor M11 constitutes the second feedback input terminal of the folded cascode input module 101, which is connected to the signal output terminal of the CLASS_AB output stage control circuit 102. The source of NMOS transistor M10, the source of NMOS transistor M11, the drain of PMOS transistor M1, and the drain of NMOS transistor M6 are connected. The source of NMOS transistor M6 is grounded.

[0029] In the folded cascode input module 101, NMOS transistor M7 cooperates with current source I5 to provide bias for NMOS transistors M9 and M10 in a common-gate structure. NMOS transistors M23 and M24 are diode-connected and cooperate with current source I4 to provide bias for NMOS transistor M25 in a second common-gate structure. PMOS transistors M12, M13, and M14 also have a common-gate structure. PMOS transistors M29 and M26 are diode-connected and cooperate with current source I3 to provide bias for PMOS transistors M27 and M28 in a second common-gate structure.

[0030] Regarding the output stage module 103, in actual application, Figure 2As shown, the design includes an NMOS transistor M21, a PMOS transistor M22, a Miller capacitor C1, a Miller capacitor C2, a zero-adjusting resistor R1, and a zero-adjusting resistor R2, wherein the source of the PMOS transistor M22 is externally connected to the power supply VCC, the gate of the PMOS transistor M22 is connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module 103, and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit 102, the other end of the Miller capacitor C1 is connected to one end of the zero-adjusting resistor R1, the other end of the zero-adjusting resistor R1, the drain of the PMOS transistor M22, one end of the zero-adjusting resistor R2, the NMOS transistor M21, and the PMOS transistor M22. The drains of the NMOS transistor M21 are connected to form the signal output terminal of the output stage module 103. While the output signal of the output stage module 103 is being output, it is also connected to the feedback input terminal of the CLASS_AB output stage control circuit 102 and the feedback input terminal of the folded cascode input module 101. The other end of the zeroing resistor R2 is connected to one end of the Miller capacitor C2. The other end of the Miller capacitor C2 is connected to the gate of the NMOS transistor M21 to form the second signal input terminal of the output stage module 103, which is used to connect to the third signal input terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS transistor M21 is grounded. In application, the output stage module 103 is used to drive an external load, and the frequency response characteristics of the op amp are compensated by the Miller capacitor and the zeroing resistor.

[0031] The above design is applied in practice, and further specifically designed that the width-to-length ratio of the PMOS tube M14 is equal to that of the PMOS tube M13, and is half of the width-to-length ratio of the PMOS tube M12; the width-to-length ratio of the NMOS tube M10 is equal to that of the NMOS tube M11, and is half of the width-to-length ratio of the NMOS tube M9; the current generated by the first bias voltage VB1 acting on the PMOS tube M15 is K1 times the current at the position set by the fourth current source I4; the width-to-length ratio of the PMOS tube M27 is equal to that of the NMOS tube M11, and is half of the width-to-length ratio of the NMOS tube M9; The width-to-length ratio of the PMOS tube M19, the PMOS tube M17, and the PMOS tube M18 are consistent with each other and are 1 / K3 times the width-to-length ratio of the PMOS tube M22. The width-to-length ratio of the NMOS tube M21 is K1 times the width-to-length ratio of the NMOS tube M20, and K3=K1. The width-to-length ratios of the PMOS tube M31 and the PMOS tube M32 are both K2 times the width-to-length ratio of the PMOS tube M30. In application, the width-to-length ratio of the PMOS transistor M29 and the width-to-length ratio of the PMOS transistor M26 are adjusted so that the drain voltages of the PMOS transistor M13, the drain voltages of the PMOS transistor M12, and the drain voltages of the PMOS transistor M14 are equal; and the width-to-length ratio of the NMOS transistor M23 and the width-to-length ratio of the NMOS transistor M24 are adjusted so that the drain voltage of the PMOS transistor M10 is equal to the drain voltage of the NMOS transistor M11.

[0032] In a specific implementation of the above-designed circuit, for the folded cascode input module 101, the NMOS transistors M10 and M11 are used as differential input ports, and the diode-connected NMOS transistor M7 generates a reference voltage V3 under the action of the current source I5. The function of the CLASS_AB output stage control circuit 102 is to proportionally mirror the current of the NMOS output transistor M21 through the NMOS transistor M20. This current flows through the diode-connected PMOS transistor M18. Since the gate terminal voltages of the PMOS transistors M17 and M19 are similar, the PMOS transistors M17 and M19 can be equivalent to PMOS transistors with a gate length of 2L, where L represents the length of the MOS transistor. Therefore, the current flowing through the PMOS transistors M17 and M19 is half the current flowing through the NMOS transistor M20. This current flows through the diode-connected NMOS transistor M8, generating a voltage V4 output by the NMOS transistor M8 to the NMOS transistor M11. Under the feedback control of the loop in the folded cascode input module 101 and the CLASS_AB output stage control circuit 102, the current output by the PMOS transistor M19 is equal to the current at the position set by the current source I5, making the voltage V4 output by the NMOS transistor M8 equal to the voltage V3 output by the NMOS transistor M7, that is, Figure 2 When V3=V4, the quiescent current of the NMOS transistor M21 and the PMOS transistor M22 in the output stage module 103 is confirmed to be 2*K3*the position current set by the current source I5. The accuracy of this current is determined by the matching between the NMOS transistor M20 and the NMOS output transistor M21. To reduce the impact of the channel length modulation effect on the accuracy of the mirror current, the design further adds NMOS transistors M33 and NMOS transistors M34 to reduce the impact of the channel length modulation effect. The sum of the gate-source voltage of NMOS transistor M23 and the gate-source voltage of NMOS transistor M24 is defined as V2. When Vout at the signal output terminal of output stage module 103 is less than the result of V2 minus the gate-source voltage of NMOS transistor M33, NMOS transistor M33 controls the drain voltage difference between NMOS transistor M20 and NMOS output transistor M21. When Vout at the signal output terminal of output stage module 103 is greater than the result of V2 minus the gate-source voltage of NMOS transistor M33, NMOS transistor M33 controls the drain voltage difference between NMOS transistor M20 and NMOS output transistor M21. In application, the current at the set position of current source I1 is equal to the current at the set position of current source I2, and the current at the set position of current source I3 is equal to the current at the set position of current source I4.

[0033] Regarding the design of the NMOS transistor M25, PMOS transistor M27, and PMOS transistor M28 in the present invention, if the second common-gate structure is not added, if the power supply voltage is high, then due to the channel length modulation effect, the sum of the current flowing through the NMOS transistor M10 and the current flowing through the NMOS transistor M11 is greater than the current flowing through the NMOS transistor M9. Since the gate of the NMOS transistor M5 is connected to the gate of the NMOS transistor M6, the difference in drain terminal voltage is very small. Therefore, the current flowing through the NMOS transistor M5 is equal to the current flowing through the NMOS transistor M6. The current relationship of the input transistors is: , the system input offset voltage is ,in, Indicates the current flowing through the PMOS tube M2, Indicates the current flowing through the PMOS tube M1, Indicates the current flowing through the NMOS tube M10, Indicates the current flowing through the NMOS tube M11, Indicates the current flowing through the NMOS tube M9, Represents the transconductance of the PMOS tube M1; after adding the NMOS tube M25, PMOS tube M27, and PMOS tube M28 of the second common-gate tube structure, the channel length modulation effect is improved. It approaches zero, greatly reducing the system input offset voltage.

[0034] Regarding the design of the present invention incorporating PMOS transistors M30, PMOS transistors M31, PMOS transistors M32, and current source I6, if these transistors are not incorporated, and an external load injects a large current into output-stage NMOS transistor M21, since NMOS transistor M20 mirrors the current of output-stage NMOS transistor M21 in equal proportion, a large current will also flow through NMOS transistor M20. This current is provided by the system's external power supply, significantly increasing the power consumption of the operational amplifier. After incorporating PMOS transistors M30, PMOS transistors M31, PMOS transistors M32, and current source I6, the external load injects a large current into output-stage NMOS transistor M21, causing the drain voltages of PMOS transistors M31 and PMOS transistors M32 to drop, entering a saturation region. At this point, the current flowing through these transistors is determined by the ratio of current source I6, PMOS transistors M30, PMOS transistors M31, and PMOS transistors M32, thereby controlling system power consumption.

[0035] Using this structure to control the output-stage transistors, by controlling the drain-source voltage differences of the matched transistors, the problems of increased input offset voltage and inaccurate quiescent current control of the output-stage transistors caused by the channel length modulation effect are resolved. This also addresses the issue of ineffective control of the system's dynamic power consumption.

[0036] The low-voltage operational amplifier designed by the above technical solution to reduce system offset voltage includes a folded cascode input module 101, a CLASS_AB output stage control circuit 102, and an output stage module 103. It solves the problems of large system offset voltage, inaccurate output stage quiescent current control, and wasted dynamic power consumption in existing low-voltage CLASS_AB operational amplifiers, improves the output stage quiescent current error caused by the channel length modulation effect, and at the same time improves the current matching of the first-stage cascode tube by adding a second-stage cascode tube, effectively reducing the input offset voltage of the operational amplifier system. When there is a large external source or sink current, the internal maximum power consumption is limited by limiting the current of the CLASS_AB output stage control circuit 102, thereby reducing both heat generation and useless power consumption, and broadening the application of the CLASS_AB output stage operational amplifier in low-voltage, high-precision circuit systems.

[0037] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the scope of knowledge possessed by ordinary technicians in this field without departing from the spirit of the present invention.

Claims

1. A low-voltage operational amplifier for reducing system offset voltage, characterized in that: It comprises a folded cascode input module (101), a CLASS_AB output stage control circuit (102), and an output stage module (103), wherein the signal output end of the folded cascode input module (101), the signal input end of the CLASS_AB output stage control circuit (102), and the signal input end of the output stage module (103) are connected; the signal output end of the CLASS_AB output stage control circuit (102) is connected to the feedback input end of the folded cascode input module (101), and the signal output end of the output stage module (103) is connected to the feedback input end of the CLASS_AB output stage control circuit (102) and the feedback input end of the folded cascode input module (101) respectively while outputting; The folded cascode input module (101) performs amplification processing on the input signal received at its signal input end according to the signal received at its feedback input end, generates a control signal and transmits it to the CLASS_AB output stage control circuit (102) and the output stage module (103) respectively; the output stage module (103) receives the control signal from the folded cascode input module (101) and performs processing to obtain an output signal for output, and simultaneously transmits it to the feedback input end of the CLASS_AB output stage control circuit (102) and the feedback input end of the folded cascode input module (101); the CLASS_AB output stage control circuit (102) performs processing on the control signal received from the folded cascode input module (101) according to the signal received at its feedback input end to obtain a result signal, and transmits it to the feedback input end of the folded cascode input module (101); The CLASS_AB output stage control circuit (102) includes an NMOS transistor M8, an NMOS transistor M20, an NMOS transistor M33, an NMOS transistor M34, a PMOS transistor M17, a PMOS transistor M18, a PMOS transistor M19, a PMOS transistor M30, a PMOS transistor M31, a PMOS transistor M32, and a sixth current source I6; wherein the source of the PMOS transistor M30, the source of the PMOS transistor M31, and the source of the PMOS transistor M32 are all connected to an external power supply VCC, and the PMOS The gate of transistor M30, the gate of PMOS transistor M31, the gate of PMOS transistor M32, the drain of PMOS transistor M30, and the positive electrode of the sixth current source I6 are connected. The negative electrode of the sixth current source I6 is grounded. The drain of PMOS transistor M31 is connected to the source of PMOS transistor M17. The drain of PMOS transistor M32 is connected to the source of PMOS transistor M18. The drain of PMOS transistor M17 is connected to the source of PMOS transistor M19. The gate of PMOS transistor M19 constitutes the CLASS_AB output stage. The first signal input terminal of the control circuit (102), the drain of the PMOS tube M19, the gate of the NMOS tube M8, and the drain of the NMOS tube M8 are connected to form the signal output terminal of the CLASS_AB output stage control circuit (102), the source of the NMOS tube M8 is grounded, the gate of the PMOS tube M17, the gate of the PMOS tube M18, the drain of the PMOS tube M18, the drain of the NMOS tube M33, and the drain of the NMOS tube M34 are connected, and the NMOS tube M33 is connected to the drain of the NMOS tube M34. The gate of the NMOS transistor M33 constitutes the second signal input terminal of the CLASS_AB output stage control circuit (102); the source of the NMOS transistor M33, the source of the NMOS transistor M34, and the drain of the NMOS transistor M20 are connected; the gate of the NMOS transistor M20 constitutes the third signal input terminal of the CLASS_AB output stage control circuit (102); the source of the NMOS transistor M20 is grounded; and the gate of the NMOS transistor M34 constitutes the feedback input terminal of the CLASS_AB output stage control circuit (102).

2. The low-voltage operational amplifier for reducing system offset voltage according to claim 1, wherein: In the structure of the folded cascode input module (101), the positive electrode of the first current source I1 is connected to an external power supply VCC, the negative electrode of the first current source I1, the source electrode of the PMOS tube M1, and the source electrode of the PMOS tube M2 are connected, the gate electrode of the PMOS tube M2 and the gate electrode of the NMOS tube M3 are connected to form a first feedback input end of the folded cascode input module (101), which is used to connect to the signal output end of the output stage module (103), the source electrode of the NMOS tube M3, the source electrode of the NMOS tube M4, and the positive electrode of the second current source I2 are connected, the negative electrode of the second current source I2 is grounded, and the gate electrode of the PMOS tube M1 and the gate electrode of the NMOS tube M4 are connected to form a signal input end of the folded cascode input module (101). The source of the PMOS tube M29 is connected to the external power supply VCC, the drain of the PMOS tube M29, the source of the PMOS tube M26, and the gate of the PMOS tube M29 are connected, the gate of the PMOS tube M26, the gate of the PMOS tube M27, the gate of the PMOS tube M28, the drain of the PMOS tube M26, and the positive electrode of the third current source I3 are connected, the negative electrode of the third current source I3 is grounded, the positive electrode of the fourth current source I4 is connected to the external power supply VCC, the negative electrode of the fourth current source I4, the drain of the NMOS tube M24, the gate of the NMOS tube M24, and the gate of the NMOS tube M25 are connected to form the second signal output end of the folded common source and common gate input module (101), which is used to connect the CLASS_AB output stage The second signal input terminal of the control circuit (102) is connected to the source of the NMOS tube M24, the drain of the NMOS tube M23, and the gate of the NMOS tube M23. The source of the NMOS tube M23 is grounded. The positive electrode of the fifth current source I5 is externally connected to the power supply VCC. The negative electrode of the fifth current source I5, the drain of the NMOS tube M7, the gate of the NMOS tube M7, the gate of the NMOS tube M9, and the gate of the NMOS tube M10 are connected. The source of the NMOS tube M7 is grounded. The source of the PMOS tube M15 and the source of the PMOS tube M16 are both externally connected to the power supply VCC. The gate of the PMOS tube M15 and the gate of the PMOS tube M16 are connected and externally connected to the first bias voltage VB1. The drain of the PMOS tube M15, The drain of the NMOS transistor M3 and the source of the PMOS transistor M12 are connected. The drain of the PMOS transistor M16, the drain of the NMOS transistor M4, the source of the PMOS transistor M13, and the source of the PMOS transistor M14 are connected. The gates of the PMOS transistor M12, the gates of the PMOS transistor M13, and the gates of the PMOS transistor M14 are connected and externally connected to a second bias voltage VB2. The drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M27. The drain of the PMOS transistor M27, the drain of the NMOS transistor M9, the gate of the NMOS transistor M5, and the gate of the NMOS transistor M6 are connected. The source of the NMOS transistor M9, the drain of the PMOS transistor M2, and the drain of the NMOS transistor M5 are connected.The source of the NMOS tube M5 is grounded, the drain of the PMOS tube M13 is connected to the drain of the NMOS tube M25 to form a first signal output terminal of the folded common source and common gate input module (101), which is used to connect to the first signal input terminal of the CLASS_AB output stage control circuit (102), the source of the NMOS tube M25 is connected to the drain of the NMOS tube M10, the drain of the PMOS tube M14 is connected to the source of the PMOS tube M28, and the drain of the PMOS tube M28 is connected to the drain of the NMOS tube M11 to form a folded common source. The third signal output terminal of the common-gate input module (101) is used to connect to the third signal input terminal of the CLASS_AB output stage control circuit (102). The gate of the NMOS tube M11 constitutes the second feedback input terminal of the folded common-source common-gate input module (101) and is used to connect to the signal output terminal of the CLASS_AB output stage control circuit (102). The source of the NMOS tube M10, the source of the NMOS tube M11, the drain of the PMOS tube M1, and the drain of the NMOS tube M6 are connected. The source of the NMOS tube M6 is grounded.

3. The low-voltage operational amplifier for reducing system offset voltage according to claim 2, wherein: The width-to-length ratio of the PMOS tube M14 is equal to that of the PMOS tube M13 and is half of that of the PMOS tube M12; the width-to-length ratio of the NMOS tube M10 is equal to that of the NMOS tube M11 and is half of that of the NMOS tube M9.

4. The low-voltage operational amplifier for reducing system offset voltage according to claim 2, wherein: The current generated by the first bias voltage VB1 acting on the PMOS transistor M15 is K1 times the current set by the fourth current source I4, and the width-to-length ratio of the PMOS transistor M27 is twice the width-to-length ratio of the PMOS transistor M28.

5. The low-voltage operational amplifier for reducing system offset voltage according to claim 2, wherein: The width-to-length ratio of the PMOS transistor M29 and the width-to-length ratio of the PMOS transistor M26 are adjusted so that the drain voltages of the PMOS transistor M13, the drain voltages of the PMOS transistor M12, and the drain voltages of the PMOS transistor M14 are equal; and the width-to-length ratio of the NMOS transistor M23 and the width-to-length ratio of the NMOS transistor M24 are adjusted so that the drain voltage of the PMOS transistor M10 is equal to the drain voltage of the NMOS transistor M11.

6. The low-voltage operational amplifier for reducing system offset voltage according to claim 1, wherein: The output stage module (103) includes an NMOS tube M21, a PMOS tube M22, a Miller capacitor C1, a Miller capacitor C2, a zero adjustment resistor R1, and a zero adjustment resistor R2, wherein the source of the PMOS tube M22 is externally connected to a power supply VCC, the gate of the PMOS tube M22 is connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module (103), and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit (102), the other end of the Miller capacitor C1 is connected to one end of the zero adjustment resistor R1, the other end of the zero adjustment resistor R1, the drain of the PMOS tube M22, one end of the zero adjustment resistor R2, the NMOS tube M22, and the NMOS tube M22. The drains of the OS transistor M21 are connected to form a signal output terminal of the output stage module (103). When the signal output terminal of the output stage module (103) outputs, the signal output terminal is connected to the feedback input terminal of the CLASS_AB output stage control circuit (102) and the feedback input terminal of the folded common source and common gate input module (101). The other end of the zero adjustment resistor R2 is connected to one end of the Miller capacitor C2. The other end of the Miller capacitor C2 is connected to the gate of the NMOS transistor M21 to form a second signal input terminal of the output stage module (103), which is used to be connected to the third signal input terminal of the CLASS_AB output stage control circuit (102). The source of the NMOS transistor M21 is grounded.

7. The low-voltage operational amplifier for reducing system offset voltage according to claim 6, wherein: The width-to-length ratios of the PMOS tube M19, the PMOS tube M17, and the PMOS tube M18 are consistent and are 1 / K3 times the width-to-length ratio of the PMOS tube M22. The width-to-length ratio of the NMOS tube M21 is K1 times the width-to-length ratio of the NMOS tube M20, and K3=K1.

8. The low-voltage operational amplifier for reducing system offset voltage according to claim 1, wherein: The width-to-length ratio of the PMOS transistor M31 and the width-to-length ratio of the PMOS transistor M32 are both K2 times the width-to-length ratio of the PMOS transistor M30.

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