Design method of high-efficiency and high-power output amplifier chip

Abstract

The invention discloses a high-efficiency and high-power output amplifier chip design method suitable for a microwave radar, and the method employs a gallium nitride (GaN) high electron mobility transistor (HEMT) as a core amplification device, combines an inverse F-class amplifier topological structure, optimizes an input impedance matching network and an output harmonic control network, and achieves the high-efficiency and high-power output of a microwave radar. And high-efficiency and high-power output under the working condition that the central frequency bandwidth is 800MHz at 5.8 GHz is successfully realized. Experimental data of the final design shows that the theoretical efficiency of the amplifier is 90.7% when the amplifier controls third harmonics, the power additional efficiency (PAE) in simulation of an ideal circuit model is 71.1% and 37.4 dBm, in the final electromagnetic simulation stage, the parasitic effect and transmission loss of an actual circuit and the non-ideal characteristics of components are considered, the power additional efficiency is 67.2%, the output power is 48.4 dBm, namely 69.18 W, and the output power is 69.18 W. And the gain is 11.6 dB. The invention is suitable for microwave radar transmitters and other high-power high-frequency electronic equipment.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic engineering, and in particular relates to a high-efficiency output amplifier suitable for a high-power and high-frequency transmitter of a microwave radar. Background Art

[0002] In the energy transmission system, the power amplifier is one of the modules that consumes the most energy in the entire communication system. At the same time, the output power of the power amplifier determines the transmission link length of the system output signal when the operating frequency is determined. The power conversion efficiency determines the energy consumption of the entire system. The design basis of the power amplifier is usually focused on how to improve the performance of output power and efficiency. Therefore, designing a high-efficiency power amplifier is the key to reducing system energy consumption and has become the goal of current power amplifier research. The design concept of the present invention is to use gallium nitride (GaN) high electron mobility transistor (HEMT) to develop an inverse F-class amplifier for microwave radar transmitters and other high-power high-frequency electronic equipment.

[0003] In practice, the inverse class F power amplifier can achieve better efficiency characteristics than the class F power amplifier, assuming the same output power and gain. For the inverse class F amplifier, when only theoretically calculated, if the third harmonic suppression control circuit is designed, the efficiency can reach 90.7%. If the fifth harmonic suppression control circuit is designed, the efficiency can reach 94.8%. Only when the harmonic suppression is infinite can 100% efficiency be achieved. So far, the design of the inverse class F amplifier at 5.8GHz is very rare. The previous research results of other researchers similar to this project were compared. Researchers from the Institute of Microelectronics of Southwest Jiaotong University designed a third harmonic suppression circuit at the output of the power amplifier using an LC impedance matching network, and designed a class F power amplifier operating at 3.5GHz, with a maximum PAE of 68% and an output power of 37dBm. Researchers from the University of Science and Technology of China designed a parasitic compensation circuit in the network to control the fifth harmonic of the output signal, and successfully constructed an inverse class F power amplifier. At 940MHz, the output power was 39.8dBm and the maximum efficiency was 87.4%. Although the efficiency has been improved to a certain extent, the output is not very satisfactory. As mentioned above, improving harmonic suppression can increase the efficiency of the amplifier, which should be considered for class F and inverse class F amplifiers. Considering the difficulty of design, the difference in operating frequency must be considered, because it is much more difficult to control high-order harmonics of GHz frequency than MHz frequency. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a high-efficiency output amplifier that successfully achieves high-efficiency and high-power output under working conditions of 5.8 GHz center frequency and 800 MHz bandwidth by using gallium nitride (GaN) high electron mobility transistor (HEMT) as a core amplifier device, combining an inverse class F amplifier topology, optimizing an input impedance matching network and an output harmonic control network.

[0005] The object of the present invention is achieved through the following technical solution: A method for designing a high-efficiency and high-power output amplifier chip, comprising the following steps:

[0006] A. Gallium nitride high electron mobility transistor GaN-HEMT is used as the core power device, and the transistor is set in the middle of the chip; the input and output interfaces of the transistor are connected to the external interface of the chip through microstrip lines to form a signal path; an input matching network, an output matching network and two bias voltage input modules are arranged on the chip, the input matching network and the output matching network are connected to a bias voltage input module respectively, and the input matching network and the output matching network are connected to the input end and the output end of the transistor respectively; the areas on both sides of the signal path and between the two bias voltage input modules are heat dissipation areas;

[0007] B. Microstrip line size adjustment: The output voltage v out (t) and current i out (t) is expressed in the form of Fourier series:

[0008]

[0009] Where V DC ,I DC are the DC voltage and current components respectively, V1 and I1 are the amplitudes of the fundamental components, ω is the angular frequency, V n and I n are the amplitudes of the nth harmonic voltage and current components, φ n and θ n is the phase of the nth harmonic voltage component and current component; the fundamental power P base and harmonic power P harmonic They are:

[0010]

[0011] The design goal is to make the harmonic power P harmonic =0, the harmonic energy is short-circuited or open-circuited by adjusting the microstrip line and output matching network;

[0012] C. Load-pull optimization: Connect an output matching network with adjustable impedance to the output of the amplifier to simulate different load conditions;

[0013] The transmission power gain of the amplifier is defined as:

[0014]

[0015] P in is the redefined total input power, V in is the signal voltage at the input end, R in is the real part of the input impedance;

[0016] Use power added efficiency PAE to reflect energy conversion efficiency:

[0017]

[0018] P DC The DC power is defined as:

[0019] P DC =V DC ×I DC

[0020] V DC is the DC voltage of the power supply, I DC is the DC current supplied by the power supply;

[0021] The performance of the antenna amplifier is measured using the two parameters of transmission power gain and power added efficiency (PAE). By adjusting the impedance of the load, the transmission power gain and power added efficiency (PAE) of the amplifier under different loads are detected to find the optimal impedance.

[0022] D. Physical space structure optimization and key harmonic suppression structure; by optimizing the length and impedance of the transmission line, the following control is achieved at the key harmonic frequency: f0 is the fundamental frequency, the second harmonic 2f0 is reflected at the output end by designing a half-wavelength transmission line λ / 2 open circuit; the third harmonic 3f0 is absorbed at the output end by designing a quarter-wavelength transmission line λ / 4 short circuit;

[0023] E. Signal path, via connection and connection method design:

[0024] E1. Keep the length of the input and output signal pins of the amplifier within 1mm;

[0025] E2. The mathematical relationship of parasitic inductance is:

[0026]

[0027] Among them, L pkgis the parasitic inductance, μ is the magnetic permeability of the pin material, l is the signal path length, and A is the effective cross-sectional area ratio of the signal path; shorten the signal path length and increase the effective cross-sectional area ratio by increasing the thickness of the material to control the parasitic inductance below 0.2nH;

[0028] E3, microstrip lines and transistors are printed on the PCB board. Inside the PCB board, the microstrip line and transistor are connected by a metal film directly connected to the PCB.

[0029] E4. Arrange 9 evenly distributed vias in the heat dissipation area of ​​the amplifier. The via shape is designed as an inverted cone structure. The via diameter on the surface of the PCB is 0.8mm, and the via diameter on the ground layer of the PCB is 0.4mm.

[0030] E5. In the PCB ground plane design, local slots and signal loop structures are introduced. The slotted area is located at the edge of the ground plane or close to the signal path, and the loop is designed in the area around the transistor.

[0031] F. Thermal performance optimization; use an external heat sink or air cooling method; the heat sink is fixed directly above the surface of the transistor with a heat dissipation gel, and the heat sink consists of multiple fins; for air cooling design, the air flow rate is increased by setting a fan outside the chip.

[0032] The beneficial effects of the present invention are as follows: the present invention adopts gallium nitride (GaN) high electron mobility transistor (HEMT) as the core amplifier device, combines the inverse F-class amplifier topology, optimizes the input impedance matching network and the output harmonic control network, and successfully achieves high efficiency and high power output under the working conditions of 5.8GHz center frequency bandwidth 800MHz. The experimental data of the final design show that the theoretical efficiency of the amplifier is 90.7% when controlling the third harmonic, and the power added efficiency (PAE) is 71.1% in the simulation of the ideal circuit model. In the final electromagnetic simulation stage, the parasitic effects, transmission losses and non-ideal characteristics of the actual circuit are taken into account, and the power added efficiency is 67.2%, the output power is 48.4dBm, i.e. 69.18W, and the gain is 11.6dB. After detailed COMSOL simulation analysis, the heat dissipation system adopts a combination of air cooling and heat conduction to control the operating temperature of the amplifier chip below 70°C. After debugging, the amplifier chip is basically consistent with the design target and design performance. The invention proposes a high-efficiency output amplifier which meets the requirements of high efficiency, high output power, high operating frequency and good thermal stability, and is suitable for microwave radar transmitters and other high-power and high-frequency electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1The schematic diagram of the DCIV test circuit for the DC bias characteristics of the GaN HEMT chip;

[0034] Figure 2 This is the test result of the relationship between DCIV current and voltage;

[0035] Figure 3 Select the trade-off points of the ideal component simulation circuit for the load pull of the CGHV59070 transistor;

[0036] Figure 4 Gain, gain compression and power added efficiency of the CGHV59070 transistor;

[0037] Figure 5 Enter the matching schematic for the ideal components;

[0038] Figure 6 Test circuit for ideal component harmonic control;

[0039] Figure 7 To show the performance results of harmonic control circuit;

[0040] Figure 8 For real capacitor parameters and EDA library;

[0041] Fig. 9 Design circuits for real components;

[0042] Fig.10 It is a display of the performance results of real components and circuits;

[0043] Fig.11 Initial design of microstrip line layout for electromagnetic simulation;

[0044] Fig.12 To display the performance results of electromagnetic simulation circuits;

[0045] Fig.13 Optimize the layout design of microstrip lines for electromagnetic simulation;

[0046] Fig.14 To display the performance results of electromagnetic simulation circuits;

[0047] Fig.15 Lay out initial designs for electromagnetic simulation layouts;

[0048] Fig.16 Optimize design for electromagnetic simulation layout;

[0049] Fig.17 For version Figure 3 D effect display diagram;

[0050] Fig.18 This is the thermal analysis result of a conventional heat sink;

[0051] Fig.19 To improve the heat sink thermal analysis results;

[0052] Fig. 20 Thermal analysis results for air cooling with heat sink. DETAILED DESCRIPTION

[0053] After a comprehensive comparison with previous studies, the present invention adopts a control circuit design that suppresses the third harmonic to achieve a breakthrough in efficiency performance. Theoretical calculations show that the effect of fifth and third harmonic suppression on efficiency is only 94.8%-90.7%=3.9%, which is not the most important parameter affecting efficiency. The present invention controls harmonics at a higher frequency, that is, at an operating frequency of 5.8GHz commonly used in microwave radars, which can ensure sufficient gain and output power while improving efficiency as much as possible. The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0054] A method for designing a high-efficiency and high-power output amplifier chip comprises the following steps:

[0055] A. The output amplifier uses an inverse class F amplifier and uses a gallium nitride high electron mobility transistor GaN-HEMT as the core power device. The transistor is set in the middle of the chip; the input and output interfaces of the transistor are connected to the external interface of the chip through microstrip lines to form a signal path; an input matching network, an output matching network and two bias voltage input modules are also provided on the chip. The input matching network and the output matching network are respectively connected to a bias voltage input module, and the input matching network and the output matching network are respectively connected to the input and output ends of the transistor. The overall structure of the chip is as follows Fig.16 As shown in the figure, 1, 6, 7, and 8 are microstrip lines, forming a signal input and output path, and the transistor is located between 6 and 7; 2 and 3 are bias voltage input modules, which provide voltages for the input matching network and the output matching network respectively; 4 is the output matching network (the input matching network is the same structure as 4 between 2 and 6, and is not numbered in the figure). The output matching network uses an output matching network that includes harmonic suppression. The areas on both sides of the signal path and between the two bias voltage input modules are heat dissipation areas, as shown in 8, 9, 10, 11, and 12 in the figure.

[0056] B. Microstrip line size adjustment: The inverse F amplifier is a high-efficiency power amplifier that combines the advantages of Class F and Class E amplifiers and achieves high efficiency and high power output by optimizing the harmonic load network. Its core principle is to use harmonic regulation and load network design to control the impedance characteristics of the fundamental and harmonics to reduce power loss and improve efficiency. The inverse F amplifier usually works in switching mode, effectively reducing switching losses through "zero voltage turn-on" (ZVS) and "zero current turn-off" (ZCS) technology, while optimizing the output voltage and current waveforms to reduce distortion. Compared with other amplifiers, the inverse F amplifier has significant advantages in harmonic management, efficiency improvement and design flexibility. It is widely used in wireless communications, radar systems and high-frequency equipment, and is an important development direction of modern high-performance power amplification technology. Compared with traditional amplifiers, the transistors in the class A amplifier always work in the amplification area, maintaining a certain static current regardless of whether there is an input signal. Although this mode has good linearity, it leads to a large amount of static power consumption, and still consumes significant energy even when the input signal is zero. In theory, the maximum efficiency of the class A amplifier is only 50% (for sinusoidal signals), but in reality, due to circuit losses, it is usually much lower than this value. Class B amplifiers reduce static power consumption by allowing transistors to alternately conduct during the positive and negative half-cycles of the input signal. However, this alternating conduction introduces "crossover distortion" near the zero point of the signal, which requires additional circuit design to compensate. Although the theoretical maximum efficiency of the Class B amplifier can reach 78.5% (for sinusoidal signals), in actual applications, its efficiency is still lower than the theoretical value due to conduction losses and the influence of crossover distortion compensation circuits. Ideally, the inverse F amplifier achieves complete separation of the voltage and current waveforms through harmonic regulation of the load network, thereby avoiding power loss. In this case, the drain efficiency can reach a theoretical 100%. Specifically, the fundamental signal meets the maximum power transfer conditions, the odd harmonics are designed to be short-circuited to eliminate their effects, and the even harmonics are designed to be open-circuited to prevent energy loss. Through this harmonic management, the inverse F amplifier is able to fully convert the output energy into effective power without switching losses caused by waveform overlap. The output voltage v of the inverse F amplifier is out (t) and current i out (t) is expressed in the form of Fourier series:

[0057]

[0058] Where V DC ,I DC are the DC voltage and current components respectively, V1 and I1 are the amplitudes of the fundamental components, ω is the angular frequency, V n and I n are the amplitudes of the nth harmonic voltage and current components, φ n and θ nis the phase of the nth harmonic voltage component and current component; the fundamental power P base and harmonic power P harmonic They are:

[0059]

[0060] The design goal of the present invention is to make the harmonic power P harmonic =0, that is, the harmonic energy is short-circuited or open-circuited by adjusting the microstrip line and the output matching network.

[0061] The power of odd and harmonic waves is controlled by the output matching network. When the impedance of the output matching network is short-circuited, there is:

[0062]

[0063] The power of even harmonics is controlled by opening the load network, and the impedance is open circuit:

[0064]

[0065] P harmonic-odd =0 and P harmonic-even =0 target, adjust the microstrip line size according to the signal wavelength to achieve open circuit and short circuit effects.

[0066] C. Load Pull Optimization: Connect an adjustable load to the output of the amplifier, usually including an output matching network with adjustable impedance, to simulate different load conditions. ADS (Advanced Design System) is a professional circuit design and simulation software developed by Keysight Technologies. It is widely used in the design and analysis of radio frequency (RF), microwave (MW), signal integrity (SI), power integrity (PI) and high-speed digital circuits. Its main purpose is to analyze and optimize the amplifier's gain, efficiency, linearity, power output and other performance parameters by applying different load conditions at the output of the amplifier. A good load design can optimize output power, improve efficiency, improve bandwidth and improve gain performance. ADS provides some traditional circuit analysis methods, but the default gain formula in its template is based on the transmission power gain (Transducer Power Gain), which mainly measures the relationship between output power and load impedance. This method does not fully consider the actual amplification performance of the input and output, and does not fully match the amplifier performance analysis target (such as total gain). Transmission power gain is defined as:

[0067]

[0068] P load is the power actually transmitted to the load, P availableis the available power of the input signal source, then:

[0069]

[0070] V load is the voltage across the load, R load is the real part of the load impedance.

[0071] In the present invention, the transmission power gain of the amplifier is defined as:

[0072]

[0073] P in is the redefined total input power, V in is the signal voltage at the input end, R in is the real part of the input impedance; using the above power gain calculation method, the input power is directly related to the actual signal voltage and impedance at the input end, which is independent of the signal source and emphasizes the matching design of the amplifier front end.

[0074] Power gain can only indicate how much the output power is greater than the input power, and cannot effectively and correctly reflect the important indicator of energy conversion efficiency when designing an amplifier. Therefore, in the present invention, the power added efficiency PAE is added to reflect the energy conversion efficiency:

[0075]

[0076] P DC The DC power is defined as:

[0077] P DC =V DC ×I DC

[0078] V DC is the DC voltage of the power supply, I DC The DC current for the power supply.

[0079] The size of the load directly affects the power output of the amplifier. When the load changes, the operating point of the amplifier may shift and the efficiency will decrease. The present invention uses two parameters, transmission power gain and power added efficiency PAE, to measure the performance of the antenna amplifier; through the above formula and certain modifications, greater flexibility is provided in terms of gain and efficiency optimization. Load pulling is to find the most suitable load match. By adjusting the impedance of the load, the transmission power gain and power added efficiency PAE of the amplifier under different loads are detected, and the optimal impedance is found to ensure that the amplifier design can achieve the best output power and efficiency. By modifying the measurement calculation formula, the input power is independent of the signal source, which can better reflect the effect of input matching and facilitate design.

[0080] D. Physical space structure optimization and key harmonic suppression structure;

[0081] By optimizing the length and impedance of the RF transmission line, the following control is achieved at the key harmonic frequency: f0 is the fundamental frequency, and the second harmonic 2f0 is reflected at the output end by designing a half-wavelength transmission line λ / 2 open circuit; the third harmonic 3f0 is absorbed at the output end by designing a quarter-wavelength transmission line λ / 4 short circuit; this design strengthens the fundamental frequency of the amplifier output signal and suppresses the harmonic power, thereby improving the power added efficiency, where:

[0082]

[0083] c is the speed of light, ∈ r is the effective dielectric constant of the microstrip line.

[0084] The empirical value of the impedance of the rectangular microstrip line obtained through experiments and simulations shows that its constant ratio is related to the characteristic impedance of air. The characteristic impedance in air is 377Ω and is finally normalized to 87 according to convention. The empirical formula for calculating the characteristic impedance is as follows:

[0085]

[0086] The characteristic impedance of each microstrip line is ensured to be 50Ω by adjusting the microstrip line width w and the dielectric thickness h;

[0087] The actual electrical length θ of the microstrip line is:

[0088]

[0089] λ eff To take into account the actual effective wavelength of parasitic effects and transmission line dielectric characteristics, l is the physical length of the microstrip line. Through optimization, at the second harmonic frequency, the simulation results show that the harmonic power at the load end is reduced by 95%. The suppression rate of the third harmonic power reaches 92%, making the output signal purer.

[0090] E. Signal path, via connection and connection method design: A series of optimized structures for key signal paths, via connections and special connection methods have been designed.

[0091] E1. By Fig.17 The length of the input and output signal pins (external connection terminals of positions 1 and 5) shown is precisely controlled within 1mm;

[0092] E2. At the same time, the key signal path is designed to be the shortest path to reduce the pin parasitic inductance to a negligible level; the mathematical relationship of parasitic inductance is:

[0093]

[0094] Among them, L pkg is the parasitic inductance, μ is the magnetic permeability of the pin material, l is the signal path length, and A is the effective cross-sectional area ratio of the signal path; by Fig.17 The length of the signal path (positions 6 and 7) shown is shortened, and the effective cross-sectional area ratio is increased by increasing the thickness of the material, so that the parasitic inductance is controlled below 0.2nH;

[0095] E3, microstrip lines and transistors are all printed on PCB boards. PCB printed circuit boards are used to support and connect electronic components in electronic devices. PCBs are usually made of insulating materials (such as glass fiber, plastic, etc.) and conductive materials (such as copper). Conductive materials are designed into shapes such as lines and pads to connect various electronic components to achieve the transmission of electrical signals. In the PCB board, the microstrip line and transistor are connected directly to the PCB using a metal film. Metal film usually refers to a conductive layer formed by copper plating or other conductive materials. Through the metal film, the signal is transmitted to various modules or components on the printed circuit board.

[0096] E4. Nine evenly distributed vias are arranged in the heat dissipation area of ​​the amplifier (areas 8, 9, 10, 11, and 12 marked in 16 in the figure). The via shape is designed as an inverted cone structure. The via diameter on the surface of the PCB is 0.8mm, and the via diameter on the ground layer of the PCB is 0.4mm. The larger diameter at the top provides a larger contact area, which can quickly transfer heat from the power device or the surface of the PCB to the inside or the ground layer. The smaller diameter at the bottom reduces thermal resistance and improves heat conduction efficiency.

[0097] E5. In the optimization of signal transmission path, a wide and short microstrip line design is adopted. The width of the signal path is 2mm and the length is controlled within 10mm. The ground layer is used as the ground layer of the PCB, covering the entire area of ​​the PCB. In the ground layer design, local slots and signal ring loop structures are introduced. The slotted area is located at the edge or close to the signal path (the edge of the area 8, 9, 10, 11, and 12 marked in Figure 16 is adjacent to the signal path). The ring loop design is formed by copper foil routing of a specific shape in the area around the transistor (positions 6 to 7 marked in Figure 16) to improve the uniformity of the signal and reduce the influence of parasitic current.

[0098] F. Thermal performance optimization; high-power amplifiers generate a lot of heat when working, and the increase in temperature will have the following effects on chip performance: decreased mobility: the electron mobility of semiconductor materials (such as GaN) decreases with increasing temperature, resulting in decreased device efficiency; reduced power added efficiency (PAE): increased temperature will lead to increased dissipated power, thereby reducing the PAE of the amplifier; gain attenuation: the gain characteristics of the device may weaken at high temperatures, affecting the signal amplification capability.

[0099] Optimizing thermal performance can effectively reduce the operating temperature of the chip, allowing it to operate within the designed temperature range, thereby maintaining stable performance. Thermal resistance is used to measure the heat dissipation efficiency of electronic devices and is a core parameter of heat dissipation design. The formula is:

[0100] R θ =R θJC +R θCS +R θSA

[0101] R θJC R is the thermal resistance from the junction to the case of the transistor, which represents the thermal conduction resistance from the internal heat source of the transistor to the outer shell; θCS is the thermal resistance from shell to heat sink, representing the contact thermal resistance between the shell and the heat sink; R θSA The thermal resistance from the heat sink to the air describes the heat transfer resistance between the heat sink and the ambient air. The lower the thermal resistance, the better the heat dissipation performance of the device and the lower the core temperature. According to the thermal resistance formula, the junction temperature of the device is calculated as:

[0102] T J =T A +R θ ·P

[0103] T J is the junction temperature, i.e. the highest temperature inside the device; T A is the ambient temperature; P is the dissipated power; according to the core transistor and other electronic components materials and production processes, additional heat dissipation function must be designed to safely and stably ensure the normal operation of the amplifier chip; an external heat sink or air cooling method is used; the thermal conductivity formula is used to describe the efficiency of heat transfer through solid materials, the formula is:

[0104]

[0105] R th is the equivalent thermal resistance, L is the material thickness, K is the thermal conductivity, which reflects the thermal conductivity of the material; A is the contact surface area. The radiator dissipates heat through convection and radiation between the surface and the air. The convection heat conduction formula is:

[0106] Q=h·A·ΔT

[0107] Q is the heat transfer power; h is the convective heat transfer coefficient, which is related to the air flow rate and the heat sink design; A is the effective heat dissipation surface area of ​​the heat sink; ΔT is the temperature difference between the heat sink surface and the air; when improving the heat dissipation design, by increasing the number of heat sink fins, measuring the operating temperature, and selecting the appropriate number of fins according to the transistor operating temperature conditions and application environment. The heat sink is fixed directly above the transistor surface by a heat dissipation gel, and the heat sink consists of multiple fins. Increasing the number of fins increases the effective heat dissipation surface area A of the heat sink, thereby increasing the heat transfer power Q; for air-cooled design, by setting a fan outside the chip to increase the air flow rate, the heat dissipation is further enhanced. To achieve the best air-cooling effect, the fan direction needs to be installed horizontally with the chip, and the front, back, left, and right positions have no effect on the results. When used with a heat sink, it needs to be kept horizontal with the fins. The relationship between the convective heat transfer coefficient h and the wind speed v is:

[0108] h∝v 0.8

[0109] Increasing wind speed can effectively improve the convective heat transfer coefficient and further enhance heat dissipation. According to the above convective heat transfer formula and the actual application scenario ambient temperature and usage requirements, different wind speeds can be used for heat dissipation. Through calculation, a balance can be found between performance and economy, and the design can be based on actual needs.

[0110] Input impedance matching network: In a power amplifier, the input impedance matching network adjusts the reactance and resistance components of the network to match the input impedance of the amplifier with the source impedance, thereby reducing reflection loss and improving power transmission efficiency. The S11 parameter in the S parameter (scattering parameter) is used to measure the matching degree of the amplifier input; the S11 parameter represents the reflection coefficient, and the smaller its value, the better the matching effect. The total S11 is designed to be -40dB.

[0111] The specific electronic component models of the amplifier chip are:

[0112] (1) The core transistor is the CGHV59070F-GaN-HEMT series produced by Wolfspeed, a Cree subsidiary.

[0113] (2) The type of microstrip line material is: RO4350B high-frequency laminate produced by Rogers.

[0114] (3) Types of capacitor and inductor materials: Although Murata ceramic capacitors (SMD) GRM155C7H104JE19, GRM1555C1H101GA01, and GRM1555C1H470GA01 were used in the design process, this was only for research and analysis and had nothing to do with the final invention design structure. The final simulation circuit and design product were both microstrip line circuits.

[0115] A. Ideal component circuit design:

[0116] (1) DCIV-Bias test and characteristic analysis

[0117] The bias voltage of the inverse F amplifier is similar to that of the single transistor class B amplifier. It is worth noting that in theory, the bias current of the class B amplifier is controlled to be close to zero at the quiescent operating point. In actual operation, it is difficult to achieve this precisely at the correct quiescent operating point, so DCIV FET curve testing is required to determine the appropriate bias voltage. Based on the electrical characteristics of the transistor, a Figure 1 The test circuit shown in Figure 1 was used and a parameter sweep simulation was performed near the characteristic voltage. The results are shown in Figure 1. Figure 2 According to the relationship between the current Ids and the bias voltage, Vgs = -3.0 V and Vds = 28 V can be determined as the voltages with the best performance.

[0118] (2) Load Pull and Result Analysis: Load Pull is the process of optimizing power output and efficiency by adjusting load impedance. Figure 3 The paper shows the selection of trade-off points for the ideal component simulation circuit of the transistor load pull. In the experiment, the load impedance is gradually adjusted and the changing trends of power and efficiency are recorded. Figure 3 The multiple colored curves in the figure represent the performance data under different load impedance conditions. The black dot marks the optimal load point, at which the PAE reaches the highest value of about 70% and the output power reaches 48dBm. The optimization goal is to select the best trade-off point between PAE and output power to achieve comprehensive optimization of the power amplifier performance. The test results are shown in Figure 2. Figure 4 As shown in the figure, the curves of gain, gain compression and power added efficiency are plotted, and the best compromise point between power and efficiency is finally selected. The horizontal axis of the left figure (gain and compression) is the output power (unit: dBm), and the vertical axis is the power gain (unit: dB). The red area of ​​the gain curve indicates the stage of gradual gain compression, and the gain drops significantly at high power output. The blue curve shows the degree of gain compression, and the best operating point is located in the area of ​​slight gain compression (about 0.5 to 1dB compression). The right figure (power added efficiency and power): The red curve shows the trend of power added efficiency changing with output power, and PAE reaches a peak of about 65%-70% at a power of 48dBm. The blue and red points correspond to the best values ​​of gain compression and power added efficiency, respectively. Through the load pull test, the point with an output power of 48dBm and a PAE of 70% was selected as the best operating point. This point takes into account the performance requirements of output power and power added efficiency. The optimal load impedance is used in actual circuit design to ensure that the power amplifier operates in the best state.

[0119] (3) Input matching circuit design

[0120] Ensure that the characteristic impedance of the input end is close to 50 ohms to achieve the maximum power transmission efficiency of the input signal. Specially designed for the power amplifier operating frequency of 5.8GHz, reduce the reflection coefficient and optimize the S parameters. The initial structure of the input matching circuit uses a simple microstrip line design, the goal is to achieve the best matching between the input end and the power amplifier transistor through impedance transformation. By adjusting the width (designed to 1073 microns) and length (designed to 5.7 mm) of the microstrip line, ensure that the impedance transformation at the input end meets the input impedance requirements of the transistor. The matching network adopts a single-stage transformation method to avoid additional losses that may be caused by a multi-stage structure. Adding an appropriate amount of passive components (capacitors) to the microstrip line to compensate for the inductance effect in the high-frequency range, this design improves the frequency response and improves the matching performance of the input end. Figure 5 Shows the test circuit used in the design.

[0121] (4) Harmonic control circuit design and result analysis

[0122] The harmonic control circuit is used to suppress high-order harmonics to improve the linear performance of the amplifier. Figure 6 The harmonic balance test circuit shown in the figure can be used to control the harmonics ideally (lossless and unlimited harmonic control) by using the program switch. Figure 7 The test results of the performance of the harmonic control circuit are shown. The curve shows that when the input power is 37.5dBm, the output power reaches 48.835dBm (marked m20), indicating that the circuit has a high-efficiency power transmission capability. When the input power is 37.5dBm, the PAE reaches 71.139% (marked m22), which is the highest value in the test, verifying the high-efficiency performance of the harmonic control network. The gain curve is 11.335dB (marked m21) when the input power is 37.5dBm, and the gain remains stable, indicating that the designed input matching and harmonic suppression network work stably. The test shows that the harmonic components in the circuit are low, especially the second and third harmonics are effectively suppressed to below 0.7 (marked m23), further improving the linear performance.

[0123] B. Non-ideal (real) component circuit design

[0124] (1) Circuit design

[0125] In the initial design and simulation, the components used were from Murata, such as Figure 8 The specific parameters of the components are shown in Figure 1As shown: Capacitor GRM155C7H104JE19: 100000 pF, operating voltage 50 volts, frequency range 100 Hz to 6 GHz, temperature range -55 to 125 degrees Celsius. Capacitor GRM1555C1H101GA01: 100 pF, operating voltage 50 volts, frequency range 100 MHz to 8.5 GHz. Capacitor GRM1555C1H470GA01: 47 pF, operating voltage 50 volts, frequency range 100 MHz to 8.5 GHz. After initially establishing the real component simulation circuit, all discrete components are replaced with microstrip lines. The microstrip line material is RO4350B produced by Rogers. According to its performance parameters and reasonable production size specifications, the design is as follows. Fig. 9 The simulation test circuit is shown in Figure 1. Microstrip lines and capacitors are used to match the input impedance to optimize signal transmission efficiency. A multi-stage matching network is designed to optimize the load impedance to improve output power and efficiency. A network structure combining passive capacitors and microstrip lines is used to suppress high-order harmonics. The harmonic balance module is used to simulate the entire circuit and record parameters such as output power, gain, and power added efficiency (PAE).

[0126] (2) Results Analysis

[0127] Fig.10 The relationship curve between power and output power is shown. When the input power is 36.3dBm, the output power reaches 48.491dBm (marked m9), indicating that the real component circuit has high power output capability. PAE reaches 70.469% (marked m11) at an input power of 36.3dBm, which is close to the performance of the ideal circuit, indicating that the circuit design of the real components has high energy efficiency. The gain is 12.191dB (marked m10) at an input power of 36.3dBm. The gain curve remains stable, indicating that the input and output matching networks are reasonably designed and have good gain stability. The test results show that the circuit design based on real components has excellent performance in output power, power added efficiency and gain, which is close to the performance of the ideal circuit, verifying the reliability of the design. The selected Murata components meet the requirements of circuit design, and their high-frequency characteristics and stable performance play a key role in improving harmonic suppression and linearity.

[0128] C. Electromagnetic simulation and design optimization

[0129] (1) Electromagnetic simulation microstrip line initial circuit design and result analysis

[0130] The main goal of layout design is to convert the circuit schematic into a circuit board layout that can be produced and processed. Fig.11As shown, this design is an equivalent size calculated directly according to the formula. Using RO4350B material, the transmission line width is calculated to be 1073 microns to achieve 50 ohm impedance. The transistor connection point width is 5.97 mm. The basic wave matching transmission line spacing at the input end of the initial design is small, resulting in unstable performance and high frequency sensitivity. Frequency offset may cause large fluctuations in system performance. After multiple optimizations, the initial design efficiency is only up to 65%. Fig.12 The test results after optimizing the size are shown. When the PAE is the highest, the PAE is 65.819%, the output power is 48.931dB, and the m gain is 11.431dB, which cannot meet the design requirements and is therefore abandoned.

[0131] (2) Electromagnetic simulation microstrip line optimization circuit design and results

[0132] Fig.13 The optimized microstrip line design is demonstrated. By adjusting the width and length of the microstrip line, the input and output impedances are optimally matched, thereby improving the power transmission efficiency. The structure of the microstrip line is optimized to suppress high-order harmonics, especially the second and third harmonics. By introducing harmonic short-circuit branches in the microstrip line, the harmonic power leakage is reduced and the signal linearity is improved. The structure of the microstrip line is optimized to suppress high-order harmonics, especially the second and third harmonics. By introducing harmonic short-circuit branches in the microstrip line, the harmonic power leakage is reduced and the signal linearity is improved. By increasing the spacing of the transmission lines, the impact of frequency offset on performance is reduced, and the stability of the circuit at different operating frequencies is improved. The layout of the microstrip line in the input and output networks is adjusted to ensure uniform power distribution and avoid losses or nonlinear problems caused by excessive local power concentration. During the optimization process, three-dimensional electromagnetic simulation is used to analyze the microstrip line structure to identify and reduce the impact of electromagnetic interference on circuit performance. Fig.14 The test results of the electromagnetic simulation of the optimized microstrip line circuit are shown. When the PAE is the highest, the PAE is 72.437%, the output power is 48.831dB, and the m-gain is 11.431dB. The added power efficiency is greatly improved, which is close to the design results of real components.

[0133] D.Layout overall design

[0134] (1) Initial design

[0135] Fig.15 The PCB drawn by traditional methods was shown, and the chip performance was reduced due to parasitic effects, so an optimized design was performed.

[0136] (2) Analysis and optimization design

[0137] After optimization, the final PCB production is as follows Fig.16The following optimizations are made to the initial design as shown: The length of the input pin is optimized to less than about 1mm, which significantly reduces the parasitic inductance. The shortened pin length controls the parasitic inductance below 0.2nH, achieving better matching with the impedance of the PCB transmission line. This improvement improves the efficiency of high-frequency signal transmission and reduces signal reflection and energy loss. A metal film connection method is used instead of the traditional long pin structure. The metal film connection method compresses the parasitic path length and further reduces the pin-related parasitic effects. This more stable mechanical structure performs well in high-frequency environments and effectively improves the high-frequency performance of the circuit. The number of vias is increased on the key signal path, using a 10-via array and arranging 4 parallel vias in the signal path. The uniform distribution of vias reduces local parasitic effects and avoids the problem of local current concentration in the signal path. The via diameter gradually transitions from 0.8mm at the top to 0.4mm at the bottom, using an inverted cone design. This structure increases the cross-sectional area and reduces the total parasitic resistance of the via. This design reduces the parasitic capacitance of the via to less than 0.1pF, improves high-frequency matching performance, and enhances signal integrity. The width of the signal path is designed to be 2mm, the length is compressed to less than 10mm and the characteristic impedance of the path is kept constant at 50Ω to ensure efficient signal transmission. Shortening the length of the signal path significantly reduces the parasitic resistance and parasitic inductance during transmission. Reasonable design of the width improves the current carrying capacity of the path while reducing the inductance effect. The combined design of inverted tapered vias and short pins controls the parasitic capacitance below 0.1pF. The power loss and distortion of high-frequency signals are effectively reduced. By reasonably designing the transmission lines, vias and pins, the signal path exhibits good impedance matching in the target frequency band, further improving the overall high-frequency performance. The schematic diagram of the 3D model is shown below. Fig.17 As shown, the final PCB board size is 80mm×60mm.

[0138] E. Heat dissipation analysis and design

[0139] (1) Theoretical calculation

[0140] The thermal resistance of CGHV59070F is 2.99℃ / W at the working point of 57W and 0.85℃ / W at the working point of 70W with a duty cycle of 10%; T_J is calculated to be 111.71℃ under the conditions of 29W dissipated power and 25℃ ambient temperature. This calculation shows that simple heat dissipation design may not meet the requirements. Excessive operating temperature will not only reduce chip performance but also may damage related devices. The heat transfer core thickness of the GHV59070F core is 0.004m, the core contact area is 5.97mm, and the equivalent thermal conductivity of the material is 37W / (m\cdotpK)). The thermal resistance is measured and calculated to be 1.96℃ / W. According to the performance of the transistor, the goal is to control the core temperature of the amplifier chip below 87.5℃ to ensure that the performance will not be significantly reduced due to high temperature. In addition, during the simulation, a thermal paste modeling model is introduced between the transistor and the heat sink to simulate a more real situation close to the real object.

[0141] (2) Thermal analysis simulation and optimization

[0142] like Fig.18 The thermal simulation results of a common heat-generating sheet on the market (ordinary aluminum heat sink, the same size as the PCB board) are shown. The core temperature of the chip is as high as 175 degrees Celsius, and even the temperature of the heat sink reaches 140 degrees Celsius. The heat dissipation system needs to be improved. Fig.19 The thermal simulation results of the heat sink with an optimized shape are shown. The fin design is used, with a total of 10 scales. The transistor core temperature is reduced to 83.56°C, and the heat sink temperature is maintained below 70°C. The improved model shows a significantly improved thermal management capability, which can meet the needs of stable operation. In addition, the increase in the number of heat sink fins and the increase in air flow rate achieve the best heat dissipation effect. Fig. 20 The thermal simulation results of increasing the number of heat sink fins and increasing the air flow rate (air cooling) are shown. The simulation simulates a wind speed of 3m / s (lower than the wind speed of a household fan), and the transistor core temperature is controlled below 68.5℃. The transistor surface temperature is 53.18℃, and the heat sink temperature is maintained at 32.75℃. The thermal performance is excellent.

[0143] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A method for designing a high-efficiency and high-power output amplifier chip, characterized in that: The following steps are involved: A. Gallium nitride high electron mobility transistor GaN-HEMT is used as the core power device, and the transistor is set in the middle of the chip; the input and output interfaces of the transistor are connected to the external interface of the chip through microstrip lines to form a signal path; an input matching network, an output matching network and two bias voltage input modules are arranged on the chip, the input matching network and the output matching network are connected to a bias voltage input module respectively, and the input matching network and the output matching network are connected to the input end and the output end of the transistor respectively; the areas on both sides of the signal path and between the two bias voltage input modules are heat dissipation areas; B. Microstrip line size adjustment: The output voltage v out (t) and current i out (t) is expressed in the form of Fourier series: Where V DC ,I DC are the DC voltage and current components respectively, V1 and I1 are the amplitudes of the fundamental components, ω is the angular frequency, V n and I n are the amplitudes of the nth harmonic voltage and current components, φ n and θ n is the phase of the nth harmonic voltage component and current component; the fundamental power P base and harmonic power P harmonic They are: The design goal is to make the harmonic power P harmonic =0, the harmonic energy is short-circuited or open-circuited by adjusting the microstrip line and output matching network; C. Load-pull optimization: Connect an output matching network with adjustable impedance to the output of the amplifier to simulate different load conditions; The transmission power gain of the amplifier is defined as: P in is the redefined total input power, V in is the signal voltage at the input end, R in is the real part of the input impedance; Use power added efficiency PAE to reflect energy conversion efficiency: P DC The DC power is defined as: P DC =V DC ×I DC V DC is the DC voltage of the power supply, I DC is the DC current supplied by the power supply; The performance of the antenna amplifier is measured using the two parameters of transmission power gain and power added efficiency (PAE). By adjusting the impedance of the load, the transmission power gain and power added efficiency (PAE) of the amplifier under different loads are detected to find the optimal impedance. D. Physical space structure optimization and key harmonic suppression structure; by optimizing the length and impedance of the transmission line, the following control is achieved at the key harmonic frequency: f0 is the fundamental frequency, the second harmonic 2f0 is reflected at the output end by designing a half-wavelength transmission line λ / 2 open circuit; the third harmonic 3f0 is absorbed at the output end by designing a quarter-wavelength transmission line λ / 4 short circuit; E. Signal path, via connection and connection method design: E1. Keep the length of the input and output signal pins of the amplifier within 1mm; E2. The mathematical relationship of parasitic inductance is: Among them, L pkg is the parasitic inductance, μ is the magnetic permeability of the pin material, l is the signal path length, and A is the effective cross-sectional area ratio of the signal path; shorten the signal path length and increase the effective cross-sectional area ratio by increasing the thickness of the material to control the parasitic inductance below 0.2nH; E3, microstrip lines and transistors are printed on the PCB board. Inside the PCB board, the microstrip line and transistor are connected by a metal film directly connected to the PCB. E4. Arrange 9 evenly distributed vias in the heat dissipation area of ​​the amplifier. The via shape is designed as an inverted cone structure. The via diameter on the surface of the PCB is 0.8mm, and the via diameter on the ground layer of the PCB is 0.4mm. E5. In the PCB ground plane design, local slots and signal loop structures are introduced. The slotted area is located at the edge of the ground plane or close to the signal path, and the loop is designed in the area around the transistor. F. Thermal performance optimization; use an external heat sink or air cooling method; the heat sink is fixed directly above the surface of the transistor with a heat dissipation gel, and the heat sink consists of multiple fins; for air cooling design, the air flow rate is increased by setting a fan outside the chip.

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