Ultrasonic waveform generation device and generation method

Abstract

The invention provides an ultrasonic waveform generation device and method, and the device comprises a first frequency control word generation circuit which is used for generating a linear frequency modulation frequency control word; a second frequency control word generation circuit for generating a frequency keying frequency control word; the first end of the waveform selection switch circuit is connected with the first frequency control word generation circuit, the second end of the waveform selection switch circuit is connected with the second frequency control word generation circuit, and the third end of the waveform selection switch circuit is used for receiving single-tone frequency control words; the waveform selection switch circuit is used for selecting one of a linear frequency modulation frequency control word, a frequency keying frequency control word and a single-tone frequency control word for output; the phase accumulator circuit is connected with the output end of the waveform selection switch circuit; and the phase amplitude conversion circuit is connected with the output end of the phase accumulator circuit and is used for calculating a corresponding sine wave amplitude value according to the phase code and generating a corresponding ultrasonic waveform.

Description

Technical Field

[0001] The present disclosure relates to the field of ultrasonic technology, and in particular to an ultrasonic waveform generating device and a generating method. Background Art

[0002] At present, the existing waveform generation device mainly generates a single-tone signal, which has only one frequency component and is inferior to a frequency modulation signal or a broadband signal in terms of distance resolution, which makes it difficult for a single-tone signal to distinguish adjacent or very close obstacles. Therefore, the signal processing capability of the ultrasonic waveform generated by the existing ultrasonic waveform generation device is poor, and the ultrasonic waveform generation device cannot support the generation of multiple ultrasonic waveforms. Summary of the invention

[0003] The present disclosure provides an ultrasonic waveform generating device and a generating method to at least solve the above technical problems existing in the prior art.

[0004] In a first aspect, an embodiment of the present disclosure provides an ultrasonic waveform generating device, the device comprising:

[0005] A first frequency control word generating circuit, used for generating a linear frequency modulation frequency control word;

[0006] A second frequency control word generating circuit, used for generating a frequency keying frequency control word;

[0007] a waveform selection switch circuit, wherein a first end of the waveform selection switch circuit is connected to the first frequency control word generation circuit, a second end of the waveform selection switch circuit is connected to the second frequency control word generation circuit, and a third end of the waveform selection switch circuit is used to receive a single-tone frequency control word; the waveform selection switch circuit is used to select one of the linear frequency modulation frequency control word, the frequency keying frequency control word and the single-tone frequency control word for output;

[0008] A phase accumulator circuit, connected to the output end of the waveform selection switch circuit, and used to generate a corresponding phase code according to the frequency control word output by the waveform selection switch circuit;

[0009] The phase amplitude conversion circuit is connected to the output end of the phase accumulator circuit and is used to calculate the corresponding sine function amplitude value according to the phase code and generate the corresponding ultrasonic waveform.

[0010] In one possible implementation manner, the first frequency control word generating circuit comprises: a frequency step calculation circuit, a frequency code accumulator circuit, a frequency upper limit comparison circuit, a frequency lower limit comparison circuit and a logic judgment circuit;

[0011] The frequency step calculation circuit is used to calculate the frequency step code according to the linear frequency modulation configuration code;

[0012] The input end of the frequency code accumulator circuit is connected to the frequency step calculation circuit, and the frequency code accumulator circuit is used to generate a linear frequency modulation frequency control word based on the frequency step code;

[0013] The output end of the frequency code accumulator circuit is connected to the first end of the waveform selection switch circuit, and the control end of the frequency code accumulator circuit is connected to the logic judgment circuit;

[0014] One end of the frequency upper limit comparison circuit is connected to the frequency code accumulator circuit, and the other end is connected to the logic judgment circuit, and the frequency upper limit comparison circuit is used to generate a first level signal based on the linear frequency modulation frequency control word;

[0015] One end of the frequency lower limit comparison circuit is connected to the frequency code accumulator circuit, and the other end is connected to the logic judgment circuit, and the frequency lower limit comparison circuit is used to generate a second level signal based on the linear frequency modulation frequency control word;

[0016] The logic judgment circuit is used to generate a switch signal for controlling the frequency code accumulator circuit based on the first level signal and the second level signal.

[0017] In one possible implementation manner, the second frequency control word generating circuit includes: a chip switching control circuit, a chip storage circuit and a frequency selection switch;

[0018] The chip switching control circuit is connected to the chip storage circuit and is used to generate a pointer signal based on the time parameter included in the frequency keying configuration code;

[0019] The chip storage circuit is connected to the frequency selection switch and is used to determine a code pattern table signal from the code pattern table based on the pointer signal;

[0020] The frequency selection switch is connected to the second end of the waveform selection switch circuit, and is used to generate the frequency keying frequency control word based on the code pattern table signal.

[0021] In one possible implementation manner, the phase-amplitude conversion circuit includes: a phase mapping circuit, a phase-amplitude table lookup conversion circuit and an interpolation calculation circuit;

[0022] One end of the phase mapping circuit is connected to the output end of the phase accumulator circuit, and the other end is connected to the phase amplitude lookup table conversion circuit, and is used to generate a corresponding mapping phase code based on the first type of phase code;

[0023] The phase amplitude table lookup conversion circuit is connected to the first end of the interpolation calculation circuit and is used to determine the corresponding sine function amplitude value from the function amplitude value table based on the mapped phase code;

[0024] The second end of the interpolation calculation circuit is connected to the output end of the phase accumulator circuit and is used to receive the second type of phase code;

[0025] The interpolation calculation circuit is used to generate a corresponding ultrasonic waveform based on the second-type phase code and the sine function amplitude value.

[0026] In one possible implementation manner, the interpolation calculation circuit includes: a delay device, a differential delay calculation circuit and a signed addition calculation circuit;

[0027] One end of the delay device is connected to the first end of the interpolation calculation circuit, and the other end is connected to the signed addition calculation circuit;

[0028] One end of the differential delay calculation circuit is connected to the first end and the second end of the interpolation calculation circuit respectively, and the other end of the differential delay calculation circuit is connected to the signed addition calculation circuit;

[0029] The signed addition calculation circuit is used to generate the ultrasonic waveform.

[0030] In one possible implementation, the differential delay calculation circuit includes: a first-order differential circuit, a second-order differential circuit, a third-order differential circuit, a first multiplication circuit, a second multiplication circuit, a third multiplication circuit, a delay circuit, a square calculation circuit, and a cubic calculation circuit;

[0031] One end of the first-order difference circuit is connected to the first end of the interpolation calculation circuit, and the other end is connected to the first multiplication circuit; one end of the delay circuit is connected to the second end of the interpolation calculation circuit, and the other end is connected to the first multiplication circuit; the first multiplication circuit is connected to the signed addition calculation circuit;

[0032] One end of the second-order difference circuit is connected to the first end of the interpolation calculation circuit, and the other end is connected to the second multiplication circuit; one end of the square calculation circuit is connected to the second end of the interpolation calculation circuit, and the other end is connected to the second multiplication circuit; the second multiplication circuit is connected to the signed addition calculation circuit;

[0033] One end of the third-order difference circuit is connected to the first end of the interpolation calculation circuit, and the other end is connected to the third multiplication circuit; one end of the cubic calculation circuit is connected to the second end of the interpolation calculation circuit, and the other end is connected to the third multiplication circuit; the third multiplication circuit is connected to the signed addition calculation circuit.

[0034] In a second aspect, an embodiment of the present disclosure provides an ultrasonic waveform generation method, which is applied to any of the above-mentioned ultrasonic waveform generation devices, and the method includes:

[0035] Obtaining linear frequency modulation configuration code, frequency keying configuration code and single tone frequency control word;

[0036] Based on the linear frequency modulation configuration code, generating a linear frequency modulation frequency control word;

[0037] Based on the frequency keying configuration code, generating a frequency keying frequency control word;

[0038] Based on a preset waveform selection code, determining a target frequency control word from the linear frequency modulation frequency control word, the frequency keying frequency control word and the single tone frequency control word;

[0039] Performing phase accumulation based on the phase increment corresponding to the target frequency control word to obtain a phase code of the sine function;

[0040] A corresponding ultrasonic waveform is generated based on the phase code.

[0041] In one possible implementation, the generating a linear frequency modulation frequency control word based on the linear frequency modulation configuration code includes:

[0042] Calculate the frequency step code according to the starting frequency, cutoff frequency and transmission duration included in the linear frequency modulation configuration code;

[0043] generating a linear frequency modulation frequency control word based on the frequency step code;

[0044] generating a first level signal and a second level signal based on the linear frequency modulation frequency control word;

[0045] Based on the first level signal and the second level signal, the process of generating the linear frequency modulation frequency control word is controlled.

[0046] In one possible implementation, the generating a frequency keying frequency control word based on the frequency keying configuration code includes:

[0047] Based on the time parameter included in the frequency keying configuration code, determining the time interval corresponding to the time parameter;

[0048] generating a chip switching trigger signal according to the time interval;

[0049] Determine a pointer signal corresponding to the chip switching trigger signal;

[0050] Determine a code pattern table signal from the code pattern table based on the pointer signal;

[0051] Based on the code pattern table signal, the frequency keying frequency control word is generated.

[0052] In one possible implementation, the generating a corresponding ultrasonic waveform based on the phase code includes:

[0053] The phase code includes a first type of phase code and a second type of phase code;

[0054] Generate a corresponding mapping phase code based on the first type phase code;

[0055] Determining a corresponding sine function amplitude value from a function amplitude value table based on the mapped phase code;

[0056] Based on the second-type phase code and the sine function amplitude value, a corresponding ultrasonic waveform is generated.

[0057] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0058] The present disclosure provides an ultrasonic waveform generating device, comprising: a first frequency control word generating circuit, used to generate a linear frequency modulation frequency control word; a second frequency control word generating circuit, used to generate a frequency keying frequency control word; a waveform selection switch circuit, wherein the first end of the waveform selection switch circuit is connected to the first frequency control word generating circuit, the second end of the waveform selection switch circuit is connected to the second frequency control word generating circuit, and the third end of the waveform selection switch circuit is used to receive a single-tone frequency control word; the waveform selection switch circuit is used to select one of the linear frequency modulation frequency control word, the frequency keying frequency control word and the single-tone frequency control word for output; a phase accumulator circuit, connected to the output end of the waveform selection switch circuit, used to generate a corresponding phase code according to the frequency control word output by the waveform selection switch circuit; a phase amplitude conversion circuit, connected to the output end of the phase accumulator circuit, used to calculate the corresponding sine function amplitude value according to the phase code, and generate a corresponding ultrasonic waveform. In this way, the generation of multiple ultrasonic waveforms can be supported, and the signal processing capability of the generated ultrasonic waveform is relatively strong.

[0059] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 1 ;

[0061] Figure 2A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 2 ;

[0062] Figure 3 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 3 ;

[0063] Figure 4 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 4 ;

[0064] Figure 5 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 5 ;

[0065] Figure 6 A schematic diagram of a processing flow of an ultrasonic waveform generation method provided in an embodiment of the present disclosure;

[0066] Figure 7 This is an application scenario diagram of an ultrasonic waveform generating device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0068] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0069] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0070] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0071] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0072] Figure 1 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 1 ;like Figure 1 As shown, an ultrasonic waveform generating device provided by an embodiment of the present disclosure includes: a first frequency control word generating circuit 1, which is used to generate a linear frequency modulation frequency control word; a second frequency control word generating circuit 2, which is used to generate a frequency keying frequency control word; a waveform selection switch circuit 3, wherein a first end of the waveform selection switch circuit 3 is connected to the first frequency control word generating circuit 1, a second end of the waveform selection switch circuit 3 is connected to the second frequency control word generating circuit 2, and a third end of the waveform selection switch circuit 3 is used to receive a single-tone frequency control word; the waveform selection switch circuit 3 is used to select one of the linear frequency modulation frequency control word, the frequency keying frequency control word and the single-tone frequency control word for output; a phase accumulator circuit 4, which is connected to the output end of the waveform selection switch circuit 3, and is used to generate a corresponding phase code according to the frequency control word output by the waveform selection switch circuit 3; a phase amplitude conversion circuit 5, which is connected to the output end of the phase accumulator circuit 4, and is used to calculate a corresponding sine function amplitude value according to the phase code and generate a corresponding ultrasonic waveform.

[0073] In some embodiments, the first frequency control word generating circuit 1 may include: a linear frequency modulation frequency control word generating circuit. The linear frequency modulation frequency control word generating circuit may be used to generate a frequency control word of a linear frequency hopping signal in real time according to a linear frequency modulation configuration code. The phase increment of the linear frequency hopping signal may change linearly over time. The generation method of the linear frequency hopping signal may include: realizing it by gradually increasing the phase increment of the accumulator. The linearly changing phase increment can make the output frequency increase or decrease linearly over time, thereby generating a linear frequency modulation signal. The second frequency control word generating circuit 2 may include a frequency keying frequency control word generating circuit. The frequency keying frequency control word generating circuit may be used to generate a frequency control word of a frequency keying signal in real time according to a frequency keying configuration code. The generation method of the frequency keying signal may include: realizing it by pre-storing two different phase increment values ​​in the frequency keying frequency control word generating circuit, and switching between them according to a specific modulation rule. For example, two frequencies f1 and f2 may be set, corresponding to two different phase increment values, respectively, and a frequency keying signal is generated by controlling the switching of these two values. The generation method of the single-tone signal may include: setting a fixed phase increment, so that the phase value output by the phase accumulator will increase linearly, and the LUT (Look-Up Table) outputs a sine wave with a constant frequency. The sine wave with a constant frequency is a single-tone signal. The waveform selection switch circuit 3 may include: a 3-to-1 switch. The waveform selection switch circuit 3 can be used to select one from the linear frequency modulation frequency control word, the frequency keying frequency control word and the single-tone frequency control word as an output according to the waveform selection code. The phase accumulator circuit 4 can be used to use the frequency control word output by the waveform selection switch circuit 3 as the accumulated step value, and the accumulated step value as the phase increment, and add it to the phase value of the previous clock cycle to generate the phase code of the current clock cycle. The phase-amplitude conversion circuit 5 can be used to calculate the corresponding sine function amplitude value and generate the corresponding ultrasonic waveform according to the phase code output by the phase accumulator circuit 4. The phase-amplitude conversion circuit 5 completes the mapping between the phase value and the amplitude value of the sine wave.

[0074] The ultrasonic waveform generating device of the disclosed embodiment can support the generation of a variety of ultrasonic waveforms. The ultrasonic waveform generating device can support three waveform modulation systems: single tone, frequency keying, and linear frequency modulation. The generated ultrasonic waveform has better signal processing capabilities. LFM (Linear Frequency Modulation) signals and FSK (Frequency-shift keying) signals can improve the detection distance of ultrasonic sensors without changing the power through more complex signal processing technologies, such as matched filtering and pulse compression. Ultrasonic waveforms can adapt to more complex environments. In complex environments, such as multiple obstacles and strong noise backgrounds, LFM signals and FSK signals can adapt to environmental changes better than single tone signals, and can provide more reliable detection results.

[0075] Figure 2 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 2 ;like Figure 2 As shown, the first frequency control word generating circuit 1 provided by the embodiment of the present disclosure includes: a frequency step calculation circuit 11, a frequency code accumulator circuit 12, a frequency upper limit comparison circuit 13, a frequency lower limit comparison circuit 14 and a logic judgment circuit 15; the frequency step calculation circuit 11 is used to calculate the frequency step code according to the linear frequency modulation configuration code; the input end of the frequency code accumulator circuit 12 is connected to the frequency step calculation circuit 11, and the frequency code accumulator circuit 12 is used to generate the linear frequency modulation frequency control word based on the frequency step code; the output end of the frequency code accumulator circuit 12 is connected to the first end of the waveform selection switch circuit 3, and the frequency code accumulator circuit 1 2 is connected to the logic judgment circuit 15; one end of the frequency upper limit comparison circuit 13 is connected to the frequency code accumulator circuit 12, and the other end is connected to the logic judgment circuit 15, the frequency upper limit comparison circuit 13 is used to generate a first level signal based on the linear frequency modulation frequency control word; one end of the frequency lower limit comparison circuit 14 is connected to the frequency code accumulator circuit 12, and the other end is connected to the logic judgment circuit 15, the frequency lower limit comparison circuit 14 is used to generate a second level signal based on the linear frequency modulation frequency control word; the logic judgment circuit 15 is used to generate a switch signal for controlling the frequency code accumulator circuit based on the first level signal and the second level signal.

[0076] In some embodiments, the linear frequency modulation configuration code may include: a digital parallel port signal of a CMOS (Complementary Metal-Oxide-Semiconductor) 1.8V level standard. The linear frequency modulation configuration code can be specifically divided into three parts: a starting frequency Fs, a cutoff frequency Fe, and a transmission duration T. The frequency control word output by the first frequency control word generation circuit 1 changes from Fs to Fe within T time. The frequency step calculation circuit 11 can be used to calculate the frequency step code according to the starting frequency Fs, the cutoff frequency Fe, and the transmission duration T. The frequency step code is calculated as follows: (Fe-Fs) / T. The frequency code accumulator circuit 12 works when the switch signal is at a high level. The switch signal stops working when the switch signal is at a low level. During operation, the frequency code accumulator circuit starts from Fs and accumulates according to the frequency step code size. The output of the frequency code accumulator circuit 12 is a linear frequency hopping frequency control word. The first level signal may include: a high level or a low level. The high level may be a logic level 1, and the low level may be a corresponding logic level 0. The second level signal may include: a high level or a low level. The high level may be a logic level 1, and the low level may be a corresponding logic level 0. The frequency upper limit comparison circuit 13 outputs a low level in response to the linear frequency modulation frequency control word output by the frequency code accumulator circuit 12 being greater than the set frequency upper limit, otherwise it outputs a high level. The frequency lower limit comparison circuit 14 outputs a low level in response to the linear frequency modulation frequency control word output by the frequency code accumulator circuit 12 being less than the set frequency lower limit, otherwise it outputs a high level. The logic judgment circuit 15 may be used to output a low level in response to the output of any one of the frequency upper limit comparison circuit 13 and the frequency lower limit comparison circuit 14 being a low level, otherwise it outputs a high level.

[0077] The ultrasonic waveform generating device of the disclosed embodiment can support the generation of a variety of ultrasonic waveforms. The ultrasonic waveform generating device can support three waveform modulation systems: single tone, frequency keying, and linear frequency modulation. The generated ultrasonic waveform has better signal processing capabilities. LFM (Linear Frequency Modulation) signals and FSK (Frequency-shift keying) signals can improve the detection distance of ultrasonic sensors without changing the power through more complex signal processing technologies, such as matched filtering and pulse compression. Ultrasonic waveforms can adapt to more complex environments. In complex environments, such as multiple obstacles and strong noise backgrounds, LFM signals and FSK signals can adapt to environmental changes better than single tone signals, and can provide more reliable detection results.

[0078] Figure 3 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 3 ;like Figure 3 As shown, the second frequency control word generating circuit 2 provided by the embodiment of the present disclosure includes: a chip switching control circuit 21, a chip storage circuit 22 and a frequency selection switch 23; the chip switching control circuit 21 is connected to the chip storage circuit 22, and is used to generate a pointer signal based on the time parameter included in the frequency keying configuration code; the chip storage circuit 22 is connected to the frequency selection switch 23, and is used to determine the code type table signal from the code type table based on the pointer signal; the frequency selection switch 23 is connected to the second end of the waveform selection switch circuit 3, and is used to generate a frequency keying frequency control word based on the code type table signal.

[0079] In some embodiments, the frequency keying configuration code may include: a digital parallel port signal of the CMOS 1.8V level standard. The frequency keying configuration code may specifically include: a chip duration Tc, a frequency point 1Fc1 and a frequency point 2Fc2. The time parameter may be a chip duration Tc. The frequency point 1Fc1 and the frequency point 2Fc2 may be input to the frequency selection switch 23. The pointer signal may include a chip switching trigger signal. The second frequency control word generation circuit 2 may specifically be composed of three submodule circuits, namely, a chip switching control circuit 21, a chip storage circuit 22 and a frequency selection switch 23. The chip switching control circuit 21 generates a chip switching trigger signal every Tc duration and sends it to the chip storage circuit 22. The chip storage circuit 22 stores a frequency keying code table, and each time a chip switching trigger signal is received from the chip switching control circuit 21, the frequency keying code table output pointer is incremented by 1. The frequency keying code table in the chip storage circuit 22 includes binary data with a byte length of 32. After receiving the code pattern table signal determined by the chip storage circuit 22, the frequency selection switch 23 selects to output Fc1 as the frequency keying frequency control word or output Fc2 as the frequency keying frequency control word according to the code pattern table.

[0080] The ultrasonic waveform generating device of the disclosed embodiment can support the generation of a variety of ultrasonic waveforms. The ultrasonic waveform generating device can support three waveform modulation systems: single tone, frequency keying, and linear frequency modulation. The generated ultrasonic waveform has better signal processing capabilities. LFM (Linear Frequency Modulation) signals and FSK (Frequency-shift keying) signals can improve the detection distance of ultrasonic sensors without changing the power through more complex signal processing technologies, such as matched filtering and pulse compression. Ultrasonic waveforms can adapt to more complex environments. In complex environments, such as multiple obstacles and strong noise backgrounds, LFM signals and FSK signals can adapt to environmental changes better than single tone signals, and can provide more reliable detection results.

[0081] Figure 4A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 4 ;like Figure 4 As shown, the phase-amplitude conversion circuit 5 provided in the embodiment of the present disclosure includes: a phase mapping circuit 51, a phase-amplitude table lookup conversion circuit 52 and an interpolation calculation circuit 53; one end of the phase mapping circuit 51 is connected to the output end of the phase accumulator circuit 4, and the other end is connected to the phase-amplitude table lookup conversion circuit 52, for generating a corresponding mapping phase code based on the first type of phase code; the phase-amplitude table lookup conversion circuit 52 is connected to the first end of the interpolation calculation circuit 53, for determining the corresponding sine function amplitude value from the function amplitude value table based on the mapping phase code; the second end of the interpolation calculation circuit 53 is connected to the output end of the phase accumulator circuit 4, for receiving the second type of phase code; the interpolation calculation circuit 53 is used to generate a corresponding ultrasonic waveform based on the second type of phase code and the sine function amplitude value.

[0082] In some embodiments, the phase code sent by the phase accumulator circuit 4 to the phase amplitude conversion circuit 5 can be divided into a first type of phase code and a second type of phase code. Among them, the first type of phase code can be a high-order code, and the second type of phase code can be a low-order code. For example, if the phase code is 2564.155, the high-order code can be 2564, and the low-order code can be the corresponding 0.155. In the phase amplitude conversion circuit 5, the phase code can be divided into a high-order code and a low-order code, the high-order code is sent to the phase mapping circuit 51, and the low-order code is sent to the interpolation calculation circuit 53. The phase mapping circuit 51 can be used to map the phase code from 0° to 360° into a phase code within the range of 0° to 90°. The phase amplitude lookup table conversion circuit 52 stores the sine function amplitude values ​​from 0° to 90°. The phase amplitude lookup table conversion circuit 52 can be used to convert the phase code output by the phase mapping circuit 51 into a sine function amplitude value. The interpolation calculation circuit 53 can be used to combine the sine function amplitude value output by the phase amplitude table conversion circuit 52 with the low-order code to generate a corresponding ultrasonic waveform through interpolation calculation.

[0083] In some embodiments, the interpolation calculation circuit 53 may include: a delay device 531, a differential delay calculation circuit and a signed addition calculation circuit 533; one end of the delay device 531 is connected to the first end of the interpolation calculation circuit 53, and the other end is connected to the signed addition calculation circuit 533; one end of the differential delay calculation circuit is respectively connected to the first end and the second end of the interpolation calculation circuit 53, and the other end of the differential delay calculation circuit is connected to the signed addition calculation circuit 533; the signed addition calculation circuit 533 is used to generate an ultrasonic waveform.

[0084] In some embodiments, the delay device 531 can be used to delay the sine function amplitude value in time to ensure that the sine function amplitude value is aligned in time before being added to other processed sine function amplitude values. The differential delay calculation circuit may include: a differential circuit, a multiplication circuit and a delay circuit. One end of the differential circuit is connected to the first end of the interpolation calculation circuit 53, and the other end is connected to the multiplication circuit; one end of the delay circuit is connected to the second end of the interpolation calculation circuit 53, and the other end is connected to the multiplication circuit; the multiplication circuit is connected to the signed addition calculation circuit 533. The signed addition calculation circuit 533 can be specifically used to: after truncating the high 16 bits of the addition result, use it as the sine function amplitude value, and generate the corresponding ultrasonic waveform amplitude.

[0085] The differential circuit can be used for differential calculation of the amplitude value of the sine function: the delay circuit can be used for time alignment of the low-order code to ensure that the low-order code matches the amplitude value of the sine function and other calculation results in time. The multiplication circuit: receives the differential calculation result from the differential circuit and the phase code from the delay circuit as input, and then performs a signed multiplication operation to obtain a multiplication result. The multiplication result is sent to the signed addition calculation circuit 533.

[0086] The ultrasonic waveform generating device of the disclosed embodiment can support the generation of a variety of ultrasonic waveforms. The ultrasonic waveform generating device can support three waveform modulation systems: single tone, frequency keying, and linear frequency modulation. The generated ultrasonic waveform has better signal processing capabilities. LFM (Linear Frequency Modulation) signals and FSK (Frequency-shift keying) signals can improve the detection distance of ultrasonic sensors without changing the power through more complex signal processing technologies, such as matched filtering and pulse compression. Ultrasonic waveforms can adapt to more complex environments. In complex environments, such as multiple obstacles and strong noise backgrounds, LFM signals and FSK signals can adapt to environmental changes better than single tone signals, and can provide more reliable detection results.

[0087] Figure 5 A schematic diagram of the structure of an ultrasonic waveform generating device provided in an embodiment of the present disclosure Figure 5 ;like Figure 5As shown, the differential delay calculation circuit provided by the embodiment of the present disclosure includes: a first-order differential circuit 5321, a second-order differential circuit 5322, a third-order differential circuit 5323, a first multiplication circuit 5324, a second multiplication circuit 5325, a third multiplication circuit 5326, a delay circuit 5327, a square calculation circuit 5328 and a cubic calculation circuit 5329; one end of the first-order differential circuit 5321 is connected to the first end of the interpolation calculation circuit 53, and the other end is connected to the first multiplication circuit 5324; one end of the delay circuit 5327 is connected to the second end of the interpolation calculation circuit 53, and the other end is connected to the first multiplication circuit 5324; the first multiplication circuit 5324 is connected to the signed addition calculation circuit 533 ; One end of the second-order differential circuit 5322 is connected to the first end of the interpolation calculation circuit 53, and the other end is connected to the second multiplication circuit 5325; one end of the square calculation circuit 5328 is connected to the second end of the interpolation calculation circuit 53, and the other end is connected to the second multiplication circuit 5325; the second multiplication circuit 5325 is connected to the signed addition calculation circuit 533; one end of the third-order differential circuit 5323 is connected to the first end of the interpolation calculation circuit 53, and the other end is connected to the third multiplication circuit 5326; one end of the cube calculation circuit 5329 is connected to the second end of the interpolation calculation circuit 53, and the other end is connected to the third multiplication circuit 5326; the third multiplication circuit 5326 is connected to the signed addition calculation circuit 533.

[0088] In some embodiments, the sine function amplitude value output by the phase amplitude lookup table conversion circuit 52 is sent to the signed addition calculation circuit 533 after time alignment by the delay device 531. The sine function amplitude value is also subjected to first-order differential calculation, second-order differential calculation and third-order differential calculation by the first-order differential circuit 5321, the second-order differential circuit 5322 and the third-order differential circuit 5323, respectively. The operation delay of the first-order differential circuit 5321, the second-order differential circuit 5322 and the third-order differential circuit 5323 is the same. The second type of phase code is subjected to time alignment processing by the delay circuit 5327 and then sent to the first multiplication circuit 5324. The second type of phase code is also subjected to square calculation and cube calculation by the square calculation circuit 5328 and the cube calculation circuit 5329, respectively, and then sent to the second multiplication circuit 5325 and the third multiplication circuit 5326, respectively. The multiplier input of the first multiplication circuit 5324 is the output of the first-order differential circuit 5321 and the delay circuit 5327. The multiplier input of the second multiplication circuit 5325 is the output of the second-order differential circuit 5322 and the square calculation circuit 5328. The multiplier input of the second multiplication circuit 5325 is the output of the third-order differential circuit 5323 and the cubic calculation circuit 5329. The input of the signed addition calculation circuit 533 is the output of the delay device 531, the first multiplication circuit 5324, the second multiplication circuit 5325 and the third multiplication circuit 5326. The signed addition calculation circuit 533 can be used to perform addition operation on each output to obtain the addition result, and after the addition result is cut off from the upper 16 bits, it is used as the amplitude value of the sine function, and the corresponding ultrasonic waveform amplitude is generated.

[0089] The ultrasonic waveform generating device of the disclosed embodiment can support the generation of a variety of ultrasonic waveforms. The ultrasonic waveform generating device can support three waveform modulation systems: single tone, frequency keying, and linear frequency modulation. The generated ultrasonic waveform has better signal processing capabilities. LFM (Linear Frequency Modulation) signals and FSK (Frequency-shift keying) signals can improve the detection distance of ultrasonic sensors without changing the power through more complex signal processing technologies, such as matched filtering and pulse compression. Ultrasonic waveforms can adapt to more complex environments. In complex environments, such as multiple obstacles and strong noise backgrounds, LFM signals and FSK signals can adapt to environmental changes better than single tone signals, and can provide more reliable detection results.

[0090] The processing flow of an ultrasonic waveform generation method provided by an embodiment of the present disclosure is described. Figure 6 , Figure 6 is a processing flow diagram of an ultrasonic waveform generation method provided by an embodiment of the present disclosure, which will be combined with Figure 6 Steps S101-S106 are shown for explanation.

[0091] Step S101, obtaining a linear frequency modulation configuration code, a frequency keying configuration code and a single tone frequency control word.

[0092] Step S102: Generate a linear frequency modulation frequency control word based on the linear frequency modulation configuration code.

[0093] Step S103: Generate a frequency keying frequency control word based on the frequency keying configuration code.

[0094] Step S104: determining a target frequency control word from the linear frequency modulation frequency control word, the frequency keying frequency control word and the single tone frequency control word based on the preset waveform selection code.

[0095] Step S105, performing phase accumulation based on the phase increment corresponding to the target frequency control word to obtain a phase code of the sine function.

[0096] Step S106: Generate a corresponding ultrasonic waveform based on the phase code.

[0097] As an example, first obtain the linear frequency modulation configuration code, the frequency keying configuration code and the single-tone frequency control word. The linear frequency modulation configuration code determines the starting frequency, ending frequency and duration of the linear frequency modulation signal, while the frequency keying configuration code defines the frequency hopping mode and duration of the frequency keying signal. The single-tone frequency control word sets a constant frequency output. Then, the linear frequency modulation frequency control word is generated according to the linear frequency modulation configuration code, and the linear frequency modulation frequency control word contains all the frequency parameters required to generate the linear frequency modulation signal. The frequency keying frequency control word is generated according to the frequency keying configuration code, and the frequency keying frequency control word contains all the frequency parameters required to generate the frequency keying signal. According to a preset waveform selection code, the target frequency control word is selected from the above three frequency control words, and the waveform selection code can be used to determine which signal waveform the finally generated ultrasonic waveform is among the linear frequency modulation signal, the frequency keying signal and the single-tone signal. Phase accumulation is performed according to the phase increment corresponding to the target frequency control word to obtain the phase code of the sine function used to generate the ultrasonic waveform. Finally, a corresponding ultrasonic waveform is generated based on the phase code of the sine function, and the ultrasonic waveform can be a signal waveform of a linear frequency modulation signal, a frequency keying signal or a single tone signal. The ultrasonic waveform corresponds to the target frequency control word.

[0098] In some embodiments, step S102 may include: calculating a frequency step code according to a starting frequency, a cutoff frequency, and a transmission duration included in the linear frequency modulation configuration code; generating a linear frequency modulation frequency control word based on the frequency step code; generating a first level signal and a second level signal based on the linear frequency modulation frequency control word; and controlling the process of generating the linear frequency modulation frequency control word based on the first level signal and the second level signal.

[0099] In some embodiments, the linear frequency modulation configuration code may include: a digital parallel port signal of the CMOS 1.8V level standard. The linear frequency modulation configuration code can be specifically divided into three parts: a starting frequency Fs, a cutoff frequency Fe, and a transmission duration T. The frequency control word changes from Fs to Fe within T time. According to the starting frequency Fs, the cutoff frequency Fe, and the transmission duration T, the frequency step code is calculated. The frequency step code is calculated as follows: (Fe-Fs) / T. A switch signal is generated based on the first level signal and the second level signal, and the process of generating a linear frequency modulation frequency control word based on the frequency step code is controlled according to the switch signal. When the switch signal is at a high level, a linear frequency modulation frequency control word is generated based on the frequency step code. When the switch signal is at a low level, the generation of the linear frequency modulation frequency control word based on the frequency step code is stopped. The first level signal may include: a high level or a low level. The high level may be a logic level 1, and the low level may be a corresponding logic level 0. The second level signal may include: a high level or a low level. The high level may be a logic level 1, and the low level may be a corresponding logic level 0. In response to the outputted linear frequency modulation frequency control word being greater than the set frequency upper limit, the outputted first level signal is a low level, otherwise the outputted first level signal is a high level. In response to the outputted linear frequency modulation frequency control word being less than the set frequency lower limit, the outputted second level signal is a low level, otherwise the outputted second level signal is a high level. In response to any one of the first level signal and the second level signal being a low level, the outputted switch signal is a low level, otherwise the outputted switch signal is a high level.

[0100] In some embodiments, step S103 may include: determining the time interval corresponding to the time parameter based on the time parameter included in the frequency keying configuration code; generating a code chip switching trigger signal according to the time interval; determining a pointer signal corresponding to the code chip switching trigger signal; determining a code pattern table signal from the code pattern table based on the pointer signal; and generating a frequency keying frequency control word based on the code pattern table signal.

[0101] In some embodiments, the frequency keying configuration code may include: a digital parallel port signal of the CMOS 1.8V level standard. The frequency keying configuration code may specifically include: a chip duration Tc, a frequency point 1Fc1 and a frequency point 2Fc2. The time parameter may be a chip duration Tc. The frequency point 1Fc1 and the frequency point 2Fc2 may be input to the frequency selection switch 23. A frequency keying frequency control word is generated based on the frequency keying configuration code. First, a time parameter, i.e., a chip duration Tc, is extracted from the frequency keying configuration code. The time parameter may determine the time interval of chip switching. For example, if Tc is set to 10 microseconds, the chip will be switched once every 10 microseconds. A chip switching trigger signal is generated according to the time interval set by Tc. The chip switching trigger signal is generated periodically according to a preset time parameter, and a new chip switching trigger signal is generated whenever a time interval of 10 microseconds is reached. A pointer signal corresponding to each chip switching trigger signal is determined. The pointer signal may be used to locate in a code pattern table. Each time a chip switching trigger signal is generated, the pointer increments to point to the next code word in the code pattern table. Based on the pointer signal, a corresponding code table signal is determined from the code table. The code table can be a predefined binary data sequence. If the code table signal indicates that the current code word corresponds to the frequency point Fc1, Fc1 is determined as the frequency keying frequency control word; if the code table signal indicates that the current code word corresponds to the frequency point Fc2, Fc2 is determined as the frequency keying frequency control word.

[0102] In some embodiments, step S106 may include: generating a corresponding mapping phase code based on the first type phase code; determining a corresponding sine function amplitude value from a function amplitude value table based on the mapping phase code; and generating a corresponding ultrasonic waveform based on the second type phase code and the sine function amplitude value.

[0103] In some embodiments, the phase code can be divided into a first type of phase code and a second type of phase code. Among them, the first type of phase code can be a high-order code, and the second type of phase code can be a low-order code. For example, the phase code is 2564.155, the high-order code can be 2564, and the low-order code can be the corresponding 0.155. The high-order code is sent to the phase mapping circuit 51, and the low-order code is sent to the interpolation calculation circuit 53. The phase mapping circuit 51 can be used to map the phase code from 0° to 360° into a phase code in the range of 0° to 90°. The phase amplitude lookup table conversion circuit 52 stores the sine function amplitude value from 0° to 90°. The phase amplitude lookup table conversion circuit 52 can be used to convert the phase code output by the phase mapping circuit 51 into a sine function amplitude value. The interpolation calculation circuit 53 can be used to combine the sine function amplitude value output by the phase amplitude lookup table conversion circuit 52 with the low-order code, and generate the corresponding ultrasonic waveform through interpolation calculation.

[0104] As an example, the input of the phase mapping circuit 51 is a high-order code, and the output is a sign code and an unsigned phase code. The working sequence of the phase mapping circuit 51 may include: the first step is to determine the quadrant represented by the high-order code, and the quadrant division method adopted by the phase mapping circuit 51 is: 0°≤high-order code<90° is the first quadrant, 90°≤high-order code<180° is the second quadrant, 180°≤high-order code<270° is the third quadrant, and 270°≤high-order code<360° is the fourth quadrant. If the high-order code input to the phase mapping circuit 51 is in the first or second quadrant, the sign code output is 1. If the high-order code input to the phase mapping circuit 51 is in the third or fourth quadrant, the sign code output is -1. If the input high-order code is in the first quadrant, the input high-order code is directly output as an unsigned phase code. If the input high-order code is in the second quadrant, the difference between 180° and the high-order code is output as an unsigned phase code. If the input high-order code is in the third quadrant, the difference of the high-order code minus 180° is output as an unsigned phase code. If the input high-order code is in the fourth quadrant, the difference of 360° minus the high-order code is output as an unsigned phase code. The phase-amplitude lookup table conversion circuit 52 can use a mask read-only memory circuit to store the amplitude value of the sine function. The phase-amplitude lookup table conversion circuit 52 directly uses the unsigned phase code output by the phase mapping circuit 51 as the address bit for the lookup table. The bit width of the amplitude value of the sine function stored in the phase-amplitude lookup table conversion circuit 52 is 16 bits.

[0105] The ultrasonic waveform generation method of the disclosed embodiment can be applied to an ultrasonic waveform generation device, and the ultrasonic waveform generation method can support the generation of a variety of ultrasonic waveforms. The ultrasonic waveform generation method can support three waveform modulation systems: single tone, frequency keying, and linear frequency modulation. The generated ultrasonic waveform has better signal processing capabilities. LFM (Linear Frequency Modulation) signals and FSK (Frequency-shift keying) signals can improve the detection distance of ultrasonic sensors without changing the power through more complex signal processing technologies, such as matched filtering and pulse compression. Ultrasonic waveforms can adapt to more complex environments. In complex environments, such as multiple obstacles, strong noise backgrounds, etc., LFM signals and FSK signals are more adaptable to environmental changes than single tone signals, and can provide more reliable detection results.

[0106] It should be noted that the description of the ultrasonic waveform generation method of the embodiment of the present disclosure is similar to the description of the above-mentioned device embodiment, and has similar beneficial effects as the device embodiment, so it will not be repeated. Figures 1 to 5 The present invention can be understood by referring to the description of any one of the accompanying drawings.

[0107] Figure 7 This is an application scenario diagram of an ultrasonic waveform generating device provided by an embodiment of the present disclosure; Figure 7 As shown, an ultrasonic waveform generating device provided by an embodiment of the present disclosure includes a linear frequency modulation frequency control word generated by a first frequency modulation frequency control word generating circuit. The linear frequency modulation frequency control word changes with time, and the linear frequency modulation configuration code input to the first frequency modulation frequency control word generating circuit is a digital parallel port signal of the CMOS1.8V level standard. The linear frequency modulation configuration code may include: a starting frequency Fs, a cutoff frequency Fe, and a transmission duration T. The linear frequency modulation frequency control word output by the first frequency modulation frequency control word generating circuit changes from Fs to Fe within T time.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0109] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An ultrasonic waveform generating device, characterized in that: The device comprises: A first frequency control word generating circuit, used for generating a linear frequency modulation frequency control word; A second frequency control word generating circuit, used for generating a frequency keying frequency control word; a waveform selection switch circuit, wherein a first end of the waveform selection switch circuit is connected to the first frequency control word generation circuit, a second end of the waveform selection switch circuit is connected to the second frequency control word generation circuit, and a third end of the waveform selection switch circuit is used to receive a single-tone frequency control word; the waveform selection switch circuit is used to select one of the linear frequency modulation frequency control word, the frequency keying frequency control word and the single-tone frequency control word for output; A phase accumulator circuit, connected to the output end of the waveform selection switch circuit, and used to generate a corresponding phase code according to the frequency control word output by the waveform selection switch circuit; The phase amplitude conversion circuit is connected to the output end of the phase accumulator circuit and is used to calculate the corresponding sine function amplitude value according to the phase code and generate the corresponding ultrasonic waveform.

2. The device according to claim 1, characterized in that The first frequency control word generating circuit comprises: a frequency step calculation circuit, a frequency code accumulator circuit, a frequency upper limit comparison circuit, a frequency lower limit comparison circuit and a logic judgment circuit; The frequency step calculation circuit is used to calculate the frequency step code according to the linear frequency modulation configuration code; The input end of the frequency code accumulator circuit is connected to the frequency step calculation circuit, and the frequency code accumulator circuit is used to generate a linear frequency modulation frequency control word based on the frequency step code; The output end of the frequency code accumulator circuit is connected to the first end of the waveform selection switch circuit, and the control end of the frequency code accumulator circuit is connected to the logic judgment circuit; One end of the frequency upper limit comparison circuit is connected to the frequency code accumulator circuit, and the other end is connected to the logic judgment circuit, and the frequency upper limit comparison circuit is used to generate a first level signal based on the linear frequency modulation frequency control word; One end of the frequency lower limit comparison circuit is connected to the frequency code accumulator circuit, and the other end is connected to the logic judgment circuit, and the frequency lower limit comparison circuit is used to generate a second level signal based on the linear frequency modulation frequency control word; The logic judgment circuit is used to generate a switch signal for controlling the frequency code accumulator circuit based on the first level signal and the second level signal.

3. The device according to claim 2, characterized in that The second frequency control word generating circuit comprises: a chip switching control circuit, a chip storage circuit and a frequency selection switch; The chip switching control circuit is connected to the chip storage circuit and is used to generate a pointer signal based on the time parameter included in the frequency keying configuration code; The chip storage circuit is connected to the frequency selection switch and is used to determine a code pattern table signal from the code pattern table based on the pointer signal; The frequency selection switch is connected to the second end of the waveform selection switch circuit, and is used to generate the frequency keying frequency control word based on the code pattern table signal.

4. The device according to claim 1, characterized in that The phase-amplitude conversion circuit comprises: a phase mapping circuit, a phase-amplitude table lookup conversion circuit and an interpolation calculation circuit; One end of the phase mapping circuit is connected to the output end of the phase accumulator circuit, and the other end is connected to the phase amplitude lookup table conversion circuit, and is used to generate a corresponding mapping phase code based on the first type of phase code; The phase amplitude table lookup conversion circuit is connected to the first end of the interpolation calculation circuit and is used to determine the corresponding sine function amplitude value from the function amplitude value table based on the mapped phase code; The second end of the interpolation calculation circuit is connected to the output end of the phase accumulator circuit and is used to receive the second type of phase code; The interpolation calculation circuit is used to generate a corresponding ultrasonic waveform based on the second-type phase code and the sine function amplitude value.

5. The device according to claim 4, characterized in that The interpolation calculation circuit includes: a delay device, a differential delay calculation circuit and a signed addition calculation circuit; One end of the delay device is connected to the first end of the interpolation calculation circuit, and the other end is connected to the signed addition calculation circuit; One end of the differential delay calculation circuit is connected to the first end and the second end of the interpolation calculation circuit respectively, and the other end of the differential delay calculation circuit is connected to the signed addition calculation circuit; The signed addition calculation circuit is used to generate the ultrasonic waveform.

6. The device according to claim 5, characterized in that The differential delay calculation circuit includes: a first-order differential circuit, a second-order differential circuit, a third-order differential circuit, a first multiplication circuit, a second multiplication circuit, a third multiplication circuit, a delay circuit, a square calculation circuit and a cubic calculation circuit; One end of the first-order difference circuit is connected to the first end of the interpolation calculation circuit, and the other end is connected to the first multiplication circuit; one end of the delay circuit is connected to the second end of the interpolation calculation circuit, and the other end is connected to the first multiplication circuit; the first multiplication circuit is connected to the signed addition calculation circuit; One end of the second-order difference circuit is connected to the first end of the interpolation calculation circuit, and the other end is connected to the second multiplication circuit; one end of the square calculation circuit is connected to the second end of the interpolation calculation circuit, and the other end is connected to the second multiplication circuit; the second multiplication circuit is connected to the signed addition calculation circuit; One end of the third-order difference circuit is connected to the first end of the interpolation calculation circuit, and the other end is connected to the third multiplication circuit; one end of the cubic calculation circuit is connected to the second end of the interpolation calculation circuit, and the other end is connected to the third multiplication circuit; the third multiplication circuit is connected to the signed addition calculation circuit.

7. An ultrasonic waveform generating method, applied to the ultrasonic waveform generating device according to any one of claims 1 to 6, characterized in that: The method comprises: Obtaining linear frequency modulation configuration code, frequency keying configuration code and single tone frequency control word; Based on the linear frequency modulation configuration code, generating a linear frequency modulation frequency control word; Based on the frequency keying configuration code, generating a frequency keying frequency control word; Based on a preset waveform selection code, determining a target frequency control word from the linear frequency modulation frequency control word, the frequency keying frequency control word and the single tone frequency control word; Performing phase accumulation based on the phase increment corresponding to the target frequency control word to obtain a phase code of the sine function; A corresponding ultrasonic waveform is generated based on the phase code.

8. The method according to claim 7, characterized in that The generating a linear frequency modulation frequency control word based on the linear frequency modulation configuration code comprises: Calculate the frequency step code according to the starting frequency, cutoff frequency and transmission duration included in the linear frequency modulation configuration code; generating a linear frequency modulation frequency control word based on the frequency step code; generating a first level signal and a second level signal based on the linear frequency modulation frequency control word; Based on the first level signal and the second level signal, the process of generating the linear frequency modulation frequency control word is controlled.

9. The method according to claim 7, characterized in that: The step of generating a frequency keying frequency control word based on the frequency keying configuration code comprises: Based on the time parameter included in the frequency keying configuration code, determining the time interval corresponding to the time parameter; generating a chip switching trigger signal according to the time interval; Determine a pointer signal corresponding to the chip switching trigger signal; Determine a code pattern table signal from the code pattern table based on the pointer signal; Based on the code pattern table signal, the frequency keying frequency control word is generated.

10. The method according to claim 7, characterized in that The generating a corresponding ultrasonic waveform based on the phase code comprises: The phase code includes a first type of phase code and a second type of phase code; Generate a corresponding mapping phase code based on the first type phase code; Determining a corresponding sine function amplitude value from a function amplitude value table based on the mapped phase code; Based on the second-type phase code and the sine function amplitude value, a corresponding ultrasonic waveform is generated.

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