Transistor stack circuit

Abstract

The invention provides a transistor stack circuit. The transistor stack circuit comprises a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors and a plurality of resistors, the transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. The first end of each resistor is coupled to the common path. The second end of each resistor is coupled with the control end of a corresponding transistor in the transistors. The impedance unit is coupled between the common path and a reference voltage terminal. When an electrostatic discharge event occurs, the impedance value of the impedance unit is greater than twice the resistance value of each resistor, and the transistors form a low impedance path.

Description

Technical Field

[0001] The present invention relates to an integrated circuit (IC), and more particularly to a transistor stacking circuit. Background Art

[0002] Among the many factors that damage integrated circuits due to electrical overstress (EOS), electrostatic discharge (ESD) may permanently damage semiconductor components within the integrated circuit, thereby affecting the function of the integrated circuit (or even causing the integrated circuit to not work properly). How to prevent ESD from damaging integrated circuits is one of the many technical issues in this field. Summary of the invention

[0003] The invention provides a transistor stacking circuit to prevent electrostatic discharge (ESD) from damaging integrated circuits.

[0004] In one embodiment of the present invention, the above-mentioned transistor stack circuit includes a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors and a plurality of first resistors. These transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. The first end of each first resistor is coupled to a common path. The second end of each first resistor is coupled to a control end of a corresponding transistor of these transistors. The impedance unit is coupled between the common path and the reference voltage end. When an ESD event occurs, the impedance value of the impedance unit is greater than twice the resistance value of each first resistor, and these transistors form a low impedance path.

[0005] In one embodiment of the present invention, the above-mentioned transistor stack circuit includes a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors and a plurality of first resistors. These transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. These transistors include a first transistor, a second transistor and a terminal transistor. The first end of the first transistor is coupled to the first signal transmission port. The second end of the first transistor is coupled to the first end of the second transistor. The second end of the terminal transistor is coupled to the second signal transmission port. Each first resistor has a first end and a second end. The first ends of these first resistors are coupled to a common path. The second end of each first resistor is coupled to the control end of a corresponding transistor in these transistors. The impedance unit is coupled between the common path and the reference voltage end. When an ESD event occurs, the voltage difference between the control end of the second transistor and the second end of the second transistor is greater than the turn on voltage of the second transistor.

[0006] Based on the above description, the impedance unit described in the embodiments of the present invention can effectively turn on each of the transistors connected in series when an ESD event occurs, thereby enabling the transistors to transmit ESD current between the first signal transmission port and the second signal transmission port. Therefore, the transistor stacking circuit can prevent ESD from damaging the integrated circuit.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 It is a schematic diagram of a circuit block of a radio frequency integrated circuit according to an embodiment of the present invention. Figure 2 A circuit diagram of a transistor stack circuit according to an embodiment is shown. Figure 3 A circuit diagram of a transistor stack circuit according to an embodiment of the present invention is shown. Figure 4 FIG. 4 is a circuit diagram of an impedance unit according to an embodiment of the present invention. Figure 5 FIG. 4 is a circuit diagram of an impedance unit according to another embodiment of the present invention. Figure 6 FIG. 4 is a circuit diagram of an impedance unit according to another embodiment of the present invention. Figure 7 FIG. 4 is a circuit diagram of an impedance unit according to another embodiment of the present invention. Figure 8 A circuit diagram of a transistor stack circuit according to another embodiment of the present invention is shown. Fig. 9 FIG. 4 is a circuit diagram showing an impedance unit and an ESD (electrostatic discharge) detection circuit according to an embodiment of the present invention. Fig.10 A circuit diagram of a transistor stack circuit according to yet another embodiment of the present invention is shown. Fig.11 A circuit diagram of a transistor stack circuit according to yet another embodiment of the present invention is shown. Fig.12 A curve diagram showing the relationship between the resistance ratio and the number of transistor stacks according to an embodiment of the present invention is shown.

Explanation of symbols

[0008] The term "coupled (or connected)" used in the entire specification of the present invention and the claims may refer to any direct or indirect means of connection. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some means of connection. The terms "first", "second", etc. mentioned in the entire specification of the present invention and the claims are used to name the names of elements (element), or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limits of the number of elements, nor to limit the order of elements. In addition, wherever possible, elements / components / steps using the same symbols in the drawings and specific embodiments represent the same or similar parts. Elements / components / steps using the same symbols or the same terms in different embodiments can refer to the relevant descriptions with each other.

[0009] Based on actual design, the transistor stack circuit described in this specification can be applied to any integrated circuit (IC). When an electrostatic discharge (ESD) event occurs, the transistor stack circuit can prevent ESD from damaging the integrated circuit. For example, the transistor stack circuit described in this specification can be applied to Figure 1 The radio frequency (RF) integrated circuit 100 or other integrated circuits are shown.

[0010] Figure 1 FIG. 1 is a schematic diagram of a circuit block of a radio frequency integrated circuit 100 according to an embodiment of the present invention. Figure 1 The RF integrated circuit 100 shown includes an RF switch series path 110, an RF switch series path 120, an RF switch shunt path 130, and an RF switch shunt path 140. For the sake of simplicity, Figure 1Other circuits / components other than the RF switch series path 110, the RF switch series path 120, the RF switch shunt path 130, and the RF switch shunt path 140 are not shown, and the other circuits / components can be arranged arbitrarily based on the actual design. The first end of the RF switch series paths 110 and 120 is coupled to the RF connection pad RFC. The RF connection pad RF2 is coupled to the second end of the RF switch series path 110 and the first end of the RF switch shunt path 130. The RF connection pad RF1 is coupled to the second end of the RF switch series path 120 and the first end of the RF switch shunt path 140. The RF connection pads RFC, RF1 and / or RF2 can be bonding pads or other types of connection pads. The second ends of the RF switch shunt paths 130 and 140 are coupled to the reference voltage terminal REF1. Based on the actual design, the reference voltage terminal REF1 can be a ground voltage terminal or other fixed voltage terminals.

[0011] Under normal operation, the RF switch series paths 110 and 120 can be used as signal transmission paths (e.g., transmitting signals or receiving signals); and the RF switch shunt paths 130 and 140 can be used as shunt networks to increase the isolation between different signal paths. The transistor stack circuit described in this specification can be applied to one or more of the RF switch series path 110, the RF switch series path 120, the RF switch shunt path 130, and the RF switch shunt path 140. When an ESD event occurs at the RF connection pads RFC, RF1, and / or RF2, the ESD current can be directed to the reference voltage terminal REF1 through the RF switch series path 110, the RF switch series path 120, the RF switch shunt path 130, and / or the RF switch shunt path 140. Therefore, the RF switch series path 110, the RF switch series path 120, the RF switch shunt path 130, and / or the RF switch shunt path 140 can prevent ESD from damaging the RF integrated circuit 100.

[0012] Several embodiments of the transistor stack circuit will be described below.

[0013] Figure 2 A circuit diagram of a transistor stack circuit 200 according to an embodiment is shown. Figure 2 The transistor stack circuit 200 shown includes a signal transmission port SP21, a signal transmission port SP22, a plurality of transistors (eg Figure 2 The transistors M2_1, M2_2, ..., M2_n-1, M2_n) and a plurality of resistors (eg Figure 2In some embodiments, the resistance value of each of the resistors R2_1 to R2_n is the same. In other embodiments, the sizes of the resistors R2_1 to R2_n may be different from each other.

[0014] Figure 2 The transistor stack circuit 200 can be applied to Figure 1 The RF switch series path 110, the RF switch series path 120, the RF switch shunt path 130 or the RF switch shunt path 140 are shown. For example, Figure 2 The transistor stack circuit 200 is applied to Figure 1 In the case of the RF switch series path 110 shown in FIG. 1 , the signal transmission ports SP21 and SP22 of the transistor stack circuit 200 serve as the first end and the second end of the RF switch series path 110, respectively. That is, the signal transmission port SP21 is coupled to the RF connection pad RFC (corresponding to Figure 2 The signal transmission port SP22 is coupled to the RF switch shunt path 130. Furthermore, the signal transmission port SP22 is also coupled to the reference voltage terminal REF1 (corresponding to Figure 2 Alternatively, in other embodiments, the signal transmission port SP21 is coupled to the RF connection pad RFC (corresponding to Figure 2 The signal transmission port SP22 can also be coupled to RF2, so that the RF switch series path 110, as one section of the circuit in the RF integrated circuit 100, is not necessarily connected to the reference voltage terminal REF1.

[0015] For example, in Figure 2 The transistor stack circuit 200 is applied to Figure 1 In the case of the RF switch shunt path 130 shown in FIG. 1 , the signal transmission ports SP21 and SP22 of the transistor stack circuit 200 serve as the first end and the second end of the RF switch shunt path 130, respectively. That is, the signal transmission port SP21 is coupled to the RF connection pad RFC (corresponding to Figure 2 The signal transmission port SP21 is coupled to the RF connection pad RF2 (corresponding to Figure 2 The signal transmission port SP22 is coupled to the reference voltage terminal REF1 (corresponding to Figure 2 The reference voltage terminal REF2).

[0016] exist Figure 2In the illustrated embodiment, transistors M2_1 to M2_n are connected in series and coupled between signal transmission ports SP21 and SP22. Transistors M2_1, M2_2, and M2_n may be referred to as a first transistor, a second transistor, and an end transistor. A first end (e.g., a drain) of transistor M2_1 is coupled to signal transmission port SP21. A second end (e.g., a source) of transistor M2_1 is coupled to a first end (e.g., a drain) of transistor M2_2. A second end of transistor M2_n is coupled to signal transmission port SP22. A first end of each of resistors R2_1 to R2_n is coupled to a common path A2. A second end of each of resistors R2_1 to R2_n is coupled to a control end (e.g., a gate) of a corresponding transistor in transistors M2_1 to M2_n. For example, a first end of resistor R2_2 is coupled to common path A2, and a second end of resistor R2_2 is coupled to a control end of transistor M2_2.

[0017] Under normal operation, the internal circuit 20 (functional circuit in the integrated circuit) can control the transistors M2_1 to M2_n through the common path A2, thereby turning on or off the path of the transistor stack circuit 200. The signal transmission port SP21 can transmit RF signals or other signals. The number n of transistors M2_1 to M2_n can be determined based on actual design. For example, the number n of transistors M2_1 to M2_n can be 4 or a larger integer. In addition, although Figure 2 The transistors M2_1 to M2_n shown are N-channel Metal-Oxide-Semiconductor (NMOS) transistors, but the present embodiment does not limit the types of transistors M2_1 to M2_n. For example, in another embodiment, transistors M2_1 to M2_n may be changed to P-channel Metal-Oxide-Semiconductor (PMOS) transistors or other types of transistors. Based on the actual design, in some embodiments, the size of each of transistors M2_1 to M2_n is the same. In other embodiments, the sizes of transistors M2_1 to M2_n may be different from each other.

[0018] When an ESD event occurs on the connection pad PAD2, the ESD voltage on the connection pad PAD2 will be coupled to the gate of the transistor M2_1 through the parasitic capacitance between the gate and the drain of the transistor M2_1, thereby turning on the transistor M2_1 (because the voltage Vgs between the gate and the source of the transistor M2_1 is greater than the threshold voltage). Then, the ESD voltage on the connection pad PAD2 will further increase the voltage of the common path A2, thereby turning on other transistors M2_2 to M2_n. Therefore, the turned-on transistors M2_1 to M2_n can transmit ESD current between the signal transmission ports SP21 and SP22, thereby preventing ESD from damaging the integrated circuit.

[0019] However, when an ESD event occurs at the connection pad PAD2, the internal circuit 20 may have a small internal resistance. In this case, the voltage of the common path A2 may be pulled down to a voltage close to the reference voltage terminal (e.g., 0 volts), thereby causing the gate voltages of other transistors M2_2 to M2_n to be pulled down to close to 0 volts, so that the transistors M2_2 to M2_n cannot be fully turned on. Therefore, when an ESD event occurs at the connection pad PAD2, the ESD protection capability provided by the transistor stack circuit 200 will be reduced, or the transistor stack circuit 200 will even lose its ESD protection capability.

[0020] Figure 3 FIG. 4 is a circuit diagram of a transistor stack circuit 300 according to an embodiment of the present invention. Figure 3 The transistor stack circuit 300 includes a signal transmission port SP31, a signal transmission port SP32, an impedance unit 310, a plurality of transistors (eg Figure 3 The transistors M3_1, M3_2, ..., M3_n-1, M3_n) and a plurality of resistors (eg Figure 3 The voltage of each of the first ends of the resistors R3_1 ˜ R3_n coupled to the common path A3 is, for example, the same as each other. Figure 3 The internal circuit 30, the common path A3, the transistor stack circuit 300, the signal transmission port SP31, the signal transmission port SP32, the resistors R3_1 to R3_n and the transistors M3_1 to M3_n can refer to Figure 2 The related descriptions of the internal circuit 20 , the common path A2 , the transistor stack circuit 200 , the signal transmission port SP21 , the signal transmission port SP22 , the resistors R2_1 ˜ R2_n and the transistors M2_1 ˜ M2_n are similar and will not be repeated here.

[0021] exist Figure 3 The transistor stack circuit 300 is shown as Figure 1In the case of the RF switch shunt path 130, the signal transmission port SP31 of the transistor stack circuit 300 is coupled to the RF connection pad RF2 and to the RF connection pad RFC through the RF switch series path 110. The signal transmission port SP32 is coupled to the reference voltage terminal REF1.

[0022] exist Figure 3 The transistor stack circuit 300 is shown as Figure 1 In the case of the RF switch series path 110, the signal transmission port SP31 of the transistor stack circuit 300 is coupled to the RF connection pad RFC, and the signal transmission port SP32 is coupled to the RF switch shunt path 130. That is, the signal transmission port SP32 is coupled to the reference voltage terminal REF1 through the RF switch shunt path 130.

[0023] When an ESD event occurs, the ESD voltage of the signal transmission port SP31 is coupled to the gate of the transistor M3_1 through the parasitic capacitance between the gate and drain of the transistor M3_1, thereby turning on the transistor M3_1 (because the voltage Vgs between the gate and source of the transistor M3_1 is greater than the threshold voltage). Figure 2 The transistor stack circuit 200 shown includes: Figure 3 The transistor stack circuit 300 further includes an impedance unit 310. The impedance unit 310 is coupled between the common path A3 and the reference voltage terminal REF3. The resistor R3_1 and the impedance unit 310 form a voltage divider circuit to divide the gate voltage of the transistor M3_1 (ESD voltage of the signal transmission port SP31) to generate a divided voltage for the common path A3.

[0024] When an ESD event occurs, the divided voltage of the common path A3 can be used to turn on transistors M3_2 to M3_n through resistors R3_2 to R3_n. For example, when an ESD event occurs, the voltage difference between the control end (e.g., gate) of transistor M3_2 and the second end (e.g., source) of transistor M3_2 is greater than the turn-on voltage (threshold voltage) of transistor M3_2, so transistor M3_2 (second transistor) is turned on. By properly adjusting the resistance ratio of resistor R3_1 and impedance unit 310, the gate-source voltage Vgs of each of transistors M3_2 to M3_n can be greater than the threshold voltage (turn-on voltage), thereby turning on each of transistors M3_2 to M3_n.

[0025] For example, based on actual design, the impedance value of the impedance unit 310 is less than 10MΩ. When an ESD event occurs, in some embodiments, the impedance value of the impedance unit 310 is greater than twice the resistance value of each of the resistors R3_1 to R3_n. In other embodiments, the number n of transistors M3_1 to M3_n is greater than 10, and the impedance value of the impedance unit 310 is greater than 5 times the resistance value of each of the resistors R3_1 to R3_n. In some other embodiments, the number n of transistors M3_1 to M3_n is greater than 40, and the impedance value of the impedance unit 310 is greater than 20 times the resistance value of each of the resistors R3_1 to R3_n. In addition, the impedance value of the impedance unit 310 may be an equivalent impedance value of the impedance unit 310 when an ESD event occurs.

[0026] Fig.12 FIG. 1 is a diagram showing a relationship curve between the resistance ratio Rg / Rgnd and the number of transistor stacks according to an embodiment of the present invention. Figure 3 and Fig.12 . Fig.12 Displays a logarithmic axis where Fig.12 The horizontal axis represents the stacking number n of the transistors M3_1 to M3_n, and the vertical axis represents the resistance ratio Rg / Rgnd. Wherein, Rg represents the resistance of the resistor R3_1, and Rgnd represents the resistance of the impedance unit 310. Fig.12 As shown in the relationship curve, the stacking number n of transistors M3_1 to M3_n has a corresponding resistance ratio Rg / Rgnd. By properly adjusting the ratio between the resistance of the resistor R3_1 and the resistance Rgnd of the impedance unit 310 (i.e., Rg / Rgnd), when an ESD event occurs, the gate-source voltage Vgs of each of the transistors M3_2 to M3_n can be greater than the threshold voltage (turn-on voltage), thereby turning on each of the transistors M3_2 to M3_n.

[0027] When an ESD event occurs, the divided voltage of the common path A3 can turn on each of the transistors M3_1 to M3_n to form a low impedance path between the signal transmission ports SP31 and SP32. The turned-on transistors M3_1 to M3_n can transmit ESD current between the signal transmission ports SP31 and SP32, so the transistor stack circuit 300 can prevent ESD from damaging the integrated circuit.

[0028] Figure 4 FIG. 4 is a circuit diagram of an impedance unit 310 according to an embodiment of the present invention. Figure 4 The impedance unit 310 shown can be used as Figure 3 One of many embodiments of the impedance unit 310 is shown. Figure 4In the illustrated embodiment, the impedance unit 310 includes a resistor element, which may be, for example, an actual resistor Rgnd4, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element may be, for example, a metal-oxide-semiconductor (MOS) (which may be an N-channel or P-channel) transistor, a field-effect transistor (FET), a bipolar transistor (BJT), a heterojunction bipolar transistor (HBT), or a diode. The first end and the second end of the resistor Rgnd4 (resistance element) are coupled to the common path A3 and the reference voltage terminal REF3, respectively. Please refer to Figure 3 and Figure 4 , the resistor R3_1 and the resistor Rgnd4 form a voltage divider circuit, and divide the gate voltage of the transistor M3_1 (ESD voltage of the signal transmission port SP31) to generate a divided voltage for the common path A3. When an ESD event occurs, the divided voltage of the common path A3 can turn on the transistors M3_1 to M3_n to form a low impedance path between the signal transmission ports SP31 and SP32.

[0029] Figure 5 FIG. 4 shows a circuit diagram of an impedance unit 310 according to another embodiment of the present invention. Figure 5 The impedance unit 310 shown can be used as Figure 3 One of many embodiments of impedance unit 310 is shown. Figure 5 The impedance unit 310 shown includes a capacitor C5 and a resistor element, wherein the resistor element is, for example, an actual resistor Rgnd5, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a metal oxide semiconductor (for example, an N-channel or P-channel) transistor, a field effect transistor, a bipolar junction transistor, a heterojunction bipolar transistor, or a diode. The capacitor C5 and the resistor Rgnd5 (resistance element) are connected in series between the common path A3 and the reference voltage terminal REF3. The product of the capacitance value of the capacitor C5 and the resistance value of the resistor Rgnd5 (resistance element) is greater than the duration of the ESD event, so that the transistor stack circuit 300 can transmit the ESD current within the duration of the ESD event. On the other hand, in an embodiment using an active element as a resistor element, the resistance value of the active element is the equivalent resistance when the ESD event occurs. Figure 5 In the illustrated embodiment, a first terminal of the capacitor C5 is coupled to the common path A3, a second terminal of the capacitor C5 is coupled to a first terminal of the resistor Rgnd5, and a second terminal of the resistor Rgnd5 is coupled to the reference voltage terminal REF3. Figure 5 In another embodiment, the first end of the resistor Rgnd5 is coupled to the common path A3, the second end of the resistor Rgnd5 is coupled to the first end of the capacitor C5, and the second end of the capacitor C5 is coupled to the reference voltage terminal REF3. In another embodiment, the capacitor C5 and the resistor Rgnd5 (resistance element) can be connected in parallel between the common path A3 and the reference voltage terminal REF3. In addition, since the impedance unit 310 of the present embodiment includes the capacitor C5, an open circuit can be formed for low-frequency signals (such as DC signals) to prevent unexpected signal distortion.

[0030] Figure 6 FIG. 4 shows a circuit diagram of an impedance unit 310 according to yet another embodiment of the present invention. Figure 6 The impedance unit 310 shown can be used as Figure 3 One of many embodiments of the impedance unit 310 is shown. Figure 6 In the illustrated embodiment, the impedance unit 310 includes a switch SW6 and a resistor element, wherein the resistor element is, for example, an actual resistor Rgnd6, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a metal oxide semiconductor (e.g., an N-channel or P-channel) transistor, a field effect transistor, a bipolar junction transistor, a heterojunction bipolar transistor, or a diode. The resistor Rgnd6 (resistance element) and the switch SW6 are connected in series between the common path A3 and the reference voltage terminal REF3. Figure 6 In the illustrated embodiment, a first terminal of the switch SW6 is coupled to the common path A3, a second terminal of the switch SW6 is coupled to a first terminal of the resistor Rgnd6, and a second terminal of the resistor Rgnd6 is coupled to the reference voltage terminal REF3. Figure 6 In another embodiment, the first end of the resistor Rgnd6 is coupled to the common path A3, the second end of the resistor Rgnd6 is coupled to the first end of the switch SW6, and the second end of the switch SW6 is coupled to the reference voltage terminal REF3. The switch SW6 is, for example, an N-channel metal oxide semiconductor transistor, a P-channel metal oxide semiconductor transistor, or other types of transistors. Figure 6 In the illustrated embodiment, the switch SW6 is controlled by the internal circuit 30. In the normal operation mode, the switch SW6 is turned off, so the impedance unit 310 does not affect the normal control of the transistor stack circuit 300 by the internal circuit 30. When an ESD event occurs, the switch SW6 is turned on. Further, the impedance unit 310 of the present embodiment includes the switch SW6, and the switch SW6 can adjust the impedance by changing the voltage and / or size to match the resistor element. Since the switch SW6 can achieve the required impedance using a smaller area, the circuit layout area can be saved.

[0031] Figure 7 FIG. 4 shows a circuit diagram of an impedance unit 310 according to yet another embodiment of the present invention. Figure 7 The impedance unit 310 shown can be used as Figure 3 One of many embodiments of the impedance unit 310 is shown. Figure 7 In the illustrated embodiment, the transistor stack circuit 300 further includes a switch SW71, and the impedance unit 310 includes a switch SW72 and a resistor element, wherein the resistor element is, for example, an actual resistor Rgnd7, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a metal oxide semiconductor (for example, an N-channel type or a P-channel type) transistor, a field effect transistor, a bipolar junction transistor, a heterojunction bipolar transistor, or a diode. The resistor Rgnd7 (resistor element) and the switch SW72 are connected in series between the common path A3 and the reference voltage terminal REF3. The first end of the switch SW71 is coupled between the common path A3 and the impedance unit 310. The second end of the switch SW71 is coupled to the internal circuit 30. In Figure 7 In the illustrated embodiment, a first terminal of the switch SW72 is coupled to the common path A3, a second terminal of the switch SW72 is coupled to a first terminal of the resistor Rgnd7, and a second terminal of the resistor Rgnd7 is coupled to the reference voltage terminal REF3. Figure 7 In another embodiment, the first end of the resistor Rgnd7 is coupled to the common path A3, the second end of the resistor Rgnd7 is coupled to the first end of the switch SW72, and the second end of the switch SW72 is coupled to the reference voltage terminal REF3. The switches SW71 and SW72 are, for example, N-channel metal oxide semiconductor transistors, P-channel metal oxide semiconductor transistors, or other types of transistors. Figure 7 In the illustrated embodiment, switches SW71 and SW72 are controlled by the internal circuit 30. In the normal operation mode, switch SW72 is turned off and switch SW71 is turned on. Therefore, the impedance unit 310 does not affect the normal control of the transistor stack circuit 300 by the internal circuit 30. When an ESD event occurs, switch SW72 is turned on and switch SW71 is turned off. Especially when the impedance of the internal circuit 30 is low, setting switch SW71 can help block the ESD voltage or current.

[0032] Figure 8 FIG. 8 is a circuit diagram of a transistor stack circuit 800 according to another embodiment of the present invention. Figure 8 The transistor stack circuit 800 includes a signal transmission port SP81, a signal transmission port SP82, an impedance unit 810, an ESD (electrostatic discharge) detection circuit 820, a plurality of transistors (eg Figure 8 The transistors M8_1, M8_2, ..., M8_n-1, M8_n) and a plurality of resistors (eg Figure 8 The resistors shown are R8_1, R8_2, ..., R8_n-1, R8_n). Figure 8 The internal circuit 80, the signal transmission port SP81, the signal transmission port SP82, the impedance unit 810, the common path A8, the transistors M8_1 to M8_n, the resistors R8_1 to R8_n and the reference voltage terminal REF8 can refer to Figure 3 The relevant descriptions of the internal circuit 30 , the transmission port SP31 , the signal transmission port SP32 , the impedance unit 310 , the common path A3 , the transistors M3_1 ˜ M3_n , the resistors R3_1 ˜ R3_n and the reference voltage terminal REF3 are not repeated here.

[0033] exist Figure 8 In the illustrated embodiment, the ESD detection circuit 820 is coupled to the signal transmission port SP81. The ESD detection circuit 820 can detect an ESD event. When an ESD event occurs, the ESD detection circuit 820 is triggered, and the ESD detection circuit 820 provides a notification signal (indicating that an ESD event has occurred) to the impedance unit 810, so that the impedance unit 810 can provide a current path between the common path A8 and the reference voltage terminal REF8 in real time, thereby turning on the transistors M8_1 to M8_n. The turned-on transistors M8_1 to M8_n can transmit ESD current between the signal transmission ports SP81 and SP82, so that the transistor stack circuit 800 can prevent ESD from damaging the integrated circuit. In the normal operation mode, the ESD detection circuit 820 is in a closed state, and the current path between the common path A8 and the reference voltage terminal REF8 is cut off.

[0034] Fig. 9 FIG. 8 is a schematic circuit diagram of an impedance unit 810 and an ESD (electrostatic discharge) detection circuit 820 according to an embodiment of the present invention. Fig. 9 The impedance unit 810 and the ESD detection circuit 820 can be used as Figure 8 The impedance unit 810 and the ESD detection circuit 820 are one of many embodiments. Fig. 9 In the illustrated embodiment, the ESD detection circuit 820 is coupled between the signal transmission port SP81, the internal circuit 80 and the reference voltage terminal REF8, and the ESD detection circuit 820 includes a detection resistor R9 and a capacitor C9. The detection resistor R9 and the capacitor C9 are connected in series between the signal transmission port SP81 and the reference voltage terminal REF8. Fig. 9 In the illustrated embodiment, a first end of the detection resistor R9 is coupled to the signal transmission port SP81, a second end of the detection resistor R9 is coupled to a first end of the capacitor C9, and a second end of the capacitor C9 is coupled to the reference voltage terminal REF8. Fig. 9In another embodiment, the first end of the capacitor C9 is coupled to the signal transmission port SP81, the second end of the capacitor C9 is coupled to the first end of the detection resistor R9, and the second end of the detection resistor R9 is coupled to the reference voltage terminal REF8.

[0035] exist Fig. 9 In the illustrated embodiment, the impedance unit 810 includes a resistor element and a switch circuit 811, wherein the resistor element is, for example, an actual resistor Rgnd9, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a metal oxide semiconductor (e.g., an N-channel or P-channel) transistor, a field effect transistor, a bipolar junction transistor, a heterojunction bipolar transistor, or a diode. The resistor Rgnd9 (resistor element) and the switch circuit 811 are connected in series between the common path A8 and the reference voltage terminal REF8. Further, in Fig. 9 In the illustrated embodiment, a first terminal of the resistor Rgnd9 is coupled to the common path A8, a second terminal of the resistor Rgnd9 is coupled to a first terminal of the switch circuit 811, and a second terminal of the switch circuit 811 is coupled to the reference voltage terminal REF8. Fig. 9 In another embodiment, the first end of the switch circuit 811 is coupled to the common path A8, the second end of the switch circuit 811 is coupled to the first end of the resistor Rgnd9, and the second end of the resistor Rgnd9 is coupled to the reference voltage terminal REF8. Fig. 9 In the illustrated embodiment, the switch circuit 811 is controlled by the internal circuit 80. In the normal operation mode, the switch circuit 811 is turned off. Therefore, the impedance unit 810 does not affect the normal control of the transistor stack circuit 800 by the internal circuit 80. When an ESD event occurs, the switch circuit 811 is turned on.

[0036] exist Fig. 9 In the illustrated embodiment, the switch circuit 811 includes a switch string SWS9 and a diode D9. The switch string SWS9 and the diode D9 are connected in series between the resistor Rgnd9 and the reference voltage terminal REF8. Fig. 9In the illustrated embodiment, the anode of the diode D9 is coupled to the resistor Rgnd9, the cathode of the diode D9 is coupled to the first end of the switch string SWS9, and the second end of the switch string SWS9 is coupled to the reference voltage terminal REF8. The common control terminal of the switch string SWS9 is coupled to the internal circuit 80. In the normal operation mode, the switch string SWS9 is turned off. When an electrostatic discharge event occurs, the switch string SWS9 is turned on. The switch string SWS9, for example, includes a plurality of transistors connected in series, such as N-channel metal oxide semiconductor transistors, P-channel metal oxide semiconductor transistors or other types of transistors. The switch string SWS9 can be coupled to the ESD detection circuit 820 and the signal transmission port SP81 through the internal circuit 80. In this way, the control signals for controlling the ESD detection circuit 820 and the switch string SWS9 can all come from the signal transmission port SP81, which can make the control logic of the switch string SWS9 clearer, and thus when an ESD event occurs, the transistor stack circuit 800 can operate smoothly. Furthermore, in another embodiment where the first terminal of the switch circuit 811 is coupled to the common path A8 , the anode of the diode D9 is coupled to the common path A8 .

[0037] Fig.10 FIG. 4 is a circuit diagram of a transistor stack circuit 1000 according to yet another embodiment of the present invention. Fig.10 The transistor stack circuit 1000 includes a signal transmission port SP101, a signal transmission port SP102, an impedance unit 1010, and a plurality of transistors (eg Fig.10 The transistors M10_1, M10_2, ..., M10_n-1, M10_n) and a plurality of resistors (eg Fig.10 The resistors shown are R101_1, R101_2, ..., R101_n-1, R101_n). Fig.10 The transistor stack circuit 1000, the signal transmission port SP101, the signal transmission port SP102, the impedance unit 1010, the common path A10, the transistors M10_1 to M10_n, the resistors R101_1 to R101_n and the reference voltage terminal REF10 can refer to Figure 3 The related descriptions of the transistor stack circuit 300 , the transmission port SP31 , the signal transmission port SP32 , the impedance unit 310 , the common path A3 , the transistors M3_1 ˜ M3_n , the resistors R3_1 ˜ R3_n and the reference voltage terminal REF3 are not repeated here.

[0038] Different from Figure 3 The transistor stack circuit 300 shown is characterized in that: Fig.10The transistor stack circuit 1000 shown also includes resistors R102_1, R102_2, ..., R102_n-2, R102_n-1. Each of these resistors R102_1 to R102_n-1 is coupled between the first ends of two corresponding resistors adjacent to each other among the resistors R101_1 to R101_n. For example, the resistor R102_1 is coupled between the first ends of two corresponding resistors adjacent to each other, R101_1 and R101_2. Similarly, the resistor R102_n-1 is coupled between the first ends of two corresponding resistors adjacent to each other, R101_n-1 and R101_n. Fig.10 In the illustrated embodiment, for example, a resistor (ie, resistors R102_1, R102_2, ..., R102_n-2, R102_n-1) is disposed between the first ends of all two adjacent corresponding resistors. Fig.10 In the transistor stack circuit 1000 architecture, multiple nodes are formed between the resistors R102_1, R102_2, ..., R102_n-2, and R102_n-1. These nodes correspond to the control terminals (such as gates) of the transistors M10_1 to M10_n. The divided voltages are formed at these nodes respectively. Figure 3 The embodiment is formed in the common path A3 of the transistor stack circuit 300. The individual divided voltages at these nodes of the transistor stack circuit 1000 are smaller than the divided voltages at the common path A3 of the transistor stack circuit 300. In comparison, the transistor stack circuit 1000 can provide a more uniform voltage division effect, so that the difference between the gate and source voltages Vgs of two adjacent transistors in the transistors M10_1 to M10_n is smaller, so that when an ESD event occurs, the transistors M10_1 to M10_n can be turned on more uniformly.

[0039] Fig.11 FIG. 1 is a circuit diagram of a transistor stack circuit 1100 according to yet another embodiment of the present invention. Fig.11 The transistor stack circuit 1100 shown includes a signal transmission port SP111, a signal transmission port SP112, an impedance unit 1110, a transistor M11_1, a transistor M11_2, a transistor M11_3, a transistor M11_4, a transistor M11_5, a transistor M11_6, a transistor M11_7, a resistor R111_1, a resistor R111_2, a resistor R111_3, a resistor R111_4, a resistor R111_5, a resistor R111_6 and a resistor R111_7. Fig.11 The transistor stack circuit 1100, the signal transmission port SP111, the signal transmission port SP112, the impedance unit 1110, the common path A11, the transistors M11_1 to M11_7, the resistors R111_1 to R111_7, and the reference voltage terminal REF11 can refer to Figure 3The transistor stack circuit 300, the transmission port SP31, the signal transmission port SP32, the impedance unit 310, the common path A3, the transistors M3_1 to M3_n, the resistors R3_1 to R3_n and the reference voltage terminal REF3 are not described here. Figure 3 The transistor stack circuit 300 shown is characterized in that: Fig.11 The transistor stack circuit 1100 further includes resistors R112_1, R112_2, and R112_3. Each of the resistors R112_1 to R112_3 is coupled between the first ends of two corresponding resistors adjacent to each other among the resistors R111_1 to R111_7. For example, the resistor R112_2 is coupled between the first ends of two corresponding resistors adjacent to each other, R111_3 and R111_4. Fig.11 In the illustrated embodiment, it is not necessary that a resistor (ie, resistors R112_1, R112_2, and R112_3) is disposed between the first ends of all two adjacent corresponding resistors, but the resistors are disposed at intervals, for example. Fig.11 In the transistor stack circuit 1100 architecture, multiple nodes are formed between the resistors R112_1, R112_2 and R112_3. These nodes correspond to the control terminals (eg, gates) of the transistors M11_1 to M11_7. The divided voltages are formed at these nodes respectively. Figure 3 The embodiment is formed in the common path A3 of the transistor stack circuit 300. The individual divided voltages at these nodes of the transistor stack circuit 1100 are smaller than the divided voltages at the common path A3 of the transistor stack circuit 300. In comparison, the transistor stack circuit 1100 can provide a more uniform voltage division effect, so that the difference between the gate and source voltages Vgs of two adjacent transistors in the transistors M11_1 to M11_7 is smaller, so that when an ESD event occurs, the transistors M11_1 to M11_7 can be turned on more uniformly.

[0040] In summary, the impedance unit described in the above embodiments can effectively turn on each of the transistors (transistor stack) connected in series when an ESD event occurs, thereby enabling the transistors to transmit ESD current between the first signal transmission port and the second signal transmission port. Therefore, the transistor stack circuit can prevent ESD from damaging the integrated circuit.

[0041] Although the present invention has been disclosed as above through embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A transistor stack circuit, characterized in that: include: a first signal transmission port; a second signal transmission port; A plurality of transistors, the transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port; a plurality of first resistors, each of the first resistors having a first terminal and a second terminal, the first terminals being coupled to a common path, and each of the second terminals being coupled to a control terminal of a corresponding transistor among the transistors; and an impedance unit coupled between the common path and a reference voltage terminal; in When an electrostatic discharge event occurs, a resistance value of the impedance unit is greater than twice a resistance value of each of the first resistors, and the transistors form a low-resistance path.

2. The transistor stack circuit according to claim 1, characterized in that: The impedance value of the impedance unit is less than 10 MΩ.

3. The transistor stack circuit according to claim 1, characterized in that: The number of the transistors is greater than 40, and the impedance value of the impedance unit is greater than 20 times the resistance value of each of the first resistors.

4. The transistor stack circuit according to claim 1, characterized in that: The number of the transistors is greater than 10, and the impedance value of the impedance unit is greater than 5 times the resistance value of each of the first resistors.

5. The transistor stack circuit according to claim 1, characterized in that: The impedance unit includes: a resistor element having a first end and a second end respectively coupled to the common path and the reference voltage end.

6. The transistor stack circuit according to claim 1, characterized in that: The impedance unit includes: a capacitor; and a resistor element, wherein the capacitor and the resistor element are connected in series or in parallel between the common path and the reference voltage terminal, The product of a capacitance value of the capacitor and a resistance value of the resistor element is greater than the duration of the electrostatic discharge event.

7. The transistor stack circuit according to claim 1, characterized in that: The impedance unit includes: a resistor element; and A first switch, wherein the resistor element and the first switch are connected in series between the common path and the reference voltage terminal.

8. The transistor stack circuit according to claim 7, characterized in that: in, In a normal operation mode, the first switch is turned off; and When the electrostatic discharge event occurs, the first switch is turned on.

9. The transistor stack circuit according to claim 7, characterized in that: Also includes: A second switch, a first terminal of the second switch is coupled between the common path and the impedance unit, and a second terminal of the second switch is coupled to an internal circuit.

10. The transistor stack circuit according to claim 9, characterized in that: in, In a normal operation mode, the first switch is turned off and the second switch is turned on; as well as When the electrostatic discharge event occurs, the first switch is turned on and the second switch is turned off.

11. The transistor stack circuit according to claim 1, characterized in that: Also includes: An electrostatic discharge detection circuit is coupled to the first signal transmission port to detect the electrostatic discharge event, wherein When the electrostatic discharge event occurs, the impedance unit provides a current path between the common path and the reference voltage terminal; as well as In a normal operating mode, the current path is interrupted.

12. The transistor stack circuit according to claim 11, characterized in that: The electrostatic discharge detection circuit is coupled between the first signal transmission port, an internal circuit and the reference voltage terminal, and the electrostatic discharge detection circuit includes: a detection resistor; and A capacitor, wherein the detection resistor and the capacitor are connected in series between the first signal transmission port and the reference voltage terminal.

13. The transistor stack circuit according to claim 11, characterized in that: The impedance unit comprises: a resistor element; and A switch circuit, wherein the resistor element and the switch circuit are connected in series between the common path and the reference voltage terminal.

14. The transistor stack circuit according to claim 13, characterized in that: The switch circuit comprises: a switch string having a common control terminal coupled to an internal circuit, wherein the switch string is turned off in the normal operation mode and turned on when the electrostatic discharge event occurs; and A diode has a cathode coupled to the switch string.

15. The transistor stack circuit according to claim 1, wherein: The transistors include: a first transistor; a second transistor; and A terminal transistor, wherein a first end of the first transistor is coupled to the first signal transmission port, a second end of the first transistor is coupled to a first end of the second transistor, a second end of the terminal transistor is coupled to the second signal transmission port, and when the electrostatic discharge event occurs, the second transistor is turned on.

16. The transistor stack circuit according to claim 1, characterized in that: The voltages of each of the first terminals of the first resistors coupled to the common path are the same.

17. The transistor stack circuit according to claim 1, characterized in that: Also includes: A plurality of third resistors, wherein each of the third resistors is coupled between the first ends of two corresponding first resistors that are adjacent to each other among the first resistors.

18. The transistor stack circuit according to claim 1, wherein: The transistor stack circuit is a radio frequency switch shunt path, the first signal transmission port is coupled to a radio frequency connection pad, and the second signal transmission port is coupled to the reference voltage terminal.

19. The transistor stack circuit according to claim 1, wherein: The transistor stack circuit is a radio frequency switch series path, the first signal transmission port is coupled to a radio frequency connection pad, and the second signal transmission port is coupled to a radio frequency switch shunt path.

20. A transistor stack circuit, characterized in that: include: a first signal transmission port; a second signal transmission port; A plurality of transistors, the transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port, wherein the transistors include a first transistor, a second transistor and a terminal transistor, a first end of the first transistor is coupled to the first signal transmission port, a second end of the first transistor is coupled to a first end of the second transistor, and a second end of the terminal transistor is coupled to the second signal transmission port; a plurality of first resistors, each of the first resistors having a first terminal and a second terminal, the first terminals being coupled to a common path, and each of the second terminals being coupled to a control terminal of a corresponding transistor among the transistors; and an impedance unit coupled between the common path and a reference voltage terminal; in When an electrostatic discharge event occurs, a voltage difference between the control terminal of the second transistor and the second terminal of the second transistor is greater than a turn-on voltage of the second transistor.

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