Grid voltage bootstrapped switch circuit, analog-to-digital converter and electronic equipment

Abstract

The invention discloses a grid voltage bootstrapped switch circuit, an analog-to-digital converter and electronic equipment, and belongs to the technical field of integrated circuits, the grid voltage bootstrapped switch circuit comprises a first transmission gate and a third transmission gate, first control signal input ends of the first transmission gate and the third transmission gate are connected with a first clock signal, and second control signal input ends of the first transmission gate and the third transmission gate are connected with a second clock signal; second control signal input ends of the first transmission gate and the third transmission gate are both connected with a second clock signal, signal input ends of the first transmission gate and the third transmission gate are both connected with an analog input signal and are also connected to a second electrode of a sixth switch tube, and a grid electrode of the sixth switch tube is connected with a fifth node. And the substrate end of the sixth switch tube is connected with the fourth node. The boost module is arranged to set the on-resistance of the sixth switch tube, so that the on-resistance is not influenced by an analog input signal, and the third switch door and the fifth switch tube are arranged to connect the analog input signal with the substrate end of the sixth switch tube, so that the influence of the substrate bias effect on the on-resistance is eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a gate voltage bootstrap switch circuit, an analog-to-digital converter, and electronic equipment. Background Art

[0002] Analog-to-digital converters (ADCs) are widely used in various fields, and the sample-and-hold module is one of the key modules of the ADC. It is a key component that determines the ADC input bandwidth and sampling frequency, and the key to determining its sampling accuracy is the sampling switch.

[0003] The accuracy of the sampling switch directly affects the effective number of bits and linearity of the ADC. Conventional sampling switches are implemented using NMOS tubes or CMOS transmission gates, but their on-resistance is nonlinear, and the resistance value of the on-resistance changes with the input signal. In addition, there are problems such as the offset effect. Therefore, the use of conventional sampling switches cannot meet the high-precision application requirements of ADC.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a gate voltage bootstrap switch circuit, an analog-to-digital converter, and an electronic device to solve the problem that conventional sampling switches cannot meet the application requirements of ADC with high precision.

[0006] In order to solve the above technical problems, the present invention provides a gate voltage bootstrap switch circuit, comprising:

[0007] A first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have opposite logic voltages;

[0008] a first transmission gate and a third transmission gate, wherein first control signal input terminals of the first transmission gate and the third transmission gate are both connected to the first clock signal, and second control signal input terminals of the first transmission gate and the third transmission gate are both connected to the second clock signal;

[0009] A fifth switch tube and a sixth switch tube, the signal input terminals of the first transmission gate and the third transmission gate are both connected to the analog input signal, and are also commonly connected to the second electrode of the sixth switch tube, the gate of the sixth switch tube is connected to the fifth node, the substrate terminal of the sixth switch tube is connected to the fourth node, and the first electrode of the sixth switch tube is connected to the analog output signal;

[0010] The signal output end of the first transmission gate is connected to a first node, the first node is also connected to a boost module, the boost module is connected to a second node so that there is a voltage difference between the second node and the first node, and the second node is connected to the fifth node;

[0011] The signal output end of the third transmission gate is connected to the fourth node, the fourth node is connected to the first electrode of the fifth switch tube, the gate of the fifth switch tube is connected to the second clock signal, and the second electrode of the fifth switch tube is grounded.

[0012] Preferably, the boost module includes a first capacitor and a first diode, the first node is connected to the first electrode of the first capacitor, the second electrode of the first capacitor is connected to the second node, the second node is also connected to the cathode of the first diode, and the anode of the first diode is connected to the power supply voltage.

[0013] Preferably, it further includes a first switch tube, the first node is connected to a first electrode of the first switch tube, a gate of the first switch tube is connected to the second clock signal, and a second electrode of the first switch tube is grounded.

[0014] Preferably, it also includes a second transmission gate, wherein the first control signal input terminal of the second transmission gate is connected to the first clock signal, the second control signal input terminal of the second transmission gate is connected to the second clock signal, the signal input terminal of the second transmission gate is connected to the analog input signal, and is also connected to the second electrode of the sixth switch tube, the signal output terminal of the second transmission gate is connected to the third node, and the third node is also connected to the gate of the fifth transistor, the first electrode of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the fifth node.

[0015] Preferably, the first clock signal is also connected to the gate of the first transistor, the second electrode of the first transistor is connected to the third node, and the first electrode of the first transistor is connected to the power supply voltage.

[0016] Preferably, it also includes a seventh switch tube and an eighth switch tube, the fifth node is connected to the second electrode of the seventh switch tube, the gate of the seventh switch tube is connected to the power supply voltage, the second electrode of the seventh switch tube is connected to the second electrode of the eighth switch tube, and the gate of the eighth switch tube is connected to the second clock signal.

[0017] Preferably, the first clock signal is converted into the second clock signal through an inverter.

[0018] Preferably, the first transmission gate, the second transmission gate and the third transmission gate have the same structure.

[0019] An analog-to-digital converter comprises the above-mentioned gate voltage bootstrap switch circuit.

[0020] An electronic device comprises the above-mentioned gate voltage bootstrap switch circuit.

[0021] In the gate voltage bootstrap switch circuit provided by the present invention, a constant voltage difference is provided between the gate and the second electrode of the sixth switch tube between the analog input signal and the analog output signal through a boost module, so that the on-resistance of the sixth switch tube is not affected by the analog input signal, and a third transmission gate and a fifth switch tube are provided, and the voltage of the substrate end and the source (second electrode) of the sixth switch tube N6 in the on state is equal, thereby eliminating the influence of the substrate bias effect on the on-resistance.

[0022] The analog-to-digital converter and the electronic device provided by the present invention belong to the same inventive concept as the gate voltage bootstrap switch circuit provided by the present invention. Therefore, the analog-to-digital converter and the electronic device provided by the present invention have at least all the advantages of the gate voltage bootstrap switch circuit provided by the present invention, which will not be repeated here. The first control signal input ends of the first transmission gate and the third transmission gate are both connected to the first clock signal, and the second control signal input ends of the first transmission gate and the third transmission gate are both connected to the second clock signal; the signal input ends of the first transmission gate and the third transmission gate are both connected to the analog input signal, and are also connected to the second electrode of the sixth switch tube, the gate of the sixth switch tube is connected to the fifth node, the substrate end of the sixth switch tube is connected to the fourth node, and the first electrode of the sixth switch tube is connected to the analog output signal; wherein the signal output end of the first transmission gate is connected to the first node, the first node is also connected to the boost module, the boost module is connected to the second node, so that there is a voltage difference between the second node and the first node, and the second node is connected to the fifth node; the signal output end of the third transmission gate is connected to the fourth node, the fourth node is connected to the first electrode of the fifth switch tube, the gate of the fifth switch tube is connected to the second clock signal, and the second electrode of the fifth switch tube is grounded. Furthermore, a constant voltage difference is provided between the gate and the second electrode of the sixth switch tube between the analog input signal and the analog output signal through a boost module, so that the on-resistance of the sixth switch tube is not affected by the analog input signal, and a third transmission gate and a fifth switch tube are set, and the voltage of the substrate end and the source (second electrode) of the sixth switch tube N6 in the on state is equal, thereby eliminating the influence of the substrate bias effect on the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a gate voltage bootstrap switch circuit diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The gate voltage bootstrap switch circuit, analog-to-digital converter, and electronic device proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions, and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0026] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0027] The inventor has found through research that the on-resistance of a conventional sampling switch will change with the change of the input signal, and there is also a bias effect.

[0028] Based on this, the core idea of ​​the present invention is to set the on-resistance of the sixth switch tube by setting a boost module so that it is not affected by the analog input signal, and to set a third switch gate and a fifth switch tube to connect the analog input signal and the substrate end of the sixth switch tube to eliminate the influence of the substrate bias effect on the on-resistance.

[0029] For details, please refer to Figure 1 , which is a schematic diagram of an embodiment of the present invention. Figure 1 As shown, a gate voltage bootstrap switch circuit comprises:

[0030] A first clock signal CLK and a second clock signal CLKN, wherein the logic voltages of the first clock signal CLK and the second clock signal CLKN are opposite;

[0031] a first transmission gate and a third transmission gate, wherein first control signal input terminals of the first transmission gate and the third transmission gate are both connected to the first clock signal CLK, and second control signal input terminals of the first transmission gate and the third transmission gate are both connected to the second clock signal CLKN;

[0032] A fifth switch tube N5 and a sixth switch tube N6, the signal input terminals of the first transmission gate and the third transmission gate are both connected to the analog input signal Input, and are also commonly connected to the second electrode of the sixth switch tube N6, the gate of the sixth switch tube N6 is connected to the fifth node Net5, the substrate terminal of the sixth switch tube N6 is connected to the fourth node Net4, and the first electrode of the sixth switch tube N6 is connected to the analog output signal Output;

[0033] The signal output end of the first transmission gate is connected to the first node Net1, the first node Net1 is also connected to the boost module, the boost module is connected to the second node Net2, so that there is a voltage difference between the second node Net2 and the first node Net1, and the second node Net2 is connected to the fifth node Net5;

[0034] The signal output end of the third transmission gate is connected to the fourth node Net4, the fourth node Net4 is connected to the first electrode of the fifth switch tube N5, the gate of the fifth switch tube N5 is connected to the second clock signal CLKN, and the second electrode of the fifth switch tube N5 is grounded.

[0035] By setting a boost module, the input analog input signal Input is boosted, and the boosted signal is transmitted to the gate of the sixth switch tube N6. A third transmission gate is also set to transmit the analog input signal Input to the substrate end of the sixth switch tube N6. In the on state, the voltage of the substrate end of the sixth switch tube N6 is equal to the source (second electrode), thereby eliminating the influence of the substrate bias effect on the on-resistance.

[0036] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present application are mainly CMOS tubes (Complementary Metal Oxide Semiconductor). Since the source and drain of the CMOS tube are symmetrical, the source and drain are interchangeable. In the embodiment of the present application, in order to distinguish the other two levels of the transistor except the gate, the input end of the transistor can be called the first electrode, the output end of the transistor can be called the second electrode, and the middle end is the gate. In addition, the first switch tube N1, the second switch tube N2, the third switch tube N3, the fourth switch tube N4, the fifth switch tube N5, the sixth switch tube N6, the seventh switch tube N7 and the eighth switch tube N8 are all N-type MOS tubes, the first electrode of the N-type MOS tube is the drain, and the second electrode is the source; the first transistor P1, the second transistor P2, the third transistor P3, the fourth transistor P4 and the fifth transistor P5 are P-type MOS tubes, the first electrode of the P-type MOS tube is the source, and the second electrode is the drain.

[0037] The second electrode (source) of the fifth switch tube N5 is connected to the substrate end (or base) and is grounded Gnd, the gate is connected to the second clock signal CLKN, and the first electrode (drain) is connected to the fourth node Net4 to be connected to the third transmission gate and the substrate end of the sixth switch tube N6.

[0038] In one embodiment, the boost module includes a first capacitor C1 and a first diode D1, the first node Net1 is connected to the first electrode of the first capacitor C1, the second electrode of the first capacitor C1 is connected to the second node Net2, the second node Net2 is also connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the power supply voltage VDD.

[0039] A first capacitor C1, a first diode D1 and a power supply voltage VDD are set, the first capacitor C1 is charged through the power supply voltage VDD and the first diode D1, and a voltage value higher than the analog input signal Input by a constant value is output from the second node Net2 when the sampling switch (sixth switch tube N6) is turned on.

[0040] Specifically, it also includes a first switch tube N1, the first node Net1 is connected to a first electrode of the first switch tube N1, a gate of the first switch tube N1 is connected to the second clock signal CLKN, and a second electrode of the first switch tube N1 is grounded.

[0041] It can be understood that the substrate end and the second electrode (source) of the first switch tube N1 are connected to the ground Gnd, and the first switch tube N1 is controlled to be turned on by the second clock signal CLKN.

[0042] Specifically, it also includes a second transmission gate, a first control signal input terminal of the second transmission gate is connected to the first clock signal CLK, a second control signal input terminal of the second transmission gate is connected to the second clock signal CLKN, a signal input terminal of the second transmission gate is connected to the analog input signal, and is also connected to the second electrode of the sixth switch tube N6, a signal output terminal of the second transmission gate is connected to the third node Net3, the third node Net3 is also connected to the gate of the fifth transistor P5, the first electrode of the fifth transistor P5 is connected to the second node Net2, and the second electrode of the fifth transistor P5 is connected to the fifth node Net5.

[0043] The second transmission gate is also connected to control conduction through the first clock signal CLK and the second clock signal CLKN, and outputs the analog input signal Input to the third node Net3, and also controls conduction between the second node Net2 and the fifth node Net5 through the fifth transistor P5.

[0044] Specifically, the first clock signal CLK is also connected to the gate of the first transistor P1, the second electrode of the first transistor P1 is connected to the third node Net3, and the first electrode of the first transistor P1 is connected to the power supply voltage VDD.

[0045] Specifically, it also includes a seventh switch tube N7 and an eighth switch tube N8, the fifth node Net5 is connected to the second electrode of the seventh switch tube N7, the gate of the seventh switch tube N7 is connected to the power supply voltage, the second electrode of the seventh switch tube N7 is connected to the second electrode of the eighth switch tube N8, and the gate of the eighth switch tube N8 is connected to the second clock signal CLKN.

[0046] In one implementation, the first clock signal CLK is converted into the second clock signal CLKN through an inverter INV.

[0047] The first clock signal CLK is the clock of the sampling switch. When the logic voltage of the first clock signal CLK is 0, the logic voltage of the second clock signal CLKN is 1.

[0048] In one embodiment, when CLK=0, CLKN=1. The first switch tube N1 is turned on, the first transmission gate composed of the second switch tube N2 and the second transistor P2 is turned off, and the first node Net1 (the left plate or cathode of the first capacitor C1) is grounded Gnd through the first switch tube N1; the second transmission gate switch composed of the third switch tube N3 and the third transistor P3 is turned off, the first transistor P1 is turned on, and the third node Net3 is pulled to the power supply voltage VDD, so the fifth transistor P5 is also turned off. Since the diode D1 is connected between the power supply voltage VDD and the second node Net2, the second node Net2 (the right plate or anode of the capacitor C1) is charged to VDD-0.7V (assuming that the forward conduction voltage drop of the first diode D1 is 0.7V). The fifth switch tube N5 is turned on, the third transmission gate composed of the fourth transistor P4 and the fourth switch tube N4 is turned off, and the fourth node Net4 is pulled to Gnd through the fifth switch tube N5. The eighth switch tube N8 is turned on, and the fifth node Net5 is pulled to Gnd, so the sixth switch tube N6 is turned off. In summary, in this state, the left plate (cathode) of the first capacitor C1 is charged to 0, the right plate (anode) is charged to VDD-0.7V, and the sixth switch tube N6 of the sampling switch is in the off state.

[0049] In one embodiment, when CLK=1, CLKN=0. The eighth switch tube N8 is turned off, so no matter whether the fifth transistor P5 is turned on or not, the charge on the first capacitor C1 will not be discharged through the fifth transistor P5, so the voltage drop between the two plates of the first capacitor C1 will also remain unchanged. The first switch tube N1 is turned off, and the first transmission gate composed of the second switch tube N2 and the second transistor P2 is turned on, and the first node Net1 (the left plate or anode of the first capacitor C1) changes from the original Gnd to the analog input signal Input, so the voltage of the second node Net2 of the right plate of the first capacitor C1, i.e., the anode, will also rise from the original VDD-0.7V to VDD-0.7V+Input, and the first diode D1 is cut off at the same time. The first transistor P1 is disconnected, the second transmission gate switch composed of the third switch tube N3 and the third transistor P3 is turned on, and the gate of the fifth transistor P5 is connected to Input. Since the source (first electrode) and the substrate terminal of the fifth transistor P5 are connected to the second node Net2, the voltage there is VDD-0.7+input, so the fifth transistor P5 is turned on, and the voltage of the fifth node Net5 (that is, the gate of the sixth switch tube N6) will be equal to the voltage of the second node Net2, that is, equal to VDD-0.7+input.

[0050] Since the source of the sixth switch tube N6 is connected to Input and the gate is connected to the fifth node Net5, Vgs of N6 = VDD-0.7V, which is a constant that is independent of the voltage of the analog input signal Input. The on-resistance R of the sixth switch tube N6 (NMOS tube) is on It can be expressed as

[0051]

[0052] where μ n and C ox is a constant related to the process, is the width-to-length ratio, which is also a constant. Vth is the threshold voltage of the sixth switch N6. Substituting the value of Vgs (VDD-0.7V) into the above formula, we can get:

[0053]

[0054] If V th is a constant, then we can see from the above formula that R on Not affected by the Input voltage. But in fact, considering the bias effect of the NMOS tube, V th Will be affected by V SB (the voltage difference between the source end and the substrate end), so in order to eliminate the substrate bias effect on the on-resistance R on The fifth switch tube N5, the fourth switch tube N4 and the fourth transistor P4 are added so that when CLK=1, the fourth node Net4 (i.e., the substrate terminal of the sixth switch tube N6) is connected to the analog input signal Input. In this way, the voltages of the source terminal and the substrate terminal of the sixth switch tube N6 are equal in the on state, i.e., V SB = 0, thus eliminating the lining effect on R on impact.

[0055] In one example, the first transmission gate, the second transmission gate, and the third transmission gate have the same structure. Figure 1 As shown, the first transmission gate includes a second switch tube N2 and a second transistor P2 which are arranged opposite to each other. The gate of the second switch tube N2 is connected to the first clock signal CLK as a first control signal input terminal, and the gate of the second transistor P2 is connected to the second clock signal CLKN as a second control signal input terminal. The source of the second switch tube N2 is connected to the source and drain of the second transistor P2, and the structure is symmetrical. The interconnection between the two is respectively connected to the analog input signal Input and the first node Net1. Similarly, the second transmission gate includes a third switch tube N3 and a third transistor P3, and the third transmission gate includes a fourth switch tube N4 and a fourth transistor P4.

[0056] An analog-to-digital converter includes the above-mentioned gate voltage bootstrap switch circuit. Specifically, the analog-to-digital converter includes a sampling and holding module, and the sampling and holding module uses the gate voltage bootstrap switch circuit in the above-mentioned embodiment as a sampling switch.

[0057] An electronic device includes the above-mentioned gate voltage bootstrap switch circuit. Specifically, the analog-to-digital converter in the electronic device includes a sampling and holding module, and the sampling and holding module uses the gate voltage bootstrap switch circuit in the above-mentioned embodiment as a sampling switch.

[0058] In summary, it can be seen that in the gate voltage bootstrap switch circuit, analog-to-digital converter, and electronic device provided in the embodiments of the present invention, a boost module is provided to boost the input analog input signal Input, and the boosted signal is transmitted to the gate of the sixth switch tube N6. A third transmission gate is also provided to transmit the analog input signal Input to the substrate end of the sixth switch tube N6. In the on state, the voltage of the substrate end of the sixth switch tube N6 is equal to the voltage of the source (second electrode), thereby eliminating the influence of the substrate bias effect on the on-resistance.

[0059] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A gate voltage bootstrap switch circuit, characterized in that: include: A first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have opposite logic voltages; a first transmission gate and a third transmission gate, wherein first control signal input terminals of the first transmission gate and the third transmission gate are both connected to the first clock signal, and second control signal input terminals of the first transmission gate and the third transmission gate are both connected to the second clock signal; A fifth switch tube and a sixth switch tube, the signal input terminals of the first transmission gate and the third transmission gate are both connected to the analog input signal, and are also commonly connected to the second electrode of the sixth switch tube, the gate of the sixth switch tube is connected to the fifth node, the substrate terminal of the sixth switch tube is connected to the fourth node, and the first electrode of the sixth switch tube is connected to the analog output signal; The signal output end of the first transmission gate is connected to a first node, the first node is also connected to a boost module, the boost module is connected to a second node so that there is a voltage difference between the second node and the first node, and the second node is connected to the fifth node; The signal output end of the third transmission gate is connected to the fourth node, the fourth node is connected to the first electrode of the fifth switch tube, the gate of the fifth switch tube is connected to the second clock signal, and the second electrode of the fifth switch tube is grounded.

2. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: The boost module includes a first capacitor and a first diode, the first node is connected to the first electrode of the first capacitor, the second electrode of the first capacitor is connected to the second node, the second node is also connected to the cathode of the first diode, and the anode of the first diode is connected to the power supply voltage.

3. The gate voltage bootstrap switch circuit according to claim 2, characterized in that: It also includes a first switch tube, the first node is connected to a first electrode of the first switch tube, a gate of the first switch tube is connected to the second clock signal, and a second electrode of the first switch tube is grounded.

4. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: It also includes a second transmission gate, wherein a first control signal input terminal of the second transmission gate is connected to the first clock signal, a second control signal input terminal of the second transmission gate is connected to the second clock signal, a signal input terminal of the second transmission gate is connected to the analog input signal, and is also commonly connected to the second electrode of the sixth switch tube, a signal output terminal of the second transmission gate is connected to a third node, and the third node is also connected to the gate of a fifth transistor, a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to the fifth node.

5. The gate voltage bootstrap switch circuit according to claim 4, characterized in that: The first clock signal is also connected to the gate of the first transistor, a second electrode of the first transistor is connected to the third node, and a first electrode of the first transistor is connected to a power supply voltage.

6. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: It also includes a seventh switch tube and an eighth switch tube, the fifth node is connected to the second electrode of the seventh switch tube, the gate of the seventh switch tube is connected to the power supply voltage, the second electrode of the seventh switch tube is connected to the second electrode of the eighth switch tube, and the gate of the eighth switch tube is connected to the second clock signal.

7. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: The first clock signal is converted into the second clock signal through an inverter.

8. The gate voltage bootstrap switch circuit according to claim 4, characterized in that: The first transmission gate, the second transmission gate and the third transmission gate have the same structure.

9. An analog-to-digital converter, characterized in that: It comprises the gate voltage bootstrap switch circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: It comprises the gate voltage bootstrap switch circuit as described in any one of claims 1 to 8.

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