Pressure converter

Abstract

The invention relates to a voltage converter which comprises a first load circuit, a second load circuit, a bipolar junction transistor, a metal oxide semiconductor field effect transistor and a NOT gate. The first end of the first load circuit receives a second power supply voltage. The first end of the second load circuit receives an input signal. A collector of the bipolar junction transistor is connected to a second terminal of the first load circuit. A base of the bipolar junction transistor is connected to a second terminal of the second load circuit. The drain of the metal oxide semiconductor field effect transistor is connected to the emitter of the bipolar junction transistor. The source of the metal oxide semiconductor field effect transistor receives a ground voltage. The gate of the metal oxide semiconductor field effect transistor receives an input signal. The input end of the NOT gate is connected to the first load circuit. The output end of the NOT gate generates the output signal.

Description

Technical Field

[0001] The present invention relates to a circuit, and more particularly to a level shifter. Background Art

[0002] Generally speaking, there are different power domains in an IC chip, and the circuits in different power domains receive different power supply voltages. For example, V DD1 The supply voltage of the power domain is V DD1 , V DD2 The supply voltage of the power domain is V DD2 , power supply voltage V DD1 Different from the power supply voltage V DD2 For example, the power supply voltage is V DD1 is 1.2V, the power supply voltage is V DD2 is 5V.

[0003] Furthermore, today's CMOS semiconductor process technology can provide different process technologies for the voltage operating range of the device. For example, the medium voltage device (MV device) process technology can be used to manufacture transistors with higher voltage stress, and the completed transistors are suitable for medium voltage operation. In addition, the low voltage device (LV device) process technology can be used to manufacture transistors with faster operating speed but lower voltage stress, and the completed transistors are suitable for low voltage operation. For example, in medium voltage operation, the voltage stress range that the gate and source of the transistor can withstand is approximately between 3.0V and 10V; in low voltage operation, the voltage stress range that the gate and source of the transistor can withstand is approximately between 0.8V and 2.0V.

[0004] Please refer to Figure 1A , which is a schematic diagram of the circuit operation between different power domains in the IC chip. DD1 In the power domain, the logic high level of the signal operated by the first circuit 102 is the power voltage V DD1 , the logic low level is the ground voltage GND. DD2 In the power domain, the signal of the second circuit 106 is operated, and its logic high level is the power voltage V DD2 , the logic low level is the ground voltage GND.

[0005] Furthermore, the signals between different power domains need to use a level shifter 104 to convert the logic level so that the circuits in different power domains can communicate normally. Basically, the main circuit of the level shifter 104 is designed in V DD2 In the power domain, only a small part of the circuit (not shown) is designed for V DD1 power domain.

[0006] For example, the first circuit 102 uses the control signal C TRL1 Communicate with the second circuit 106. At this time, the converter 104 receives the control signal C of the first circuit 102. TRL1 The input signal IN of the transformer 104 is used as the input signal IN of the transformer 104, and the output signal OUT generated by the transformer 104 is used as another control signal C TRLA , and transmits it to the second circuit 106. That is, the voltage converter 104 can convert V DD1 The logic high level in the power domain (that is, V DD1 ) control signal C TRL1 Convert to V DD2 The logic high level in the power domain (that is, V DD2 ) control signal C TRLA In addition, the voltage converter 104 can also convert V DD1 The control signal C of the logic low level (i.e. GND) in the power domain TRL1 Convert to V DD2 The control signal C of the logic low level (i.e. GND) in the power domain TRLA In this way, the two circuits 102 and 106 can communicate normally.

[0007] Of course, if the first circuit 102 uses more control signals to communicate with the second circuit 106, more converters are needed. For example, if the first circuit 102 uses ten control signals to communicate with the second circuit 106, ten converters are needed to convert the logic levels of the ten control signals.

[0008] Please refer to Figure 1B , which is a conventional voltage converter. The voltage converter 110 can convert a signal between the power supply voltage V DD1 The input signal IN to the ground voltage GND and the inverting input signal ZIN are converted into a signal range within the power supply voltage V DD2 The output signal OUT between the power supply voltage V DD1 It can be, for example, 1.2V, the power supply voltage V DD2 It can be, for example, 5V, and the ground voltage GND is 0V. That is, the power supply voltage V DD2Greater than the power supply voltage V DD1 , and the power supply voltage V DD1 Greater than the ground voltage GND.

[0009] like Figure 1B As shown, the voltage converter 110 includes a NOT gate 116, a cross-coupled circuit 112, and a differential pair circuit 114. The NOT gate 116 is designed at V DD1 The power domain, the cross-coupling circuit 112 and the differential pair circuit 114 are designed in V DD2 Power domain. Furthermore, the cross-coupling circuit 112 includes a P-type transistor MP1 and a P-type transistor MP2. The differential pair circuit 114 includes an N-type transistor MN1 and an N-type transistor MN2. Among them, the P-type transistor MP1, the P-type transistor MP2, the N-type transistor MN1 and the N-type transistor MN2 are all Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET transistor for short).

[0010] The two power terminals of the NOT gate 116 are respectively connected to the power supply voltage V DD1 The input terminal of the NOT gate 116 receives the input signal IN, and the output terminal of the NOT gate 116 generates an inverted input signal ZIN.

[0011] The cross-coupling circuit 112 is connected to the power supply voltage V DD2 , node a and node b. The source of the P-type transistor MP1 is connected to the power supply voltage V DD2 The drain of the P-type transistor MP1 is connected to the node a, and the gate of the P-type transistor MP1 is connected to the node b. The source of the P-type transistor MP2 is connected to the power supply voltage V DD2 , the drain of the P-type transistor MP2 is connected to the node b, the gate of the P-type transistor MP2 is connected to the node a, and the voltage of the node b is the output signal OUT.

[0012] The differential pair circuit 114 is connected to the ground voltage GND, the node a and the node b. The drain of the N-type transistor MN1 is connected to the node a, the source of the N-type transistor MN1 is connected to the ground voltage GND, and the gate of the N-type transistor MN1 receives the input signal IN. The drain of the N-type transistor MN2 is connected to the node b, the source of the N-type transistor MN2 is connected to the ground voltage GND, and the gate of the N-type transistor MN2 receives the inverted input signal ZIN.

[0013] When the input signal IN of the voltage converter 110 is at a logic high level, the power supply voltage V DD1 When the inverted input signal ZIN is the logic low level ground voltage GND, the N-type transistor MN1 and the P-type transistor MP2 are turned on, and the N-type transistor MN2 and the P-type transistor MP1 are turned off. Therefore, the voltage at the node b is the power supply voltage V DD2 , so the output signal OUT is the logic high level power supply voltage V DD2 That is, the voltage converter 110 converts the logic high level power supply voltage V DD1 Converts to another logic high level supply voltage V DD2 .

[0014] Furthermore, when the input signal IN of the voltage converter 110 is the ground voltage GND of the logic low level and the inverted input signal ZIN is the power supply voltage V of the logic high level, DD1 , the N-type transistor MN1 and the P-type transistor MP2 are turned off, and the N-type transistor MN2 and the P-type transistor MP1 are turned on. Therefore, the voltage of the node b is the ground voltage GND, so the output signal OUT is the ground voltage GND of the logic low level. In other words, the voltage converter 110 converts the ground voltage GND of the logic low level into the ground voltage GND of the same logic low level.

[0015] From the above description, we can see that Figure 1B In the voltage converter 110, the maximum voltage stress borne by the four transistors MP1, MP2, MN1, and MN2 is approximately equal to the power supply voltage V DD2 That is to say, the four transistors MP1, MP2, MN1, and MN2 in the known converter 110 must be medium voltage devices (MV devices). Furthermore, since the N-type transistors MN1 and MN2 manufactured by the medium voltage device (MV device) process have a threshold voltage that is equal to the power supply voltage V DD1 In other words, the gate of the N-type transistor MN1 or the N-type transistor MN2 in the differential pair circuit 114 receives the power supply voltage V DD1 When the N-type transistor MN1 or the N-type transistor MN2 is turned on completely, the driving capability of the N-type transistor MN1 or the N-type transistor MN2 is insufficient, so that the operating speed of the voltage converter 110 cannot be increased.

[0016] To solve Figure 1BThe defect of the voltage converter 110 can be solved by modifying the N-type transistors MN1 and MN2 in the differential pair circuit 114 into low voltage devices (LV devices). Furthermore, in order to solve the problem that the low voltage devices cannot withstand high voltage stress, the differential pair circuit needs to be further modified.

[0017] Please refer to Figure 1C , which shows another known voltage converter. The voltage converter 120 includes a NOT gate 116, a cross-coupling circuit 112 and a differential pair circuit 134. The structures of the NOT gate 116 and the cross-coupling circuit 112 are the same as Figure 1B The following only introduces the differential pair circuit 134.

[0018] The differential pair circuit 134 is connected to the ground voltage GND, the node a and the node b. The differential pair circuit 134 includes an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3 and an N-type transistor MN4. Among them, the N-type transistor MN1 and the N-type transistor MN2 are low voltage devices (LV devices), and the N-type transistor MN3 and the N-type transistor MN4 are medium voltage devices (MV devices). Furthermore, the N-type transistor MN3 and the N-type transistor MN4 are native transistors, or called depletion-mode transistors. The native transistor is a transistor with an initial conductive characteristic (already-on), and its threshold voltage Vt is very low, approximately between -0.3 volts and +0.3 volts.

[0019] The drain of the N-type transistor MN3 is connected to the node a, the gate of the N-type transistor MN3 receives the input signal IN, the drain of the N-type transistor MN4 is connected to the node b, the gate of the N-type transistor MN4 receives the inverted input signal ZIN, the drain of the N-type transistor MN1 is connected to the source of the N-type transistor MN3, the source of the N-type transistor MN1 is connected to the ground voltage GND, the gate of the N-type transistor MN1 receives the input signal IN, the drain of the N-type transistor MN2 is connected to the source of the N-type transistor MN4, the source of the N-type transistor MN2 is connected to the ground voltage GND, and the gate of the N-type transistor MN2 receives the inverted input signal ZIN.

[0020] Basically, the operation of the transformer 120 is the same as Figure 1B The voltage converter 110 is not described here. Furthermore, since the N-type transistor MN3 and the N-type transistor MN4 are medium voltage components, they can withstand higher voltage stress and share the voltage stress of the N-type transistor MN1 and the N-type transistor MN2. Therefore, the N-type transistor MN1 and the N-type transistor MN2, which are low voltage components, withstand lower voltage stress and can operate normally.

[0021] In addition, since the N-type transistors MN1 and MN2 are low voltage devices, their threshold voltages Vt are very low, approximately equal to the power supply voltage V DD1 When the gate of the N-type transistor MN1 or the N-type transistor MN2 receives the power supply voltage V DD1 When , the N-type transistor MN1 or the N-type transistor MN2 can be fully turned on, so that the voltage converter 120 can operate normally.

[0022] However, most of the current CMOS semiconductor manufacturing processes do not support the production of native transistors. Special processes and additional costs are required to produce native transistors. In particular, CMOS semiconductor manufacturing processes that include the deep N-type well process (DNW process) cannot support the production of native transistors. In other words, most IC chips today do not design Figure 1C A transformer 120 is provided.

[0023] Please refer to Figure 2A , which shows another known voltage converter. The voltage converter 150 does not include native transistors, and the manufacturing of the voltage converter 150 is compatible with the CMOS semiconductor process technology. The voltage converter 150 includes a NOT gate 116, a cross-coupling circuit 112 and a differential pair circuit 154. The structures of the NOT gate 116 and the cross-coupling circuit 112 are the same as Figure 1B The following only introduces the differential pair circuit 154.

[0024] The differential pair circuit 154 is connected to the ground voltage GND, the node a and the node b. The differential pair circuit 154 includes an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3 and an N-type transistor MN4. Among them, the N-type transistor MN1 and the N-type transistor MN2 are low voltage devices (LV devices), and the N-type transistor MN3 and the N-type transistor MN4 are medium voltage devices (MV devices).

[0025] The drain of the N-type transistor MN3 is connected to the node a, the gate of the N-type transistor MN3 receives a bias voltage Vbias, the drain of the N-type transistor MN4 is connected to the node b, the gate of the N-type transistor MN4 receives the bias voltage Vbias, the drain of the N-type transistor MN1 is connected to the source of the N-type transistor MN3, the source of the N-type transistor MN1 is connected to the ground voltage GND, the gate of the N-type transistor MN1 receives the input signal IN, the drain of the N-type transistor MN2 is connected to the source of the N-type transistor MN4, the source of the N-type transistor MN2 is connected to the ground voltage GND, and the gate of the N-type transistor MN2 receives the inverted input signal ZIN. Among them, the bias voltage Vbias is less than the power supply voltage V DD2, and the bias voltage Vbias is greater than the power supply voltage V DD1 The bias voltage Vbias keeps the N-type transistor MN3 and the P-type transistor MN4 in a conducting state.

[0026] Basically, the operation of the transformer 150 is the same as Figure 1B and Figure 1C The voltage converters 110 and 120 are not described in detail here. Furthermore, since the N-type transistors MN3 and MN4 are medium voltage components, they can withstand higher voltage stress and share the voltage stress of the N-type transistors MN1 and MN2. Therefore, the N-type transistors MN1 and MN2, which are low voltage components, withstand lower voltage stress and can operate normally.

[0027] However, since the converter 150 needs to additionally receive a bias voltage Vbias, a bias voltage generator needs to be additionally designed in the IC chip to provide the bias voltage Vbias to the converter 150 .

[0028] Please refer to Figure 2B , which is a schematic diagram of the circuit operation between different power domains in another IC chip. DD1 In the power domain, the logic high level of the signal of the first circuit 202 is the power voltage V DD1 , the logic low level is the ground voltage GND. DD2 In the power domain, the signal of the second circuit 206 is operated, and its logic high level is the power voltage V DD2 , the logic low level is the ground voltage GND. Furthermore, the level shifter 150 can convert the logic level. Furthermore, the level shifter 150 is Figure 2A The transformer 150 is shown.

[0029] Since the voltage converter 150 needs to receive an additional bias voltage Vbias, and the bias voltage Vbias is between the power supply voltage V DD2 With the power supply voltage V DD1 Therefore, the bias voltage generator 208 is designed to be between V DD2 In other words, the bias voltage generator 208 receives the power supply voltage V DD2 , and generates a bias voltage Vbias to the converter 150. After the bias voltage generator 208 generates the bias voltage Vbias to the converter 150, the converter 150 can operate normally.

[0030] For example, the first circuit 202 uses the control signal C TRL1 Communicate with the second circuit 206. At this time, the converter 150 receives the control signal C of the first circuit 202. TRL1 The input signal IN of the transformer 150 is used as the input signal IN of the transformer 150, and the output signal OUT generated by the transformer 150 is used as another control signal C TRLA , and transmitted to the second circuit 206.

[0031] However, Figure 2B In the IC chip 200, the bias voltage generator 208 must operate continuously and supply the bias voltage Vbias to the converter 150. However, when the first circuit 202 is in standby or not operating, the bias voltage generator 208 still continues to operate to provide the bias voltage Vbias, thereby causing additional energy consumption of the IC chip 200.

[0032] In order to solve the above problems, V DD1 The first circuit 202 of the power domain can send an enable signal EN to the bias voltage generator 208 to control the bias voltage generator 208. When the first circuit 202 is in standby or not operating, the enable signal EN is not activated, and the bias voltage generator 208 does not generate the bias voltage Vbias. When the first circuit 202 is operating, the enable signal EN is activated, and the bias voltage generator 208 generates the bias voltage Vbias. Furthermore, when the converter 150 receives the bias voltage Vbias and operates normally, the first circuit 202 can use the control signal C TRL1 Communicate with the second circuit 206. That is, the first circuit 202 controls the bias voltage generator 208 in the above manner to prevent the bias voltage generator 208 from consuming extra energy.

[0033] However, since the first circuit 202 is designed at V DD1 Power domain, bias voltage generator 208 is designed at V DD2 Power domain, V DD1 The logic level of the power domain is related to V DD2 The logic levels of the power domains are different. That is, the enable signal EN of the first circuit 202 cannot be used to directly control the bias voltage generator 208 .

[0034] In order to enable communication between the first circuit 202 and the bias voltage generator 208, it is necessary to further modify Figure 2B IC chip 200. Please refer to Figure 3 The IC chip is 300, at V DD2 In the power domain, a voltage converter 350 is designed to convert the enable signal EN of the first circuit 202 into another enable signal EN A, so that the bias voltage generator 208 can be based on the enable signal EN A to operate.

[0035] exist Figure 3 In the IC chip 300, the bias voltage generator 208 needs to be based on the enable signal EN A To generate the bias voltage Vbias, the voltage converter 350 needs to receive the bias voltage Vbias to output the enable signal EN. A .

[0036] However, when the first circuit 202 activates the enable signal EN, the voltage converter 350 has not yet received the bias voltage Vbias, and the voltage converter 350 cannot generate the control signal EN. A To the bias voltage generator 208. That is to say, the voltage converter 350 and the bias voltage generator 208 in the IC chip 300 cannot operate normally. Of course, the voltage converter 150 cannot operate either, and the first circuit 202 cannot use the control signal C TRL1 Communicates with the second circuit 206 . Summary of the invention

[0037] The present invention provides a converter, which converts an input signal with a signal range between a first power supply voltage and a ground voltage into an output signal with a signal range between a second power supply voltage and the ground voltage. The converter includes: a first load circuit, a first end of the first load circuit receives the second power supply voltage; a second load circuit, a first end of the second load circuit receives the input signal; a bipolar junction transistor, a collector of the bipolar junction transistor is connected to a second end of the first load circuit, and a base of the bipolar junction transistor is connected to a second end of the second load circuit; a first metal oxide semiconductor field effect transistor, a drain of the first metal oxide semiconductor field effect transistor is connected to an emitter of the bipolar junction transistor, a source of the first metal oxide semiconductor field effect transistor receives the ground voltage, and a gate of the first metal oxide semiconductor field effect transistor receives the input signal; and a NOT gate, a first power supply end of the NOT gate receives the second power supply voltage, a second power supply end of the NOT gate receives the ground voltage, an input end of the NOT gate is connected to the first load circuit, and an output end of the NOT gate generates the output signal.

[0038] The present invention provides a converter, which converts an input signal with a signal range between a first power supply voltage and a ground voltage into an output signal with a signal range between a second power supply voltage and the ground voltage. The converter includes: a first load circuit, a first end of which receives the second power supply voltage; a second load circuit, a first end of which receives the input signal; y bipolar junction transistors, wherein the bases of the y bipolar junction transistors are connected to the second load circuit, and y is an integer greater than or equal to 1; among the y bipolar junction transistors, a collector of a first bipolar junction transistor is connected to a second end of the first load circuit, an emitter of a yth bipolar junction transistor is connected to a first node, a collector of the other bipolar junction transistors is connected to an emitter of a previous bipolar junction transistor, and an emitter of the other bipolar junction transistors is connected to a collector of a subsequent bipolar junction transistor. a gate of z metal oxide semiconductor field effect transistors, wherein the gates of the z metal oxide semiconductor field effect transistors receive the input signal, z is an integer greater than or equal to 1, and y and z are not 1 at the same time; among the z metal oxide semiconductor field effect transistors, a drain of a first metal oxide semiconductor field effect transistor is connected to the first node, a source of a zth metal oxide semiconductor field effect transistor receives the ground voltage, a drain of the other metal oxide semiconductor field effect transistors is connected to a source of the previous metal oxide semiconductor field effect transistor, and a source of the other metal oxide semiconductor field effect transistors is connected to a drain of the next metal oxide semiconductor field effect transistor; and a NOT gate, a first power supply terminal of the NOT gate receives the second power supply voltage, a second power supply terminal of the NOT gate receives the ground voltage, an input terminal of the NOT gate is connected to the first load circuit, and an output terminal of the NOT gate generates the output signal.

[0039] The present invention proposes a converter, which converts an input signal with a signal range between a first power supply voltage and a ground voltage and an inverted input signal into an output signal with a signal range between a second power supply voltage and the ground voltage. The converter includes: a first load circuit, which is connected to the second power supply voltage, a first node and a second node, and the voltage of the second node is the output signal; a second load circuit, a first end of which receives the input signal; a third load circuit, a first end of which receives the inverted input signal; a first bipolar junction transistor, a collector of which is connected to the first node, and a base of which is connected to a second end of the second load circuit; a second bipolar junction transistor, a collector connected to the second node, a base of the second bipolar junction transistor connected to a second end of the third load circuit; a first metal oxide semiconductor field effect transistor, a drain of the first metal oxide semiconductor field effect transistor connected to an emitter of the first bipolar junction transistor, a source of the first metal oxide semiconductor field effect transistor receiving the ground voltage, and a gate of the first metal oxide semiconductor field effect transistor receiving the input signal; and a second metal oxide semiconductor field effect transistor, a drain of the second metal oxide semiconductor field effect transistor connected to an emitter of the second bipolar junction transistor, a source of the second metal oxide semiconductor field effect transistor receiving the ground voltage, and a gate of the second metal oxide semiconductor field effect transistor receiving the inverted input signal.

[0040] The present invention provides a converter, which converts an input signal and an inverted input signal in a signal range between a first power supply voltage and a ground voltage into an output signal in a signal range between a second power supply voltage and the ground voltage. The converter comprises: a first load circuit, the first load circuit is connected to the second power supply voltage, a first node and a second node, and the voltage of the second node is the output signal; a second load circuit, a first end of the second load circuit receives the input signal; a third load circuit, a first end of the third load circuit receives the inverted input signal; a first group of y bipolar junction transistors, wherein the y bipolar junction transistors of the first group are ... first load circuit, a first end of the second load circuit receives the inverted input signal; a first group of y bipolar junction transistors, wherein the y bipolar junction transistors of the first group are connected to the second power supply voltage, a first node and a second node, and the voltage of the second node is the output signal; a first load circuit, a first end of the second load circuit receives the input signal; a third load circuit, a first end of the third load circuit receives the inverted input signal; a first group of y bipolar junction transistors, wherein the y bipolar junction transistors of the first group are connected to the second power supply voltage, a first node and a second node, and the voltage of the second node is the output signal; a first load circuit, a first end of the second load circuit receives the inverted input signal; a first group of y bipolar junction transistors The base of the transistor is connected to the second load circuit, y is an integer greater than or equal to 1; among the y bipolar junction transistors in the first group, a collector of a first bipolar junction transistor is connected to the first node, an emitter of a y-th bipolar junction transistor is connected to a third node, a collector of other bipolar junction transistors is connected to an emitter of a previous bipolar junction transistor, and an emitter of other bipolar junction transistors is connected to a collector of a subsequent bipolar junction transistor; a second group of y bipolar junction transistors, wherein the bases of the y bipolar junction transistors in the second group are connected to the third load circuit; in the y bipolar junction transistors in the second group a collector of a first bipolar junction transistor connected to the second node, an emitter of a yth bipolar junction transistor connected to a fourth node, a collector of the other bipolar junction transistors connected to an emitter of a previous bipolar junction transistor, and an emitter of the other bipolar junction transistors connected to a collector of a subsequent bipolar junction transistor; a third group of z metal oxide semiconductor field effect transistors, wherein the gates of the z metal oxide semiconductor field effect transistors of the third group receive the input signal, z is an integer greater than or equal to 1, and y and z are not 1 at the same time; the z metal oxide semiconductor field effect transistors of the third group a first metal oxide semiconductor field effect transistor, a drain of a first metal oxide semiconductor field effect transistor is connected to the third node, a source of a z-th metal oxide semiconductor field effect transistor receives the ground voltage, a drain of the other metal oxide semiconductor field effect transistors is connected to a source of the previous metal oxide semiconductor field effect transistor, and a source of the other metal oxide semiconductor field effect transistors is connected to a drain of the next metal oxide semiconductor field effect transistor; and a fourth group of z metal oxide semiconductor field effect transistors, wherein the gates of the z metal oxide semiconductor field effect transistors of the fourth group receive the inverted input signal;Among the z MOSFETs of the fourth group, a drain of a first MOSFET is connected to the fourth node, a source of a z MOSFET receives the ground voltage, a drain of the other MOSFETs is connected to a source of the previous MOSFET, and a source of the other MOSFETs is connected to a drain of the next MOSFET.

[0041] In order to better understand the above and other aspects of the present invention, the following preferred embodiments are specifically described in detail with reference to the accompanying drawings as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1A A schematic diagram of the circuit operation between different power domains in an IC chip;

[0043] Figure 1B is a known transformer;

[0044] Figure 1C is another known transformer;

[0045] Figure 2A is a known transformer;

[0046] Figure 2B A schematic diagram of circuit operation between different power domains in another IC chip;

[0047] Figure 3 A schematic diagram of circuit operation between different power domains in another IC chip;

[0048] Figure 4A The first embodiment of the single-terminal converter of the present invention;

[0049] Figure 4B and Figure 4C It is a schematic diagram of the operation of the single-terminal converter of the present invention;

[0050] Figure 4D The second embodiment of the single-terminal converter of the present invention;

[0051] Figure 4E The third embodiment of the single-terminal converter of the present invention;

[0052] Figure 4F The fourth embodiment of the single-terminal converter of the present invention;

[0053] Figure 4G The fifth embodiment of the single-terminal converter of the present invention;

[0054] Figure 4H and Fig. 4I are examples of two load circuits in the fifth embodiment;

[0055] Figure 5A This is the first embodiment of the differential converter of the present invention;

[0056] Figure 5B and Figure 5C It is a schematic diagram of the operation of the differential converter of the present invention;

[0057] Figure 5D The second embodiment of the differential converter of the present invention;

[0058] Figure 5E A third embodiment of a differential converter according to the present invention; and

[0059] Fig. 5F and Figure 5G These are examples of two load circuits in the third embodiment.

[0060]

Explanation of symbols

[0061] 100, 200, 300: IC chip

[0062] 102, 202: First Circuit

[0063] 104, 110, 120, 150, 350, 400, 420, 430, 440, 450, 500, 520, 530: Transformer

[0064] 106, 206: Second Circuit

[0065] 112: Cross-coupled circuit

[0066] 114, 134, 154, 501, 503: Differential pair circuit

[0067] 116, 408, 508: NOT gate

[0068] 208: Bias voltage generator

[0069] 402, 406, 409, 502, 504, 506, 534, 536: Load circuit

[0070] 431~43x: Sub-load circuit DETAILED DESCRIPTION

[0071] The present invention provides a voltage converter, the manufacturing of which is compatible with the current CMOS process technology, and does not require the use of additional special process technology. Furthermore, the voltage converter does not need to receive the bias voltage Vbias to operate normally. In other words, the voltage converter of the present invention can be used in Figure 3Of course, the transformer of the present invention can also be used in Figure 1A The level shifter 104 of the present invention includes a single ended type level shifter and a differential type level shifter, as described below.

[0072] Please refer to Figure 4A , which shows a first embodiment of a single-terminal voltage converter of the present invention. The voltage converter 400 is designed at V DD2 Power domain. The voltage converter 400 includes a NOT gate 408, a bipolar junction transistor (BJT transistor) Q1, a metal oxide semiconductor field effect transistor MN1, and two load circuits 402 and 406. The bipolar junction transistor Q1 is an NPN transistor, the bipolar junction transistor Q1 is a medium voltage device (MV device), the metal oxide semiconductor field effect transistor MN1 is an N-type transistor, and the metal oxide semiconductor field effect transistor MN1 is a low voltage device (LV device).

[0073] The first terminal of the load circuit 402 is connected to the power supply voltage V DD2 The second terminal of the load circuit 402 is connected to the collector of the bipolar junction transistor Q1. The two power terminals of the NOT gate 408 are respectively connected to the power supply voltage V DD2 and the ground voltage GND. The input terminal of the NOT gate 408 is connected to the load circuit 402, and the output terminal of the NOT gate 408 generates an output signal OUT. The first terminal of the load circuit 406 receives the input signal IN, and the second terminal of the load circuit 406 is connected to the base of the bipolar junction transistor Q1. Furthermore, the emitter of the bipolar junction transistor Q1 is connected to the drain of the metal oxide semiconductor field effect transistor MN1, the source of the metal oxide semiconductor field effect transistor MN1 is connected to the ground voltage GND, and the gate of the metal oxide semiconductor field effect transistor MN1 receives the input signal IN.

[0074] According to the first embodiment of the present invention, since the MOSFET MN1 is a low voltage device, its threshold voltage Vt is very low. In addition, the turn on voltage of the BJT Q1 is approximately 0.7V. In other words, the logic high level power supply voltage V DD1The MOSFET MN1 and the BJT Q1 can be easily turned on. For example, the power voltage V DD1 is 1.2V, the power supply voltage V DD2 is 5V.

[0075] Basically, the load circuits 402 and 406 can be resistors, such as polysilicon resistors. The operation of the converter 400 is described below using resistors as the load circuits 402 and 406. Figure 4B and Figure 4C , which is a schematic diagram of the operation of the single-terminal converter of the present invention. Figure 4B and Figure 4C As shown, in the load circuit 402, the first end of the resistor r1 is connected to the power supply voltage V DD2 , the second end of the resistor r1 is connected to the node c, the collector of the bipolar junction transistor Q1 is connected to the node c, and the input end of the NOT gate 408 is connected to the node c. In the load circuit 406, the first end of the resistor r2 receives the input signal IN, and the second end of the resistor r2 is connected to the base of the bipolar junction transistor Q1.

[0076] like Figure 4B As shown, when the input signal IN of the voltage converter 400 is a logic high level power supply voltage V DD1 When , the MOSFET MN1 and the BJT Q1 are turned on, and the voltage of the node c is the ground voltage (GND). Therefore, the output signal OUT generated by the NOT gate 408 is the power supply voltage V DD2 That is, the voltage converter 400 converts the logic high level power supply voltage V DD1 Converts to another logic high level supply voltage V DD2 .

[0077] like Figure 4C As shown, when the input signal IN of the converter 400 is a ground voltage (GND) of a logic low level, the metal oxide semiconductor field effect transistor MN1 and the bipolar junction transistor Q1 are turned off, and the voltage of the node c is the power supply voltage V DD2 Therefore, the output signal OUT generated by the NOT gate 408 is a ground voltage (GND) of a logic low level. That is, the voltage converter 400 converts the ground voltage GND of a logic low level into another ground voltage (GND) of a logic low level.

[0078] Obviously, when the input signal IN of the converter 400 is the ground voltage (GND) of the logic low level, the MOSFET MN1 and the BJT Q1 are turned off, and the converter 400 does not generate any DC current, which can effectively save power loss.

[0079] In the converter 400 of the first embodiment described above, the load circuits 402 and 406 are described by taking polysilicon resistors as an example. The resistance value of the resistor r2 in the load circuit 406 is related to the base current of the bipolar junction transistor Q1. For example, the larger the resistance value of the resistor r2, the smaller the base current of the bipolar junction transistor Q1. Therefore, without considering the base current, the load circuit 406 can also be omitted. In other words, the resistance value of the resistor r2 in the load circuit 406 can be greater than or equal to zero. When the resistance value of the resistor r2 in the load circuit 406 is equal to zero, it means that the base of the bipolar junction transistor Q1 directly receives the input signal IN.

[0080] In addition, the load circuit 402 can also be composed of a metal oxide semiconductor field effect transistor. Figure 4D , which illustrates a second embodiment of a single-terminal converter of the present invention. Compared with the converter 400 of the first embodiment, the difference is that in the converter 420 of the second embodiment, the load circuit 402 is composed of a metal oxide semiconductor field effect transistor MP1. The following only introduces the connection relationship of the load circuit 402, and the rest is not repeated.

[0081] The load circuit 402 includes a metal oxide semiconductor field effect transistor MP1, which is a P-type transistor and a medium voltage device (MV device). The source of the metal oxide semiconductor field effect transistor MP1 receives a power supply voltage V DD2 , the drain of the MOSFET MP1 is connected to the node c, and the gate of the MOSFET MP1 receives the ground voltage (GND). Therefore, the MOSFET MP1 can be equivalent to a resistor.

[0082] Basically, the operation of the transformer 420 of the second embodiment is similar to Figure 4B and Figure 4C , I will not go into details here.

[0083] In addition, the load circuit 402 may also include a plurality of sub-load circuits connected to the power supply voltage V DD2 Between the collector of the bipolar junction transistor Q1. Figure 4E , which illustrates a third embodiment of a single-terminal converter of the present invention. Compared with the converter 400 of the first embodiment, the difference is that the load circuit 402 is composed of x sub-load circuits 431-43x, where x is an integer greater than 1. The following only introduces the connection relationship of the load circuit 402, and the rest is not repeated.

[0084] The load circuit 402 includes x sub-load circuits 431-43x, each of which is composed of x metal oxide semiconductor field effect transistors MP1-MPx and connected to a power supply voltage V DD2 and node c. The gates of all x metal oxide semiconductor field effect transistors MP1-MPx receive the ground voltage (GND). Furthermore, the source of the first metal oxide semiconductor field effect transistor MP1 is connected to the power supply voltage V DD2 , the drain of the xth MOSFET MPx is connected to the node c, the source of the other MOSFETs is connected to the drain of the previous MOSFET, and the drain of the other MOSFETs is connected to the source of the next MOSFET. Therefore, each MOSFET MP1-MPx can be equivalent to a resistor.

[0085] Basically, the operation of the transformer 430 of the third embodiment is similar to Figure 4B and Figure 4C Of course, the x sub-load circuits 431-43x can also be composed of x polysilicon resistors connected in series to the power supply voltage V DD2 Between node c, its operation principle is similar to Figure 4B and Figure 4C , I will not go into details here.

[0086] In addition, the voltage converter 430 of the third embodiment can also be slightly modified to become the fourth embodiment. Figure 4F , which illustrates a fourth embodiment of a single-terminal voltage converter of the present invention. Compared with the voltage converter 430 of the third embodiment, in the voltage converter 440 of the fourth embodiment, the input terminal of the inverter 408 is connected to the node d. The node d is the power supply voltage V DD2 One of the nodes between and node c. Figure 4F In the example, the source of the x-th metal oxide semiconductor field effect transistor is connected to the node d. Of course, the present invention is not limited thereto. A person skilled in the art may connect the input end of the NOT gate 408 to the power supply voltage V in the load circuit 402 according to actual needs. DD2 One of the nodes between node c and node d.

[0087] Basically, the operation of the transformer 440 of the fourth embodiment is similar to Figure 4B and Figure 4C Similarly, when the x sub-load circuits 431-43x are x polysilicon resistors, the input end of the NOT gate 408 can also be connected to the power supply voltage V DD2 One of the nodes between node c and node d.

[0088] Furthermore, the voltage converter of the present invention is not limited to having only a single bipolar junction transistor and a single metal oxide semiconductor field effect transistor MN1. Figure 4G , which illustrates a fifth embodiment of a single-terminal voltage converter of the present invention. Compared to the voltage converter 400 of the first embodiment, the voltage converter 450 of the fifth embodiment includes y bipolar junction transistors Q1-Qy and z metal oxide semiconductor field effect transistors MN1-MNz. The following only introduces the connection relationship between the y bipolar junction transistors Q1-Qy and the z metal oxide semiconductor field effect transistors MN1-MNz, and the rest is not repeated.

[0089] The y bipolar junction transistors Q1-Qy are connected between the second end of the load circuit 402 and the node e in a cascode manner. The z metal oxide semiconductor field effect transistors MN1-MNz are connected between the node e and the ground voltage (GND) in a cascode manner. Wherein, y and z are both integers greater than or equal to 1. When y and z are both equal to 1, the fifth embodiment voltage converter 450 is the same as the first embodiment voltage converter 400. When y and z are not 1 at the same time, the fifth embodiment voltage converter 450 is different from the first embodiment voltage converter 400.

[0090] The load circuit 409 receives an input signal IN, and the bases of the y bipolar junction transistors Q1 to Qy are connected to the load circuit 409. Furthermore, the collector of the first bipolar junction transistor Q1 is connected to the second end of the load circuit 402, the emitter of the yth bipolar junction transistor Qy is connected to the node e, the collectors of the other bipolar junction transistors are connected to the emitter of the previous bipolar junction transistor, and the emitters of the other bipolar junction transistors are connected to the collector of the next bipolar junction transistor.

[0091] Furthermore, the gates of all z MOSFETs MN1 to MNz receive the input signal IN. Furthermore, the drain of the first MOSFET MN1 is connected to the node e, the source of the z MOSFET MNz is connected to the ground voltage GND, the drains of the other MOSFETs are connected to the source of the previous MOSFET, and the sources of the other MOSFETs are connected to the drain of the next MOSFET.

[0092] Basically, the operation of the transformer 450 of the fifth embodiment is similar to Figure 4B and Figure 4C , which will not be described here. Among them, the load circuit 409 in the converter 450 of the fifth embodiment can be composed of resistors, such as polysilicon resistors. In addition, if the base current is not considered, the load circuit 409 can also be omitted. That is, when the resistance value of the resistor in the load circuit 409 is equal to zero, it means that the bases of the y bipolar junction transistors Q1-Qy directly receive the input signal IN.

[0093] According to the fifth embodiment of the present invention, the load circuit 409 has two different examples, as described below. Figure 4H and Fig. 4I , which is illustrated as an example of two load circuits in the fifth embodiment.

[0094] like Figure 4H As shown, the load circuit 409 includes y resistors r1-ry, wherein first ends of the y resistors r1-ry receive the input signal IN, and second ends of the y resistors r1-ry are connected to bases of corresponding y bipolar junction transistors Q1-Qy.

[0095] like Fig. 4I As shown, the load circuit 409 includes a resistor r1 , a first end of the resistor r1 receives an input signal IN, and a second end of the resistor r1 is connected to all bases of y bipolar junction transistors Q1 ˜Qy.

[0096] Please refer to Figure 5A, which illustrates the first embodiment of the differential converter of the present invention. The converter 500 includes a NOT gate 508, a load circuit 502 and a differential pair circuit 501. The differential pair circuit 501 includes: two bipolar junction transistors Q1 and Q2, two metal oxide semiconductor field effect transistors MN1 and MN2 and two load circuits 504 and 506. Furthermore, the bipolar junction transistors Q1 and Q2 are NPN transistors, the bipolar junction transistors Q1 and Q2 are medium voltage devices (MV devices), the metal oxide semiconductor field effect transistors MN1 and MN2 are N-type transistors, and the metal oxide semiconductor field effect transistors MN1 and MN2 are low voltage devices (LV devices).

[0097] The two power terminals of the NOT gate 508 are connected to the power supply voltage V DD1 and the ground voltage GND. The input terminal of the NOT gate 508 receives the input signal IN, and the output terminal of the NOT gate 508 generates the inverted input signal ZIN. Furthermore, the load circuit 502 is connected to the power supply voltage V DD2 , node f and node g, and the voltage at node f is the output signal OUT.

[0098] In the differential pair circuit 501, a first end of a load circuit 504 receives an input signal IN, a second end of the load circuit 504 is connected to a base of a bipolar junction transistor Q1, a collector of the bipolar junction transistor Q1 is connected to a node g, an emitter of the bipolar junction transistor Q1 is connected to a drain of a metal oxide semiconductor field effect transistor MN1, a source of the metal oxide semiconductor field effect transistor MN1 is connected to a ground voltage GND, and a gate of the metal oxide semiconductor field effect transistor MN1 receives the input signal IN.

[0099] In the differential pair circuit 501, a first terminal of a load circuit 506 receives an inverted input signal ZIN, a second terminal of the load circuit 506 is connected to a base of a bipolar junction transistor Q2, a collector of the bipolar junction transistor Q2 is connected to a node f, an emitter of the bipolar junction transistor Q2 is connected to a drain of a metal oxide semiconductor field effect transistor MN2, a source of the metal oxide semiconductor field effect transistor MN2 is connected to a ground voltage GND, and a gate of the metal oxide semiconductor field effect transistor MN2 receives the inverted input signal ZIN.

[0100] Basically, the MOSFETs MN1 and MN2 are low voltage devices with very low threshold voltages Vt. The turn on voltage of the bipolar junction transistors Q1 and Q2 is about 0.7V. In other words, the logic high level power supply voltage V DD1 The MOSFET MN1 and the BJT Q1 can be easily turned on. For example, the power supply voltage is V DD1 is 1.2V, the power supply voltage is V DD2 is 5V.

[0101] Furthermore, the load circuits 504 and 506 may be resistors, such as polysilicon resistors, and the load circuit 502 may be a metal oxide semiconductor field effect transistor. The following uses resistors as the load circuits 504 and 506, and the load circuit 502 as a metal oxide semiconductor field effect transistor to illustrate the operation of the converter 500. Figure 5B and Figure 5C , which is a schematic diagram of the operation of the differential converter of the present invention. Figure 5B and Figure 5C As shown, in the load circuit 504, the first end of the resistor r1 receives the input signal IN, and the second end of the resistor r1 is connected to the base of the bipolar junction transistor Q1. In the load circuit 506, the first end of the resistor r2 receives the inverted input signal ZIN, and the second end of the resistor r2 is connected to the base of the bipolar junction transistor Q2.

[0102] Furthermore, the load circuit 502 includes two metal oxide semiconductor field effect transistors MP1 and MP2, the two metal oxide semiconductor field effect transistors MP1 and MP2 are P-type transistors, and the two metal oxide semiconductor field effect transistors MP1 and MP2 are medium voltage devices (MV devices). The source of the metal oxide semiconductor field effect transistor MP1 is connected to the power supply voltage V DD2 The drain of the metal oxide semiconductor field effect transistor MP1 is connected to the node g, and the gate of the metal oxide semiconductor field effect transistor MP1 is connected to the node f. The source of the metal oxide semiconductor field effect transistor MP2 is connected to the power supply voltage V DD2 , the drain of the metal oxide semiconductor field effect transistor MP2 is connected to the node f, and the gate of the metal oxide semiconductor field effect transistor MP2 is connected to the node g.

[0103] like Figure 5B As shown, when the input signal IN of the voltage converter 500 is a logic high level power supply voltage V DD1, and when the inverting input signal ZIN is the ground voltage GND of the logic low level, the metal oxide semiconductor field effect transistors MN1, MP2 and the bipolar junction transistor Q1 are turned on, the metal oxide semiconductor field effect transistors MN2, MP1 and the bipolar junction transistor Q2 are turned off, the voltage of the node g is the ground voltage (GND), and the voltage of the node f is the power supply voltage V DD2 Therefore, the output signal OUT generated by the voltage converter 500 is a power supply voltage V DD2 That is, the voltage converter 500 converts the logic high level power supply voltage V DD1 Converts to another logic high level supply voltage V DD2 .

[0104] like Figure 5C As shown, when the input signal IN of the voltage converter 500 is the ground voltage GND of the logic low level, and the inverting input signal ZIN is the power supply voltage V of the logic high level, DD1 When , the MOSFETs MN1, MP2 and the BJT Q1 are turned off, the MOSFETs MN2, MP1 and the BJT Q2 are turned on, and the voltage at the node g is the power supply voltage V DD2 , the voltage of the node f is the ground voltage (GND). Therefore, the output signal OUT generated by the voltage converter 500 is the ground voltage GND of a logic low level. That is, the voltage converter 500 converts the ground voltage GND of a logic low level into another ground voltage GND of a logic low level.

[0105] In the above-mentioned converter 500, the load circuits 504 and 506 are explained by taking polysilicon resistors as an example. Among them, the resistance value of the resistor r1 in the load circuit 504 is related to the base current of the bipolar junction transistor Q1, and the resistance value of the resistor r2 in the load circuit 506 is related to the base current of the bipolar junction transistor Q2. Therefore, without considering the base current, the load circuits 504 and 506 can also be omitted. In other words, the resistance value of the resistor r1 in the load circuit 504 can be greater than or equal to zero, and the resistance value of the resistor r2 in the load circuit 506 can be greater than or equal to zero. When the resistance values ​​of the resistors r1 and r2 are equal to zero, it means that the base of the bipolar junction transistor Q1 directly receives the input signal IN, and the base of the bipolar junction transistor Q2 directly receives the inverted input signal ZIN.

[0106] In addition, the load circuit 502 can also be composed of a metal oxide semiconductor field effect transistor and a resistor. Figure 5D, which illustrates a second embodiment of a differential converter of the present invention. Compared with the converter 500 of the first embodiment, the difference is that in the converter 520 of the second embodiment, the load circuit 502 includes metal oxide semiconductor field effect transistors MP1, MP2 and resistors ra, rb. The following only introduces the connection relationship of the load circuit 502, and the rest is not repeated.

[0107] In the load circuit 502, the MOSFETs MP1 and MP2 are P-type transistors, and the MOSFETs MP1 and MP2 are medium voltage devices (MV devices). The source of the MOSFET MP1 receives a power supply voltage V DD2 The drain of the metal oxide semiconductor field effect transistor MP1 is connected to the first end of the resistor ra, the second end of the resistor ra is connected to the node g, and the gate of the metal oxide semiconductor field effect transistor MP1 is connected to the node f. Furthermore, the source of the metal oxide semiconductor field effect transistor MP2 receives the power supply voltage V DD2 The drain of the metal oxide semiconductor field effect transistor MP2 is connected to the first end of the resistor rb, the second end of the resistor rb is connected to the node f, and the gate of the metal oxide semiconductor field effect transistor MP2 is connected to the node g.

[0108] basically, Figure 5D The operation of the second embodiment of the transformer 520 is similar to Figure 5B and Figure 5C , I will not go into details here.

[0109] Please refer to Figure 5E , which illustrates a third embodiment of a differential converter of the present invention. Compared with the converter 500 of the first embodiment, the differential pair circuit 503 of the converter 530 of the third embodiment includes two load circuits 534 and 536, 2y bipolar junction transistors Q11-Q1y, Q21-Q2y, and 2z metal oxide semiconductor field effect transistors MN11-MN1z, MN21-MN2z. The following only introduces the connection relationship of the differential pair circuit 503, and the rest is not repeated.

[0110] In the differential pair circuit 503, the first group of y bipolar junction transistors Q11-Q1y are connected between the node g and the node i in a cascode manner. The second group of y bipolar junction transistors Q21-Q2y are connected between the node f and the node h in a cascode manner. The third group of z metal oxide semiconductor field effect transistors MN11-MN1z are connected between the node i and the ground voltage (GND) in a cascode manner. The fourth group of z metal oxide semiconductor field effect transistors MN21-MN2z are connected between the node h and the ground voltage (GND) in a cascode manner. Wherein, y and z are both integers greater than or equal to 1. When y and z are both equal to 1, the third embodiment voltage converter 530 is the same as the first embodiment voltage converter 500. When y and z are not 1 at the same time, the third embodiment voltage converter 530 is different from the first embodiment voltage converter 500.

[0111] The load circuit 534 receives the input signal IN, and the bases of the first group of y bipolar junction transistors Q11-Q1y are connected to the load circuit 534. Furthermore, among the first group of y bipolar junction transistors Q11-Q1y, the collector of the first bipolar junction transistor Q11 is connected to the node g, the emitter of the yth bipolar junction transistor Q1y is connected to the node i, the collectors of the other bipolar junction transistors are connected to the emitter of the previous bipolar junction transistor, and the emitters of the other bipolar junction transistors are connected to the collector of the next bipolar junction transistor.

[0112] Furthermore, the gates of the z MOSFETs MN11 to MN1z of the third group receive the input signal IN. Furthermore, among the z MOSFETs MN11 to MN1z of the third group, the drain of the first MOSFET MN11 is connected to the node i, and the source of the z MOSFET MN1z is connected to the ground voltage GND. The drains of the other MOSFETs are connected to the source of the previous MOSFET, and the sources of the other MOSFETs are connected to the drain of the next MOSFET.

[0113] The load circuit 536 receives the inverted input signal ZIN, and the bases of the second group of y bipolar junction transistors Q21-Q2y are connected to the load circuit 536. Furthermore, among the second group of y bipolar junction transistors Q21-Q2y, the collector of the first bipolar junction transistor Q21 is connected to the node f, the emitter of the yth bipolar junction transistor Q2y is connected to the node h, the collectors of the other bipolar junction transistors are connected to the emitter of the previous bipolar junction transistor, and the emitters of the other bipolar junction transistors are connected to the collector of the next bipolar junction transistor.

[0114] Furthermore, the gates of the z MOSFETs MN21-MN2z of the fourth group receive the inverted input signal ZIN. Furthermore, among the z MOSFETs MN21-MN2z of the fourth group, the drain of the first MOSFET MN21 is connected to the node h, and the source of the z MOSFET MN2z is connected to the ground voltage GND. The drains of the other MOSFETs are connected to the source of the previous MOSFET, and the sources of the other MOSFETs are connected to the drain of the next MOSFET.

[0115] Basically, the operation of the transformer 530 of the third embodiment is similar to Figure 5B and Figure 5C , which will not be described in detail here. Among them, the load circuits 534 and 536 in the converter 530 of the third embodiment can be composed of resistors, such as polysilicon resistors. In addition, without considering the size of the base current, the load circuits 534 and 536 can also be omitted. In other words, the resistance value in the load circuits 534 and 536 can be greater than or equal to zero. When the resistance value of the resistor in the load circuits 534 and 536 is equal to zero, it means that the bases of the y bipolar junction transistors Q11~Q1y in the first group directly receive the input signal IN, and the bases of the y bipolar junction transistors Q21~Q2y in the second group directly receive the inverted input signal ZIN.

[0116] According to the third embodiment of the present invention, the load circuits 534 and 536 have two different examples, as described below. Fig. 5F and Figure 5G , which is illustrated as an example of two load circuits in the third embodiment.

[0117] like Fig. 5FAs shown, the load circuit 534 includes y resistors r11-r1y, the first ends of the y resistors r11-r1y receive the input signal IN, and the second ends of the y resistors r11-r1y are connected to the bases of the corresponding y bipolar junction transistors Q11-Q1y. The load circuit 536 includes y resistors r21-r2y, the first ends of the y resistors r21-r2y receive the inverted input signal ZIN, and the second ends of the y resistors r21-r2y are connected to the bases of the corresponding y bipolar junction transistors Q21-Q2y.

[0118] like Figure 5G As shown, the load circuit 534 includes a resistor rc, a first end of the resistor rc receives the input signal IN, and a second end of the resistor rc is connected to all bases of y bipolar junction transistors Q11-Q1y. The load circuit 536 includes a resistor rd, a first end of the resistor rd receives the inverted input signal ZIN, and a second end of the resistor rd is connected to all bases of y bipolar junction transistors Q21-Q2y.

[0119] In summary, the present invention provides a voltage converter. The voltage converter of the present invention can be a single-ended type level shifter or a differential type level shifter. Furthermore, the manufacturing of the voltage converter is compatible with the current CMOS process technology, and no additional special process technology is required. Furthermore, the voltage converter does not need to receive a bias voltage Vbias to operate normally.

[0120] In addition, in the above embodiment of the present invention, the function of the load circuit is to suppress the base current of the bipolar junction transistor in the converter to save unnecessary power consumption. In addition, in the above embodiment of the present invention, the function of the load circuit can further limit the collector current of the bipolar junction transistor in the converter to avoid unnecessary latch-up problems.

[0121] In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A voltage converter, which converts an input signal having a signal range between a first power supply voltage and a ground voltage into an output signal having a signal range between a second power supply voltage and the ground voltage, the voltage converter comprising: a first load circuit, a first end of the first load circuit receiving the second power supply voltage; a second load circuit, a first end of the second load circuit receiving the input signal; a bipolar junction transistor, wherein the collector of the bipolar junction transistor is connected to the second end of the first load circuit, and the base of the bipolar junction transistor is connected to the second end of the second load circuit; a first metal oxide semiconductor field effect transistor, wherein a drain of the first metal oxide semiconductor field effect transistor is connected to an emitter of the bipolar junction transistor, a source of the first metal oxide semiconductor field effect transistor receives the ground voltage, and a gate of the first metal oxide semiconductor field effect transistor receives the input signal; as well as A NOT gate, wherein a first power supply terminal of the NOT gate receives the second power supply voltage, a second power supply terminal of the NOT gate receives the ground voltage, an input terminal of the NOT gate is connected to the first load circuit, and an output terminal of the NOT gate generates the output signal.

2. The converter as claimed in claim 1, wherein the first load circuit comprises a first resistor, a first end of the first resistor receives the second power supply voltage, a second end of the first resistor is connected to a first node, the collector of the bipolar junction transistor is connected to the first node, and the input end of the NOT gate is connected to the first node.

3. The converter as described in claim 1, wherein the first load circuit includes a second metal oxide semiconductor field effect transistor, the source of the second metal oxide semiconductor field effect transistor receives the second power supply voltage, the drain of the second metal oxide semiconductor field effect transistor is connected to the first node, the gate of the second metal oxide semiconductor field effect transistor receives the ground voltage, the collector of the bipolar junction transistor is connected to the first node, and the input of the NOT gate is connected to the first node.

4. The converter as claimed in claim 1, wherein the first load circuit includes x sub-load circuits, the x sub-load circuits are connected between the second power supply voltage and the first node, the collector of the bipolar junction transistor is connected to the first node, the input end of the NOT gate is connected to the first node, and x is an integer greater than 1. 5 . The converter as claimed in claim 4 , wherein the x sub-load circuits are composed of x resistors, and the x resistors are connected in series between the second power supply voltage and the first node.

6. A converter as described in claim 4, wherein the x sub-load circuits are composed of x metal oxide semiconductor field effect transistors, and the x metal oxide semiconductor field effect transistors are P-type transistors; the gates of the x P-type transistors receive the ground voltage; among the x P-type transistors, the source of the first P-type transistor receives the second power supply voltage, the drain of the xth P-type transistor is connected to the first node, the sources of the other P-type transistors are connected to the drain of the previous P-type transistor, and the drains of the other P-type transistors are connected to the source of the next P-type transistor.

7. A converter as described in claim 1, wherein the first load circuit includes x sub-load circuits, the x sub-load circuits are connected between the second power supply voltage and the first node, the collector of the bipolar junction transistor is connected to the first node, the input of the NOT gate is connected to a second node between the second power supply voltage and the first node, and x is an integer greater than 1. 8 . The converter as claimed in claim 1 , wherein the second load circuit comprises a second resistor, a first end of the second resistor receives the input signal, and a second end of the resistor is connected to the base of the bipolar junction transistor. 9 . The converter as claimed in claim 8 , wherein a resistance value of the second resistor is greater than or equal to zero.

10. A voltage converter, which converts an input signal having a signal range between a first power supply voltage and a ground voltage into an output signal having a signal range between a second power supply voltage and the ground voltage, the voltage converter comprising: a first load circuit, a first end of the first load circuit receiving the second power supply voltage; a second load circuit, a first end of the second load circuit receiving the input signal; y bipolar junction transistors, wherein the bases of the y bipolar junction transistors are connected to the second load circuit, and y is an integer greater than or equal to 1; among the y bipolar junction transistors, the collector of a first bipolar junction transistor is connected to the second end of the first load circuit, the emitter of the yth bipolar junction transistor is connected to the first node, the collectors of the other bipolar junction transistors are connected to the emitter of the previous bipolar junction transistor, and the emitters of the other bipolar junction transistors are connected to the collector of the next bipolar junction transistor; z metal oxide semiconductor field effect transistors, wherein the gates of the z metal oxide semiconductor field effect transistors receive the input signal, z is an integer greater than or equal to 1, and y and z are not 1 at the same time; among the z metal oxide semiconductor field effect transistors, the drain of the first metal oxide semiconductor field effect transistor is connected to the first node, the source of the zth metal oxide semiconductor field effect transistor receives the ground voltage, the drains of the other metal oxide semiconductor field effect transistors are connected to the source of the previous metal oxide semiconductor field effect transistor, and the sources of the other metal oxide semiconductor field effect transistors are connected to the drain of the next metal oxide semiconductor field effect transistor; as well as A NOT gate, wherein a first power supply terminal of the NOT gate receives the second power supply voltage, a second power supply terminal of the NOT gate receives the ground voltage, an input terminal of the NOT gate is connected to the first load circuit, and an output terminal of the NOT gate generates the output signal.

11. The converter as claimed in claim 10, wherein the second load circuit comprises y resistors, first ends of the y resistors receive the input signal, and second ends of the y resistors are connected to bases of the corresponding y bipolar junction transistors. 12 . The converter as claimed in claim 10 , wherein the second load circuit comprises a resistor, a first end of the resistor receives the input signal, and a second end of the resistor is connected to bases of the y BJTs.

13. The converter as claimed in claim 12, wherein a resistance value of the resistor is greater than or equal to zero.

14. A converter, which converts an input signal and an inverted input signal in a signal range between a first power supply voltage and a ground voltage into an output signal in a signal range between a second power supply voltage and the ground voltage, the converter comprising: a first load circuit, the first load circuit being connected to the second power supply voltage, the first node and the second node, and the voltage of the second node being the output signal; a second load circuit, a first end of the second load circuit receiving the input signal; a third load circuit, a first end of the third load circuit receiving the inverted input signal; a first bipolar junction transistor, wherein a collector of the first bipolar junction transistor is connected to the first node, and a base of the first bipolar junction transistor is connected to the second end of the second load circuit; a second bipolar junction transistor, wherein a collector of the second bipolar junction transistor is connected to the second node, and a base of the second bipolar junction transistor is connected to the second end of the third load circuit; a first metal oxide semiconductor field effect transistor, wherein a drain of the first metal oxide semiconductor field effect transistor is connected to an emitter of the first bipolar junction transistor, a source of the first metal oxide semiconductor field effect transistor receives the ground voltage, and a gate of the first metal oxide semiconductor field effect transistor receives the input signal; as well as A second metal oxide semiconductor field effect transistor, wherein the drain of the second metal oxide semiconductor field effect transistor is connected to the emitter of the second bipolar junction transistor, the source of the second metal oxide semiconductor field effect transistor receives the ground voltage, and the gate of the second metal oxide semiconductor field effect transistor receives the inverted input signal.

15. A converter as described in claim 14, wherein the first load circuit includes a third metal oxide semiconductor field effect transistor and a fourth metal oxide semiconductor field effect transistor; the source of the third metal oxide semiconductor field effect transistor receives the second power supply voltage, the drain of the third metal oxide semiconductor field effect transistor is connected to the first node, and the gate of the third metal oxide semiconductor field effect transistor is connected to the second node; the source of the fourth metal oxide semiconductor field effect transistor receives the second power supply voltage, the drain of the fourth metal oxide semiconductor field effect transistor is connected to the second node, and the gate of the fourth metal oxide semiconductor field effect transistor is connected to the first node.

16. A converter as described in claim 14, wherein the first load circuit includes a third metal oxide semiconductor field effect transistor, a fourth metal oxide semiconductor field effect transistor, a first resistor and a second resistor; the source of the third metal oxide semiconductor field effect transistor receives the second power supply voltage, the drain of the third metal oxide semiconductor field effect transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first node, and the gate of the third metal oxide semiconductor field effect transistor is connected to the second node; the source of the fourth metal oxide semiconductor field effect transistor receives the second power supply voltage, the drain of the fourth metal oxide semiconductor field effect transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the second node, and the gate of the fourth metal oxide semiconductor field effect transistor is connected to the first node.

17. A converter as described in claim 14, wherein the second load circuit includes a first resistor, and the third load circuit includes a second resistor; the first end of the first resistor receives the input signal, and the second end of the first resistor is connected to the base of the first bipolar junction transistor; the first end of the second resistor receives the inverted input signal, and the second end of the second resistor is connected to the base of the second bipolar junction transistor. 18 . The converter as claimed in claim 17 , wherein a resistance value of the first resistor is greater than or equal to zero, and a resistance value of the second resistor is greater than or equal to zero.

19. A converter, which converts an input signal and an inverted input signal in a signal range between a first power supply voltage and a ground voltage into an output signal in a signal range between a second power supply voltage and the ground voltage, the converter comprising: a first load circuit, the first load circuit being connected to the second power supply voltage, the first node and the second node, and the voltage of the second node being the output signal; a second load circuit, a first end of the second load circuit receiving the input signal; a third load circuit, a first end of the third load circuit receiving the inverted input signal; A first group of y bipolar junction transistors, wherein the bases of the y bipolar junction transistors of the first group are connected to the second load circuit, and y is an integer greater than or equal to 1; among the y bipolar junction transistors of the first group, the collector of a first bipolar junction transistor is connected to the first node, the emitter of a yth bipolar junction transistor is connected to a third node, the collectors of the other bipolar junction transistors are connected to the emitter of a previous bipolar junction transistor, and the emitters of the other bipolar junction transistors are connected to the collector of a subsequent bipolar junction transistor; a second group of y bipolar junction transistors, wherein the bases of the y bipolar junction transistors of the second group are connected to the third load circuit; among the y bipolar junction transistors of the second group, the collector of a first bipolar junction transistor is connected to the second node, the emitter of a yth bipolar junction transistor is connected to the fourth node, the collectors of the other bipolar junction transistors are connected to the emitter of the previous bipolar junction transistor, and the emitters of the other bipolar junction transistors are connected to the collector of the next bipolar junction transistor; a third group of z metal oxide semiconductor field effect transistors, wherein the gates of the z metal oxide semiconductor field effect transistors of the third group receive the input signal, z is an integer greater than or equal to 1, and y and z are not 1 at the same time; among the z metal oxide semiconductor field effect transistors of the third group, the drain of a first metal oxide semiconductor field effect transistor is connected to the third node, the source of the zth metal oxide semiconductor field effect transistor receives the ground voltage, the drains of the other metal oxide semiconductor field effect transistors are connected to the source of the previous metal oxide semiconductor field effect transistor, and the sources of the other metal oxide semiconductor field effect transistors are connected to the drain of the next metal oxide semiconductor field effect transistor; as well as a fourth group of z metal oxide semiconductor field effect transistors, wherein gates of the z metal oxide semiconductor field effect transistors of the fourth group receive the inverted input signal; Among the z metal oxide semiconductor field effect transistors of the fourth group, the drain of the first metal oxide semiconductor field effect transistor is connected to the fourth node, the source of the zth metal oxide semiconductor field effect transistor receives the ground voltage, the drains of the other metal oxide semiconductor field effect transistors are connected to the source of the previous metal oxide semiconductor field effect transistor, and the sources of the other metal oxide semiconductor field effect transistors are connected to the drain of the next metal oxide semiconductor field effect transistor.

20. The converter as claimed in claim 19, wherein the second load circuit comprises y resistors, the first ends of the y resistors in the second load circuit receive the input signal, and the second ends of the y resistors in the second load circuit are connected to the bases of the corresponding y bipolar junction transistors in the first group; the third load circuit comprises y resistors, the first ends of the y resistors in the third load circuit receive the inverted input signal, and the second ends of the y resistors in the third load circuit are connected to the bases of the corresponding y bipolar junction transistors in the second group.

21. The converter as described in claim 19, wherein the second load circuit includes a first resistor, a first end of the first resistor receives the input signal, and a second end of the first resistor is connected to the bases of the y bipolar junction transistors in the first group; the third load circuit includes a second resistor, a first end of the second resistor receives the inverted input signal, and a second end of the second resistor is connected to the bases of the y bipolar junction transistors in the second group; wherein the resistance value of the first resistor is greater than or equal to zero, and the resistance value of the second resistor is greater than or equal to zero.

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