Dual-CDAC switch switching strategy circuit applied to SAR ADC

Abstract

The invention provides a dual-CDAC single-capacitor switch switching circuit applied to an SAR ADC. The dual-CDAC single-capacitor switch switching circuit comprises a non-overlapping clock generation source, and an SAR logic structure corresponding to a switching circuit related to innovative CDAC and CADC. According to the novel switching circuit, through the structure of the two sub CADCs, the sub CADCs are selected in the first switching process, overall reference voltage switching is adopted in the subsequent switching process, only switching of a single capacitor is involved in the subsequent switching process, the switching mode is simple, the aim of low power consumption of the SAR ADC is achieved, meanwhile, the total number of the capacitors is reduced, and the switching efficiency is improved. The area of the whole module is reduced, and the cost is saved.

Description

Technical Field

[0001] The invention relates to a SAR ADC switch capacitor switching strategy circuit, belongs to the technical field of analog integrated circuits, and is mainly applied to a SAR ADC analog-to-digital converter. Background Art

[0002] The successive approximation ADC (SAR ADC) has attracted attention in the fields of biomedicine, sensors and other low-power applications due to its simple structure, small chip area, low power consumption and good digital process compatibility. With the gradual improvement of accuracy, the requirements for SAR ADC are also gradually increasing, such as the number of CDAC capacitors increases exponentially by 2 and the increase in power consumption when switching the CADC capacitor array. The traditional switch switching strategy predicts the result first and then compares it, and then modifies the last prediction result or continues to predict the next result based on the comparison result. This switching strategy requires repeated switching of the switch, resulting in a large amount of power consumption, and has high requirements for the switching speed, which often becomes a bottleneck. Later, the monotonic switch switching strategy was proposed, which adopts the method of comparing first and then switching. After each comparison, the voltage is switched from Vref to GND to avoid frequent switching. Compared with the traditional switching strategy, it has obvious energy efficiency advantages, but the reference voltage value changes greatly during the switch switching, so the power consumption overhead generated during the switching is still very large. The above studies have proved the advantages of the switch strategy with Vcm as the intermediate reference voltage in terms of power consumption, but the capacitance of CDAC increases exponentially, so the power consumption overhead brought by the architecture itself increases exponentially by 2. Only by optimizing the CDAC architecture under the same accuracy can the power consumption overhead be qualitatively changed. Therefore, we will further reduce the energy consumption by optimizing the CDAC architecture based on Vcm as the reference voltage. A dual CDAC switch strategy with a simpler architecture is proposed. This switching strategy determines the selection of CDAC through the first comparison of two sub-CDAC structures. The subsequent comparison only involves the switching of the capacitance at a single position in CDAC. The highest two bits of resolution do not generate power consumption. This switching strategy can achieve higher-precision resolution with the same number of CDAC capacitors, and the energy consumption overhead is lower during each switch.

[0003] In summary, although SAR ADC is already a low-power ADC, there is still a lot of room for research and development in the structure and switching strategy of CDAC to achieve higher performance and lower power consumption. This patent aims to propose a new SAR ADC switching circuit. Compared with the traditional SAR CDAC structure, under the same accuracy conditions, although one CDAC is added, the number of CADC capacitors is reduced from the traditional 2 n-1 Reduced to 2 n-2This saves half of the capacitor cost, reduces the total number of capacitors to reduce the layout area, and optimizes the switching strategy to reduce power consumption and improve the performance of SAR ADC. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a new CDAC switching circuit for SAR ADC. By simply improving its switching method, the goal of ultra-low power consumption of SAR ADC is achieved, and the switching strategy can achieve higher precision resolution under the same number of CDAC capacitors.

[0005] The technical solution to achieve the purpose of the present invention is:

[0006] A switching circuit of a high-efficiency dual-CDAC single-capacitor switch applied to a SAR ADC includes a non-overlapping clock generation source; a switched capacitor circuit for implementing sampling and quantization of the SAR ADC; and a novel switch switching circuit is applied in the CDAC to achieve the design goal of ultra-low power consumption of the SAR ADC.

[0007] Figure 1 Among the switches S1-S16 shown in the figure, S1, S3, S5, and S7 are bootstrap switches, and the remaining switches are CMOS switches. The 4-bit dual CDAC switch capacitor circuit includes C1-C8 capacitors and S1-S8 switches. C1-C4 and S1-S4, C5-C8 and S5-S8 respectively constitute two sub-CDACs, wherein C1, C2 and C3, C4 are the capacitor arrays at both ends of the differential input P and N of one sub-CDAC, and C5, C6 and C7, C8 are the capacitor arrays at both ends of the differential input P and N of the other sub-CDAC, and their capacitance values ​​are all unit capacitance C.

[0008] In the upper sub-CDAC, one end of S1 and S3 is connected to the input terminal Vip and Vin respectively, and the other end is connected to the upper plate of C1, C2, C3, and C4; one end of S2 and S4 is connected to the comparator Vxp and Vxn respectively, and the other end is connected to the upper plate of C1, C2, C3, and C4; one end of S9 and S10 is connected to the lower plate of C1 and C2 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively; one end of S11 and S12 is connected to the lower plate of C3 and C4 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively, where Vcm is half of Vref; In the sub-CDAC on the lower side, one end of S5 and S7 is connected to the input terminal Vip and Vin respectively, and the other end is connected to the upper plates of C5, C6, C7, and C8; one end of S6 and S8 is connected to Vxp and Vxn of the comparator respectively, and the other end is connected to the upper plates of C5, C6, C7, and C8; one end of S13 and S14 is connected to the lower plates of C5 and C6 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively; one end of S15 and S16 is connected to the lower plates of C7 and C8 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively, where Vcm is half of Vref. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of the switching process of the switch switching circuit proposed in the present invention.

[0010] Figure 2 This is a structural diagram of the switch switching circuit used in the present invention. DETAILED DESCRIPTION

[0011] A novel SAR ADC switch capacitor switching strategy circuit structure. In order to make the purpose and technical advantages of the present invention clearer, the specific implementation of the present invention is described below with reference to the accompanying drawings and examples, but the following description does not limit the scope of application of the present invention.

[0012] like Figure 1 Shown is a circuit structure diagram of the present invention, Figure 2 It is a specific implementation scheme of the SAR ADC switch capacitor switching strategy, which includes a comparator, a dual CDAC, a dual CADC single capacitor switching strategy in the present invention, and corresponding SAR logic and other basic structures.

[0013] First, in the sampling phase, S1, S2, S3, S4, S5, S6, S7, and S8 are closed, and the two ends of the differential input are connected to the two sub-CDACs respectively. The two sub-CDAC differential sides are connected to Vref and GND respectively, that is, C3, C4, C5, and C6 are connected to Vref, and C1, C2, C7, and C8 are connected to GND, so as to complete the sampling. After the sampling is completed, S1, S3, S5, and S7 are disconnected. In this case, by comparing the size of the sampled Vxp and Vxn, Vxp = Vip, Vxn = Vin, if Vip is greater than Vin, then the highest bit B[3] of the SAR ADC output is 1, otherwise it is output 0, thereby determining the highest bit B[3]. No charge redistribution occurs in this process, so no energy consumption is generated.

[0014] In the second stage, the dual CDAC single capacitor switch strategy in the present invention starts working. If in the sampling stage, Vip is greater than Vin, that is, B[3]=1, S2 and S4 are disconnected, the capacitor connected to Vref at the P end is switched to Vcm, and the capacitor connected to GND at the N end is also switched to Vcm, that is, C5 and C6 are switched from Vref to Vcm, and C7 and C8 are switched from GND to Vcm. At this time, Vxp=Vip-Vcm, Vxn=Vin+Vcm, if Vxp is greater than Vxn, that is, Vip is greater than Vin+2Vcm, then the second highest bit of the SAR ADC output B[2]=1, otherwise B[2]=0;

[0015] If Vip is less than Vin, that is, B[3]=0, S6 and S8 are disconnected, the capacitor connected to GND at the P end is switched to Vcm, and the capacitor connected to Vref at the N end is also switched to Vcm, that is, C1 and C2 are switched from GND to Vcm, and C3 and C4 are switched from Vref to Vcm. At this time, Vxp=Vip+Vcm, Vxn=Vin-Vcm. If Vxp is greater than Vxn, that is, Vip is greater than Vin-2Vcm, then B[2]=1, otherwise B[2]=0. Therefore, the second highest bit B[2] is determined. No charge redistribution occurs in this process, so no energy consumption is generated.

[0016] In the third stage, since there are four combinations of B[3]B[2]: 00, 01, 10, and 11, take case A as an example, B[3]B[2] is 11. At this time, S2 and S4 are still open, S6 and S8 are closed, and the capacitor connected to Vcm at the P end is switched to GND, that is, C5 and C6 are switched from Vcm to GND. At this time, Vxp = Vip-Vcm, Vxn = Vin+2Vcm. If Vxp is greater than Vxn, that is, Vip is greater than Vin+3Vcm, then the third bit B[1] of the SAR ADC output is 1, otherwise B[1] is 0. When B[1]=1, the capacitor connected to Vcm at the N terminal is switched to Vref, that is, C7 is switched from Vcm to Vref. At this time, Vxp=Vip-3 / 2Vcm, Vxn=Vin+2Vcm. If Vxp is greater than Vxn, that is, Vip is greater than Vin+7 / 2Vcm, then the lowest bit of the SAR ADC output B[0]=1, otherwise B[0]=0. Charge redistribution occurs in the third stage, so power consumption is generated.

Claims

1. A dual CDAC switch switching strategy circuit applied to SAR ADC, characterized in that: Among the switches S1-S16, S1, S3, S5, and S7 are bootstrap switches, and the remaining switches are CMOS switches; the 4-bit dual CDAC switch capacitor circuit includes C1-C8 capacitors and S1-S8 switches; C1-C4 and S1-S4, C5-C8 and S5-S8 respectively constitute two sub-CDACs, wherein C1, C2 and C3, C4 are capacitor arrays at both ends of the differential input P and N of one of the sub-CDACs, and C5, C6 and C7, C8 are capacitor arrays at both ends of the differential input P and N of the other sub-CDAC; In the upper sub-CDAC, one end of S1 and S3 is connected to the input terminal Vip and Vin respectively, and the other end is connected to the upper plate of C1, C2, C3, and C4; one end of S2 and S4 is connected to the comparator Vxp and Vxn respectively, and the other end is connected to the upper plate of C1, C2, C3, and C4; one end of S9 and S10 is connected to the lower plate of C1 and C2 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively; one end of S11 and S12 is connected to the lower plate of C3 and C4 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively, where Vcm is half of Vref; In the sub-CDAC on the lower side, one end of S5 and S7 is connected to the input terminal Vip and Vin respectively, and the other end is connected to the upper plates of C5, C6, C7, and C8; one end of S6 and S8 is connected to Vxp and Vxn of the comparator respectively, and the other end is connected to the upper plates of C5, C6, C7, and C8; one end of S13 and S14 is connected to the lower plates of C5 and C6 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively; one end of S15 and S16 is connected to the lower plates of C7 and C8 respectively, and the other end is connected to the voltage reference Vref, Vcm, and GND respectively, where Vcm is half of Vref.

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