Power efficient successive approximation analog-to-digital converter

Abstract

Systems and methods for power efficient successive approximation analog-to-digital converters (SAR ADCs) are disclosed herein. In one aspect, the SAR ADC includes a sampling and digital-to-analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of memory circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of memory circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of a plurality of bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the plurality of bits during a corresponding time period.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202110490416.6, application date May 6, 2021, and invention name “Power-Efficient Successive Approximation Analog / Digital Converter”. Technical Field

[0003] The present disclosure relates generally to communication systems, including but not limited to power efficient successive approximation analog-to-digital converters (SAR-ADCs). Background Art

[0004] The latest developments in communication and computing devices require high data rates. For example, network switches, routers, hubs, or any communication device can exchange data at high speeds (e.g., 1 Mbps to 100 Gbps) to stream data in real time or process large amounts of data in a seamless manner. To improve bandwidth efficiency, the amplitude or voltage of a signal can represent multiple bits, and the signal can be exchanged between two or more communication devices through a cable or wireless medium. For example, a 1.2V signal can represent [00010110], and a 1.3V signal can represent [00011001]. In order to convert the voltage of an input signal into a corresponding bit, some communication devices implement a SAR ADC. For example, a SAR ADC can determine a number of bits corresponding to an input signal by successive approximation. Summary of the invention

[0005] Various embodiments disclosed herein relate to a device for data communication. In some embodiments, the device includes a sampling and digital / analog conversion (DAC) circuit for sampling an input voltage to obtain a first sampled voltage. In some embodiments, the device includes a first comparator coupled to the sampling and DAC circuit. In some embodiments, the device includes a first set of storage circuits coupled to the first comparator and the sampling and DAC circuit. In some embodiments, the first set of storage circuits is configured to store the state of a first subset of a plurality of bits corresponding to the input voltage. In some embodiments, the device includes a second comparator coupled to the sampling and DAC circuit. In some embodiments, the device includes a second set of storage circuits coupled to the second comparator and the sampling and DAC circuit. In some embodiments, the second set of storage circuits is configured to store the state of a second subset of the plurality of bits corresponding to the input voltage. In some embodiments, the device includes a control circuit coupled to the first comparator and the second comparator. The control circuit may be configured to select the first comparator to determine the state of the target bit in the plurality of bits corresponding to the input voltage during a first time period. The first comparator may determine the state of the target bit according to the first sampled voltage.

[0006] In some embodiments, the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator.

[0007] In some embodiments, a corresponding one of the first set of storage circuits is configured to store the determined state of the target bit.

[0008] In some embodiments, the control circuit is configured to select another target bit of the plurality of bits during a second time period, and the second comparator is configured to determine the state of the other target bit. In some embodiments, the control circuit is configured to select the first comparator during the first time period and select the second comparator during the second time period according to a predetermined sequence. In some embodiments, the sampling and DAC circuit is configured to sample the input voltage based at least in part on the state of the target bit to obtain a second sampled voltage. In some embodiments, the second comparator is configured to determine the state of the other target bit based on the second sampled voltage. In some embodiments, a corresponding one of the second set of storage circuits is configured to store the determined state of the other target bit.

[0009] In some embodiments, the control circuit is configured to select the first comparator for the target bit in response to the target bit being one of the first subset of the plurality of bits.

[0010] In some embodiments, an output of the first comparator is directly coupled to an input port of the first group of storage circuits, wherein an output of the second comparator is directly coupled to an input port of the second group of storage circuits.

[0011] Various embodiments disclosed herein relate to an apparatus for data communication. In some embodiments, the apparatus includes a receiver. In some embodiments, the receiver includes a sampling and digital / analog conversion (DAC) circuit for sampling an input voltage. In some embodiments, the receiver includes a first comparator coupled to the sampling and DAC circuit. In some embodiments, the receiver includes a first set of storage circuits coupled between the first comparator and the sampling and DAC circuit. In some embodiments, the receiver includes a second comparator coupled to the sampling and DAC circuit. In some embodiments, the receiver includes a second set of storage circuits coupled between the second comparator and the sampling and DAC circuit. In some embodiments, the receiver includes a control circuit configured to select a corresponding comparator from the first comparator and the second comparator for each of a plurality of bits corresponding to the input voltage to determine the state of each of the plurality of bits during a corresponding time period. In some embodiments, the apparatus includes a processor coupled to the receiver. In some embodiments, the processor is configured to receive the states of the plurality of bits from the first set of storage circuits and the second set of storage circuits, and perform logic calculations based on the received states of the plurality of bits.

[0012] In some embodiments, the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator.

[0013] In some embodiments, the control circuit is configured to select the first comparator for a first subset of the plurality of bits and to select the second comparator for a second subset of the plurality of bits.

[0014] In some embodiments, the sampling and DAC circuit is configured to sample the input voltage for a first bit of the plurality of bits to obtain a first sampled voltage. In some embodiments, the first comparator is configured to determine a state of the first bit of the plurality of bits based on the first sampled voltage. In some embodiments, the corresponding one of the first set of storage circuits is configured to store the determined state of the first bit of the plurality of bits. In some embodiments, based at least in part on the determined state of the first bit of the plurality of bits from the corresponding one of the first set of storage circuits, the sampling and DAC circuit is configured to sample the input voltage for a second bit of the plurality of bits to obtain a second sampled voltage. In some embodiments, the second comparator is configured to determine a state of the second bit of the plurality of bits based on the second sampled voltage.

[0015] In some embodiments, an output of the first comparator is directly coupled to an input port of the first group of storage circuits, wherein an output of the second comparator is directly coupled to an input port of the second group of storage circuits.

[0016] Various embodiments disclosed herein relate to a method for data communication. In some embodiments, the method includes sampling an input voltage by a sampling and digital / analog conversion (DAC) circuit to obtain a first sampled voltage. In some embodiments, the method includes determining a state of a first bit of a plurality of bits corresponding to the input voltage according to the first sampled voltage by a first comparator coupled to a first set of storage circuits. In some embodiments, the method includes sampling the input voltage by the sampling and DAC circuit to obtain a second sampled voltage. In some embodiments, the method includes determining a state of a second bit of the plurality of bits according to the second sampled voltage by a second comparator coupled to a second set of storage circuits different from the first set of storage circuits.

[0017] In some embodiments, the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator.

[0018] In some embodiments, the method includes storing the determined state of the first bit by a corresponding one of the first set of storage circuits, and storing the determined state of the second bit by a corresponding one of the second set of storage circuits. In some embodiments, sampling the input voltage by the sampling and DAC circuit to obtain the second sampled voltage is based at least in part on the determined state of the first bit stored by the corresponding one of the first set of storage circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0020] Figure 1A is a block diagram depicting a network environment including one or more access points in communication with one or more devices or stations in accordance with one or more embodiments.

[0021] Figure 1B and 1C is a block diagram depicting a computing device that may be used in conjunction with the methods and systems described herein, according to one or more embodiments.

[0022] Figure 2 is a block diagram depicting a communication device in accordance with one or more embodiments.

[0023] Figure 3 is a schematic diagram of a SAR ADC according to one or more embodiments.

[0024] Figure 4 is a method of demonstrating the Figure 3 Timing diagram of the operation of the SAR ADC.

[0025] Figure 5 is a flow chart depicting a process of determining a plurality of bits corresponding to an input voltage by successive approximation in accordance with one or more embodiments.

[0026] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0027] In order to read the description of the various embodiments below, the following description of the various sections of the specification and their corresponding contents may be useful:

[0028] - Section A describes a network environment and a computing environment that can be used to practice the embodiments described herein; and

[0029] - Section B describes embodiments of systems and methods for a power efficient SAR ADC according to one or more embodiments.

[0030] A. Computing and Network Environment

[0031] Before discussing specific embodiments of the present solution, it is helpful to describe aspects of the operating environment and associated system components (eg, hardware elements) in conjunction with the methods and systems described herein. Figure 1A, depicting an embodiment of a network environment. Briefly, the network environment includes a wireless communication system, which includes one or more access points (APs) 106, one or more wireless communication devices 102, and network hardware components 192. The wireless communication device 102 may, for example, include a laptop computer 102, a tablet computer 102, a personal computer 102, and / or a cellular telephone device 102. Figure 1B and 1C The details of the embodiments of each wireless communication device 102 and / or AP 106 are described in more detail. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, etc. AP 106 may be operably coupled to network hardware 192 via a local area network connection. Network hardware 192, which may include routers, gateways, switches, bridges, modems, system controllers, appliances, etc., may provide a local area network connection for the communication system. Each of AP 106 may have an associated antenna or antenna array to communicate with wireless communication devices in its area. Wireless communication devices 102 may register with a specific AP 106 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communications), some wireless communication devices may communicate directly via allocated channels and communication protocols. Some of the wireless communication devices 102 may be mobile or relatively stationary relative to AP 706.

[0032] In some embodiments, AP 106 includes a device or module (including a combination of hardware and software) that allows wireless communication device 102 to connect to a wired network using wireless fidelity (WiFi) or other standards. AP 106 may sometimes be referred to as a wireless access point (WAP). AP 106 may be implemented (e.g., configured, designed and / or constructed) to operate in a wireless local area network (WLAN). In some embodiments, AP 106 may be connected to a router (e.g., via a wired network) as a standalone device. In other embodiments, an access point may be a component of a router. AP 106 may provide access to a network for multiple devices. AP 106 may, for example, be connected to a wired Ethernet connection and use a radio frequency link to provide wireless connections for other devices 102 to utilize the wired connection. AP 106 may be implemented to support standards for sending and receiving data using one or more radio frequencies. These standards and the frequencies they use may be defined by IEEE (e.g., IEEE 802.11 standards). AP 106 may be configured and / or used to support public Internet hotspots and / or on a network for extending the Wi-Fi signal range of the network.

[0033] In some embodiments, the access point 106 may be used for a wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency based network protocol, and / or variants thereof) (e.g., within a home or within a building). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access points 106 may operate in accordance with various aspects of the present disclosure presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to networked nodes such as servers) via one or more access points 106.

[0034] The network connection may include any type and / or form of network, and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, a computer network. The topology of the network may be a bus, a star, or a ring network topology. The network may be any such network topology known to those skilled in the art that is capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0035] The communication device 102 and the access point 106 may be deployed as and / or executed on any type and form of computing device, such as a computer, network device, or appliance capable of communicating over any type and form of network and performing the operations described herein. Figure 1B and 1C A block diagram of a computing device 100 is depicted for practicing an embodiment of a wireless communication device 102 or AP 106. Figure 1B and 1C As shown, each computing device 100 includes a central processing unit 121 and a main memory unit 122. Figure 1B As shown, computing device 100 may include storage device 128, installation device 116, network interface 118, I / O controller 123, display devices 124a to 124n, keyboard 126, and pointing device 127 (e.g., mouse). Storage device 128 may include an operating system and / or software. Figure 1C As shown, each computing device 100 may also include additional optional elements that communicate with the central processing unit 121, such as a memory port 103, a bridge 170, one or more input / output devices 130a to 130n, and a cache memory 140.

[0036] The central processing unit 121 is any logic circuit that responds to and processes instructions retrieved from the main memory unit 122. In many embodiments, the central processing unit 121 is provided by a microprocessor unit, such as: a microprocessor unit manufactured by Intel Corporation of Santa Clara, California; a microprocessor unit manufactured by International Business Machines of White Plains, New York; or a microprocessor unit manufactured by Advanced Micro Devices of Sunnyvale, California. The computing device 100 may be based on any of these processors or any other processor capable of operating as described herein.

[0037] The main memory unit 122 may be one or more memory chips capable of storing data and allowing any storage location to be directly accessed by the microprocessor 121, such as static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and any type or variation of solid-state drive (SSD). The main memory 122 may be based on any of the above-mentioned memory chips or any other available memory chip capable of operating as described herein. Figure 1B In the illustrated embodiment, processor 121 communicates with main memory 122 via a system bus 150 (described in greater detail below). Figure 1C An embodiment of computing device 100 is depicted in which the processor communicates directly with main memory 122 via memory port 103. For example, in Figure 1C In the embodiment, the main memory 122 may be DRDRAM.

[0038] Figure 1C An embodiment is depicted in which the main processor 121 communicates directly with the cache memory 140 via a secondary bus (sometimes referred to as a backside bus). In other embodiments, the main processor 121 communicates with the cache memory 140 using the system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1CIn the illustrated embodiment, the processor 121 communicates with various I / O devices 130 via a local system bus 150. Various buses may be used to connect the central processing unit 121 to any of the I / O devices 130, such as a VESAVL bus, an ISA bus, an EISA bus, a Micro Channel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI Express bus, or a NuBus. For embodiments in which the I / O device is a video display 124, the processor 121 may use an Advanced Graphics Port (AGP) to communicate with the display 124. Figure 1C An embodiment of the computer 100 is depicted in which the main processor 121 can communicate directly with the I / O device 130b, such as via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technology. Figure 1C Also depicted is an embodiment in which local busses and direct communications are mixed: processor 121 communicates with I / O device 130a using a local interconnect bus while communicating directly with I / O device 130b.

[0039] There may be a variety of I / O devices 130a to 130n in the computing device 100. Input devices include keyboards, mice, trackpads, trackballs, microphones, dials, touchpads, touch screens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye sublimation printers. Figure 1B As shown, the I / O devices may be controlled by an I / O controller 123. The I / O controller may control one or more I / O devices, such as a keyboard 126; and a pointing device 127, such as a mouse or light pen. In addition, the I / O devices may also provide storage and / or installation media 116 for the computing device 100. In other embodiments, the computing device 100 may provide a USB connection (not shown) to receive a handheld USB storage device, such as a USB flash drive line of devices manufactured by Twintech Industry, Inc. of Los Alamitos, California.

[0040] Reference again Figure 1B, the computing device 100 may support any suitable installation device 116, such as a disk drive, a CD-ROM drive, a CD-R / RW drive, a DVD-ROM drive, a flash memory drive, a tape drive of various formats, a USB device, a hard drive, a network interface, or any other device suitable for installing software and programs. The computing device 100 may further include a storage device, such as one or more hard drives or a redundant array of independent disks, for storing an operating system and other related software and for storing application software programs (e.g., any program or software 120 used to implement (e.g., configured and / or designed for) the systems and methods described herein). Optionally, any of the installation devices 116 may also be used as a storage device. In addition, the operating system and software may be run from a bootable medium.

[0041] In addition, the computing device 100 may include a network interface 118 to interface to the network 104 through various connections, including (but not limited to) a standard telephone line, a LAN or WAN link (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), a broadband connection (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet-over-SONET), a wireless connection, or some combination of any or all of the above. The connection may be established using various communication protocols, such as TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and direct asynchronous connection. In one embodiment, the computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). The network interface 118 may include a built-in network adapter, a network interface card, a PCMCIA network card, a card bus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device suitable for docking the computing device 100 to any type of network capable of communicating and performing the operations described herein.

[0042] In some embodiments, the computing device 100 may include or be connected to one or more display devices 124a to 124n. Therefore, any of the I / O devices 130a to 130n and / or the I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide for the connection and use of the display devices 124a to 124n by the computing device 100. For example, the computing device 100 may include any type and / or form of video adapters, video cards, drivers, and / or libraries to dock, communicate, connect, or otherwise use the display devices 124a to 124n. In one embodiment, the video adapter may include multiple connectors to dock to the display devices 124a to 124n. In other embodiments, the computing device 100 may include multiple video adapters, each of which is connected to the display devices 124a to 124n. In some embodiments, any portion of the operating system of the computing device 100 may be configured to use multiple displays 124a to 124n. In a further embodiment, the I / O device 130 may be a bridge between the system bus 150 and an external communication bus (such as a USB bus, an Apple Desktop bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a FibreChannel bus, a Serial Attached Small Computer System Interface bus, a USB connection, or an HDMI bus).

[0043] Figure 1B and 1CA computing device 100 of the type depicted in the drawings may operate under the control of an operating system that controls the scheduling of tasks and access to system resources. The computing device 100 may run any operating system, such as any version of the MICROSOFT WINDOWS operating system, different versions of the Unix and Linux operating systems, any version of the MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include (but are not limited to): Android produced by Google Inc.; WINDOWS 7, 8 and 10 produced by Microsoft Corporation in Redmond, Washington; MAC OS produced by Apple Computer in Cupertino, California; WebOS produced by Research In Motion (RIM); OS / 2 produced by International Business Machines in Armonk, New York; and Linux, a free-to-use operating system released by Caldera, Inc. in Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0044] The computer system 100 may be any workstation, phone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunication device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunication or media device capable of communication. In some embodiments, the computing device 100 may have a different processor, operating system, and input device consistent with the device. For example, in one embodiment, the computing device 100 is a smart phone, mobile device, tablet computer, or personal digital assistant. In addition, the computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunication device capable of communication and having sufficient processor power and memory capacity to perform the operations described herein.

[0045] Aspects of the operating environment and components described above will become apparent in the context of the systems and methods disclosed herein.

[0046] B. Power-Efficient SAR ADC

[0047] Various embodiments disclosed herein relate to a power efficient SAR ADC. In some embodiments, the SAR ADC includes a digital / analog conversion (DAC) circuit for sampling an input voltage. In some embodiments, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In some embodiments, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select a corresponding comparator from the first comparator and the second comparator for each of a plurality of bits corresponding to the input voltage to determine a state of each of the plurality of bits during a corresponding time period.

[0048] Advantageously, the disclosed SAR ADC can achieve speed and power efficiency. In one aspect, the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator. Therefore, selectively configuring the first comparator and the second comparator allows the state of different bits of the input voltage to be determined in an efficient manner. For example, the state of the most significant bit (MSB) can be determined by the first comparator in a rapid manner, wherein the state of the least significant bit (LSB) can be determined by the second comparator with high sensitivity. In one configuration, the output ports of the first comparator and the second comparator are coupled to a storage circuit so that the first comparator and the second comparator can store the determined bit state through the storage circuit. However, a large number of storage circuits (e.g., more than 7) coupled to the first comparator and the second comparator may result in a large amount of capacitive load, which may reduce the power efficiency and / or operating speed of the first comparator and the second comparator. By implementing a first comparator coupled to a first group of storage circuits and a second comparator coupled to a second group of storage circuits, the capacitive load at the output port of the first comparator and the second comparator can be reduced. Due to the reduced capacitive loading, the first comparator and the second comparator may operate in a fast and power efficient manner.

[0049] Figure 22 is a block diagram depicting a communication device 200 according to one or more embodiments. In some embodiments, the communication device 200 is a system, device, or apparatus for network communication. For example, the communication device 200 is implemented as a part of the network device 106, the node 192, or the device 102. In some embodiments, the device 200 includes a transmitter 210, a receiver 220, and a processor 280. These components can operate together to communicate with another communication device through a network cable (e.g., Ethernet, USB, FireWire, etc.) and / or through a wireless medium (e.g., Wi-Fi, Bluetooth, 60Ghz link, cellular network, etc.). In some embodiments, the communication device 200 includes a transmitter 210, a receiver 220, and a processor 280. Figure 2 More, fewer, or different components than those shown.

[0050] The transmitter 210 is a circuit or component that receives the transmission data TX Data from the processor 280 and generates the output signals Out+, Out-. The transmitter 210 may receive the N-bit digital data TX Data from the processor 280 and generate the output signals Out+, Out- having the voltage or current corresponding to the digital data TXData. The output signals Out+, Out- may be differential signals. In some embodiments, the transmitter 210 may generate a single-ended signal or a signal of different representation for the output signals Out+, Out-. In some embodiments, the transmitter 210 transmits the output signals Out+, Out- through a network cable. In some embodiments, the transmitter 210 provides the output signals Out+, Out- to a wireless transmitter (not shown), and the wireless transmitter may up-convert the output signals Out+, Out- to generate wireless transmission signals at a radio frequency, and transmit the wireless transmission signals through a wireless medium.

[0051] The receiver 220 is a circuit or component that receives input signals In+, In- and generates received data RX Data. In some embodiments, the receiver 220 receives the input signals In+, In- through a network cable. The input signals In+, In- may be differential signals. In some embodiments, the receiver 220 may receive single-ended signals or signals of different representations for the input signals In+, In-. In some embodiments, the receiver 220 receives the input signals In+, In- from a wireless receiver (not shown), which may receive wireless received signals through a wireless medium, and down-convert the wireless received signals to generate input signals In+, In- at baseband frequency. In some embodiments, the receiver 220 receives the input signals In+, In-, and generates N-bit digital data RX Data corresponding to the voltage or current of the input signals In+, In-. The receiver 220 may provide the digital data RX Data to the processor 280. In some embodiments, the receiver 220 includes a SAR ADC 225, which may convert the input signals In+, In- into N-bit digital data RX Data in a power-efficient manner. A detailed description of the implementation and operation of the SAR ADC 225 is provided below with respect to Figures 3 to 5 supply.

[0052] The processor 280 is a circuit or component capable of performing logical calculations. In some embodiments, the processor 280 is implemented as a field programmable gate array, an application specific integrated circuit, or a state machine. The processor 280 can be electrically coupled to the transmitter 210 and the receiver 220 via conductive traces or bus connections. In this configuration, the processor 280 can receive data RX Data from the receiver 220 and perform logical calculations or execute various applications based on the state of the received data RX Data. The processor 280 can also generate data TX Data and provide the data TX data to the transmitter 210.

[0053] Figure 3 SAR ADC 300 may be implemented as Figure 2 SAR ADC 225. In some embodiments, SAR ADC 300 includes sampling and DAC circuit 310, comparators 330A, 330B, a first group of storage circuits 360A, a second group of storage circuits 360B, and control circuit 370. These components can operate together to receive input signals In+, In-, and perform successive approximation analog / digital conversion to generate N-bit data RX Data corresponding to the voltage of input signals In+, In-. In some embodiments, SAR ADC 300 includes a comparison circuit 310. Figure 3 More, fewer or different components may be shown. Although Figure 3 , the sampling and DAC circuit 310, the comparators 330A, 330B, and the storage circuits 360A, 360B are shown as generating and processing differential signals, but some or all of these components may generate and process single-ended signals.

[0054] In some embodiments, the sampling and DAC circuit 310 is a circuit or component that samples the input signals In+, In- and generates DAC output signals DAC Out+, DAC Out-. In one implementation, the sampling and DAC circuit 310 is implemented as a capacitive DAC circuit. In some embodiments, the sampling and DAC circuit 310 includes an input port for receiving the input signals In+, In-, a feedback port for receiving N-bit data RX Data, and an output port for outputting DAC output signals DAC Out+, DAC Out-. In one configuration, the N to M feedback ports of the sampling and DAC circuit 310 are coupled to the N to M output ports of the first group of storage circuits 360A, and the M feedback ports of the sampling and DAC circuit 310 are coupled to the M output ports of the second group of storage circuits 360B. In one example, N may be 9 and M may be 4. In one configuration, the first output port of the sampling and DAC circuit 310 is coupled to the first input port of the comparator 330A and the first input port of the comparator 330B. In one configuration, the second output port of the sampling and DAC circuit 310 is coupled to the second input port of the comparator 330A and the second input port of the comparator 330B. In this configuration, the sampling and DAC circuit 310 receives the input signal In+, In- at the input port and receives the N-bit data RX Data at the feedback port, and samples the input signal In+, In-. The sampling and DAC circuit 310 can perform DAC according to the N-bit data RX Data to generate a DAC output signal DAC Out+, DAC Out- at the output port. The sampling and DAC circuit 310 can provide the DAC output signal DAC Out+, DAC Out- to the comparators 330A, 330B. In one method, for the X-th bit of the N-bit data RX Data, the DAC output signal DAC Out+, DAC Out- indicates the voltage (e.g., Vin+, Vin-) of the input signal In+, In-, where the voltage corresponds to the N to X MSBs of the data RX. In one method, the sampling and DAC circuit 310 generates the DAC output signal DAC Out+, DAC Out- according to the following equation:

[0055]

[0056] In some embodiments, the comparator 330A is a circuit or component that receives the DAC output signals DAC Out+, DAC Out- and determines the state of the corresponding bit of the data RX Data according to the DAC output signals DAC Out+, DAC Out-. In one configuration, the comparator 330A includes a first output port coupled to the sampling and DAC circuit 310 to receive the DAC output signal DAC Out+, a second output port coupled to the sampling and DAC circuit 310 to receive the DAC output signal DAC Out-, a first output port coupled to the first input port of the first group of storage circuits 360A, a second output port coupled to the second input port of the first group of storage circuits 360A, and a clock input port coupled to the first clock output port of the control circuit 370. The first output port of the comparator 330A can be directly coupled to the first input port of the storage circuit 360A, and the second output port of the comparator 330A can be directly coupled to the second input port of the storage circuit 360A. Similarly, the first output port of the comparator 330B can be directly coupled to the first input port of the storage circuit 360B, and the second output port of the comparator 330B can be directly coupled to the second input port of the storage circuit 360B. In this configuration, the comparator 330A may be enabled or disabled according to the clock signal CLK1 from the control circuit 370. For example, in response to a rising edge or logic state '1' of the clock signal CLK1, the comparator 330A is enabled. For example, in response to a falling edge or logic state '0' of the clock signal CLK1, the comparator 330A is disabled. When the comparator 330A is enabled, the comparator 330A may determine the state of the bit according to the DAC output signals DAC Out+, DAC Out-, and generate a comparator output Comp Out1+, Comp Out1- indicating the determined state of the bit at the output port. For example, when the comparator 330A is enabled, in response to the voltage difference of the DAC output signals DAC Out+, DAC Out- being higher than 0V or a reference voltage, the comparator 330A may generate a comparator output Comp Out1+ having a logic state '1' and a comparator output Comp Out1- having a logic state '0'. For example, when the comparator 330A is enabled, in response to the voltage difference of the DAC output signals DAC Out+, DAC Out- being lower than 0V or the reference voltage, the comparator 330A may generate a comparator output Comp Out1+ having a logic state '0' and a comparator output Comp Out1- having a logic state '1'. When the comparator 330A is disabled, the comparator 330A may reset the comparator outputs Comp Out1+, Comp Out1- to a logic state '0'. The comparator 330A may provide the comparator outputs Comp Out1+, Comp Out1- to the first group of storage circuits 360A.The comparator outputs Comp Out1+ and Comp Out1- may be differential signals.

[0057] In some embodiments, the comparator 330B is a circuit or component that receives the DAC output signals DAC Out+, DAC Out- and determines the corresponding bits of the data RX Data according to the DAC output signals DAC Out+, DAC Out-. In some embodiments, the comparator 330A has a higher detection speed and / or a higher power efficiency than the comparator 330B, wherein the comparator 330B has a higher sensitivity than the comparator 330A. In one configuration, the comparator 330B includes a first input port coupled to the first output port of the sampling and DAC circuit 310 to receive the DAC output signal DAC Out+, a second input port coupled to the second output port of the sampling and DAC circuit 310 to receive the DAC output signal DAC Out-, a first output port coupled to the first input port of the second group of storage circuits 360B, a second output port coupled to the second input port of the second group of storage circuits 360B, and a clock input port coupled to the second clock output port of the control circuit 370. The operation of the comparator 330B is similar to that of the comparator 330A, except that the comparator 330B is enabled or disabled in response to the clock signal CLK2 instead of the clock signal CLK1, and the comparator 330B provides the comparator outputs Comp Out2+, Comp Out2- to the second group of storage circuits 360B instead of the first group of storage circuits 360A. Therefore, for the sake of brevity, a detailed description of the duplicated parts is omitted here.

[0058] In some embodiments, the first group of storage circuits 360A is a group of components that store N to M bits (e.g., MSB) of data. In one embodiment, the first group of storage circuits 360A is embodied as N to M flip-flops or latches. In some embodiments, the first input port of each storage circuit 360A is coupled to the first output port of the comparator 330A, and the second input port of each storage circuit 360A is coupled to the second output port of the comparator 330A. In some embodiments, the enable port of each storage circuit 360A is coupled to the corresponding enable output port of the control circuit 370, and the output port of each storage circuit 360A is coupled to the corresponding feedback port of the sampling and DAC circuit 310. In this configuration, each storage circuit 360A can be enabled or disabled according to the corresponding bit of the N to M bit enable signal En1. For example, in response to the enable signal EN1 having

[00001] , the first storage circuit 360A is enabled; in response to the enable signal EN1 having

[00010] , the second storage circuit 360A is enabled; in response to the enable signal EN1 having

[00100] , the third storage circuit 360A is enabled; in response to the enable signal EN1 having

[01000] , the fourth storage circuit 360A is enabled; in response to the enable signal EN1 having

[10000] , the fifth storage circuit 360A is enabled. For example, in response to the enable signal EN1 having

[00000] , all the first group storage circuits 360A are disabled. When the storage circuit 360A is enabled, the storage circuit 360A can update the corresponding bit of the data RX Data according to the comparator outputs Comp Out1+ and Comp Out1-. For example, if the storage circuit 360A is enabled in response to the comparator output Comp Out1+ having a logic state of '1' and the comparator output Comp Out1- having a logic state of '0', the storage circuit 360A may update the corresponding bit of the data RX Data to '1'. For example, if the storage circuit 360A is enabled in response to the comparator output Comp Out1- having a logic state of '1' and the comparator output Comp Out1+ having a logic state of '0', the storage circuit 360A may update the corresponding bit of the data RX Data to '0'. If the storage circuit 360A is disabled, the storage circuit 360A may keep or maintain the corresponding bit of the data RX Data regardless of the comparator outputs Comp Out1+, Comp Out1- at the input port.

[0059] In some embodiments, the second group of storage circuits 360B is a group of components that stores M-bit (e.g., LSB) data. In one embodiment, the second group of storage circuits 360B is embodied as M flip-flops or latches. In some embodiments, the first input port of each storage circuit 360B is coupled to the first output port of the comparator 330B, and the second input port of each storage circuit 360B is coupled to the second output port of the comparator 330B. In some embodiments, the enable port of each storage circuit 360B is coupled to the corresponding enable output port of the control circuit 370, and the output port of each storage circuit 360B is coupled to the corresponding feedback port of the sampling and DAC circuit 310. The operation of the storage circuit 360B is similar to that of the first group of storage circuits 360A, except that each of the storage circuits 360B is enabled or disabled in response to the corresponding state of the M-bit enable signal En2 instead of the N to M-bit enable signal En1, and each of the storage circuits 360B stores and outputs the corresponding bit of the M-bit (e.g., LSB) of the data RX Data instead of the N to M-bit (e.g., MSB) of the data RX Data. Therefore, for the sake of brevity, a detailed description of the replication part is omitted here.

[0060] In some embodiments, the control circuit 370 is a component that configures the comparators 330A, 330B and the storage circuits 360A, 360B to perform successive approximation analog / digital conversion. In one embodiment, the control circuit 370 is implemented as a state machine or a digital logic circuit. In some embodiments, the control circuit 370 includes, for example, an input port for receiving a clock signal CLK from a clock generator (not shown), a first clock output port coupled to the clock input port of the comparator 330A, a second clock output port coupled to the clock input port of the comparator 330B, N to M enable output ports coupled to the enable port of the first group of storage circuits 360A, and M enable output ports coupled to the enable port of the second group of storage circuits 360B. In this configuration, the control circuit 370 can generate a clock signal CLK1 at the first clock output port according to the clock signal CLK, and provide the clock signal CLK1 to the first comparator 330A. In addition, the control circuit 370 may generate a clock signal CLK2 at the second clock output port according to the clock signal CLK, and provide the clock signal CLK2 to the second comparator 330B. In addition, the control circuit 370 may generate an N to M-bit enable signal En1 at the N to M enable output ports according to the clock signal CLK, and provide the N to M-bit enable signal En1 to the first group of storage circuits 360A. In addition, the control circuit 370 may generate an M-bit enable signal En2 at the M enable output ports according to the clock signal CLK, and provide the M-bit enable signal En2 to the second group of storage circuits 360B. In some embodiments, one or more of the signals CLK1, CLK2, En1, En2 are generated regardless of the clock signal CLK, but may be generated according to the comparator outputs Comp Out1+, Comp Out1- and / or the comparator outputs Comp Out2+, Comp Out2-. For example, signals CLK1 , CLK2 , En1 , En2 may be generated in response to rising edges of comparator outputs Comp Out1+, Comp Out1 −, Comp Out2+, Comp Out2 −.

[0061] In one aspect, the control circuit 370 generates clock signals CLK1, CLK2 and enable signals En1, En2 to configure the sampling and DAC circuit 310, the comparators 330A, 330B, and the storage circuits 360A, 360B to perform successive approximation analog-to-digital conversion. In one method, the control circuit 370 may generate a clock signal CLK1 having a pulse sequence to select or enable the comparator 330A during a corresponding time period to determine the state of the N to M bits (e.g., MSB) of the data RX Data, while generating a clock signal CLK2 having a logic state '0 to disable the comparator 330B. When the comparator 330A is enabled, the control circuit 370 may generate an N to M bit enable signal En1 to configure the storage circuit 360A to store the determined state of the N to M bits (e.g., MSB) of the data RX Data. For example, for the MSB of the data RX Data, the sampling and DAC circuit 310 may sample the input signals In+, In- to generate DAC output signals DAC Out+, DAC Out-. In response to the rising edge or logic state '1' of the clock signal CLK1, the comparator 330A may generate comparator outputs CompOut1+, Comp Out1- indicating the state of the MSB according to the DAC output signals DAC Out+, DAC Out-. Then, in response to the pulse or logic state '1' of the corresponding bit of the enable signal En1, the corresponding storage circuit 360A may store the state of the MSB of the data RX Data according to the comparator outputs Comp Out1+, Comp Out1-. For the subsequent bits of the data RX Data, the sampling and DAC circuit 310 may sample the input signals In+, In- according to the state of the previous bit of the data RX Data to generate the DAC output signals DAC Out+, DAC Out-. In response to the rising edge or logic state '1' of the clock signal CLK1, the comparator 330A may generate comparator outputs Comp Out1+, Comp Out1- indicating the state of the subsequent bits according to the DAC output signals DAC Out+, DAC Out-. Then, in response to the pulse or logic state '1' of the corresponding bit of the enable signal En1, the corresponding storage circuit 360A can store the state of the subsequent bit of the data RX Data according to the comparator output Comp Out1+, Comp Out1-. The process can be repeated for the remaining bits of the data RX Data from N to M bits.

[0062] After determining the state of the N to M bits of the data RX Data, the control circuit 370 may generate a clock signal CLK2 having a pulse train to select or enable the comparator 330B during the corresponding time period to determine the state of the M bit (e.g., LSB) of the data RX Data, while generating a clock signal CLK1 having a logic state '0' to disable the comparator 330A. When the comparator 330B is enabled, the control circuit 370 may generate an M-bit enable signal En2 to configure the storage circuit 360B to store the determined state of the M bit (e.g., LSB) of the data RX Data. For example, for the Mth bit of the data RX Data, the sampling and DAC circuit 310 may sample the input signals In+, In- according to the previous state of the N to M bits of the data RX Data to generate the DAC output signals DAC Out+, DAC Out-, and the comparator 330B may generate the comparator outputs Comp Out2+, Comp Out2- indicating the state of the Mth bit according to the DAC output signals DAC Out+, DAC Out-. Then, the corresponding storage circuit 360B may store the state of the Mth bit of the data RX Data. For the subsequent bits of the data RX Data, the sampling and DAC circuit 310 may sample the input signals In+, In- according to the state of the previous bit of the data RX Data to generate DAC output signals DAC Out+, DAC Out-. In response to the rising edge of the clock signal CLK2 or the logic state '1', the comparator 330B may generate the comparator outputs Comp Out2+, Comp Out2- indicating the state of the subsequent bits according to the DAC output signals DAC Out+, DAC Out-. Then, in response to the pulse or the logic state '1' of the corresponding bit of the enable signal En2, the corresponding storage circuit 360B may store the state of the subsequent bits of the data RX Data according to the comparator outputs Comp Out2+, Comp Out2-. The process may be repeated for the remaining bits of the M bits of the data RX Data.

[0063] Advantageously, the SAR ADC 300 can achieve speed and power efficiency. In one aspect, the comparator 330A has a higher detection speed and / or higher power efficiency than the comparator 330B, wherein the comparator 330B has a higher sensitivity than the comparator 330A. Therefore, the comparator 330A can determine the state of a first subset of the bits (e.g., MSB) of the data RX Data, wherein the comparator 330B can determine the state of a second subset of the bits (e.g., LSB) of the data RX Data. In one embodiment, a multiplexer can be added between the output ports of the comparators 330A, 330B and the input ports of the storage circuits 360A, 360B, and the multiplexer can electrically couple the comparator 330A or the comparator 330B to the storage circuits 360A, 360B. However, electrically coupling the comparator 330A or the comparator 330B to the storage circuits 360A, 360B can increase the capacitive load at the output ports of the comparators 330A, 330B. This increased capacitive loading may reduce speed and power efficiency. By implementing comparator 330A with an output port directly coupled to an input port of storage circuit 360A and comparator 330B with an output port directly coupled to an input port of storage circuit 360B, the capacitive loading at the output ports of comparators 330A, 330B may be reduced, thereby achieving speed and power efficiency.

[0064] Figure 4 is a method of demonstrating the Figure 3 A timing diagram 400 of the operation of the SAR ADC 300 is shown. In some embodiments, the control circuit 370 generates clock signals CLK1, CLK2 and enable signals En1, En2 to configure the sampling and DAC circuit 310, the comparators 330A, 330B and the storage circuits 360A, 360B to perform successive approximation analog / digital conversion to determine the state of the N-bit data RXData. Figure 4 In the example shown, N is 9 and M is 4. In some embodiments, the principles disclosed herein may be applied to perform successive approximation analog / digital conversion to determine the states of different numbers of bits of data RX Data. In one approach, control circuit 370 may generate a clock signal CLK1 having pulses at times T1 to T5 and a clock signal CLK2 having pulses at times T6 to T9. In one aspect, comparator 330A is enabled at times T1 to T5 in response to pulses of clock signal CLK1, while comparator 330B is disabled. In one aspect, comparator 330B is enabled at times T6 to T9 in response to pulses of clock signal CLK2, while comparator 330A is disabled.

[0065] In one example, near or before time T1, the sampling and DAC circuit 310 may sample the input signals In+, In- to generate DAC output signals DAC Out+, DAC Out-. After the DAC output signals DAC Out+, DAC Out- are stable at time T1, the comparator 330A may generate comparator outputs Comp Out1+, Comp Out1- indicating the state of the first bit (or MSB) of the data RX Data according to the DAC output signals DAC Out+, DAC Out-. Then, in response to the logic state '1' of the enable signal En1 (9), the corresponding storage circuit 360A may store the state of the first bit or MSB of the data RX Data.

[0066] In one example, after time T1 and around or before time T2, the sampling and DAC circuit 310 may perform DAC according to the state of the first bit of the data RX Data to generate DAC output signals DAC Out+, DAC Out-. After the DAC output signals DAC Out+, DAC Out- are stable at time T2, the comparator 330A may generate comparator outputs Comp Out1+, Comp Out1- indicating the state of the subsequent bit (or the second bit) according to the DAC output signals DAC Out+, DAC Out-. Then, in response to the logic state '1' of the enable signal En1 (8), the corresponding storage circuit 360A may store the state of the subsequent bit (or the second bit) of the data RX Data.

[0067] In one example, after time T2 and around or before time T3, the sampling and DAC circuit 310 may perform DAC according to the determined states of the two bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T3, the comparator 330A may generate comparator outputs Comp Out1+, Comp Out1- indicating the state of the subsequent bit (or the third bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En1 (7), the corresponding storage circuit 360A may store the state of the subsequent bit (or the third bit) of the data RX Data.

[0068] In one example, after time T3 and around or before time T4, the sampling and DAC circuit 310 may perform DAC according to the determined states of the three bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T4, the comparator 330A may generate comparator outputs Comp Out1+, Comp Out1- indicating the state of the subsequent bit (or the fourth bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En1 (6), the corresponding storage circuit 360A may store the state of the subsequent bit (or the fourth bit) of the data RX Data.

[0069] In one example, after time T4 and around or before time T5, the sampling and DAC circuit 310 may perform DAC according to the determined states of the four bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T5, the comparator 330A may generate comparator outputs Comp Out1+, Comp Out1- indicating the states of the subsequent bits (or the fifth bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En1(5), the corresponding storage circuit 360A may store the states of the subsequent bits (or the fifth bit) of the data RX Data.

[0070] In one example, after time T5 and around or before time T6, the sampling and DAC circuit 310 may perform DAC according to the determined states of the five bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T6, the comparator 330B may generate comparator outputs Comp Out2+, Comp Out2- indicating the state of the subsequent bit (or the sixth bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En2 (4), the corresponding storage circuit 360B may store the state of the subsequent bit (or the sixth bit) of the data RX Data.

[0071] In one example, after time T6 and around or before time T7, the sampling and DAC circuit 310 may perform DAC according to the determined state of the six bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T7, the comparator 330B may generate comparator outputs Comp Out2+, Comp Out2- indicating the state of the subsequent bit (or the seventh bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En2 (3), the corresponding storage circuit 360B may store the state of the subsequent bit (or the seventh bit) of the data RX Data.

[0072] In one example, after time T7 and around or before time T8, the sampling and DAC circuit 310 may perform DAC according to the determined states of the seven bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T8, the comparator 330B may generate comparator outputs Comp Out2+, Comp Out2- indicating the states of the subsequent bits (or the eighth bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En2(2), the corresponding storage circuit 360B may store the states of the subsequent bits (or the eighth bit) of the data RX Data.

[0073] In one example, after time T8 and around or before time T9, the sampling and DAC circuit 310 may perform DAC according to the determined state of the eight bits of the data RX Data to generate DAC output signals DAC+, DAC-. After the DAC output signals DAC+, DAC- are stable at time T9, the comparator 330B may generate comparator outputs Comp Out2+, Comp Out2- indicating the state of the subsequent bit (or the ninth bit) according to the DAC output signals DAC+, DAC-. Then, in response to the logic state '1' of the enable signal En2(1), the corresponding storage circuit 360B may store the state of the subsequent bit (or the ninth bit) of the data RX Data.

[0074] Figure 5 1 is a flow chart depicting a process 500 for determining a plurality of bits corresponding to an input voltage by successive approximation according to one or more embodiments. In some embodiments, the process 500 is performed by the device 200 (e.g., the SAR ADC 225 or the SAR ADC 300). In other embodiments, the process 500 is performed by other entities. In some embodiments, the process 500 includes a method for determining a plurality of bits corresponding to an input voltage by successive approximation according to one or more embodiments. Figure 5 More, fewer or different steps than those shown.

[0075] In one approach, to determine the state of a target bit of the N-bit data RX Data, the device 200 samples 505 an input voltage (e.g., the voltage of the input signals In+, In-) through a DAC circuit (e.g., the sampling and DAC circuit 310). The device 200 performs 510 DAC through the DAC circuit (e.g., the sampling and DAC circuit 310) to generate DAC output signals DAC Out+, DAC Out-. Initially, the target bit may be the MSB of the N-bit data RX Data. The DAC circuit may perform DAC based on the known or determined state of one or more previous bits of the N-bit data RX Data, as described above with respect to Figure 3 and 4 described.

[0076] In one method, the device 200 selects 520 a comparator to determine the state of the target bit during the corresponding time period. For example, the control circuit 370 may generate clock signals CLK1, CLK2 to select one of the comparators 330A, 330B. In one aspect, the comparator 330A is coupled to the first group of storage circuits 360A and the comparator 330B is coupled to the second group of storage circuits 360B. The comparator 330A may have a higher detection speed and / or higher power efficiency than the comparator 330B, wherein the comparator 330B may have a higher sensitivity than the comparator 330A. In one aspect, the control circuit 370 selects the comparator 330A in response to the target bit being one of the first subset of predetermined bits (e.g., N to M bits (e.g., MSB)) of the N-bit data RX data. In one aspect, the control circuit 370 selects the comparator 330B in response to the target bit being one of the second subset of predetermined bits (e.g., M bits (e.g., LSB)) of the N-bit data RX data.

[0077] In one approach, the device 200 determines 530 the state of the target bit according to the sampled voltage through the selected comparator. In one approach, the device 200 may store 540 the state of the determined bit through one of a set of corresponding storage circuits coupled to the selected comparator. For example, the control circuit 370 may generate an enable signal En1 or an enable signal En2 to enable one of a set of corresponding storage circuits to store the state of the determined bit.

[0078] In one approach, the device 200 determines 550 whether the state of the additional bit is undetermined. For example, the control circuit 370 may determine that the state of the additional bit of the data RX Data is undetermined in response to the target bit not being the LSB of the N-bit data RX Data. In response to determining that the state of the additional bit (or the subsequent MSB) is undetermined, the device 200 may select the additional bit as the target bit and proceed to step 510. For example, the control circuit 370 may determine that the state of all N bits of the data RX Data is determined in response to the target bit being the LSB of the N-bit data RX Data. In response to determining that the state of all bits of the N-bit data Rx Data is determined, the device 200 may end 570 the process 500.

[0079] Advantageously, SAR ADC 300 can achieve speed and power efficiency. As described above, comparator 330A can have a higher detection speed and / or higher power efficiency than comparator 330B, wherein comparator 330B can have a higher sensitivity than comparator 330A. Therefore, comparator 330A can determine the state of a first subset of bits (e.g., MSBs) of data RX Data, wherein comparator 330B can determine the state of a second subset of bits (e.g., LSBs) of data RX Data. By implementing comparator 330A having an output port directly coupled to an input port of storage circuit 360A and comparator 330B having an output port directly coupled to an input port of storage circuit 360B, capacitive loading at the output ports of comparators 330A, 330B can be reduced, thereby achieving speed and power efficiency.

[0080] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in connection with transmit spatial streams, sounding frames, responses, and subsets of devices in order to identify or distinguish one or the other. These terms are not intended to relate entities (e.g., first device and second device) only in time or according to order, although in some cases, these entities may contain such a relationship. These terms also do not limit the number of possible entities that can operate in a system or environment. It should be understood that the above-mentioned system may provide multiple of any or each of those components, and these components may be provided on a stand-alone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the above-mentioned systems and methods may be provided as one or more computer-readable programs or executable instructions, which are embodied on or in one or more articles of manufacture, such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or tapes. The programs may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any byte code language (e.g., JAVA). A software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0081] Although the foregoing written description of the methods and systems enables a person of ordinary skill to make and use embodiments thereof, the person of ordinary skill will understand and appreciate that there are variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems of the present disclosure should not be limited to the above-described embodiments, methods, and examples, but should be limited to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A device comprising: A sampling and digital / analog conversion DAC circuit, wherein the sampling and digital / analog conversion DAC circuit is used to sample an input voltage to obtain a first sampled voltage; a first comparator coupled to the sampling and DAC circuit; a first set of storage circuits coupled to the first comparator and the sampling and DAC circuits, the first set of storage circuits being configured to store a first subset of a plurality of bits corresponding to the input voltage; a second comparator coupled to the sampling and DAC circuit; a second set of storage circuits coupled to the second comparator and the sampling and DAC circuits, the second set of storage circuits being configured to store a second subset of the plurality of bits corresponding to the input voltage; as well as A control circuit is coupled to the first comparator and the second comparator, the control circuit being configured to select the first comparator to determine a state of a target bit from the first subset of the plurality of bits corresponding to the input voltage during a first time period to determine the state of the target bit according to the first sampled voltage. 2 . The apparatus according to claim 1 , wherein the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator. 3 . The device of claim 1 , wherein the control circuit is configured to select the second comparator to determine a state of another target bit of the plurality of bits during a second time period for the other target bit.

4. The device of claim 1, wherein a corresponding one of the first set of storage circuits is configured to store a determined state of the target bit.

5. The device of claim 4, wherein the sampling and DAC circuit is configured to: receiving the determined state of the target bit from the corresponding one of the first set of storage circuits, and Based at least in part on the determined state of the target bit from the corresponding one of the first set of storage circuits, the input voltage is sampled to obtain a second sampled voltage.

6. A device according to claim 5, wherein the control circuit is configured to select the second comparator to determine the state of another target bit among the multiple bits during a second time period, wherein the second comparator is configured to determine the state of the another target bit based on the second sampled voltage from the sampling and DAC circuit.

7. The device of claim 6, wherein a corresponding one of the second set of storage circuits is configured to store a determined state of the another target bit.

8. The device of claim 1, wherein the control circuit is configured to select the first comparator for the target bit in response to the target bit being one of the first subset of the plurality of bits.

9. The apparatus of claim 1, wherein an output of the first comparator is directly coupled to an input port of the first group of storage circuits, wherein an output of the second comparator is directly coupled to an input port of the second group of storage circuits.

10. A device comprising: A receiver, the receiver comprising: A sampling and digital / analog conversion DAC circuit, wherein the sampling and digital / analog conversion DAC circuit is used to sample the input voltage, a first comparator coupled to the sampling and DAC circuit, a first set of storage circuits, the first set of storage circuits being coupled between the first comparator and the sampling and DAC circuit, a second comparator coupled to the sampling and DAC circuit, a second set of storage circuits coupled between the second comparator and the sampling and DAC circuit, and a control circuit configured to, for each of a plurality of bits corresponding to the input voltage, select a corresponding comparator from the first comparator and the second comparator to determine a state of the each of the plurality of bits during a corresponding time period; and A processor is coupled to the receiver, the processor being configured to receive states of the plurality of bits from the first set of storage circuits and the second set of storage circuits and to perform a logic calculation based on the received states of the plurality of bits. 11 . The apparatus of claim 10 , wherein the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator.

12. The apparatus of claim 10, wherein the control circuit is configured to select the first comparator for a first subset of the plurality of bits and to select the second comparator for a second subset of the plurality of bits.

13. The apparatus of claim 10, wherein the sampling and DAC circuit is configured to sample the input voltage for a first bit of the plurality of bits to obtain a first sampled voltage, wherein the first comparator is configured to determine a state of the first bit of the plurality of bits according to the first sampled voltage.

14. The apparatus of claim 13, wherein a corresponding one of the first set of storage circuits is configured to store a determined state of the first bit of the plurality of bits.

15. The apparatus of claim 14 , wherein based at least in part on the determined state of the first bit of the plurality of bits from the corresponding one of the first set of storage circuits, the sampling and DAC circuit is configured to sample the input voltage for a second bit of the plurality of bits to obtain a second sampled voltage, wherein the second comparator is configured to determine the state of the second bit of the plurality of bits based on the second sampled voltage.

16. The apparatus of claim 10, wherein an output of the first comparator is directly coupled to an input port of the first group of storage circuits, wherein an output of the second comparator is directly coupled to an input port of the second group of storage circuits.

17. A method comprising: Sampling the input voltage by a sampling and digital / analog conversion DAC circuit to obtain a first sampling voltage; determining, by a first comparator coupled to a first group of storage circuits, a state of a first bit of a plurality of bits corresponding to the input voltage according to the first sampled voltage; Sampling the input voltage by the sampling and DAC circuit to obtain a second sampled voltage; as well as A state of a second bit of the plurality of bits is determined based on the second sampled voltage by a second comparator coupled to a second group of storage circuits different from the first group of storage circuits. 18 . The method of claim 17 , wherein the first comparator has a faster detection speed than the second comparator, wherein the second comparator has a higher sensitivity than the first comparator.

19. The method of claim 17, further comprising: storing, by a corresponding one of the first group of storage circuits, a determined state of the first bit; and The determined state of the second bit is stored by a corresponding one of the second group of storage circuits.

20. The method of claim 19, wherein sampling the input voltage by the sampling and DAC circuit to obtain the second sampled voltage is based at least in part on the determined state of the first bit stored by the corresponding one of the first set of storage circuits.

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