Digital-to-analog converter
By splitting the 2R resistor in the R-2R trapezoidal resistor DAC into small unit resistors and switches, and using the V-I conversion module and decoding module to control the switch array, the problem that DAC is difficult to meet the high accuracy and low cost at the same time when achieving high accuracy and high linearity, achieving higher resolution and higher linearity effects.
Patent Information
- Application Number
- CN202510003098.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-16
AI Technical Summary
In the prior art, when the voltage mode R-2R trapezoidal resistor DAC achieves high accuracy and high linearity, it is difficult to meet the needs of high accuracy and low cost at the same time. Especially in integrated circuit design, the number and area of unit resistance increase with the increase of resolution, resulting in limited accuracy.
By splitting the 2R resistor on the left in the traditional R-2R architecture into a small unit resistor and corresponding switches, and combining the V-I conversion module and the decoding module, the switch opening and closing in the switch array module is controlled to generate the corresponding analog voltage, thereby achieving higher resolution over the same resistance area or using fewer unit resistors to achieve higher linearity.
Achieve higher resolution DACs on the same resistance area, or in the same resolution DACs, use smaller numbers, larger areas and higher matching unit resistances to achieve higher linearity and meet the needs of high accuracy and low cost.
Smart Images
Figure CN120017066A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a digital-to-analog converter. Background Art
[0002] Digital to Analog Converter (DAC) is the interface between digital circuits and the analog world. DAC can convert digital signals into analog signals and plays a vital role in the fields of audio, video and communication. The resolution and accuracy of DAC are its important parameters. Among them, the DAC with R-2R ladder resistor architecture has the characteristic that the number of unit resistors is only proportional to the resolution, so it is widely used by designers, especially in the field of high-precision DAC.
[0003] In the voltage-mode R-2R ladder resistor DAC in the related art, the number of unit resistors and the number of unit current sources are proportional to the resolution, that is, the larger the unit resistor area, the higher the matching, and thus the higher the linearity and accuracy of the DAC. However, in the design of integrated circuits, a large number of highly matched unit resistors means a larger chip area and higher cost. Therefore, how to achieve a DAC with higher accuracy and higher linearity on a limited chip area has become a challenge. Summary of the invention
[0004] The purpose of the present invention is to solve the problem in the related art that the voltage-mode R-2R ladder resistor DAC cannot simultaneously meet the requirements of high precision and low cost, and to provide a digital-to-analog converter that can realize a higher-resolution DAC on a unit resistor array with the same total area, or, in the case of the same resolution DAC, can use fewer, larger and more matched unit resistors to achieve higher linearity while meeting the requirements of high precision and low cost.
[0005] In order to achieve the above object, the present invention adopts the following technical solutions: A digital-to-analog converter includes a VI conversion module and an R-2R ladder array module, wherein the low-order branch of the R-2R ladder array module includes 2 m A small unit resistor is connected in series, and the resistance of the small unit resistor is 2R / 2 m The input end of the VI conversion module is connected to the reference voltage, the output end of the VI conversion module is connected to the first input end of the switch array module, the second input end of the switch array module is connected to the control end of the decoding module, and the output end of the switch array module is connected to the input end of the low-order branch; the VI conversion module can output a first current to the switch array module, and the decoding module can convert an m-bit binary codeword into a 2 mThe switch array module can control the opening and closing of the corresponding switch in the switch array module according to the converted code word; and m is a positive integer.
[0006] The present invention splits the left 2R resistor in the traditional R-2R structure into a resistor and an unchanged 2 m The control of high and medium-high codewords continues the traditional R-2R architecture DAC method. By controlling each 2R resistor, the reference voltage V REF The analog voltage of high and medium-high binary weights is generated by switching between the ground and the ground. The VI conversion module uses the operational amplifier clamp to generate an accurate first current. The low-order codeword controls the first current through a decoding module to generate a corresponding low-order binary weight analog voltage for the turning off and on of the switch in the switch array module, so that the increase of m-bit resolution can be achieved on the same resistance area, which solves the problem that the number of resistors and the resistance layout area of the R-2R ladder resistor DAC increase with the improvement of resolution, thereby limiting the accuracy.
[0007] Preferably, a third operational amplifier is further included, wherein the positive input terminal of the third operational amplifier is connected to the output terminal of the R-2R trapezoidal array module, and the negative input terminal of the third operational amplifier is connected to its own output terminal; the third operational amplifier can increase the driving capability of the digital-to-analog converter and reduce the output impedance of the digital-to-analog converter.
[0008] Preferably, the switch array module comprises 2 m -1 switch, the first input end of each switch is connected to the output end of the VI conversion module, the second input end of each switch is connected to the control end of the decoding module, and the output end of each switch is connected between two corresponding adjacent small unit resistors.
[0009] Preferably, the VI conversion module includes a first conversion module and a second conversion module, wherein the first end of the first conversion module is connected to the output end of the first operational amplifier, the second end of the first conversion module is connected to the negative input end of the first operational amplifier, and the third end of the first conversion module is connected to the positive input end of the second operational amplifier; the first end of the second conversion module is connected to the output end of the second operational amplifier, the second end of the second conversion module is connected to the negative input end of the second operational amplifier, and the third end of the second conversion module is the output end of the reference module in the VI conversion module; the positive input end of the first operational amplifier is the input end of the reference module.
[0010] Preferably, the first conversion module includes a first NMOS transistor, and the second conversion module includes a second NMOS transistor, the gate of the first NMOS transistor serves as the first end of the first conversion module, the source of the first NMOS transistor serves as the second end of the first conversion module, and the drain of the first NMOS transistor serves as the third end of the first conversion module; the gate of the second NMOS transistor serves as the first end of the second conversion module, the source of the second NMOS transistor serves as the third end of the second conversion module, and the drain of the second NMOS transistor serves as the second end of the second conversion module.
[0011] Preferably, the reference module also includes a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is connected to a power supply, and the second end of the first resistor is connected to the drain of the first NMOS transistor and the positive input of the second operational amplifier; the first end of the second resistor is connected to the first end of the third resistor, and the second end of the second resistor is grounded; the second end of the third resistor is connected to the source of the first NMOS transistor and the negative input of the first operational amplifier; the first end of the fourth resistor is connected to the drain of the second NMOS transistor and the negative input of the second operational amplifier, and the second end of the fourth resistor is connected to the power supply.
[0012] Preferably, the digital-to-analog converter has a total of n bits of binary code, and the R-2R trapezoidal array module also includes x-bit mid-high-bit branches and y-bit high-bit branches, each of the mid-high-bit branches includes a switch, and resistors with resistance values of 2R and R respectively; each of the high-bit branches includes a switch and a resistor with a resistance value of 2R; the switches of the corresponding mid-high-bit branches are connected to a reference voltage or grounded according to the binary code words from the m+1th to the m+xth bits; the switches of the corresponding high-bit branches are connected to or from the ground according to the temperature code words, and the temperature code words are obtained according to the binary code words from the m+x+1th to the nth bits; y is equal to 2 or 3.
[0013] Preferably, after the switches in the middle and high-order branches and the high-order branches are grounded, the current source position and the output end are exchanged according to the reciprocity theorem, and the output end voltage after the exchange is equal to the output end voltage of the original circuit. The current of the low-order branch after the exchange is: I3=1 / 2 n-m I, The output voltage after the exchange: V I =(b0 B *2 0 +b1 B *2 1 +……+b m-1 B *2 m-1 )*V REF / 2n Among them, b0 B ~b m-1 B is the 1st to mth binary code word of the digital-to-analog converter, V REF is the reference voltage.
[0014] Preferably, the decoding module converts the 1st to mth binary codewords of the digital-to-analog converter into a codeword selected from 2 to the power of m, so that the Mth switch in the switch array module is closed according to the converted codeword, and the remaining switches are disconnected; if M is equal to 0, all switches in the switch array module are disconnected, M = 1, 2, ..., 2 m -1.
[0015] Preferably, it comprises a 6-bit mid-high-order branch and a 3-bit high-order branch, the 7th-12th bit binary codeword controls the mid-high-order branch, and the 1st-3rd bit temperature codeword obtained according to the 13th-14th bit binary codeword controls the high-order branch; m=6, the decoding module is a 6-64 decoding module, and the 1st-6th bit binary codeword is converted into a 64-selected-1 codeword; the low-order branch comprises 64 small unit resistors connected in series, and the switch array module comprises 63 switches, and the first input end of each switch is connected to the output end of the VI conversion module, and the second input end of the switch is connected to the control end of the decoding module, and the control end of the switch is connected between two corresponding adjacent small unit resistors, and the resistance value of the small unit resistor is one-sixty-fourth of the resistance value of the 2R resistor.
[0016] Therefore, the present invention has the following beneficial effects: adopting a segmented strategy, the R-2R resistor on the left side of the traditional R-2R architecture is split into small unit resistors and corresponding switches, the middle and high branches and high branches on the right side are consistent with the traditional analog voltage generation method, and the decoding module uses the current generated by the VI conversion module to control the opening and closing of the switch in the switch array module connected to the low branch to generate a corresponding analog voltage, so that a higher precision resolution can be achieved on the same resistance area, solving the problem that the number of resistors and the area of the resistor layout of the R-2R ladder resistor DAC increase with the increase of resolution, thereby limiting the precision. It enables a higher resolution DAC to be achieved on a unit resistor array with the same total area, or in the case of the same resolution DAC, a smaller number of unit resistors with a larger area and higher matching can be used to achieve higher linearity. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a circuit structure diagram of a digital-to-analog converter provided in Example 1.
[0018] Figure 2 This is a circuit structure diagram of a traditional voltage-mode R-2R ladder resistor digital-to-analog converter provided in Example 1.
[0019] Figure 3 This is a circuit structure diagram of an equal current source injected into an R-2R resistor digital-to-analog converter provided in Example 1.
[0020] Figure 4 This is a circuit structure diagram of another digital-to-analog converter provided in Example 2.
[0021] Figure 5 This is a principle derivation diagram of low-bit analog voltage generation of a digital-to-analog converter provided in Example 2.
[0022] Figure 6 This is a diagram of the linearity simulation results of the digital-to-analog converter provided in Example 2. DETAILED DESCRIPTION
[0023] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments: Embodiment 1: This embodiment provides a digital-to-analog converter, such as Figure 1 As shown, it includes: a VI conversion module, a decoding module, an R-2R ladder array module, a switch array module, a decoding module and a third operational amplifier, wherein the R-2R ladder array module includes a low-order branch, a middle-high-order branch and a high-order branch, the input end of the VI conversion module is connected to a reference voltage, the output end of the VI conversion module is connected to a first input end of the switch array module, the second input end of the switch array module is connected to a control end of the decoding module, the output end of the switch array module is connected to the input end of the low-order branch, the low-order branch, the middle-high-order branch and the high-order branch are connected in sequence, and the output end of the high-order branch is connected to the third operational amplifier.
[0024] The switch array module includes 2 m -1 switch, low level branch includes 2 m Small unit resistor, 2 m The sum of the resistance values of the small unit resistors is 2R; the VI conversion module inputs the first current to the switch array module; the decoding module converts the m-bit binary codeword into a codeword of 2 to the mth power, and inputs the converted codeword to the switch array module; the switch array module can control the closing or opening of the corresponding number of switches according to the converted binary code, m represents the number of binary code bits controlled by the low-order branch, m is a positive integer, specifically, m is a positive integer greater than 1.
[0025] The VI conversion module consists of two conversion modules and two operational amplifiers, where the positive input terminal of the first operational amplifier is connected to the reference voltage V REF , reference voltage V REF It can be generated by a bandgap reference module or by an external reference voltage source.
[0026] like Figure 1 As shown, in this embodiment, the low-order branch includes 2 m A small unit resistor R 0,1 ~R 0,2 m , the switch array module includes 2 m - 1 switch S 0,1 ~S 0,2 m -1 .
[0027] The decoding module is m-2 m Decoding module, when working, m-2 m The decoding module converts the 1st to mth binary code word b0 of the digital-to-analog converter B ~b m-1 B Convert to 2 m Choose a codeword so that S 0,1 ~S 0,2 m -1 The Mth switch S in the switch array 0,M The remaining switches are closed, and the remaining switches are open. M represents the number of switches in the switch array module, M = 0, 1, 2, ..., 2 m -1. When M=0, S 0,1 ~S 0,2 m -1 All switches in the switch array are open.
[0028] There are x middle and high-order branches in total, and each middle and high-order branch has the same structure, including a switch, an R resistor with a resistance value of R, and a 2R resistor with a resistance value of 2R; the switch of the corresponding middle and high-order branch is controlled to connect to the reference voltage or the ground according to the binary code from the m+1th to the m+xth bit.
[0029] There are y high-order branches in total, and each high-order branch has the same structure, including a switch and a resistor R with a resistance value of R. The switch of the corresponding high-order branch is connected to a reference voltage or ground according to the temperature code word control. The temperature code word is obtained according to the binary code word from the m+x+1th to the nth bit, and y is equal to 2 or 3, that is, the R-2R trapezoidal array module generally sets a 2-3 route high-order branch controlled by the temperature code word.
[0030] V I The end is the output voltage end of the R-2R ladder array module, and is connected to the positive input end of the third operational amplifier.
[0031] The relationship between the small unit resistance and the 2R resistance is: R 0,1～ R 0,2 m =2R / 2m .
[0032] After the resistances of the middle and high branches are grounded, according to the reciprocity definition, the current source position, that is, the output end of the VI conversion module, is connected to the output voltage end V of the R-2R ladder array module. I The positions are swapped, and the output voltage of the R-2R ladder array module after the swap is equal to the output voltage of the R-2R ladder array module of the original circuit. The current flowing through the low-order branch after the swap is: I3=1 / 2 n-m I The output terminal V of the R-2R ladder array module after the exchange / original circuit I Voltage: V I =(b0 B *2 0 +b1 B *2 1 +……+b m-1 B *2 m-1 )*V REF / 2 n Among them, b0 B ~b m B is the 1st to mth binary code word of the digital-to-analog converter, V REF is the reference voltage, and I is the first current output from the VI conversion module to the R-2R ladder array module.
[0033] The digital-to-analog converter in this embodiment also includes a third operational amplifier, the negative input terminal of the third operational amplifier is connected to its own output terminal, and the positive input terminal is connected to the high-order branch output terminal. The third operational amplifier plays a buffering role in the digital-to-analog converter, which can increase the driving capability of the digital-to-analog converter, reduce the output impedance of the digital-to-analog converter, and make the analog output voltage of the digital-to-analog converter more stable.
[0034] When working, the middle and high-order branches and the high-order branches adopt the traditional R-2R architecture digital-to-analog converter method to control the middle and high-order and high-order codewords respectively; that is, the middle and high-order branches and the high-order branches controlled by the m+1-n-th binary codewords themselves are switched to V REF or ground at the output terminal V R-2R The analog voltage generated is: V R-2R =(b m B *2 0 +b m+1 B *2 1 +……+b n-1B *2 n-m-1 )*V REF / 2 n-m Among them, b m B ~b n-1 B It is the m+1th to nth binary code word of the digital-to-analog converter.
[0035] In summary, the control of the low-order codeword is controlled by the decoding module to control the current of the VI conversion module to generate a corresponding low-order binary weighted analog voltage, and the analog voltages obtained by the low-order codeword and the medium-high-order codeword and the high-order codeword are combined to obtain the final output analog voltage of the high-precision digital-to-analog converter based on the R-2R architecture provided in this embodiment.
[0036] The following further illustrates the technical solution and technical effects of the present invention through specific examples and specific application scenarios. The following examples are explanations of the present invention and the present invention is not limited to the following examples.
[0037] like Figure 2 As shown in the figure, the conventional voltage-mode R-2R ladder resistor DAC switches the resistor ladder at V REF It switches between ground and output at the V1 end. Its advantage is that it has a constant output impedance and the resolution can be increased by one bit with each additional resistor ladder. However, in the design of high-precision DAC, the matching of unit resistance is positively correlated with the resistance area. The larger the unit resistance area, the higher the matching, the higher the linearity of the DAC, and the higher the precision. In the design of integrated circuits, a large number of unit resistors with high matching requirements means a larger chip area and higher cost. It has become a challenge to achieve a DAC with higher precision and higher linearity on the same chip area.
[0038] Another common structure of R-2R resistor ladder DAC is to inject equal current sources into the R-2R resistor network, such as Figure 3 As shown. Figure 2 Like the traditional voltage-mode R-2R ladder resistor, the number of unit resistors is proportional to the resolution, and the number of unit current sources is proportional to the resolution. The accuracy of the DAC of this architecture not only has high matching requirements for unit resistors, but also has higher requirements for matching requirements for unit current sources.
[0039] Figure 2 and Figure 3The accuracy of the two digital-to-analog converters in the embodiment is limited by the chip area cost problem brought about by the increase in the number of unit resistors. The high-precision digital-to-analog converter based on the R-2R architecture provided in this embodiment is used to solve the problem that the number of resistors and the area of the resistor layout of the R-2R ladder resistor DAC continue to increase with the improvement of resolution, thereby limiting the accuracy. The increase of m-bit resolution can be achieved on the same resistor area, so that a higher-resolution DAC can be achieved on a unit resistor array with the same total area, or in the case of the same resolution DAC, a smaller number of unit resistors with larger areas and higher matching can be used to achieve higher linearity.
[0040] Specifically, Figure 1 As shown, the VI conversion module includes a first conversion module, a second conversion module, a first operational amplifier AMP1, and a second operational amplifier AMP2. The first end of the first conversion module is connected to the output end of the first operational amplifier AMP1, and the positive input end of the first operational amplifier AMP1 is connected to the reference voltage V RE , the second end of the first conversion module is connected to the negative input end of the first operational amplifier AMP1; the positive input end of the second operational amplifier AMP2 is connected to the third end of the first conversion module, the negative input end of the second operational amplifier AMP2 is connected to the second end of the second conversion module, the output end of the second operational amplifier AMP2 is connected to the first end of the second conversion module, the third end of the second conversion module is the output end of the VI conversion module, and the positive input end of the first operational amplifier AMP1 is the input end of the VI conversion module. Reference voltage V REF It can be generated by a bandgap reference module or by an external reference voltage source.
[0041] In this embodiment, the first conversion module includes a first NMOS transistor M N1 The second conversion module includes a second NMOS transistor M N2 , the first NMOS transistor M N1 The gate of the first NMOS transistor M is used as the first terminal of the first conversion module. N1 The source of the first NMOS transistor M is used as the second end of the first conversion module. N1 The drain of the second NMOS transistor M is used as the third terminal of the first conversion module; N2 The gate of the second NMOS transistor M is used as the first terminal of the second conversion module. N2 The source of the second NMOS transistor M is used as the third terminal of the second conversion module. N2 The drain of the second conversion module serves as the second end of the second conversion module.
[0042] Furthermore, the VI conversion module further includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, the first resistor R1 and the fourth resistor R4 have the same resistance, and the sum of the resistances of the second resistor R2 and the third resistor R3 is 2R. The specific connection relationship is: the first end of the first resistor R1 is connected to the power supply VDD, the second end of the first resistor R1 is connected to the first NMOS transistor M N1 The drain of the second operational amplifier AMP2 is connected to the positive input terminal; the first end of the second resistor R2 is connected to the first end of the third resistor R3, and the second end of the second resistor R2 is grounded; the second end of the third resistor R3 is connected to the first NMOS transistor M N1 and the negative input terminal of the first operational amplifier AMP1; in this embodiment, R1~R4 are all selected as resistors with a resistance value of R. According to the voltage clamping principle of the first operational amplifier AMP1, the first NMOS transistor M N1 The source voltage V2 is equal to the reference voltage V REF The voltage of the first NMOS transistor M is the same as that of the N1 The current of the first conversion module is V REF / 2R.
[0043] The second NMOS transistor M N2 The gate of the second NMOS transistor M is connected to the output terminal of the second operational amplifier AMP2. N2 The source of the second NMOS transistor M is connected to the first input terminal of the switch array module. N2 The drain of is connected to the negative input terminal of the second operational amplifier AMP2 and the first end of the fourth resistor R4 respectively, and the second end of the fourth resistor R is connected to the power supply VDD. According to the voltage clamping principle of the second operational amplifier AMP2, the voltage V3 connected to the positive input terminal of the second operational amplifier AMP2 is the same as the voltage V4 connected to the negative input terminal of the second operational amplifier AMP2. Since the resistance between the V3 and V4 points and the power supply voltage is R, the current of the two conversion modules of the VI conversion module is equal, both of which are V REF / 2R. Therefore, the first current I of the VI conversion module is V REF / 2R, and the current direction is downward.
[0044] like Figure 1 As shown, the low-level branch includes 2 m Small unit resistors R with the same resistance value 0,1 ~R 0,2 m , the switch array module includes 2 m - 1 switch S 0,1 ~S2 m -1 , small unit resistor R 0,1~R 0,2 m Connect in series, with a small unit resistor R at the end 0,2 m Connected to the middle and high branches, the small unit resistor R at the head end 0,1 Ground.
[0045] The output end of a switch is also connected between two adjacent small unit resistors. The first input end of the switch is connected to the output end of the VI conversion module, and the second output end of the switch is connected to m-2 m The control terminal of the decoding module is connected. For example: a small unit resistor R 0,1 And small unit resistor R 0,2 In series, unit resistance R 0,1 And small unit resistor R 0,2 The connection points are connected together with switch S 0,1 At the output of the switch S 0,1 The first input terminal and the output terminal of the VI conversion module, the switch S 0,1 The second output terminal is connected to m-2 m The control end of the decoding module is connected, and so on, so the number of switches in the switch array module is one less than the number of small unit resistors in the low-order branch.
[0046] like Figure 1 As shown, each mid-high branch has the same structure, including an R resistor, a 2R resistor and a switch, and the x mid-high branches are connected in sequence, and the first mid-high branch is connected to the low branch. Specifically: one end of the R resistor is connected to one end of the 2R resistor, the other end of the R resistor is connected to one end of the R resistor in the next mid-high branch, the other end of the 2R resistor is connected to the output end of the switch, and the input end of the switch is grounded or referenced to a voltage.
[0047] Each high-order branch has the same structure, including a 2R resistor and a switch, y high-order branches are connected to each other, the last middle high-order branch is connected to the first high-order branch, and the last high-order branch is connected to the positive input terminal of the third operational amplifier. Specifically: one end of the 2R resistor is connected to the output terminal of the switch, the input terminal of the switch is grounded or the reference voltage, and the other end of the 2R resistor is connected to one end of the 2R resistor of the next high-order branch.
[0048] When the digital-to-analog converter provided in this embodiment is working, the high-order branch control code word b1 T ~b y T is the temperature code word, temperature code word b1 T ~b y T The control code word b of the middle and high-order branch is obtained from the binary code word of the m+x+1th to the nth bit. m B ~bm+x-1 B It is binary code, and the low-order branch control code word is b0 B ~b m-1 B It is binary code.
[0049] Specific: (1) High-order branch controlled by temperature codeword.
[0050] When the temperature code is 1, the switch corresponding to the temperature code is switched to V REF At one end, when the temperature code word is 0, the switch corresponding to the temperature code word is switched to ground.
[0051] If the temperature code word has three bits, then the temperature code word b1 T ~b3 T With the high binary code b m+x B ~b n-1 B The relationship is: b1 T =b n-2 B +b n-1 B b2 T =b n-1 B b3 T =b n-2 B *b n-1 B (2) Mid- and high-order branches controlled by binary code words.
[0052] The high-order binary code b m B ~b m+x-1 B When it is 1, the switch S m ~S m+x-1 Switch to V REF One end, the high-order binary code b m B ~b m+x-1 B When it is 0, switch S m ~S m+x-1 Switch to ground.
[0053] Among them, n represents the number of bits of the digital-to-analog converter, which is a positive integer; m represents the number of codeword bits controlled by the low-order branch, which is a positive integer, n is greater than m, and generally 2 or 3 high-order paths controlled by temperature codewords are set in the R-2R trapezoidal array module, that is, y is equal to 2 or 3.
[0054] The analog voltage generated by the switch corresponding to the high-order temperature codeword and the medium- and high-order binary codeword is consistent with the traditional R-2R architecture, which is: V R-2R =(b m B *2 0 +b m+1 B *2 1 +……+b n-2 B *2 n-2-m +b n-1 B *2 n-1-m )*V REF / 2 n-m Among them, V R-2R For the mid-high branch and the high branch itself, switch the resistor ladder to V REF or ground at the output terminal V I The analog voltage generated is the sum of the analog voltages generated by the middle and high branches and the high branch, b m B ~b n-1 B is the m+1~nth binary code word of the digital-to-analog converter, V REF It is a reference voltage, which can usually be generated by a reference bandgap module inside the chip or provided by an external reference voltage source.
[0055] (3)VI conversion module.
[0056] like Figure 1 As shown in the figure, the VI conversion module consists of two circuits and two operational amplifiers. REF Converted into current, the first operational amplifier and the second operational amplifier act as voltage clamps, clamping the voltages at the positive input and negative input of the operational amplifier to the same potential, that is: V REF =V2, V3=V4.
[0057] The current magnitudes of the two currents I1 and I2 of the VI conversion module are: I1=(V DD -V3) / R = V2 / 2R; I2=(V DD -V4) / R.
[0058] V REF =V2, V3=V4 Substituting into the above formula we can get: I1=I2=V REF / 2R.
[0059] Therefore, the VI conversion module uses the voltage clamp of the first operational amplifier and the second operational amplifier to convert the reference voltage V REF Converted into the first current V REF / 2R, where 2R is the sum of the resistances of the second resistor R2 and the third resistor R3 in the R-2R circuit.
[0060] (4) The analog voltage provided by the low-level branch.
[0061] m-2 m The decoding module converts the 1st to mth binary code word b0 of the digital-to-analog converter B ~b m-1 B Convert to 2 m Select the codeword 1, so that the switch array S 0,1 ~S 0,2 m -1 The Mth switch S in 0,M Closed, the rest of the switches are open, M = 0, 1, 2, ..., 2 m -1, where b0 B ~b m-1 B The relationship with M is: M=N2=b0 B *2 0 +b1 B *2 1 +……+b m-2 B *2 m-2 +b m-1 B *2 m-1 When M = 0, the switch array S 0,1 ~S 0,2 m -1 All switches in the switch are open.
[0062] Low binary code b0 B ~b m-1 B By m-2 m The decoding module controls the switch array S 0,1 ~S 0,2 m -1 The closing and closing of the VI conversion module injects the resistor R into the low-level branch. 0,1 ~R 0,2 m The first current generates a low-bit binary-weighted analog voltage.
[0063] (5) The analog voltage output by the digital-to-analog converter.
[0064] Using the reciprocity theorem, in a linear circuit containing only one current source and no controlled source, the current source and the voltmeter are swapped, and the voltmeter reading remains unchanged.
[0065] The switches of the middle-high branch and the high-level branch are grounded, and the first current injection position of the VI conversion module in this embodiment is exchanged with the output position of the R-2R ladder resistor. According to the R-2R ladder resistor characteristic, the resistor R 0,1 ~R 0,2 m The current on is I3 = 1 / 2 n-m I, and the output voltage of the R-2R ladder module in the converted circuit is equal to the output voltage of the R-2R ladder module in the original circuit: V I =(1 / 2 n-m I)*(b0 B *2 0 +b1 B *2 1 +……+b m-1 B *2 m-1 )*(2R / 2 m ) Therefore, I = V REF Substituting / 2R, we have: V I =(b0 B *2 0 +b1 B *2 1 +……+b m-1 B *2 m-1 )*V REF / 2 n Where V I Represents the analog voltage generated by the current injection of the V-1 conversion module, that is, the low-order binary code b0 B ~b m-1 B The analog output voltage generated by the control.
[0066] According to the superposition theorem, the binary code word b0 B ~b n-1 B The resulting analog output voltage is: V I =(b0 B *2 0 +b1 B *2 1+b2 B *2 2 +...+b n-2 B *2 n-2 +b n-1 B *2 n-1 )*V REF / 2 n It is proved that the DAC improved based on the R-2R ladder resistor architecture DAC designed in this embodiment is composed of binary code word b0 B ~b n-1 B A controlled DAC that produces an analog output voltage corresponding to the binary weight.
[0067] The digital-to-analog converter further includes a third operational amplifier, the negative input terminal of the third operational amplifier is connected to the output terminal, and the positive output terminal is connected to the output terminal of the high-order branch. According to the voltage clamping principle, there is: V OUT =V1=(b0 B *2 0 +b1 B *2 1 +b2 B *2 2 +...b n-2 B *2 n-2 +b n-1 B *2 n-1 )*V REF / 2 n The third operational amplifier plays a buffering role in the digital-to-analog converter, which can increase the driving capability of the digital-to-analog converter, reduce the output impedance of the digital-to-analog converter DAC, and make the analog output voltage of the digital-to-analog converter more stable.
[0068] The digital-to-analog converter provided in this embodiment has the first to m bits through m-2 m The decoding module controls the switch array S 0,1 ~S 0,2 m -1 The first current injected into the VI conversion module is generated, and the m+1th to m+xth bits generate analog voltages through binary code words; the temperature code word is obtained through the (m+x+1)th bit and the nth bit, and an analog voltage is generated through the obtained temperature code, and the analog voltages generated by the three are added together to obtain the analog voltage finally output by the digital-to-analog converter.
[0069] Based on the above, the digital-to-analog converter provided in this embodiment has the following beneficial effects: The leftmost 2R resistor in the traditional R-2R architecture is split into two m The R-2R resistor on the right remains unchanged, and the high and medium-high codewords are controlled. Therefore, the high and medium-high codewords are controlled in the same way as the traditional R-2R architecture. The control of the low codeword is controlled by the decoder to control the current V REF / 2R for switch array S 0,1 ~S 0,2 m -1 The closing and closing of the resistor generates a corresponding low-bit binary weight analog voltage. This enables the increase of m-bit resolution on the same resistor area, improves accuracy and reduces costs, and is suitable for R-2R architecture digital-to-analog converters of any bit number.
[0070] Embodiment 2: This embodiment provides a digital-to-analog converter. Based on the first embodiment, a specific example is provided for a 14-digit voltage-type R-2R architecture digital-to-analog converter, and the accuracy of the traditional 14-digit R-2R architecture digital-to-analog converter is improved by 6 digits. The leftmost 2R resistor in the traditional R-2R architecture is split into 64 small unit resistors, and the R-2R resistor on the right remains unchanged, and high-order and mid-high-order codeword control is performed. Therefore, the high-order and mid-high-order codeword control is the same as the control of the traditional R-2R architecture, and the low-order control is controlled by the decoder to control the current V REF / 2R for switch array S 0,1 ~S 0,63 The closing and closing of the resistor generates a corresponding low-bit binary weight analog voltage, which enables the increase of 6 bits of resolution on the same resistor area, improving accuracy while reducing costs.
[0071] Specific: like Figure 4 As shown, a digital-to-analog converter includes: a VI conversion module, a decoding module, an R-2R ladder array module, a switch array module, a decoding module and a third operational amplifier, wherein the R-2R ladder array module includes a low-order branch, a middle-high-order branch and a high-order branch, the input end of the VI conversion module is connected to a reference voltage, the output end of the VI conversion module is connected to a first input end of the switch array module, the second input end of the switch array module is connected to a control end of the decoding module, the output end of the switch array module is connected to the input end of the low-order branch, the low-order branch, the middle-high-order branch and the high-order branch are connected in sequence, and the output end of the high-order branch is connected to the third operational amplifier.
[0072] It should be noted that this embodiment takes a 14-bit voltage-type R-2R architecture DAC as an example to improve the accuracy of 6 digits. That is, based on the first embodiment, n is 14 bits, m is 6 bits, x=6, y=3.
[0073] During operation, the high-order branch is controlled by the high-order codeword, and the medium-high-order branch is controlled by the medium-high-order codeword. The control method continues the control method of the traditional R-2R architecture digital-to-analog converter. The switch is switched between the reference voltage and the ground through each 2R resistor control switch to generate high-order and medium-high-order binary weighted analog voltages; the low-order branch cooperates with the VI conversion module, and the low-order codeword controls the first current of the VI conversion module through the decoding module to turn off and close the corresponding switches in the switch array module to generate a corresponding low-order binary weighted analog voltage. According to the superposition principle, the analog voltages obtained by the low-order codeword, the medium-high-order codeword, and the high-order codeword are combined to obtain the final output analog voltage of the high-precision digital-to-analog converter based on the R-2R architecture provided in this embodiment.
[0074] By improving the traditional voltage-mode R-2R ladder resistor digital-to-analog converter, the leftmost 2R resistor is split into a resistor and 64 unchanged small unit resistors on the original architecture. This allows the resolution of the digital-to-analog converter to be expanded by 6 bits while the total area of the resistors remains unchanged, solving the pain point of the high-precision R-2R architecture digital-to-analog converter that the number of unit resistors is proportional to the resolution, reducing the area cost of the digital-to-analog converter, and improving the resolution, accuracy, and linearity of the digital-to-analog converter.
[0075] The circuit structure of the 14-bit digital-to-analog converter with improved 6-bit accuracy provided by this embodiment is further described below.
[0076] like Figure 4 As shown, in this embodiment, the circuit structure of the VI conversion module is consistent with the circuit structure of the VI conversion module in the first embodiment, and its working principle is also the same. The reference voltage V is clamped by the principle of voltage clamping. REF Converts to an accurate first current V REF / 2R.
[0077] The low-order binary codeword is converted into a 64-to-1 codeword through a 6-64 decoding module, which controls the switch array module switch S 0,1 ~S 0,63 One or 0 of the switches are turned on, and the first current V REF / 2R is injected into the resistor R in the low-order branch through the switch array module 0,1 ~R 0,64The different positions in the resistor ladder DAC can increase the 6-bit resolution on the basis of the traditional voltage-mode R-2R resistor ladder DAC, so that a higher-resolution digital-to-analog converter can be realized on a unit resistor array with the same total area, or in the case of the same resolution digital-to-analog converter, a higher linearity can be achieved with fewer, larger and more matched unit resistors.
[0078] The low-order branch consists of 64 small unit resistors R with the same resistance value connected in series. 0,1 ~R 0,64 , the switch array module includes 63 switches S 0,1 ~S 0,63 Its circuit structure is consistent with the circuit structure of the low-order branch and the switch array module in the first embodiment, and its working principle is also the same.
[0079] Specifically, Figure 4 As shown, the small unit resistor R 0,1 The first end is grounded, and the small unit resistor R 0,1 The second end is connected to a small unit resistor R 0,2 First terminal, switch S 0,1 Output connection, switch S 0,1 The first input terminal is connected to the output terminal of the VI conversion module, and the switch S 0,1 The second input terminal is connected to the control terminal of the decoding module; the small unit resistor R 0,2 The second end is connected to a small unit resistor R 0,3 First terminal, switch S 0,2 Output connection, switch S 0,2 The first input terminal is connected to the output terminal of the VI conversion module, the second input terminal is connected to the control terminal of the decoding module, and so on. The last small unit resistor R 0,64 The second end is connected to the ground branch.
[0080] In this embodiment, all the middle and high level branches include 6 switches (switches S6 to S7). 11 ) and 6 R resistors with a resistance value of R, and 6 2R resistors with a resistance value of 2R; all high-order branches include a total of three switches S T0 ~S T2 And three 2R resistors with a resistance of 2R.
[0081] In other embodiments, the 2R resistor may also be a plurality of resistors connected in series, as long as the resistance of the 2R resistor is twice the resistance of the R resistor.
[0082] V I The terminal is the output voltage terminal, which is connected to the positive input terminal of the third operational amplifier. The relationship between the small unit resistance in the low-order branch and the 2R resistance is: R 0,1～64 =2R / 64.
[0083] The negative input terminal of the third operational amplifier is connected to the output terminal, and the positive output terminal of the third operational amplifier is connected to the output terminal of the R-2R trapezoidal array module. The third operational amplifier can increase the driving capability of the digital-to-analog converter, reduce the output impedance of the digital-to-analog converter, and make the analog output voltage of the digital-to-analog converter more stable.
[0084] Based on the above architecture, the output process of the high-precision digital-to-analog converter based on the R-2R architecture provided in this embodiment is as follows: when working, the traditional R-2R architecture digital-to-analog converter is used to control the high-order and mid-high-order codewords, and the mid-high-order branch is controlled by each 2R resistor control switch S6~S 11 , the high-level branch is controlled by a 2R resistor in each branch. T0 ~S T2 At the reference voltage V REF The VI conversion module uses the op amp clamp to generate V REF / 2R current, the low-order code word controls the current V through the decoder REF / 2R for switch array S 0,1 ~S 0,63 The opening and closing of the switch generates an analog voltage corresponding to the binary weight of the low bit.
[0085] Specific: In this embodiment, the low-order resistance ladder control code word b0 obtained by the low-order branch B ~b5 B It is binary code, high resistance ladder control code word b1 T ~b3 T Thermometer code, mid-high resistance ladder control code b6 B ~b 11 B It is binary code.
[0086] (1) Thermometer code.
[0087] When the thermometer code b1 T ~b3 T When S is 1, T0 ~S T2 The switch is switched to the reference voltage V REF One end, when the thermometer code b1 T ~b3 T When S is 0, T0 ~S T2 Switch to ground, thermometer code b1 T ~b3 T With the high binary code b 12 B ~b13 B The relationship is: b1 T =b 12 B +b 13 B , b2 T =b 13 B , b3 T =b 12 B *b 13 B .
[0088] (2) Middle and high-order binary code words and high-order binary codes.
[0089] The high-order binary code b6 B ~b 11 B When it is 1, switches S6~S 11 Switch to V REF At one end, the high-order binary code b6 B ~b 11 B When it is 0, switches S6~S 11 Switch to ground.
[0090] The high-order binary code and the medium-high-order binary code control switch array S6~S 11 With S T0 ~S T2 The analog voltage generated is consistent with the traditional R-2R architecture and is: V R-2R =(b6 B *2 0 +b7 B *2 1 +b8 B *2 2 +b9 B *2 3 +b 10 B *2 4 +b 11 B *2 5 +b 12 B *2 6 +b 13 B *2 7 )*V REF / 2 8 .
[0091] Among them, V R-2R The R-2R architecture itself switches the resistor ladder to V REF or ground at the output terminal V1 to generate the analog voltage, b6 B ~b 13 B is the 6th to 13th binary code word of the digital-to-analog converter, V REF It is a reference voltage, usually generated by a reference bandgap module inside the chip or provided by an external reference voltage source.
[0092] In this embodiment, the decoding module is 6-64 (m-2 m Decoding module, m is 6) decoding module, converts the 0th to 5th binary code word b0 B ~b5 B Convert to a 64-choose-1 codeword so that S 0,1 ~S 0,63 The Mth switch S in the switch array 0,n Closed, the rest of the switches are open, b0 B ~b5 B The relationship with M is: M=b0 B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 3 +b4 B *2 4 +b5 B *2 5 .
[0093] When M=0, S 0,1 ~S 0,63 All switches in the switch array are open.
[0094] (3) Low-order binary code.
[0095] Low binary code b0 B ~b5 B The switch S in the switch array module is controlled by the 6-64 decoding module 0,1 ~S 0,63 The first current output by the VI conversion module is injected into the low-order branch resistor R 0,1 ~R 0,64 position, thereby producing a low-order binary-weighted analog voltage.
[0096] Figure 5 The low-order binary code is b0 B ~b5 BThe principle derivation diagram of the analog voltage generation mechanism. Using the reciprocity theorem, in a linear circuit containing only one current source and no controlled source, the current source and the voltmeter are swapped, and the voltmeter reading remains unchanged.
[0097] Therefore, the first current injection position of the VI conversion module is interchanged with the output position of the R-2R ladder array module, and the switches of the middle and high branches are grounded. According to the R-2R ladder resistance characteristics, the resistor R 0,1 ~R 0,64 The current on the n-m I, n is 14, m is 6, nm=8), and: V I =(1 / 256I)*M*2R / 64.
[0098] Set I = V REF Substitute the calculation formula of / 2R and M into the above V I The calculation formula is: V I =(b0 B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 3 +b4 B *2 4 +b5 B *2 5 )*V REF / 2 14 .
[0099] Where V I Indicates the low binary code b0 B ~b5 B The analog output voltage generated by the control is the low-order binary code b0 B ~b5 B The analog output voltage generated by the control.
[0100] The binary code word b0 after conversion according to the reciprocity theorem B ~b 13 B The analog output voltage generated is the same as the binary code b0 before conversion. B ~b 13 B The analog output voltages generated are equal, that is, the output voltage obtained by the digital-to-analog converter with improved 6-bit resolution provided in this embodiment is: V I =(b0 B*2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 2 +…+b 12 B *2 12 +b 13 B *2 13 )*V REF / 2 14 .
[0101] Therefore, the digital-to-analog converter designed in this embodiment based on the improved R-2R ladder resistor architecture is composed of binary codewords b 0B ~b 13B A controlled digital-to-analog converter produces an analog output voltage corresponding to the binary weight.
[0102] The connection method of the third operational amplifier is the same as that in the first embodiment. According to the voltage clamping principle, V OUT =V I =(b0 B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 2 +…+b 12 B *2 12 +b 13 B *2 13 )*V REF / 2 14 The third operational amplifier plays a buffering role in the DAC, which can increase the driving capability of the DAC, reduce the output impedance of the DAC, and make the analog output voltage of the DAC more stable.
[0103] Figure 6 This is a graph of the linearity simulation results of the digital-to-analog converter provided in this embodiment. From the simulation results, it can be seen that the integral nonlinearity (INL) is 0.266 and the differential nonlinearity (DNL) is 0.219. Therefore, the linearity result of the digital-to-analog converter structure provided in the embodiment of the present application is good and is suitable for the application of high-precision digital-to-analog converters.
[0104] The above-described embodiment is only a preferred solution of the present invention and does not limit the present invention in any form. There are other variations and modifications without exceeding the technical solution described in the claims.
Claims
1. A digital-to-analog converter, characterized in that: It includes a VI conversion module and an R-2R ladder array module, wherein the low-order branch of the R-2R ladder array module includes 2 m The resistance is 2R / 2 m The input end of the VI conversion module is connected to the reference voltage, the output end of the VI conversion module is connected to the first input end of the switch array module, the second input end of the switch array module is connected to the control end of the decoding module, and the output end of the switch array module is connected to the input end of the low-order branch; the VI conversion module outputs the first current to the switch array module, and the decoding module converts the m-bit binary codeword into a 2 m A code word of bit selection one, the switch array module controls the opening and closing of the corresponding switch in the switch array module according to the converted code word; m is a positive integer.
2. A digital-to-analog converter according to claim 1, characterized in that: It also includes a third operational amplifier, the positive input terminal of the third operational amplifier is connected to the output terminal of the R-2R trapezoidal array module, and the negative input terminal of the third operational amplifier is connected to its own output terminal; the third operational amplifier can increase the driving capability of the digital-to-analog converter and reduce the output impedance of the digital-to-analog converter.
3. A digital-to-analog converter according to claim 1, characterized in that: The switch array module includes 2 m -1 switch, the first input end of each switch is connected to the output end of the VI conversion module, the second input end of each switch is connected to the control end of the decoding module, and the output end of each switch is connected between two corresponding adjacent small unit resistors.
4. A digital-to-analog converter according to claim 1, characterized in that: The VI conversion module includes a first conversion module and a second conversion module, wherein a first end of the first conversion module is connected to an output end of a first operational amplifier, a second end of the first conversion module is connected to a negative input end of the first operational amplifier, and a third end of the first conversion module is connected to a positive input end of the second operational amplifier; a first end of the second conversion module is connected to an output end of a second operational amplifier, a second end of the second conversion module is connected to a negative input end of the second operational amplifier, and a third end of the second conversion module is an output end of the VI conversion module; and a positive input end of the first operational amplifier is an input end of the VI conversion module.
5. A digital-to-analog converter according to claim 4, characterized in that: The first conversion module includes a first NMOS transistor, and the second conversion module includes a second NMOS transistor. The gate of the first NMOS transistor serves as the first end of the first conversion module, the source of the first NMOS transistor serves as the second end of the first conversion module, and the drain of the first NMOS transistor serves as the third end of the first conversion module; the gate of the second NMOS transistor serves as the first end of the second conversion module, the source of the second NMOS transistor serves as the third end of the second conversion module, and the drain of the second NMOS transistor serves as the second end of the second conversion module.
6. A digital-to-analog converter according to claim 5, characterized in that: The VI conversion module also includes a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is connected to a power supply, and the second end of the first resistor is connected to the drain of the first NMOS transistor and the positive input of the second operational amplifier; the first end of the second resistor is connected to the first end of the third resistor, and the second end of the second resistor is grounded; the second end of the third resistor is connected to the source of the first NMOS transistor and the negative input of the first operational amplifier; the first end of the fourth resistor is connected to the drain of the second NMOS transistor and the negative input of the second operational amplifier, and the second end of the fourth resistor is connected to the power supply.
7. A digital-to-analog converter according to any one of claims 1 to 6, characterized in that: The digital-to-analog converter has a total of n bits of binary code, and the R-2R trapezoidal array module also includes an x-bit middle and high-bit branch and a y-bit high-bit branch, each of the middle and high-bit branches includes a switch, and a resistor with resistance values of 2R and R respectively; each of the high-bit branches includes a switch and a resistor with a resistance value of 2R; the switches of the corresponding middle and high-bit branches are controlled to be connected to a reference voltage or to ground according to the binary code words from the m+1th bit to the m+xth bit; the switches of the corresponding high-bit branches are controlled to be connected to or to ground according to the temperature code words, and the temperature code words are obtained according to the binary code words from the m+x+1th bit to the nth bit; y is equal to 2 or 3.
8. A digital-to-analog converter according to claim 7, characterized in that: After the switches in the middle and high-order branches and the high-order branches are grounded, the output end position of the VI conversion module is exchanged with the output end of the R-2R ladder array module according to the reciprocity theorem. The output end voltage of the R-2R ladder array module of the exchanged circuit is equal to the output end voltage of the R-2R ladder array module of the original circuit. The current of the low-order branch of the exchanged circuit is: I3=1 / 2 n-m I; R-2R trapezoidal array module output voltage after the exchange / original circuit: V I =(b0 B *2 0 +b1 B *2 1 +……+b m-1 B *2 m-1 )*V REF / 2 n , wherein b0 B ~b m-1 B is the 1st to mth binary code word of the digital-to-analog converter, V REF is the reference voltage, and I is the first current output from the VI conversion module to the R-2R ladder array module.
9. A digital-to-analog converter according to claim 8, characterized in that: The decoding module converts the 1st to mth binary codewords of the digital-to-analog converter into a codeword selected from 2 to the power of m, so that the Mth switch in the switch array module is closed according to the converted codeword, and the other switches are disconnected; if M is equal to 0, all switches in the switch array module are disconnected, M = 1, 2, ..., 2 m -1.
10. A digital-to-analog converter according to claim 7, characterized in that: The invention comprises a 6-bit middle and high-bit branch and a 3-bit high-bit branch, wherein the 7th to 12th bit binary codeword controls the middle and high-bit branch, and the 1st to 3rd bit temperature codeword obtained according to the 13th to 14th bit binary codeword controls the high-bit branch; wherein m=6, the decoding module is a 6-64 decoding module, and the 1st to 6th bit binary codeword is converted into a 64-selected 1 codeword; the low-bit branch comprises 64 small unit resistors connected in series, and the switch array module comprises 63 switches, wherein the first input end of each switch is connected to the output end of the VI conversion module, the second input end of the switch is connected to the control end of the decoding module, and the control end of the switch is connected between two corresponding adjacent small unit resistors, and the resistance value of the small unit resistor is one-sixty-fourth of the resistance value of the 2R resistor.