Error code correction method and system for FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an FPGA error code correction method and system, and relates to the technical field of data coding and decoding, and the method comprises the steps: generating Galois field elements based on a received code element vector and a primitive polynomial, and obtaining an adjoint polynomial through 8-code element parallel processing calculation; calculating a coefficient of an error position polynomial through a BM iterative algorithm based on the adjoint polynomial; on the basis of an error position polynomial, 10 Galois field elements are substituted in parallel through a Chien search method, and an error position is obtained through calculation; establishing an evaluation polynomial and an error pattern calculation formula, and performing polynomial division calculation by combining the derivative of the error position polynomial to obtain an error pattern; and performing error code judgment based on the error position and the error pattern, and correcting an error code element through Galois field XOR operation to obtain an updated code element vector. A parallel pipeline design structure is adopted, the FPGA automatically corrects the received error module data in real time under the condition that retransmission is not needed, and the real-time performance and reliability of error code correction are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data encoding and decoding, and in particular to a method and system for correcting errors in FPGA. Background Art

[0002] FPGA, or field programmable gate array, is a common data processing core in communication systems. FPGA has reconfigurable characteristics, can adjust and match various communication protocols, and is also high-speed, so it is widely used in digital signal transmission. In a typical data transceiver architecture, FPGA connects to the wireless communication module through a high-speed serial interface to complete baseband signal processing, protocol encapsulation and physical layer data transmission. However, in actual operation, the transmission medium usually has non-ideal characteristics. Factors such as attenuation caused by the length effect of the transmission cable, impedance mismatch caused by ambient temperature changes, and environmental electromagnetic interference will cause signal waveform distortion, causing inter-symbol interference, clock jitter and noise superposition of the signal, and ultimately causing bit errors. To ensure data reliability, traditional solutions use retransmission mechanisms and verification retransmission strategies. For example, if the module sends the same data again or multiple times, the FPGA end can obtain the correct data through multiple receptions. A big problem with this is that the FPGA has a large delay in obtaining correct data and poor real-time performance. Especially in application scenarios with poor channel conditions, the cumulative delay caused by multiple retransmissions will be more obvious.

[0003] At present, the Chinese invention patent application with application number CN102123060B discloses a method for error testing based on FPGA, which includes: converting the received test data from serial to parallel into parallel data; synchronizing the converted parallel data with the locally generated symbol data; comparing the received parallel data with the locally generated symbol data to calculate the bit error rate. The error testing method of this application uses the integration and flexibility of FPGA to improve the design concept of traditional circuits, instruments, and communication protocols, and can be used in production lines and R&D as the main control chip of error testing instruments. However, this application does not take into account the working conditions of poor channel conditions, and lacks consideration of improving the real-time performance of error correction. Summary of the invention

[0004] The technical problem solved by the present invention is that the error correction technology of traditional FPGA often requires retransmission of communication data. In application scenarios with poor channel conditions, it is difficult to balance stability and real-time performance in the processing of erroneous code elements in communication data.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: A method for correcting an error in an FPGA, comprising: Step S1: Generate a Galois field element α^n based on the received codeword vector and the primitive polynomial, and obtain the adjoint polynomial by parallel processing of 8 codewords; Step S2: Calculate the coefficients of the error position polynomial based on the adjoint polynomial by using the BM iterative algorithm; Step S3: Based on the error location polynomial, the error location SITE is calculated by substituting 10 Galois field elements in parallel through the Qian search method; Step S4: establishing an evaluation polynomial and an error pattern calculation formula, and performing polynomial division calculation based on the derivative of the error position polynomial to obtain the error pattern e; Step S5: Perform error code judgment based on the error position SITE and the error pattern e, and correct the error codeword through Galois Field XOR operation to obtain an updated codeword vector.

[0006] Preferably, in step S11, a Galois field GF(2^8) is defined based on the determined primitive polynomial p(x), wherein the primitive element is denoted as α; Step S12, based on the RS coding theory and the determined primitive polynomial p (x) to obtain the generating polynomial g (x), solving the root of the generating polynomial g (x) to obtain the Galois field element α ^ n; Where n is the power of the root of the generator polynomial and is also the syndrome index; Step S13, pre-calculating based on the Galois Field element α^n to obtain the adjoint polynomial weight α^(kn); Wherein, k is the code element position index; Step S14, segmenting the received code element vector into groups of 8 code elements to obtain a code element segment set; Perform 8-symbol parallel processing calculations on each group of symbol segments in the symbol segment set, perform Galois field multiplication and Galois field addition calculations on each group of symbol segments and the corresponding adjoint polynomial weight to obtain partial sum results, perform cumulative sum calculations on the partial sum results corresponding to each group of symbol segments to obtain coefficients of the adjoint polynomial S, and obtain based on the coefficients of the adjoint polynomial S; Its mathematical expression is: S=[R(1), ..., R(α^n), ..., R(a^(2t-1))]; p(x)=x^8+x^4+x^3+x^2+1; ; Among them, p(x) represents the expansion of the selected primitive polynomial, g(x) represents the expansion of the generating polynomial, x represents the Galois field form variable, that is, the power of the primitive element α, S represents the adjoint polynomial, R(α^n) represents the received codeword vector corresponding to the adjoint index n, and t represents the maximum number of corrected codewords.

[0007] Preferably, in step S21, an error location polynomial Λ(x) is established, and the mathematical expression of Λ(x) is: ; Wherein, Λ(x) represents the error position polynomial, and t represents the maximum number of corrected code elements; Step S22, solving the error location polynomial Λ(x) by using the BM iterative algorithm, assigning two initial values ​​to each iteration parameter based on a preset initial value set, performing 2t iteration operations on the assigned iteration parameters based on the BM iterative algorithm to obtain error location polynomial coefficients, and obtaining the error location polynomial Λ(x) based on the error location polynomial coefficients; The iteration parameters include error position polynomial coefficients, auxiliary polynomial coefficients, current polynomial order, current deviation value and last deviation value, and t represents the maximum number of corrected code elements.

[0008] Preferably, in step S31, the root of the error position polynomial is calculated in the Galois Field GF(2^8) by using an improved Qian search method, and the processing logic of the improved Qian search method includes: Substitute 10 Galois Field elements α^n into the error position polynomial Λ(x) at the same time in each clock cycle, calculate the error position polynomial value, if the error position polynomial value is 0, mark the Galois Field element as a candidate root, if the error position polynomial value is non-zero, mark the Galois Field element as a eliminated root; The candidate roots are screened in three levels, and the wrong position roots are obtained by screening the candidate roots through the series connection of 10-choose-5 root value selectors, 5-choose-3 root value selectors and 3-choose-2 root value selectors; Step S32, if there is no error position root, there is no bit error, and the error position SITE is an empty set; If an error position root exists, the inverse of the error position root is processed, and the error position SITE is obtained based on the inverse of the error position root and a Galois Field inverse element lookup table (LUT).

[0009] Preferably, in step S41, an evaluation polynomial is established, and an error pattern e is calculated based on the adjoint polynomial S and the error position polynomial Λ; Perform polynomial multiplication on the adjoint polynomial S and the error position polynomial Λ, and truncate the high-order terms by performing modular calculation with x^(2t-1) to obtain the evaluation polynomial; Step S42, performing derivative calculation on the error position polynomial Λ, and obtaining the error position polynomial derivative Λ`(x) retaining only the odd-order coefficients based on the derivative definition in the Galois Field; Establish an error pattern calculation formula, perform polynomial division on the evaluation polynomial and the error position polynomial derivative Λ`(x) to obtain the error pattern polynomial e(x), substitute the error position root into the error pattern polynomial e(x) to calculate the error pattern e corresponding to the error position SITE; The mathematical expressions for the error pattern calculation formula and the evaluation polynomial are: ; e(x) = -(Ω(x) / Λ`(x)); Among them, Ω(x) represents the evaluation polynomial, e(x) represents the error pattern polynomial, mod represents the modular operation, Λ`(x) represents the derivative of the error position polynomial, and x represents the Galois field form variable.

[0010] Preferably, in step S51, error judgment is performed based on the error position SITE. When the error position SITE is an empty set, the error judgment result is that there is no error. After reaching a preset delay period, the received code element vector is output; When the error position SITE is not an empty set, the error judgment result is that there is a bit error. The codeword at the error position SITE is extracted from the received codeword vector to obtain the error codeword. The error codeword and the corresponding value in the error pattern e are subjected to Galois field addition processing to obtain the error correction codeword. The error codeword is replaced with the corresponding error correction codeword to obtain an updated codeword vector. After the preset delay period is reached, the updated codeword vector is output.

[0011] An FPGA error correction system includes: an RS decoding timing adjustment module, an RS decoding adjoint polynomial operation module, an RS decoding iteration operation module, an RS decoding root calculation module, an RS decoding error pattern operation module and an RS decoding error correction operation module; The RS decoding timing adjustment module is used to unify the timing of the received code elements; The RS decoding adjoint polynomial operation module is used to realize the coefficient calculation of the adjoint polynomial S; The RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x); The RS decoding root calculation module is used to locate the error symbol position to obtain the error position SITE; The RS decoding error pattern calculation module is used to calculate the error pattern e corresponding to each error position SITE; The RS decoding error correction operation module is used to obtain an updated codeword vector by correcting the error codewords in the received codeword vector.

[0012] Preferably, the RS decoding timing adjustment module is used to unify the timing of the received code elements, perform timing standardization processing on the packet form of the received code elements, eliminate the dynamic interval influence between the start symbol, the data segment, and the end symbol in the packet protocol, and output a uniformly spaced received code element sequence, wherein the packet form is a packet protocol constructed by a packet start, a packet data, and a packet end, and each packet data consists of 198 code elements; The RS decoding companion polynomial operation module is used to realize the coefficient calculation of the companion polynomial S. The coefficients of the companion polynomial S are obtained by calculating the received codeword vector at the Galois field element through an 8-codeword parallel multiplier array and an XOR accumulator tree.

[0013] Preferably, the RS decoding iterative operation module is used to implement iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x), split the BM algorithm into a non-feedback pipeline through the Galois field multiplier and latch register in the four-stage independent iterative unit, and update the coefficients of the error position polynomial step by step to obtain the error position polynomial Λ(x); The RS decoding root-finding operation module is used to locate the error codeword position and obtain the error position SITE. The qian search method of parallel substitution of 10 Galois field elements is implemented through a 10-element parallel test unit. The candidate roots are screened through a series of 10-to-5 root value selectors, 5-to-3 root value selectors and 3-to-2 root value selectors to obtain the error position root, and the error position SITE is determined based on the error position root.

[0014] Preferably, the RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error position SITE, and implement the polynomial division calculation of the evaluation polynomial and the error position polynomial derivative through the polynomial division logic unit, and calculate the error pattern e based on the error pattern polynomial e(x) and the Galois field inverse element lookup table (LUT); The RS decoding error correction operation module is used to correct the error codewords in the received codeword vector to obtain an updated codeword vector, locate the error codeword through the address mapping unit and the error position SITE, and complete the Galois field XOR calculation to cover the error codeword through the XOR operator array to obtain an updated codeword vector.

[0015] Beneficial effects of the invention: This application innovatively proposes a decoding algorithm to identify erroneous codewords through a three-step process of "finding the adjoint polynomial", "finding the error position polynomial", and then "finding the error position". It is possible to correct up to 2 erroneous codewords in every 198 codewords received, and only a small amount of bandwidth is used to transmit supervisory codewords to complete error identification. Without the need for retransmission, the FPGA automatically corrects the received erroneous module data in real time, reducing the delay in obtaining correct data and improving the reliability of the receiving system. The FPGA is able to correct the received module data in real time, thereby uploading and displaying the correct image data in real time. In some application scenarios with high requirements for image output stability and real-time performance, this application is a technical solution with significantly improved effects, achieving a level of error correction performance requirements that are difficult to achieve with current technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A basic flow chart of an FPGA error correction method provided by the present invention; Figure 2 A schematic diagram of the basic framework of an FPGA error correction system provided by the present invention; Figure 3 A schematic diagram of the structure of a RS decoding adjoint polynomial operation module in an FPGA error correction system provided by the present invention; Figure 4 A schematic diagram of the structure of an RS decoding iterative operation module in an FPGA error correction system provided by the present invention; Figure 5 The present invention provides a schematic diagram of the structure of a RS decoding root-finding operation module in an FPGA error correction system. DETAILED DESCRIPTION

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings. It is obvious that the described embodiments are only part of the embodiments of the present invention, but not all of the embodiments.

[0018] Example 1, reference Figure 1 , as an embodiment of the present invention, provides an FPGA error correction method, comprising: Step S1: Generate a Galois field element α^n based on the received codeword vector and the primitive polynomial, and obtain the adjoint polynomial by parallel processing of 8 codewords; Step S2: Calculate the coefficients of the error position polynomial based on the adjoint polynomial by using the BM iterative algorithm; Step S3: Based on the error location polynomial, the error location SITE is calculated by substituting 10 Galois field elements in parallel through the Qian search method; Step S4: establishing an evaluation polynomial and an error pattern calculation formula, and performing polynomial division calculation based on the derivative of the error position polynomial to obtain the error pattern e; Step S5: Perform error code judgment based on the error position SITE and the error pattern e, and correct the error codeword through Galois Field XOR operation to obtain an updated codeword vector.

[0019] In this embodiment, step S11, based on the determined primitive polynomial p(x), a Galois field GF(2^8) is defined, and its primitive element is denoted as α; Step S12, based on the RS coding theory and the determined primitive polynomial p (x) to obtain the generating polynomial g (x), solving the root of the generating polynomial g (x) to obtain the Galois field element α ^ n; Where n∈{0,1,2,3}, n is the power of the root of the generating polynomial and is also the index of the syndrome; Step S13, pre-calculating based on the Galois Field element α^n to obtain the adjoint polynomial weight α^(kn); Where, k∈{0,1,...,197}, k is the code element position index; Step S14, segmenting the received code element vector into groups of 8 code elements to obtain a code element segment set, wherein the number of code elements in the received code element vector is 198, and when segmenting into groups of 8 code elements, the last group is padded with zeros; Perform 8-symbol parallel processing calculations on each group of symbol segments in the symbol segment set, perform Galois field multiplication and Galois field addition calculations on each group of symbol segments and the corresponding adjoint polynomial weight to obtain partial sum results, perform cumulative sum calculations on the partial sum results corresponding to each group of symbol segments to obtain coefficients of the adjoint polynomial S, and obtain based on the coefficients of the adjoint polynomial S; Its mathematical expression is: S=[R(1), ..., R(α^n), ..., R(a^(2t-1))]; p(x)=x^8+x^4+x^3+x^2+1; ; Among them, p(x) represents the expansion of the selected primitive polynomial, g(x) represents the expansion of the generating polynomial, x represents the Galois field form variable, that is, the power of the primitive element α, S represents the adjoint polynomial, R(α^n) represents the received codeword vector corresponding to the adjoint index n, and t represents the maximum number of corrected codewords.

[0020] In this embodiment, in step S21, an error location polynomial Λ(x) is established, and the mathematical expression of Λ(x) is: ; Wherein, Λ(x) represents the error position polynomial, and t represents the maximum number of corrected code elements; Step S22, solving the error location polynomial Λ(x) by using the BM iterative algorithm, assigning two initial values ​​to each iteration parameter based on a preset initial value set, performing 2t iteration operations on the assigned iteration parameters based on the BM iterative algorithm to obtain error location polynomial coefficients, and obtaining the error location polynomial Λ(x) based on the error location polynomial coefficients; The iteration parameters include error position polynomial coefficients, auxiliary polynomial coefficients, current polynomial order, current deviation value and last deviation value, and t represents the maximum number of corrected code elements.

[0021] In this embodiment, step S31, the root of the error position polynomial is calculated in the Galois Field GF(2^8) by using the improved Qian search method, and the processing logic of the improved Qian search method includes: Substitute 10 Galois Field elements α^n into the error position polynomial Λ(x) at the same time in each clock cycle, calculate the error position polynomial value, if the error position polynomial value is 0, mark the Galois Field element as a candidate root, if the error position polynomial value is non-zero, mark the Galois Field element as a eliminated root; The candidate roots are screened in three levels, and the wrong position roots are obtained by screening the candidate roots through the series connection of 10-choose-5 root value selectors, 5-choose-3 root value selectors and 3-choose-2 root value selectors; Step S32, if there is no error position root, there is no bit error, and the error position SITE is an empty set; If an error position root exists, the inverse of the error position root is processed, and the error position SITE is obtained based on the inverse of the error position root and a Galois Field inverse element lookup table (LUT).

[0022] In this embodiment, step S41, establishing an evaluation polynomial, and calculating the error pattern e based on the adjoint polynomial S and the error location polynomial Λ; Perform polynomial multiplication on the adjoint polynomial S and the error position polynomial Λ, and truncate the high-order terms by performing modular calculation with x^(2t-1) to obtain the evaluation polynomial; Step S42, performing derivative calculation on the error position polynomial Λ, and obtaining the error position polynomial derivative Λ`(x) retaining only the odd-order coefficients based on the derivative definition in the Galois Field; Establish an error pattern calculation formula, perform polynomial division on the evaluation polynomial and the error position polynomial derivative Λ`(x) to obtain the error pattern polynomial e(x), substitute the error position root into the error pattern polynomial e(x) to calculate the error pattern e corresponding to the error position SITE; The mathematical expressions for the error pattern calculation formula and the evaluation polynomial are: ; e(x) = -(Ω(x) / Λ`(x)); Among them, Ω(x) represents the evaluation polynomial, e(x) represents the error pattern polynomial, mod represents the modular operation, Λ`(x) represents the derivative of the error position polynomial, and x represents the Galois field form variable.

[0023] In this embodiment, step S51, error judgment is performed based on the error position SITE. When the error position SITE is an empty set, the error judgment result is that there is no error. After reaching a preset delay period, the received code element vector is output; When the error position SITE is not an empty set, the error judgment result is that there is a bit error. The codeword at the error position SITE is extracted from the received codeword vector to obtain the error codeword. The error codeword and the corresponding value in the error pattern e are subjected to Galois field addition processing to obtain the error correction codeword. The error codeword is replaced with the corresponding error correction codeword to obtain an updated codeword vector. After the preset delay period is reached, the updated codeword vector is output.

[0024] Example 2, reference Figure 2-5 , which is an embodiment of the present invention, provides an FPGA error correction system, including: an RS decoding timing adjustment module, an RS decoding adjoint polynomial operation module, an RS decoding iteration operation module, an RS decoding root calculation module, an RS decoding error pattern operation module and an RS decoding error correction operation module; The RS decoding timing adjustment module is used to unify the timing of the received code elements; The RS decoding adjoint polynomial operation module is used to realize the coefficient calculation of the adjoint polynomial S; The RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x); The RS decoding root calculation module is used to locate the error symbol position to obtain the error position SITE; The RS decoding error pattern calculation module is used to calculate the error pattern e corresponding to each error position SITE; The RS decoding error correction operation module is used to obtain an updated codeword vector by correcting the error codewords in the received codeword vector.

[0025] Preferably, the RS decoding timing adjustment module is used to unify the timing of the received code elements, perform timing standardization processing on the packet form of the received code elements, eliminate the dynamic interval influence between the start symbol, the data segment, and the end symbol in the packet protocol, and output a uniformly spaced received code element sequence, wherein the packet form is a packet protocol constructed by a packet start, a packet data, and a packet end, and each packet data consists of 198 code elements; The RS decoding companion polynomial operation module is used to realize the coefficient calculation of the companion polynomial S. The coefficients of the companion polynomial S are obtained by calculating the received codeword vector at the Galois field element through an 8-codeword parallel multiplier array and an XOR accumulator tree.

[0026] Preferably, the RS decoding iterative operation module is used to implement iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x), split the BM algorithm into a non-feedback pipeline through the Galois field multiplier and latch register in the four-stage independent iterative unit, and update the coefficients of the error position polynomial step by step to obtain the error position polynomial Λ(x); The RS decoding root-finding operation module is used to locate the error codeword position and obtain the error position SITE. The qian search method of parallel substitution of 10 Galois field elements is implemented through a 10-element parallel test unit. The candidate roots are screened through a series of 10-to-5 root value selectors, 5-to-3 root value selectors and 3-to-2 root value selectors to obtain the error position root, and the error position SITE is determined based on the error position root.

[0027] Preferably, the RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error position SITE, and implement the polynomial division calculation of the evaluation polynomial and the error position polynomial derivative through the polynomial division logic unit, and calculate the error pattern e based on the error pattern polynomial e(x) and the Galois field inverse element lookup table (LUT); The RS decoding error correction operation module is used to correct the error codewords in the received codeword vector to obtain an updated codeword vector, locate the error codeword through the address mapping unit and the error position SITE, and complete the Galois field XOR calculation to cover the error codeword through the XOR operator array to obtain an updated codeword vector.

[0028] in, Figure 3 This shows the parallel structure for finding the adjoint polynomial: refer to Figure 3 , c0~cn7 represents the code element, r^0~r^n7 represents the coefficient to be multiplied by each code element. It can be seen that the solution of the adjoint polynomial adopts the parallel structure of 8 code elements, that is: every 8 code elements are multiplied with their corresponding coefficients at the same time, and then added at the same time (the addition operation in the Galois field is the XOR operation). In this way, the processing results of 8 code elements are obtained at one time. Finally, several 8-code element processing results are continuously added to obtain the coefficients of the adjoint polynomial. The figure above is a coefficient structure for finding the adjoint polynomial. The adjoint polynomial usually has several coefficients, but the implementation structure is the same. You only need to replace the code element with the corresponding multiplication coefficient r.

[0029] Due to the use of an 8-code element parallel processing structure, if a code length has 255 code elements, it only takes 32 operations to process all the code elements. Compared with the usual single-code element serial processing structure, it takes 255 times to process all the code elements, which improves the efficiency by nearly 8 times and reduces the time by nearly 8 times, thus realizing the acceleration of the algorithm.

[0030] in, Figure 4 The design architecture for finding the error location polynomial Λ is shown: refer to Figure 4 In the structure for solving the error position polynomial, there is no feedback. The output of the current iterative operation is used as the input of the next iterative operation, and the current iterative operation does not require the feedback of the next iterative operation, thus realizing the pipeline structure. A major advantage of this structure is that it can continuously calculate the results. Since there is no feedback between each iterative operation, the independence and simultaneity of each iterative operation is guaranteed. Each iterative operation can be carried out simultaneously without interfering with each other, so the error position polynomial can be solved continuously, the input is continuously updated, and the result is continuously updated. This structure has stronger real-time performance and more efficient and fast processing capabilities than the usual feedback processing structure.

[0031] The fundamental basis for solving the error position polynomial is the BM iterative algorithm. The iterative algorithm after adjustment and optimization is as follows: ; ; In the process of iteratively solving the error location polynomial, Lock_1 and Lock_2 are two latches in the RS decoding iterative operation module, which are used to store the intermediate calculation results generated by the iterative calculation; The function of Lock_1 is to latch the operation results d(1) and Λ(1) of d(j)_1 and Λ(j)(x)_1 in the first iterative operation in the second iterative operation, so as to output d(1) and Λ(1) to the third iterative operation for related operations.

[0032] The function of Lock_2 is to latch the calculation results d(1), Λ(1), d(2), Λ(2) of d(j)_1 / 2 and Λ(j)(x)_1 / 2 in the first and second iterative operations in the third iterative operation, so as to output d(1), Λ(1), d(2), Λ(2) to the fourth iterative operation for related operations.

[0033] In the first iteration, the calculation of X^(ji)_1 and Λ(j)(x)_1 only requires the participation of S(1), while the calculation of d(j)_1 requires the participation of {S(1) S(2)} and Λ(1).

[0034] In the second iterative operation, the calculation of X^(ji)_2 and Λ(j)(x)_2 requires the participation of d(1), Λ(1), and X(1), and the calculation of d(j)_2 requires the participation of {S(1) S(2) S(3)} and Λ(2).

[0035] The calculation of X^(ji)_3 in the third iteration requires the participation of d(2), Λ(2), and X(2). The calculation requires the participation of d(1), Λ(1), d(2), Λ(2), and X(2); the calculation of d(j)_3 requires the participation of {S(2) S(3) S(4)} and Λ(3).

[0036] The fourth iterative operation does not involve the calculation of X^(ji) and d(j). Only Λ(j)(x) needs to be calculated to obtain the final result of Λ. The calculation of Λ(j)(x)_4 requires the participation of d(1), Λ(1), d(2), Λ(2), d(3), Λ(3), and X(3).

[0037] d(n) represents the calculation result of d(j)_n, Λ(n) represents the calculation result of Λ(j)(x)_n, and X(n) represents the calculation result of X^(ji)_n.

[0038] in, Figure 5 This shows a parallel and pipelined structure for finding error locations: refer to Figure 5 , the error position is firstly solved by parallel processing, that is, every 10 Galois Field values ​​are substituted into Λ to solve. If Λ=0, it means that this Galois Field value is the root of Λ. The reason why 10 Galois Field values ​​are processed in parallel instead of 8 is that when solving the adjoint polynomial, every 8 code elements are processed in parallel. Solving the error position will have more steps than solving the adjoint polynomial. In order to achieve a speed balance between the two, the parallel degree of solving the error position should be relatively improved, so 10 values ​​are selected for parallel processing; the error position is also solved by a pipeline structure, which is composed of Figure 5 It can be seen that the solution of each part does not require feedback and is relatively independent. In this way, several groups of 10 Galois field values ​​in a Galois field set can be continuously and parallelly substituted into Λ to find the root, and then the 10 result values ​​are continuously subjected to three-layer screening to continuously narrow the range of the root value, and 5 results that may have root values ​​are selected from the 10 results, and then 3 results that may have root values ​​are selected from the 5 results, and finally 2 results that may have root values ​​are selected from the 3 results. The 10 result values ​​are continuously generated, and the three-layer screening is also continuously carried out until 2 root values ​​are found in a Galois field set or a Galois field set is searched until 2 root values ​​are found in a Galois field set (when the root value is less than 2), and then the search for the error position of the current code length is ended, and the error position has been determined at this time.

[0039] Galois Field set GF(2^m)={0, a^0, a^1, ..., a^(2^m-2)}. Substitute a^n into Λ. If Λ=0, it means that a^n is the root of Λ. Therefore, by continuously substituting a^0, a^1, ..., a^(2^m-2) into Λ, it can be determined whether 0, 2^m-2, 2^m-3, ..., 1 are error positions. In this way, all positions of a code length are confirmed to be wrong.

[0040] The main innovation of the present invention lies in the three steps of "finding the adjoint polynomial", "finding the error position polynomial", and then "finding the error position". These three steps all adopt parallel and pipeline design structures, and achieve rate matching among the three steps, so that not only the operation efficiency and rate of each step are greatly improved, but also each step can work in coordination, and will not cause confusion due to the speed imbalance between the steps.

[0041] It should be understood by those skilled in the art that the embodiments of the present invention may provide methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. Among them, the storage medium may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, referred to as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, referred to as EEPROM), erasable programmable read-only memory (Erasable Programmable Read Only Memory, referred to as EPROM), programmable read-only memory (Programmable Red-Only Memory, referred to as PROM), read-only memory (Read-Only Memory, referred to as ROM), magnetic memory, flash memory, magnetic disk or optical disk. These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0042] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for correcting an error in an FPGA, characterized in that: include: Step S1: Generate a Galois field element α^n based on the received codeword vector and the primitive polynomial, and obtain the adjoint polynomial by parallel processing of 8 codewords; Step S2: Calculate the coefficients of the error position polynomial based on the adjoint polynomial by using the BM iterative algorithm; Step S3: Based on the error location polynomial, the error location SITE is calculated by substituting 10 Galois field elements in parallel through the Qian search method; Step S4: establishing an evaluation polynomial and an error pattern calculation formula, and performing polynomial division calculation based on the derivative of the error position polynomial to obtain the error pattern e; Step S5: Perform error code judgment based on the error position SITE and the error pattern e, and correct the error codeword through Galois Field XOR operation to obtain an updated codeword vector.

2. The method for correcting an error in an FPGA according to claim 1, wherein: Step S11, defining a Galois field GF(2^8) based on the determined primitive polynomial p(x), wherein the primitive element is denoted as α; Step S12, based on the RS coding theory and the determined primitive polynomial p (x) to obtain the generating polynomial g (x), solving the root of the generating polynomial g (x) to obtain the Galois field element α ^ n; Where n is the power of the root of the generator polynomial and is also the syndrome index; Step S13, pre-calculating based on the Galois Field element α^n to obtain the adjoint polynomial weight α^(kn); Wherein, k is the code element position index; Step S14, segmenting the received symbol vector into groups of 8 symbols to obtain a symbol segment set, performing 8-symbol parallel processing calculation on each group of symbol segments in the symbol segment set, performing Galois field multiplication and Galois field addition calculation on each group of symbol segments and the corresponding adjoint polynomial weight to obtain a partial sum result, accumulating and summing the partial sum results corresponding to each group of symbol segments to obtain the coefficient of the adjoint polynomial S, and obtaining based on the coefficient of the adjoint polynomial S; Its mathematical expression is: S=[R(1), ..., R(α^n), ..., R(a^(2t-1))]; p(x)=x^8+x^4+x^3+x^2+1; ; Among them, p(x) represents the expansion of the selected primitive polynomial, g(x) represents the expansion of the generating polynomial, x represents the Galois field form variable, that is, the power of the primitive element α, S represents the adjoint polynomial, R(α^n) represents the received codeword vector corresponding to the adjoint index n, and t represents the maximum number of corrected codewords.

3. The method for correcting an error in an FPGA according to claim 1, wherein: Step S21, establish the error location polynomial Λ(x), the mathematical expression of Λ(x) is: ; Wherein, Λ(x) represents the error position polynomial, and t represents the maximum number of corrected code elements; Step S22, solving the error location polynomial Λ(x) by using the BM iterative algorithm, assigning two initial values ​​to each iteration parameter based on a preset initial value set, performing 2t iteration operations on the assigned iteration parameters based on the BM iterative algorithm to obtain error location polynomial coefficients, and obtaining the error location polynomial Λ(x) based on the error location polynomial coefficients; The iteration parameters include error position polynomial coefficients, auxiliary polynomial coefficients, current polynomial order, current deviation value and last deviation value, and t represents the maximum number of corrected code elements.

4. The method for correcting an error in an FPGA according to claim 1, wherein: Step S31, calculating the root of the error position polynomial in the Galois Field GF(2^8) by using an improved Qian search method, the improved Qian search method processing logic includes: Substitute 10 Galois Field elements α^n into the error position polynomial Λ(x) at the same time in each clock cycle, calculate the error position polynomial value, if the error position polynomial value is 0, mark the Galois Field element as a candidate root, if the error position polynomial value is non-zero, mark the Galois Field element as a eliminated root; The candidate roots are screened in three levels, and the wrong position roots are obtained by screening the candidate roots through the series connection of 10-choose-5 root value selectors, 5-choose-3 root value selectors and 3-choose-2 root value selectors; Step S32, if there is no error position root, there is no bit error, and the error position SITE is an empty set; If an error position root exists, the inverse of the error position root is processed, and the error position SITE is obtained based on the inverse of the error position root and a Galois Field inverse element lookup table (LUT).

5. The method for correcting an error in an FPGA according to claim 1, wherein: Step S41, establishing an evaluation polynomial, and calculating the error pattern e based on the adjoint polynomial S and the error location polynomial Λ; Perform polynomial multiplication on the adjoint polynomial S and the error position polynomial Λ, and truncate the high-order terms by performing modular calculation with x^(2t-1) to obtain the evaluation polynomial; Step S42, performing derivative calculation on the error position polynomial Λ, and obtaining the error position polynomial derivative Λ`(x) retaining only the odd-order coefficients based on the derivative definition in the Galois Field; Establish an error pattern calculation formula, perform polynomial division on the evaluation polynomial and the error position polynomial derivative Λ`(x) to obtain the error pattern polynomial e(x), substitute the error position root into the error pattern polynomial e(x) to calculate the error pattern e corresponding to the error position SITE; The mathematical expressions for the error pattern calculation formula and the evaluation polynomial are: ; e(x) = -(Ω(x) / Λ`(x)); Among them, Ω(x) represents the evaluation polynomial, e(x) represents the error pattern polynomial, mod represents the modular operation, Λ`(x) represents the derivative of the error position polynomial, and x represents the Galois field form variable.

6. The method for correcting bit errors of an FPGA as claimed in claim 1, wherein: Step S51, performing error judgment based on the error position SITE, when the error position SITE is an empty set, the error judgment result is that there is no error, and the received code element vector is output after reaching a preset delay period; When the error position SITE is not an empty set, the error judgment result is that there is a bit error. The codeword at the error position SITE is extracted from the received codeword vector to obtain the error codeword. The error codeword and the corresponding value in the error pattern e are subjected to Galois field addition processing to obtain the error correction codeword. The error codeword is replaced with the corresponding error correction codeword to obtain an updated codeword vector. After the preset delay period is reached, the updated codeword vector is output.

7. An FPGA error correction system, used to implement the FPGA error correction method according to claim 1, characterized in that: include: RS decoding timing adjustment module, RS decoding adjoint polynomial operation module, RS decoding iteration operation module, RS decoding root calculation module, RS decoding error pattern operation module and RS decoding error correction operation module; The RS decoding timing adjustment module is used to unify the timing of the received code elements; The RS decoding adjoint polynomial operation module is used to realize the coefficient calculation of the adjoint polynomial S; The RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x); The RS decoding root calculation module is used to locate the error symbol position to obtain the error position SITE; The RS decoding error pattern calculation module is used to calculate the error pattern e corresponding to each error position SITE; The RS decoding error correction operation module is used to obtain an updated codeword vector by correcting the error codewords in the received codeword vector.

8. The FPGA error correction system according to claim 7, characterized in that: The RS decoding timing adjustment module is used to unify the timing of the received code elements, perform timing standardization processing on the packet form of the received code elements, eliminate the dynamic interval influence between the start symbol, data segment, and end symbol in the packet protocol, and output a uniformly spaced received code element sequence, wherein the packet form is a packet protocol constructed by packet start, packet data, and packet end, and each packet data consists of 198 code elements; The RS decoding companion polynomial operation module is used to realize the coefficient calculation of the companion polynomial S. The coefficients of the companion polynomial S are obtained by calculating the received codeword vector at the Galois field element through an 8-codeword parallel multiplier array and an XOR accumulator tree.

9. The FPGA error correction system according to claim 7, characterized in that: The RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x). The BM algorithm is split into a non-feedback pipeline through the Galois field multiplier and latch register in the four-stage independent iteration unit, and the coefficients of the error position polynomial are updated stage by stage to obtain the error position polynomial Λ(x). The RS decoding root-finding operation module is used to locate the error codeword position and obtain the error position SITE. The qian search method of parallel substitution of 10 Galois field elements is implemented through a 10-element parallel test unit. The candidate roots are screened through a series of 10-to-5 root value selectors, 5-to-3 root value selectors and 3-to-2 root value selectors to obtain the error position root, and the error position SITE is determined based on the error position root.

10. The FPGA error correction system according to claim 7, characterized in that: The RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error position SITE, and implements the polynomial division calculation of the evaluation polynomial and the error position polynomial derivative through the polynomial division logic unit, and calculates the error pattern e based on the error pattern polynomial e(x) and the Galois field inverse element lookup table (LUT); The RS decoding error correction operation module is used to correct the error codewords in the received codeword vector to obtain an updated codeword vector, locate the error codeword through the address mapping unit and the error position SITE, and complete the Galois field XOR calculation to cover the error codeword through the XOR operator array to obtain an updated codeword vector.

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