High-precision millisecond time message generation method based on FPGA
The FPGA module generates a high-precision millisecond clock signal based on the 1PPS and 10MHz clock signal, and groups packets with the time message data, solving the problem of unstable timing accuracy in the prior art, and achieving high-precision millisecond time message output.
Patent Information
- Application Number
- CN202411265273.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-05-16
AI Technical Summary
When the prior art uses the 1PPS+TOD protocol to obtain time information, the timing accuracy is unstable and generally greater than 100ns.
Through the FPGA module, the received 1PPS pulse signal and 10MHz clock signal are used to generate a high-precision millisecond clock signal, and packet it with the time message data to output high-precision millisecond time message.
It realizes the output of high-precision millisecond time packets, improves timing accuracy, and ensures the stability of time synchronization.
Smart Images
Figure CN120017238A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of satellite communication technology, and in particular to a high-precision millisecond time message generation method based on FPGA. Background Art
[0002] When conventional users acquire time information, they often obtain accurate time information from the carrier device through the 1PPS+TOD protocol. Specifically, it is necessary to start transmitting the time information (TOD) message 1ms after capturing the rising edge of the 1PPS, and transmit it within 500ms. The TOD message indicates the current 1PPS trigger rising edge time, and the TOD protocol message is sent once per second. In practical applications, the time synchronization accuracy is mostly improved by changing the rising edge time of the output PPS second pulse, but the timing accuracy of this method is unstable, and the timing accuracy is generally greater than 100ns. Summary of the invention
[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a high-precision millisecond time message generation method based on FPGA to increase timing accuracy and stability.
[0004] The objective of the present invention is achieved through the following technical solutions: A high-precision millisecond time message generation method based on FPGA, comprising: Step S1: In the demodulation stage, the receiver module receives the satellite signal, demodulates the 1PPS pulse signal and the first time message data and outputs them to the CPU module; Step S2: In the synchronization calibration stage, after the CPU module receives the 1PPS pulse signal and the first time message data, it completes the local time update to obtain the second time message data and calibrates the constant temperature crystal oscillator module, so that the constant temperature crystal oscillator module outputs an accurate and stable 10MHz clock signal to the FPGA; Step S3: During the data transmission phase, the CPU module transmits the second time message data to the FPGA, and the FPGA stores the data transmitted by the CPU module in the first buffer area, waiting for further packet processing; Step S4: In the ms moment generation stage, the FPGA captures the rising edge of the 1PPS pulse signal output by the receiver module, generates a millisecond clock signal using the 10MHz clock signal output by the constant temperature crystal oscillator module, and counts the millisecond pulses; Step S5: In the time message packet output stage, the counting information of the millisecond clock signal and the second time message data stored in the first buffer area are packetized to obtain the third time message data, and the third time message data is stored in the second buffer area. The FPGA reads the second buffer area and outputs the third time message data.
[0005] Furthermore, the step S4 specifically includes: The FPGA collects the 1PPS pulse signal output by the receiver module with a period of 100ns. When the rising edge of the PPS is collected, the first counting register ms_div_cnt and the second counting register ms_time_cnt are cleared. The rising edge of the 10MHz clock signal is used as a trigger signal. When the first rising edge of the 10MHz clock signal is detected, the millisecond clock signal is pulled high. At the same time, the first counting register ms_div_cnt counts the rising edges of the 10MHz clock signal from zero. When ms_div_cnt counts to 4999, the millisecond clock signal is inverted and ms_div_cnt is cleared. Whenever ms_div_cnt=4999, the second counting register ms_time_cnt is incremented by 1, and the second counting register ms_time_cnt counts until 999 and then is cleared.
[0006] Furthermore, the counting information of the millisecond clock signal is obtained by continuously assigning the counting value of the second counting register ms_time_cnt through an assign statement.
[0007] Furthermore, the CPU module and the FPGA communicate with each other via an SPI bus; and the FPGA outputs the third time message data via a UART serial port.
[0008] Furthermore, the second buffer area has 2 more bits than the first buffer area for storing counting information of the millisecond clock signal.
[0009] The beneficial effects of the present invention are: The present invention uses a 10MHz clock signal and a 1PPS pulse signal to obtain a high-precision millisecond clock signal, and packages the counting information of the millisecond clock signal and the message data, and the output third time message data carries high-precision millisecond counting information, that is, high-precision millisecond time message output is realized. When the user equipment uses the 1PPS+TOD protocol to obtain accurate time information, the TOD data carrying high-precision millisecond counting information can effectively improve the timing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 A working principle diagram of a high-precision millisecond time message generation method based on FPGA provided by the present invention; Figure 2 This is a schematic diagram of high-precision millisecond time message output in the present invention. DETAILED DESCRIPTION
[0011] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0012] See also Figure 1-Figure 2 , the present invention provides a technical solution: like Figure 1 , a high-precision millisecond time message generation method based on FPGA, comprising: Step S1: In the demodulation stage, the receiver module receives the satellite signal, demodulates the 1PPS pulse signal and the first time message data and outputs them to the CPU module; The receiver module receives satellite signals through an external antenna and transmits time information and 1PPS to the CPU module through the UART interface.
[0013] Step S2: In the synchronization calibration stage, after the CPU module receives the 1PPS pulse signal and the first time message data, it completes the local time update to obtain the second time message data and calibrates the constant temperature crystal oscillator module, so that the constant temperature crystal oscillator module outputs an accurate and stable 10MHz clock signal to the FPGA; In some specific embodiments, the CPU module completes the local time update and obtains the second time message data by updating the time information and measuring and correcting the difference with the local time.
[0014] Step S3: During the data transmission phase, the CPU module transmits the second time message data to the FPGA, and the FPGA stores the data transmitted by the CPU module in the first buffer area, waiting for further packet processing; Step S4: In the ms moment generation stage, the FPGA captures the rising edge of the 1PPS pulse signal output by the receiver module, generates a millisecond clock signal using the 10MHz clock signal output by the constant temperature crystal oscillator module, and counts the millisecond pulses; Step S4 specifically includes: The FPGA collects the 1PPS pulse signal output by the receiver module with a period of 100ns. When the rising edge of the PPS is collected, the first counting register ms_div_cnt and the second counting register ms_time_cnt are cleared. The rising edge of the 10MHz clock signal is used as a trigger signal. When the first rising edge of the 10MHz clock signal is detected, the millisecond clock signal is pulled high. At the same time, the first counting register ms_div_cnt counts the rising edges of the 10MHz clock signal from zero. When ms_div_cnt counts to 4999, the millisecond clock signal is inverted and ms_div_cnt is cleared. Whenever ms_div_cnt=4999, the second counting register ms_time_cnt is incremented by 1, and the second counting register ms_time_cnt counts until 999 and then is cleared.
[0015] The principle of the present invention to obtain a high-precision millisecond clock signal (1KHz) by using a 10MHz clock signal and a 1PPS pulse signal is that one pulse of a 10MHz clock is 100ns, and the high level of a 1ms pulse with a duty cycle of 50% required is 500us. If 10MHz is used as a trigger signal, 5000 pulses are required, that is, 500us / 100ns=5000; the result of the ms moment generation stage is as follows Figure 2 As shown, the FPGA captures the rising edge of the 1PPS signal output by the receiver as the 0 time of ms, and then accumulates ms by counting; when ms_div_cnt=4999, ms_div_cnt is cleared to start counting again, and at the same time, a standard millisecond clock pulse with a period of 50% is obtained by inverting it. The accuracy of the millisecond clock signal (1KHz) obtained by pulse counting can be better than ±100ns.
[0016] Step S5: In the time message packet output stage, the counting information of the millisecond clock signal and the second time message data stored in the first buffer area are packetized to obtain the third time message data, and the third time message data is stored in the second buffer area. The FPGA reads the second buffer area and outputs the third time message data.
[0017] In some embodiments, the counting information of the millisecond clock signal is obtained by continuously assigning the counting value of the second counting register ms_time_cnt through an assign statement. The second buffer area has 2 more bits than the first buffer area for storing the counting information of the millisecond clock signal. The counting information of the millisecond clock signal represents the current ms time information. At this time, the second buffer is a register rich in ms time information, and the output third time message data carries high-precision millisecond counting information, that is, high-precision millisecond time message output is achieved.
[0018] In some embodiments, the CPU module and the FPGA communicate via an SPI bus; and the FPGA outputs the third time message data via a UART serial port.
[0019] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.
Claims
1. A high-precision millisecond time message generation method based on FPGA, characterized in that: include: Step S1: In the demodulation stage, the receiver module receives the satellite signal, demodulates the 1PPS pulse signal and the first time message data and outputs them to the CPU module; Step S2: In the synchronization calibration stage, after the CPU module receives the 1PPS pulse signal and the first time message data, it completes the local time update to obtain the second time message data and calibrates the constant temperature crystal oscillator module, so that the constant temperature crystal oscillator module outputs an accurate and stable 10MHz clock signal to the FPGA; Step S3: During the data transmission phase, the CPU module transmits the second time message data to the FPGA, and the FPGA stores the data transmitted by the CPU module in the first buffer area, waiting for further packet processing; Step S4: In the ms moment generation stage, the FPGA captures the rising edge of the 1PPS pulse signal output by the receiver module, generates a millisecond clock signal using the 10MHz clock signal output by the constant temperature crystal oscillator module, and counts the millisecond pulses; Step S5: In the time message packet output stage, the counting information of the millisecond clock signal and the second time message data stored in the first buffer area are packetized to obtain the third time message data, and the third time message data is stored in the second buffer area. The FPGA reads the second buffer area and outputs the third time message data.
2. The method for generating high-precision millisecond time messages based on FPGA according to claim 1, characterized in that: The step S4 specifically includes: The FPGA collects the 1PPS pulse signal output by the receiver module with a period of 100ns. When the rising edge of the PPS is collected, the first counting register ms_div_cnt and the second counting register ms_time_cnt are cleared. The rising edge of the 10MHz clock signal is used as a trigger signal. When the first rising edge of the 10MHz clock signal is detected, the millisecond clock signal is pulled high. At the same time, the first counting register ms_div_cnt counts the rising edges of the 10MHz clock signal from zero. When ms_div_cnt counts to 4999, the millisecond clock signal is inverted and ms_div_cnt is cleared. Whenever ms_div_cnt=4999, the second counting register ms_time_cnt is incremented by 1, and the second counting register ms_time_cnt counts until 999 and then is cleared.
3. The method for generating high-precision millisecond time messages based on FPGA according to claim 2, characterized in that: The counting information of the millisecond clock signal is obtained by continuously assigning the counting value of the second counting register ms_time_cnt through an assign statement.
4. The method for generating high-precision millisecond time messages based on FPGA according to claim 1, characterized in that: The CPU module and the FPGA communicate with each other via the SPI bus; the FPGA outputs the third time message data via the UART serial port.
5. The method for generating high-precision millisecond time messages based on FPGA according to claim 3, characterized in that: The second buffer area has 2 more bits than the first buffer area for storing counting information of the millisecond clock signal.