A Digital Gain Control Method and System for Dual-Mode Communication in Power Grid

Abstract

The present invention discloses a digital gain control method and system for dual-mode communication in a power grid, belonging to the field of communication technologies. The system includes an analog front-end module, a digital system module, and a synchronization system module. The analog front-end module includes a programmable gain amplifier and a digital-to-analog converter. The digital system module includes a digital filtering module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor. After the received signal is processed by the analog front-end module, the quantized digital signal obtained after processing is transmitted to the digital system module, and finally the data processed by the digital system is output to the synchronization system module to complete the digital gain control of communication, solving the technical problems of poor signal data consistency and poor stability in the digital gain control process in the prior art.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to a digital gain control method and system for dual-mode power grid communication. Background Art

[0002] With the rapid development of smart grids, high-power line carrier communication (HPLC) and high-reliability radio frequency communication (HRF) play important roles in the fields of power grid automation, power consumption information collection, distributed energy access, etc. as two main communication methods. However, the power line channel environment is complex, with problems such as large noise interference and severe attenuation; wireless communication is easily affected by environmental factors, with problems such as signal fading and multipath effects. These factors will lead to a decline in the quality of communication signals and affect the reliability and stability of communication.

[0003] To overcome the above problems, orthogonal frequency division multiplexing (OFDM) technology has been introduced into the power grid communication field. OFDM is a multi-carrier transmission scheme that can effectively combat specific frequency attenuation and narrowband interference. It divides the entire communication frequency band into multiple mutually orthogonal and overlapping sub-bands, significantly improving the spectrum utilization efficiency and having strong anti-interference ability. In a dual-mode communication system based on OFDM technology, wired and wireless have similar physical frame structures, including three parts: preamble, frame control, and payload. At the receiving end, the signal processing process usually includes the following steps:

[0004] 1. Automatic gain control (AGC): Using the time-domain repetition characteristic of the preamble sequence, adjust the amplitude of the received signal to keep its energy moderate and stable.

[0005] 2. Frame synchronization: Determine the starting position of the valid data through delay correlation or local cross-correlation calculation.

[0006] 3. Channel estimation and frequency offset estimation: Estimate the channel and frequency offset based on the preamble data.

[0007] 4. Demodulation and decoding: Demodulate, deinterleave, and decode the payload to finally recover the user data.

[0008] In the above process, as a key module of the receiver, AGC directly affects the accuracy of signal synchronization, channel estimation, and frequency offset estimation, and thus determines the overall performance of the receiver. If the AGC adjustment is improper, it may lead to signal distortion, synchronization failure, or channel estimation error, seriously affecting the communication quality.

[0009] Currently, a two-stage cascaded AGC structure is generally adopted in the receiver to achieve the optimization and stable processing of the dynamic range of the received signal. This structure includes an analog gain control stage and a digital gain control stage. Through the collaborative work of the two-stage gain control, it is ensured that the received signal can be accurately gain-adjusted in both the analog domain and the digital domain, thereby improving the dynamic range and signal processing performance of the system.

[0010] However, the traditional digital AGC still has the following problems in practical applications:

[0011] 1. Long window time: The traditional method usually requires a long signal window to cover the signal characteristics, which increases the time pressure for synchronization.

[0012] 2. Data consistency disruption: Before the AGC stabilizes, the signal data is affected by the gain change, which may lead to the disruption of data consistency. Especially in the case of a short leading time or a large synchronization lock-in delay, the data may even become unavailable. Summary of the Invention

[0013] Aiming at the problems of long window time and data consistency disruption existing in the prior art, the present invention proposes a digital gain control method and system for power grid dual-mode communication, aiming to improve the accuracy and stability of digital gain control.

[0014] To achieve the above object, the present invention provides a digital gain control method for power grid dual-mode communication.

[0015] Preferably, the received signal is quantized to obtain a quantized digital signal, and then the quantized digital signal is subjected to gain control calculation. Finally, the calculated gain control data is output to the synchronization module to complete the digital gain control of the communication.

[0016] Preferably, the gain control calculation includes the following steps: configuring and starting, inputting quantized data and reading cached data, calculating the gain, amplifying the quantized data and updating the cached data, updating the cached data and reading the cached data, compensating the gain of the cached data, emptying the cached data and switching the data path.

[0017] Preferably, the configuring and starting step includes: the processor configures the parameters of the digital automatic gain control module, and starts the digital automatic gain control calculation process after the configuration is completed; the parameters include the total number of data points, the number of input data points, the number of stored data points, the filtering threshold of the amplitude interval data points, and the amplification retention shift number.

[0018] Preferably, the steps of inputting quantized data and reading cached data include: the digital filter transmits the quantized data to the control core according to the number of input data points, and the data stack transmits the quantized data to the control core according to the number of stored data points.

[0019] Preferably, the step of calculating the gain includes: the control core calculates the left shift amplification bits based on the input quantization and cached data according to the amplitude interval data point filtering threshold and the amplified retention shift bits.

[0020] Preferably, the steps of amplifying the quantized data and updating the cached data include: the left shift amplifier receives the left shift amplification bits from the control core, amplifies the input data, and transmits the output data to the data stack, and the data stack updates the data.

[0021] Preferably, the steps of updating the cached data and reading the cached data include: after receiving the synchronization lock signal, while the data stack updates the data, it reads the data in the stack to the bidirectional shift amplifier.

[0022] Preferably, the step of compensating the gain of the cached data includes: after receiving the synchronization lock signal, the bidirectional shift amplifier receives the left shift amplification bits output by the control core and compensates the shift amplification bits of the data from the data stack.

[0023] Preferably, the steps of clearing the cached data and switching the data path include: after receiving the synchronization lock signal, the data stack determines whether the data in the data stack is empty; if it is empty, it selects the first path of data from the left shift amplifier, and if it is not empty, it selects the second path of data from the bidirectional shift amplifier and performs channel estimation and frequency offset calculation.

[0024] To achieve the above object, the present invention also provides a digital gain control system for dual-mode communication in a power grid, including an analog front-end module, a digital system module, and a synchronization system module.

[0025] Preferably, after the received signal is processed by the analog front-end module, the processed quantized digital signal is transmitted to the digital system module, and finally the data processed by the digital system is output to the synchronization system module to complete the digital gain control of the communication.

[0026] Preferably, the analog front-end includes a programmable gain amplifier and a digital-to-analog converter;

[0027] Preferably, the digital system includes a digital filter module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor.

[0028] Preferably, the programmable gain amplifier adopts a two-stage cascade structure, and its gain configuration is derived from the digital system.

[0029] Preferably, the programmable gain amplifier transmits the signal to the digital-to-analog converter, and the digital-to-analog converter processes the signal to obtain a quantized digital signal.

[0030] Preferably, the configuration parameters of the core control module are sourced from the processor, and the configuration parameters include: the total number of calculated data points N, the number of input data points N1, the number of stored data points N2, the filtering threshold of the number of data points in the amplitude range , the amplification retention shift number R; the configuration parameters satisfy: N = N1 + N2, 1 < < N / (W - 1), 1 < R < W, where W is the digital quantization data bit width; the digital filter module and the data stack transmit the data to the core control module, and the left shift amplifier receives the amplification factor output by the core control module and performs an arithmetic left shift operation on the data transmitted by the digital filter module.

[0031] Preferably, the left shift amplifier transfers the data to the data stack and caches the data after the left shift operation and the number of bits of the left shift operation.

[0032] Preferably, the data stack adopts a ping-pong storage structure and stores the data output by the left shift amplifier in real time before the synchronization signal is issued by the synchronization module, and provides backtracking data to the core control module for digital gain calculation in each digital gain control cycle; the storage and read data addresses of the data stack adopt a unidirectional increasing and loop-back manner; after the synchronization module releases the synchronization signal and before its own read-empty signal is valid, the data stack stores the data output by the left shift amplifier in real time, and at the same time outputs the backtracking data to the bidirectional shift amplifier; the backtracking data includes left-shifted amplified data and the number of left-shifted amplification bits.

[0033] Preferably, the input data of the bidirectional shift amplifier comes from the data stack, including: left-shifted amplified data and the corresponding amplification shift number; the bidirectional shift amplifier receives the amplification shift number locked by the core control module; when the data path of the bidirectional shift amplifier is selected, the calculation of the effective amplification shift number is performed: the effective amplification shift number is equal to the difference between the corresponding amplification shift number and the amplification shift number locked by the core control module; when the effective amplification shift number is greater than zero, the bidirectional shift amplifier performs a right shift reduction operation; when the effective amplification shift number is less than zero, the bidirectional shift amplifier performs a left shift amplification operation; when the effective amplification shift number is equal to zero, the data remains unchanged.

[0034] Preferably, the first path data of the first data path selector is from the left shift amplifier, and the second path data is from the bidirectional shift amplifier. When the data in the data stack is empty, the first data path selector selects the first path data; otherwise, it selects the second path data. The first path data of the second data path selector is from the first data selector, and the second path data is from the left shift amplifier. When the lock signal of the synchronization module is high and continuously valid, the second data selector selects the first signal; otherwise, it selects the second path data.

[0035] Preferably, the synchronization module issues a lock signal. After the lock signal is locked, the receiver used in the digital gain control process retrieves some data before the lock signal is locked from the data stack and performs channel estimation and frequency offset calculation. Moreover, this part of the data is consistent with the lock amplification shift number after passing through the bidirectional shift amplifier.

[0036] Compared with the prior art, the technical solution of the present invention has the following advantages / beneficial effects:

[0037] 1. Through the reverse compensation mechanism of the data stack and the bidirectional shift amplifier, the consistency of signal data is ensured, the number of available signal data is increased, and the overall performance of the system is improved.

[0038] 2. By retrieving the signal peak value through the data backtracking method, the stabilization time in the digital gain control process is significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0040] Figure 1 is a flow chart of a digital gain control method for dual-mode power grid communication according to the present invention.

[0041] Figure 2 is a flow chart of gain control calculation used in the present invention.

[0042] Figure 3 is a schematic diagram of a digital gain control system for dual-mode power grid communication according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely below. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all of them. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. Therefore, the detailed description of the embodiments of the present invention provided below is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it may not be further defined and explained in subsequent figures.

[0045] Embodiment 1:

[0046] As Figure 1 shown, the present invention provides a digital gain control method for dual-mode communication in a power grid, which is applicable to both wired communication and wireless communication.

[0047] The received signal is quantized to obtain a quantized digital signal, and then the quantized digital signal is subjected to gain control calculation. Finally, the calculated gain control data is output to the synchronization module to complete the digital gain control of communication.

[0048] As Figure 2 shown, the gain control calculation includes the following steps: configuring startup, inputting quantized data and reading cached data, calculating gain, amplifying quantized data and updating cached data, updating cached data and reading cached data, compensating the gain of cached data, emptying cached data and switching data paths.

[0049] The step of configuring startup includes: the processor configures the parameters of the digital automatic gain control module, and starts the digital automatic gain control calculation process after the configuration is completed; the parameters include the total number of data points, the number of input data points, the number of stored data points, the filtering threshold of the number of data points in the amplitude range, and the amplification retention shift number.

[0050] The step of inputting quantized data and reading cached data includes: the digital filter transmits the quantized data to the control core according to the number of input data points, and the data stack transmits the quantized data to the control core according to the number of stored data points.

[0051] The step of calculating gain includes: the control core calculates the left shift amplification number based on the input quantization and cached data according to the filtering threshold of the number of data points in the amplitude range and the amplification retention shift number.

[0052] The steps of quantifying data amplification and cache data update include: The left shift amplifier receives the left shift amplification bits from the control core, amplifies the input data, and transmits the output data to the data stack, where the data stack updates the data.

[0053] The steps of cache data update and reading cache data include: After the data stack receives the synchronization lock signal, while updating the data, the data stack reads out the data in the stack to the bidirectional shift amplifier.

[0054] The steps of cache data gain compensation include: After the bidirectional shift amplifier receives the synchronization lock signal, the bidirectional shift amplifier receives the left shift amplification bits output by the control core and compensates the shift amplification bits for the data from the data stack.

[0055] The steps of clearing cache data and switching data paths include: After the data stack receives the synchronization lock signal, it judges whether the data in the data stack is empty; if it is empty, it selects the first path of data from the left shift amplifier, and if it is not empty, it selects the second path of data from the bidirectional shift amplifier and performs channel estimation and frequency offset calculation.

[0056] After completing the above steps, the calculation result is output, and the entire gain control process is completed.

[0057] Embodiment 2: As Figure 3 shown, a digital gain control system for dual-mode power grid communication is provided, including an analog front-end module, a digital system module, and a synchronization system module.

[0058] After the received signal is processed by the analog front-end module, the processed quantized digital signal is transmitted to the digital system module, and finally the data processed by the digital system is output to the synchronization system module to complete the digital gain control of communication.

[0059] The analog front-end includes a programmable gain amplifier and a digital-to-analog converter. The programmable gain amplifier adopts a two-stage cascaded structure, and its gain configuration comes from the digital system. The overall dynamic range is -20dB~67dB, and the gain step is 3dB. The quantization bit width of the digital-to-analog converter is 14bit, and the sampling rate is 25MHz; the programmable gain amplifier transmits the signal to the digital-to-analog converter to obtain the quantized digital signal.

[0060] The digital system includes a digital filter module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor.

[0061] The programmable gain amplifier adopts a two-stage cascaded structure, and its gain configuration comes from the digital system.

[0062] The programmable gain amplifier transmits the signal to the digital-to-analog converter, and the quantized digital signal is obtained after being processed by the digital-to-analog converter.

[0063] The configuration parameters of the core control module are sourced from the processor. The configuration parameters include: the total number of calculated data points N, the number of input data points N1, the number of stored data points N2, the filtering threshold for the number of data points in the amplitude range , the amplification retention shift number R; the configuration parameters satisfy: N = N1 + N2, 1 < < N / (W - 1), 1 < R < W, where W is the digital quantization data bit width;

[0064] The digital filter module and the data stack transmit data to the core control module. The left shift amplifier receives the amplification factor output by the core control module and performs an arithmetic left shift operation on the data transmitted by the digital filter module.

[0065] The left shift amplifier transfers the data to the data stack and caches the data after the left shift operation and the number of bits of the left shift operation.

[0066] The data stack adopts a ping-pong storage structure and stores the data output by the left shift amplifier in real time before the synchronization module issues a synchronization signal. And in each digital gain control cycle, it provides backtracking data to the core control module for digital gain calculation; the storage and read data addresses of the data stack adopt a unidirectional increasing and loop-back method; after the synchronization module releases the synchronization signal and before its own read-empty signal is valid, the data stack stores the data output by the left shift amplifier in real time and outputs the backtracking data to the bidirectional shift amplifier; the backtracking data includes the left-shifted amplified data and the left-shifted amplification bits.

[0067] The input data of the bidirectional shift amplifier comes from the data stack, including: the left-shifted amplified data and the corresponding amplification shift number; the bidirectional shift amplifier receives the amplification shift number locked by the core control module; when the data path of the bidirectional shift amplifier is selected, the calculation of the effective amplification shift number is performed: the effective amplification shift number is equal to the difference between the corresponding amplification shift number and the amplification shift number locked by the core control module; when the effective amplification shift number is greater than zero, the bidirectional shift amplifier performs a right shift reduction operation; when the effective amplification shift number is less than zero, the bidirectional shift amplifier performs a left shift amplification operation; when the effective amplification shift number is equal to zero, the data remains unchanged.

[0068] The first path data of the first data path selector comes from the left shift amplifier, and the second path data comes from the bidirectional shift amplifier. When the data in the data stack is empty, the first data path selector selects the first path data; otherwise, it selects the second path data. The first path data of the second data path selector comes from the first data selector, and the second path data comes from the left shift amplifier. When the lock signal of the synchronization module is high and continuously valid, the second data selector selects the first signal; otherwise, it selects the second path data.

[0069] The synchronization module issues a lock signal. After the lock signal is locked, the receiver used in the digital gain control process retrieves some data before the lock signal is locked from the data stack and performs channel estimation and frequency offset calculation, and this part of the data is consistent with the lock amplification shift number after passing through the bidirectional shift amplifier.

[0070] The digital system includes a digital filter module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor.

[0071] The above are only the preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be regarded as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. For those of ordinary skill in the art in this technical field, without departing from the spirit and scope of the present invention, several improvements and refinements can also be made, and these improvements and refinements should also be regarded as within the protection scope of the present invention.

Claims

1. A digital gain control method for dual-mode communication in a power grid, characterized in that, The received signal is quantized to obtain a quantized digital signal, and then the quantized digital signal is subjected to gain control calculation. Finally, the calculated gain control data is output to the synchronization module to complete the digital gain control of communication. The gain control calculation includes the following steps: configuration startup, input quantization data and read cache data, calculate gain, amplify quantization data and update cache data, update cache data and read cache data, perform gain compensation on cache data, clear cache data and switch data paths. The configuration startup step: refers to the processor configuring the parameters of the digital automatic gain control module, and starting the digital automatic gain control calculation process after the configuration is completed; the parameters include the total number of data points, the number of input data points, the number of stored data points, the filtering threshold for the number of data points in the amplitude range, and the amplification retention shift number. The step of input quantization data and read cache data includes: the digital filter transmits the quantization data to the control core according to the number of input data points, and the data stack transmits the quantization data to the control core according to the number of stored data points. The step of calculating gain includes: the control core calculates the left shift amplification number based on the input quantization and cache data according to the filtering threshold for the number of data points in the amplitude range and the amplification retention shift number. The step of amplifying quantization data and updating cache data includes: the left shift amplifier amplifies the input data after receiving the left shift amplification number from the control core, and transmits the output data to the data stack, and the data stack updates the data. The step of updating cache data and reading cache data includes: after the data stack receives the synchronization lock signal, while updating the data in the data stack, the data in the stack is read out to the bidirectional shift amplifier. The step of performing gain compensation on cache data includes: after the bidirectional shift amplifier receives the synchronization lock signal, the bidirectional shift amplifier receives the left shift amplification number output by the control core and compensates the data from the data stack for the shift amplification number. The step of clearing cache data and switching data paths includes: after the data stack receives the synchronization lock signal, it judges whether the data in the data stack is empty; if it is empty, it selects the first path of data from the left shift amplifier, and if it is not empty, it selects the second path of data from the bidirectional shift amplifier and performs channel estimation and frequency offset calculation.

2. A digital gain control system for dual-mode communication in a power grid, characterized in that, It includes an analog front-end module, a digital system module, and a synchronization module. After the received signal is processed by the analog front-end module, the obtained quantized digital signal is transmitted to the digital system module, and finally the data processed by the digital system module is output to the synchronization module to complete the digital gain control of communication. The analog front-end includes a programmable gain amplifier and a digital-to-analog converter. The digital system module includes a digital filtering module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor; among which, the digital filtering module, the left shift amplifier, the data stack, the bidirectional shift amplifier, the first data path selector, and the second data path selector are connected in series in sequence. The processor is connected to the core control module, and the core control module is respectively connected to the digital filtering module, the left shift amplifier, the data stack, and the bidirectional shift amplifier. The left shift amplifier is connected to the first data path selector and the second data path selector, and the first data path selector is connected to the second data path selector; The programmable gain amplifier adopts a two-stage cascaded structure, and its gain configuration is derived from the digital system module; The programmable gain amplifier transmits the signal to the digital-to-analog converter, and the quantized digital signal is obtained after being processed by the digital-to-analog converter; The configuration parameters of the core control module are sourced from the processor. The configuration parameters include: the total number of calculated data points N, the number of input data points N1, the number of stored data points N2, and the amplitude interval data point filtering threshold , the amplification retention shift number of bits R; the configuration parameters satisfy: N = N1 + N2, 1 < < N / (W - 1), 1 < R < W, where W is the digital quantization data bit width; the digital filter module and the data stack pass the data to the core control module. The left shift amplifier receives the amplification factor output by the core control module and performs an arithmetic left shift operation on the data passed in by the digital filter module; The left shift amplifier transfers the data to the data stack and caches the data after the left shift operation and the number of bits of the left shift operation; The data stack adopts a ping-pong storage structure, and the data output by the left shift amplifier is stored in real time before the synchronization signal is sent by the synchronization module. And in each digital gain control cycle, the data stack provides the backtracking data to the core control module for the calculation of digital gain; the storage and read data addresses of the data stack adopt a unidirectional increasing and loop-back method; after the synchronization module releases the synchronization signal and before its own read-empty signal is valid, the data stack stores the data output by the left shift amplifier in real time, and at the same time outputs the backtracking data to the bidirectional shift amplifier; the backtracking data includes the left-shifted amplified data and the left-shifted amplification bits; The input data of the bidirectional shift amplifier comes from the data stack, including: the left-shifted amplified data and the corresponding amplified shift bits; the bidirectional shift amplifier receives the amplified shift bits locked by the core control module; when the data path of the bidirectional shift amplifier is selected, the calculation of the effective amplified shift bits is carried out: the effective amplified shift bits is equal to the difference between the corresponding amplified shift bits and the amplified shift bits locked by the core control module; when the effective amplified shift bits is greater than zero, the bidirectional shift amplifier performs a right shift reduction operation; when the effective amplified shift bits is less than zero, the bidirectional shift amplifier performs a left shift amplification operation; when the effective amplified shift bits is equal to zero, the data remains unchanged; The first path of data of the first data path selector comes from the left shift amplifier, and the second path of data comes from the bidirectional shift amplifier. When the data in the data stack is empty, the first data path selector selects the first path of data, otherwise it selects the second path of data; the first path of data of the second data path selector comes from the first data path selector, and the second path of data comes from the left shift amplifier. When the lock signal of the synchronization module is high and remains valid, the second data path selector selects the first path of data, otherwise it selects the second path of data; The synchronization module issues a locking signal. After the locking signal is locked, the receiver used in the digital gain control process retraces part of the data before the locking signal is locked from the data stack and performs channel estimation and frequency offset calculation, and this part of the data is made to be consistent with the locked amplification shift number after passing through a bidirectional shift amplifier.

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