Video coding and decoding protection device and method, electronic equipment, storage medium and program

Abstract

The invention provides a video coding and decoding protection device and method, electronic equipment, a storage medium and a program, and relates to the technical field of computers and communication, in particular to the video processing and video coding and decoding technology, and the video coding and decoding protection device is in communication connection with a video coding and decoding IP core; the video coding and decoding protection device is also in communication connection with the bus controller; the video coding and decoding protection device is used for acquiring a working state signal of a video coding and decoding IP core and a coding and decoding control signal of a bus controller; performing protection processing on the coding and decoding control signal according to the current state of the working state signal; and controlling the video coding and decoding IP core to execute video coding and decoding operation according to the protection processing result of the coding and decoding control signal. According to the embodiment of the invention, the application stability and reliability of the video coding and decoding IP core can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer and communication technology, and in particular to video processing and video encoding and decoding technology. Background Art

[0002] As people's demand for various video information increases day by day, video codec technology has become more important. Video codecs can be divided into software codecs and hardware codecs. In general, software codecs can bring better compression effects, while hardware codecs have the advantages of real-time and low latency. Therefore, in some application scenarios that require high codec speeds, such as AI (Artificial Intelligence) real-time reasoning, hardware codecs will be used. Hardware codecs are implemented based on chips that support video applications. If you want to develop such chips, you need to integrate video codec IP (Intellectual Property Core) cores into the chip. Since the video codec IP core is relatively complex to design, it is usually necessary to purchase a mature video codec IP core developed by a third party and integrate it into its own chip architecture. For the integrator, the use of commercial third-party video codec IP cores will greatly reduce the development time and shorten the product cycle, but how to ensure the stability and reliability of the video codec IP core application is also a key issue for each integrator. Summary of the invention

[0003] The embodiments of the present disclosure provide a video codec protection device, method, electronic device, storage medium and program, which can improve the stability and reliability of video codec IP core applications.

[0004] In a first aspect, an embodiment of the present disclosure provides a video codec protection device, wherein the video codec protection device is communicatively connected to a video codec IP core; the video codec protection device is also communicatively connected to a bus controller; wherein the video codec protection device is used to:

[0005] Acquire the working status signal of the video codec IP core and the codec control signal of the bus controller;

[0006] Performing protection processing on the encoding and decoding control signal according to the current state of the working state signal;

[0007] The video codec IP core is controlled to perform video codec operations according to the protection processing result of the codec control signal.

[0008] In a second aspect, an embodiment of the present disclosure provides a video codec protection method, which is applied to a video codec protection device, wherein the video codec protection device is communicatively connected to a video codec IP core; the video codec protection device is also communicatively connected to a bus controller; the video codec protection method comprises:

[0009] Acquire the working status signal of the video codec IP core and the codec control signal of the bus controller;

[0010] Performing protection processing on the encoding and decoding control signal according to the current state of the working state signal;

[0011] The video codec IP core is controlled to perform video codec operations according to the protection processing result of the codec control signal.

[0012] In a third aspect, an embodiment of the present disclosure provides an electronic device, including the video codec protection device described in the first aspect; the electronic device further includes:

[0013] at least one processor; and

[0014] A memory is communicatively coupled to the at least one processor.

[0015] In a fourth aspect, an embodiment of the present disclosure further provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the video codec protection method provided in the embodiment of the second aspect.

[0016] In a fifth aspect, an embodiment of the present disclosure further provides a computer program product, including a computer program, which, when executed by a processor, implements the video codec protection method provided in the embodiment of the second aspect.

[0017] The disclosed embodiment connects a video codec protection device between the bus controller and the video codec IP core, obtains the working status signal of the video codec IP core and the codec control signal of the bus controller through the video codec protection device, and performs protection processing on the codec control signal according to the current state of the working status signal, thereby controlling the video codec IP core to perform video codec operations according to the protection processing result of the codec control signal. This can solve the problems of low stability and reliability of the existing directly integrated video codec IP core when performing video codec processing, and can improve the stability and reliability of the video codec IP core application.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0020] Figure 1 It is a structural schematic diagram of the connection relationship between the video codec IP core and the bus controller in the prior art;

[0021] Figure 2 It is a structural schematic diagram of a video encoding and decoding protection device provided by an embodiment of the present disclosure;

[0022] Figure 3 It is a structural schematic diagram of another video coding and decoding protection device provided by an embodiment of the present disclosure;

[0023] Figure 4 It is a schematic diagram of the connection relationship between a video coding and decoding protection device and other modules provided by an embodiment of the present disclosure;

[0024] Figure 5 It is a structural schematic diagram of another video coding and decoding protection device provided by an embodiment of the present disclosure;

[0025] Figure 6 is a flow chart of a video coding protection method provided by an embodiment of the present disclosure;

[0026] Figure 7 It is a flow chart of a video codec protection method performed by a video codec protection device based on protection logic provided by an embodiment of the present disclosure;

[0027] Figure 8 It is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0029] When the integrator integrates a mature video codec IP core developed by a third party into the chip architecture, if the chip with the video codec IP core is applied to real business scenarios, it is very important to ensure that the system can run for a long time without errors or downtime. However, this stability is usually difficult to achieve. The difficulty lies in that some problems often need to be reproduced in specific scenarios, under specific complex software stacks, and after running for a long time. If there is no quick way to reproduce the problem, it will make it difficult to locate the problem.

[0030] For codec video applications, one of the common stability issues is that an unknown bug (buggy, error or fault) generates an incorrect software control flow, which in turn causes an error in the video codec IP core. For general error flows, the protection mechanism inside the video codec IP core can block them and provide error status information. However, if an error flow that cannot be blocked by the protection mechanism of the video codec IP core is encountered, it will cause confusion inside the IP core, that is, the video codec IP core itself is no longer reliable. When the video codec IP core becomes internally confused and the unknown source of the bug cannot be found, it is often necessary to continue looking for clues inside the video codec IP core. However, for the integrator of the third-party video codec IP core, it will be difficult to expand due to insufficient understanding of the inside of the video codec IP core, and thus it is impossible to continue tracking the problem.

[0031] At the hardware level, when integrating a third-party video codec IP core, the video codec IP core is usually connected to the interfaces of other modules in the chip, such as the bus AXI (Advanced eXtensible Interface) and APB (Advanced Peripheral Bus), as well as interrupts, clocks, and resets. Then, various verifications such as timing analysis, power consumption analysis, simulation verification, and FPGA (Field Programmable Gate Array) verification are performed based on the integrated chip structure to ensure the reliability of the entire system hardware level. In other words, the video codec IP core manufacturer guarantees the reliability of the video codec IP core itself, the integrator is responsible for the reliability of the integrated connection, and then the reliability of the entire system including other hardware modules is guaranteed through verification testing.

[0032] At the software level, the integrator usually integrates the SDK (Software Development Kit) provided by the third-party IP core company into its own software stack. In the design of the software stack, the open source Linux (Unix-based open source operating system) operating system or other real-time operating systems are usually used. Taking the Linux operating system as an example, the SDK is usually divided into a driver layer and a user state layer. The application controls the video codec IP core by calling the API (Application Programming Interface) provided by the SDK user state layer. The API communicates with the hardware by setting multiple registers of the video codec IP core.

[0033] In summary, the stability and reliability of the video codec IP core at the system level depends on four aspects: the reliability of the IP core itself, the reliability of the integrated IP core, the reliability of other hardware modules, and the reliability of the software control process of the video codec IP core.

[0034] For third-party IP core companies, they pay more attention to the video codec IP core itself, ensuring the correctness, performance and image quality of its codec, so a lot of tests by third-party IP core companies will focus on whether it can work normally under different resolutions, different bit rates and different scenarios. The business scenarios are relatively simple. However, how to ensure the reliability of the video codec IP core itself in real business scenarios, on chips integrated with video codec IP cores, under complex software stack applications, and under high concurrency based on multi-threading and multi-process, while integrating these various factors, is often not a concern for third-party IP core manufacturers.

[0035] For the integrator, during the chip development stage, various analyses and verifications will be performed to ensure the reliability of integration and other hardware modules. However, based on the belief that the commercial video codec IP core itself should be reliable enough, usually no additional design is done to ensure the reliability of the video codec IP core itself.

[0036] The reliability of the software control process is based on the reliability of the SDK provided by the third-party IP core manufacturer on the one hand, and on the reliability of the control process of the application based on the SDK on the other hand. Due to the flexibility of the software, errors are usually easy to occur in both aspects, which in turn affects the stability of the system. When the software error touches the hardware level of the video codec IP core, the video codec IP core will report an interrupt through the internal error mechanism, and then the application can query the status register to determine the specific error, and then do further debugging.

[0037] Figure 1 FIG. 1 is a schematic diagram of the connection relationship between the video codec IP core and the bus controller in the prior art. Figure 1 As shown, the codec IP may be the main hardware structure of the video codec IP core, and the registers connected to the codec IP may be all register structures of the video codec IP core, which are the register sets opened by the video codec IP core to control the codec functions. That is, Figure 1 The registers and codec IP shown in the figure constitute a complete video codec IP core. The interface of the video codec IP core generally includes the interface of AXI and APB bus, as well as other interfaces such as interrupt, reset and clock. After the integrator connects the hardware interface, Figure 1 As shown in the figure, when the bus controller configures the registers of the video codec IP core through software, the values ​​of these registers will eventually be transmitted to the video codec IP core through the APB bus interface, and the image data used for encoding or decoding in the memory will be accessed by the video codec IP core through the AXI interface. When the bus controller sends the start control signal through software, the codec of the video codec IP core starts to perform the video encoding and decoding task until the frame task is completed and the software layer of the bus controller is notified.

[0038] The existing technical solutions guarantee the stability of the video codec system to a certain extent through standardized software and hardware design processes, but various problems will still be encountered in actual applications. In general, there are usually no problems with the video codec IP core, integrated video codec IP core and other hardware modules, but the reliability of the software is difficult to guarantee. Due to the flexibility of the software, various stability problems may be triggered. Although the status register will prompt the error direction when the software error reaches the video codec IP core level, due to the diversity and uncontrollability of software errors, it is very likely that the software error will cause confusion inside the hardware video codec IP core and give wrong status information, thereby misleading the debugging direction. Moreover, once the software error problem is sporadic and difficult to reproduce, it will make the problem solving very difficult. It is specifically reflected in the following aspects:

[0039] (1) Various software errors may cause the registers in the video codec IP core to be written randomly:

[0040] First, in some software designs, the codec program maps the video codec IP core registers to the user state to facilitate reading and writing the registers of the video codec IP core. Once the registers of the video codec IP core are mapped to the user state, it means that these registers used to control the hardware can be accessed in the form of memory read and write. In a multi-process and multi-threaded operating environment, if other process software is wrong and illegally accesses memory, such as memory out of bounds, it may affect these registers, that is, write some wrong data into the registers of the video codec IP core. When the video codec IP core is working, that is, the video codec IP core is reading and writing these registers to perform the encoding and decoding tasks of the current frame, once the registers are rewritten by other processes, different results will be produced according to the specific circumstances of the rewrite. The registers may be rewritten by other similar codec control logic into related information of other code streams, and the registers may also be changed into meaningless garbled codes by other programs unrelated to the codec control logic due to memory out of bounds. Especially when the register is changed to garbled characters, the protection mechanism of the video codec IP core itself is difficult to cope with this risk. The video codec IP core is likely to enter an unknown disordered state, and the reported status information is no longer reliable. In other words, it is difficult to obtain the real cause of the error from the hardware status, which cannot help locate the problem and may even mislead the positioning direction.

[0041] Secondly, even if the software design does not map the video codec IP core registers to the user state, that is, the reading and writing of the registers are uniformly managed at the driver layer, although this can prevent other processes from writing registers randomly to a certain extent, the driver level must ensure that it can fully consider the synchronization and mutual exclusion of various multi-process and multi-threaded concurrent situations, and the requirements for driver reliability will be very high. If the driver is not well written, it means that the risk of the above registers being written randomly still exists.

[0042] Finally, the user's application scenarios are often complex, and the video codec IP core may be interrupted by various signals when working. If the signal processing at all levels of the software stack, from the SDK to the application, is not carefully considered, it is easy to produce erroneous software control processes, which may cause registers to be written randomly.

[0043] (2) Once the registers of the video codec IP core are randomly written, it is difficult to find the root cause of the error:

[0044] First, the registers of the video codec IP core are randomly written. When tracking the cause of the error, the register dump (referring to the process of printing or saving the register contents of the chip core as a file) may not be the first scene. The register status seen at this time will be correct, that is, the error scene where the register is randomly written cannot be captured, and then it cannot be discovered that the error is caused by the register being randomly written.

[0045] Secondly, when the registers of the video codec IP core are written randomly, the integrator may find that the video codec IP core is in an error state and think that it is an error of the video codec IP core itself. However, they are not familiar enough with the internal structure of the third-party video codec IP core and cannot debug deeply.

[0046] Finally, when the registers of the video codec IP core are randomly written, it is usually an occasional problem that is difficult to reproduce. The third-party IP core manufacturer will not be able to reproduce it. When the integrator cannot find the necessary conditions for reproduction, the third-party IP core manufacturer will not be able to provide more relevant suggestions.

[0047] In one example, Figure 2 is a structural diagram of a video encoding and decoding protection device provided by an embodiment of the present disclosure, such as Figure 2 As shown, the video codec protection device 110 is connected to the video codec IP core 120 for communication; the video codec protection device 110 is also connected to the bus controller 130 for communication; wherein the video codec protection device 110 is used for:

[0048] Obtaining the working status signal of the video codec IP core 120 and the codec control signal of the bus controller 130;

[0049] Performing protection processing on the encoding and decoding control signal according to the current state of the working state signal;

[0050] The video codec IP core 120 is controlled to perform video codec operations according to the protection processing result of the codec control signal.

[0051] Among them, the video codec protection device 110 can be a hardware protection logic device, which is used to protect the signal sent by the bus controller 130 to the video codec IP core 120. The video codec IP core 120 is a reusable logic unit in the integrated circuit design, which is mainly used for compression and decompression of video data. IP core refers to a reusable module in the form of a logic unit and chip design provided by one party in semiconductor design. The IP core can be authorized to another party for use. The external processor can be a processor in the chip structure, which can usually be a CPU (central processing unit) or a GPU (graphics processing unit), etc. The embodiment of the present disclosure does not limit the type and function of the external processor. The bus controller 130 can be a controller for controlling the encoding and decoding operation of the video codec IP core 120. Exemplarily, the bus controller 130 can be an APB bus controller, as long as it can control the encoding and decoding operation of the video codec IP core 120, and the embodiment of the present disclosure does not limit the controller type of the bus controller 130.

[0052] The working state signal may be a signal for reflecting whether the video codec IP core 120 is in working state. The codec control signal may be a signal sent by the bus controller 130 to the video codec IP core 120 for controlling the video codec IP core 120 to perform video codec operations.

[0053] In the process of the bus controller 130 performing software control on the video codec IP core 120, the bus controller 130 can control the video codec IP core 120 to perform video codec operations through codec control signals. It is understandable that when the video codec IP core 120 is in a working state, the bus controller 130 should not send control instructions to the video codec IP core 120. Therefore, if the bus controller 130 sends a control instruction to the video codec IP core 120 when the video codec IP core 120 is in a working state, it will cause problems in the software control process.

[0054] To avoid the problems of the video codec IP core in the software control process and improve the reliability and stability of the video codec IP core, such as Figure 1As shown, in the embodiment of the present disclosure, a video codec protection device 110 is configured between the bus controller 130 and the video codec IP core 120. The video codec protection device 110 receives the codec control signal sent by the bus controller 130 to the video codec IP core 120 to obtain the control information of the bus controller 130 on the video codec IP core 120. At the same time, the video codec protection device 110 can also obtain the working state signal of the video codec IP core 120 to obtain the current working state of the video codec IP core 120 according to the working state signal of the video codec IP core 120.

[0055] Accordingly, the video codec protection device 110 can perform protection processing on the codec control signal according to the current state of the working state signal, so as to prevent the bus controller 130 from sending an erroneous codec control signal to the video codec IP core 120. Specifically, when the video codec protection device 110 determines that the video codec IP core 120 is in the working state according to the current state of the working state signal of the video codec IP core 120, it can shield the codec control signal sent by the bus controller 130 to the video codec IP core 120, so as to prevent the codec control signal from writing the register of the video codec IP core 120 randomly; when the video codec protection device 110 determines that the video codec IP core 120 is in the idle state according to the current state of the working state signal of the video codec IP core 120, it can allow the bus controller 130 to send the codec control signal to the video codec IP core 120, that is, allow the bus controller 130 to control the video codec IP core 120, so as to control the video codec IP core 120 to perform normal video codec operations through normal codec control signals.

[0056] It can be seen that the video codec protection device 110 implements shielding or enabling processing of the codec control signal sent by the bus controller 130 according to the current state of the working state signal of the video codec IP core 120, that is, completes the protection processing of the codec control signal. Furthermore, according to the protection processing result of the codec control signal, the video codec IP core 120 is controlled to perform the video codec operation, which can limit the software control flow of the video codec IP core 120 from the hardware level, and avoid the wrong codec control signal from writing the register of the video codec IP core 120. The above-mentioned video codec protection device 110 provides a protection mechanism for hardware video codec IP, which can avoid the impact of non-standard software control flow on the reliability of the video codec IP core 120 itself, improve the protection effectiveness of the video codec IP core 120, and can reduce the generation of stability problems to a certain extent, thereby improving the stability and reliability of the application of the video codec IP core 120.

[0057] The disclosed embodiment connects a video codec protection device between the bus controller and the video codec IP core, obtains the working status signal of the video codec IP core and the codec control signal of the bus controller through the video codec protection device, and performs protection processing on the codec control signal according to the current state of the working status signal, thereby controlling the video codec IP core to perform video codec operations according to the protection processing result of the codec control signal. This can solve the problems of low stability and reliability of the existing directly integrated video codec IP core when performing video codec processing, and can improve the stability and reliability of the video codec IP core application.

[0058] In one example, Figure 3 It is a structural diagram of another video codec protection device provided by an embodiment of the present disclosure. Based on the technical solutions of the above embodiments, the embodiment of the present disclosure has been optimized and improved, and a variety of specific optional implementation methods of the video codec protection device are provided.

[0059] Correspondingly, such as Figure 3 As shown, the video codec protection device 110 may include a flip module 111, a first AND gate module 112 and a second AND gate module 113, and the codec control signal may include a chip select signal and a write control signal; wherein:

[0060] The input end of the flip module 111 is communicatively connected to the output end of the working status signal of the video codec IP core 120, the first output end of the flip module 111 is communicatively connected to the first input end of the first AND gate module 112, and the second output end of the flip module 111 is also communicatively connected to the first input end of the second AND gate module 113.

[0061] The second input terminal of the first AND gate module 112 is communicatively connected to the output terminal of the chip selection signal (PSEL) of the bus controller 130 , and the output terminal of the first AND gate module 112 is communicatively connected to the first input terminal of the video codec IP core 120 .

[0062] The second input terminal of the second AND gate module 113 is communicatively connected to the output terminal of the write control signal (PWRITE) of the bus controller 130 , and the output terminal of the second AND gate module 113 is communicatively connected to the second input terminal of the video codec IP core 120 .

[0063] Among them, the flip module 111 can be used to flip the working state signal of the video codec IP core 120. The working state signal can be referred to as a busy signal, which is output by the video codec IP core 120. When the signal is at a high level, it indicates that the video codec task is in progress, and when it is at a low level, it indicates that it is idle. The first AND gate module 112 and the second AND gate module 113 can be two basic logic gate circuits of AND gates. The chip select signal PSEL can be a chip select signal of the APB bus, which is used to select the target device. The write control signal PWRITE can be a write control signal of the APB bus, which indicates a write operation when it is at a high level.

[0064] Optionally, the flip module 111 may adopt a flip circuit structure, which may be any type of circuit structure with a signal flipping function, and the embodiment of the present disclosure does not limit the specific internal structure of the flip module 111. The input end of the flip module 111 may be connected to the output end of the working state signal of the video codec IP core 120, so as to input the working state signal of the video codec IP core 120 as an input signal to the flip module 111. At the same time, the first output end of the flip module 111 is communicatively connected to the first input end of the first AND gate module 112, and the second output end of the flip module 111 is also communicatively connected to the first input end of the second AND gate module 113, so that after flipping the working state signal, the flipped signal is input to the first AND gate module 112 through the first output end, and the flipped signal is input to the second AND gate module 112 through the second output end.

[0065] The second input terminal of the first AND gate module 112 is communicatively connected to the output terminal of the chip select signal of the bus controller 130 , and the output terminal of the first AND gate module 112 is communicatively connected to the first input terminal of the video codec IP core 120 to implement protection processing of the chip select signal of the bus controller 130 .

[0066] The second input end of the second AND gate module 113 is communicatively connected to the output end of the write control signal of the bus controller 130 , and the output end of the second AND gate module 113 is communicatively connected to the second input end of the video codec IP core 120 to implement protection processing of the write control signal of the bus controller 130 .

[0067] In the APB bus environment, the access to the registers of the video codec IP core is usually controlled by the chip select signal PSEL, the write control signal PWRITE and the transmission enable signal PENABLE. When the master device needs to access the registers of the codec of the video codec IP core, the bus controller will pull up the corresponding PSEL signal, and will also pull up the PWRITE signal, and then transmit through the address bus and the data bus to configure the registers of the video codec IP core. In order to implement the protection mechanism under the APB bus framework, it is necessary to protect and control the PWRITE signal and the PSEL signal. The signal of the APB bus is generally generated by the APB bus controller. In the system architecture, the APB bus signal is part of the standard interface, and it is generally not recommended to directly modify the signal generated by the APB bus controller. The above technical solution, by adopting a flip module, a first AND gate module and a second AND gate module to form a video codec protection device, thereby providing the protection logic of the video codec IP core in the form of hardware, realizing secondary processing of the bus signal, and not directly modifying the signal of the bus itself, so that the access protection can be realized without modifying the internal functional logic of the video codec IP core and the bus controller. This protection mechanism is more standardized and will not affect other peripherals on the bus.

[0068] Figure 4 is a schematic diagram of the connection relationship between a video codec protection device and other modules provided by an embodiment of the present disclosure. In a specific example, Figure 4 As shown, the video codec protection device can control the PSEL signal and PWRITE signal sent by the bus controller according to the busy signal, thereby forming a protection for the video codec IP core codec. Optionally, the protection logic of the video codec protection device can be: when the video codec IP core is executing the codec task, the bus controller is prohibited from writing to the register of the video codec IP core; when the codec task of the video codec IP core is completed, the bus controller is restored to the write access of the register of the video codec IP core. The video codec IP core can store the data involved in the video codec operation in the memory through the AXI bus. Therefore, the core of the video codec protection device is to shield the erroneous write operation by adding control logic to the PWRITE signal and PSEL signal of the bus controller. It can be understood that the specific hardware structure of the video codec protection device can also be integrated in the hardware design inside the video codec IP core, and the embodiment of the present disclosure does not limit this.

[0069] In an optional embodiment of the present disclosure, Figure 3As shown, the video codec protection device 110 can also be used to: generate a codec protection signal corresponding to the codec control signal according to the type of the codec control signal; control the current signal state of the codec protection signal according to the current state of the working state signal; and control the video codec IP core to perform the video codec operation according to the current signal state of the codec protection signal.

[0070] The codec protection signal may be a substitute signal generated after performing protection processing on the codec control signal, and is used to replace the codec control signal to control the video codec IP core 120 to perform video codec operations.

[0071] When a codec protection signal corresponding to the codec control signal is generated according to the type of the codec control signal, such as Figure 3 As shown, for the chip select signal PSEL, a corresponding first codec protection signal protected_PSEL can be generated; for the write control signal PWRITE, a corresponding second codec protection signal protected_PWRITE can be generated. Further, the video codec protection device 110 can control the current signal states of the first codec protection signal protected_PSEL and the second codec protection signal protected_PWRITE according to the current state of the working state signal busy, and then control the video codec IP core 120 to perform the video codec operation according to the current signal state of the codec protection signal.

[0072] By generating a corresponding codec protection signal for the codec control signal, the codec protection signal is used to replace the codec control signal to control the video codec IP core to perform video codec operations. This can be a shielding or enabling effect on the codec control signal, thereby realizing the protection logic of the video codec IP core.

[0073] In an optional embodiment of the present disclosure, Figure 3 As shown, the video codec protection device 110 can also be used to: when it is determined that the current state of the working state signal is the working state, control the current signal state of the codec protection signal to be a signal shielding state; when it is determined that the current state of the working state signal is the idle state, set the current signal state of the codec protection signal to the current signal state of the codec control signal.

[0074] Specifically, Figure 3As shown, the video codec protection device 110 can determine the current state of the working state signal busy according to the value of the working state signal busy. Optionally, when the working state signal busy is at a high level, that is, the value is 1, it can be determined that the current state of the working state signal is the working state; when the working state signal busy is at a low level, that is, the value is 0, it can be determined that the current state of the working state signal is the idle state.

[0075] Correspondingly, if the video codec protection device 110 determines that the current state of the working state signal is the working state, the current signal state of the codec protection signal can be controlled to be a signal shielding state. Optionally, the signal shielding state can be a low level state, that is, the signal value is 0. If the video codec protection device 110 determines that the current state of the working state signal is the idle state, the current signal state of the codec protection signal can be set to the current signal state of the codec control signal, that is, the codec control signal can be encoded.

[0076] In a specific example, Figure 3 As shown, if the video codec protection device 110 determines that the busy signal is at a high level, that is, when the value is 1, it can be determined that the current state of the busy signal is a working state, indicating that the video codec IP core 120 is currently executing a video codec task of a certain frame of video. At this time, the video codec protection device 110 can flip the busy signal through the flip module 111, that is, the first output end and the second output end of the flip module 111 both output low-level signals. Correspondingly, the first input end of the first AND gate module 112 has a value of 0, then no matter how much the value of PSEL received at the second input end of the first AND gate module 112 is, the output end of the first AND gate module 112 will output a low-level signal, that is, the value of protected_PSEL is 0. Similarly, the first input end of the second AND gate module 113 has a value of 0, then no matter how much the value of PWRITE received at the second input end of the second AND gate module 113 is, the output end of the second AND gate module 113 will output a low-level signal, that is, the value of protected_PWRITE is 0. Therefore, when the busy signal takes a value of 1, that is, when the video codec IP core 120 is currently executing a video codec task, PSEL and PWRITE can be effectively shielded.

[0077] Similarly, if the video codec protection device 110 determines that the busy signal is at a low level, that is, when the value is 0, it can be determined that the current state of the busy signal is an idle state, indicating that the video codec IP core 120 is not currently performing a video codec task. At this time, the video codec protection device 110 can flip the busy signal through the flip module 111, that is, the first output end and the first output end of the flip module 111 both output high-level signals. Correspondingly, the first input end of the first AND gate module 112 is 1, then the protected_PSEL output by the output end of the first AND gate module 112 is the same as the value of the PSEL received by its second input end. That is, when the value of PSEL is 1, the value of protected_PSEL is also 1; when the value of PSEL is 0, the value of protected_PSEL is also 0. Similarly, the first input end of the second AND gate module 113 is 1, then the protected_PWRITE output by the output end of the second AND gate module 113 is the same as the value of PWRITE received by its second input end. That is, when PWRITE takes a value of 1, protected_PWRITE also takes a value of 1; when PWRITE takes a value of 0, protected_PWRITE also takes a value of 0. Therefore, when the busy signal takes a value of 0, that is, when the video codec IP core 120 is not currently executing a video codec task, PSEL and PWRITE can be enabled.

[0078] In summary, the video codec protection device can implement the following protection logic:

[0079] If busy = 1, set protected_PSEL = 0 and protected_PWRITE = 0 to prohibit write operations on the video codec IP core;

[0080] If busy = 0, protected_PSEL and protected_PWRITE are allowed to transmit PSEL and PWRITE signals normally, and write operations are allowed for the video codec IP core.

[0081] In the above technical solution, when the working state signal is high, the external bus controller is not allowed to set the register opened to the outside by the video codec IP core. Only when the codec of the video codec IP core completes the work, the hardware interrupt state bit is pulled high, and the hardware interrupt signal is triggered, that is, when the working state signal is low, the bus controller is allowed to set the register of the video codec IP core again, thereby forming an effective protection mechanism for the video codec IP core.

[0082] Figure 5FIG. 1 is a schematic diagram of the structure of another video codec protection device provided by an embodiment of the present disclosure. In an optional embodiment of the present disclosure, Figure 5 As shown, the video codec protection device 110 may further include a counter 114, wherein a first input terminal of the counter 114 is communicatively connected to an output terminal of a working status signal of the video codec IP core 120, a second input terminal of the counter 114 is communicatively connected to an output terminal of a chip select signal of the bus controller 130, and a third input terminal of the counter 114 is communicatively connected to an output terminal of a write control signal of the bus controller 130; wherein: the counter 114 is used to count the number of erroneous write operations of the bus controller 130.

[0083] In an optional embodiment of the present disclosure, the video codec protection device 110 is also used to: when it is determined that the current state of the working state signal is the working state, and when it is determined that the current signal state of the codec control signal is the write operation state, determine that the bus controller is currently performing an erroneous write operation; and trigger the counter to count the number of operations of the erroneous write operation.

[0084] The counter 114 can count the number of erroneous write operations of the bus controller 130. The erroneous write operation refers to the write operation performed by the bus controller 130 on the video codec IP core 120 through the chip select signal PSEL and the write control signal PWRITE during the period when the video codec IP core 120 performs the video codec operation. If the video codec protection device determines that the current state of the working state signal is the working state, and at the same time determines that the current signal state of the codec control signal is the write operation state, it can be determined that the bus controller 130 is currently performing an erroneous write operation. Optionally, during the busy=1 period, the counter 114 can perform the operation of accumulating the current count by 1 each time the rising edge of the PSEL signal and the PWRITE signal is detected, that is, when an erroneous write register operation is detected, so as to trigger the counting of the number of erroneous write operations.

[0085] Optionally, the output terminal of the counter 114 ( Figure 5 The bus controller 130 (not shown) can be connected to an external processor for communication, and is used to send the statistical result of the number of erroneous write operations of the bus controller 130 to the external processor through the output signal count. Optionally, the external processor can be a processor in a chip, etc. Correspondingly, the user can judge whether there is an erroneous write operation during busy=1 based on the output signal count. If count is not 0, it means that an erroneous write operation has occurred; if count is 0, it means that no erroneous write operation has occurred. Because the random write operation may occur more than once, the specific value of count can also record how many erroneous write operations were shielded during the execution of the encoding and decoding task of the current frame by the video codec IP core 120, and provide clues to the user as debugging information.

[0086] The above technical solution, by configuring the counter to increase the hardware counting logic, can timely record the erroneous write operation of the storage bus controller, and provide clues to the user as debugging information, which is helpful for the user to further find the root cause of the erroneous write operation and further improve the reliability and stability of the video codec IP core.

[0087] In an optional embodiment of the present disclosure, Figure 5 As shown, the video codec protection device 110 may also be used to: when it is determined that the bus controller has the erroneous write operation, control the target state flag bit of the target register in the video codec IP core to be enabled.

[0088] The target register may be one of the registers in the video codec IP core 120. The target status flag may be one of the bits selected from the configurable bits of the target register, and is used to identify whether an erroneous write operation occurs in the bus controller.

[0089] In order to further improve the prompt effect of the erroneous write operation and improve the debugging efficiency, when the video codec protection device 110 determines that the bus controller 130 has an erroneous write operation, a signal can be used to represent whether an erroneous write operation has occurred, and this signal can be finally connected to the target state flag of the target register of the video codec IP core 120. The target state flag of the target register can be a certain bit on the existing state register of the video codec IP core 120. When the video codec protection device 110 determines that the bus controller 130 has an erroneous write operation, it can control the target state flag of the target register in the video codec IP core 120 to be enabled. In this way, when the video codec task is completed, the video codec IP core 120 can report the erroneous state of the target state flag of the target register through an interrupt. The target state flag can tell the user that there is an erroneous write operation trying to write the register randomly during this period, and the erroneous write operation is shielded by the protection mechanism, which can be used for reference by the user to further self-check the root cause of the erroneous write operation.

[0090] Optionally, the video codec protection device 110 can be connected to the target state flag of the target register of the video codec IP core 120 through the output signal count of the counter 114. When the value of count is non-0, the target state flag of the target register in the video codec IP core 120 can be controlled to be 1, indicating that the target state flag is enabled. When the target state flag is enabled, it indicates that the target state flag is currently in an error state, that is, the bus controller performs an error write operation.

[0091] In an optional embodiment of the present disclosure, Figure 3As shown, the video codec protection device 110 can also be used to: when it is determined that the bus controller 130 has an erroneous write operation, obtain the data to be written sent by the bus controller 130 through the codec data signal; and store the data to be written in the target memory.

[0092] The codec data signal may be a signal sent by the bus controller 130 to the video codec IP core 120, which is used to send the data content to be written by the error write operation. The data to be written is also the data to be written by the error write operation. The target memory may be a memory used by the video codec IP core 120 to store the data to be written by the error write operation.

[0093] If the chip design allows for more area to be used, the hardware design logic can be further increased to record the specific data on the address bus and data bus of each masked erroneous write operation as the data to be written, and store the data to be written in the target memory. Optionally, the target memory can be ROM (Read-Only Memory) or NAND flash (Non-Volatile Memory Device), or other memory that does not lose data when the power is off. The size of the target memory can be configured according to actual needs to ensure that when an erroneous write operation occurs, the masked data can be dumped (the process of dumping the data in the memory to an external storage device) even if the system needs to be powered off and restarted. Similarly, the data stored in the target memory can also be used as debugging information to provide clues to users, and can also provide warning information for irregular software control processes.

[0094] The above technical solution proposes a protection mechanism for the hardware video codec IP core through the video codec protection device. When the video codec IP core is executing the video codec task, the external write operation to its register is shielded. When the video codec IP core completes the video codec task, the external write operation to its register is allowed. The protection mechanism of the video codec protection device based on the hardware circuit design can be applied when the integrator integrates the video codec IP core into its own chip architecture, and can also be applied to the self-design of the video codec IP core. On the one hand, the protection mechanism of the video codec IP core can effectively prevent the register from being written randomly due to the wrong software control flow when the codec of the video codec IP core is working, thereby causing the internal disorder of the video codec IP core, thereby ensuring that the video codec IP core is maintained in a persistent normal state to a greater extent; on the other hand, if the register is written randomly when the video codec IP core is running, the video codec protection device will record the error state and error data, which can also be used as an observation method to provide inspiration for solving system stability problems.

[0095] In one example, Figure 6 This is a flowchart of a video codec protection method provided by an embodiment of the present disclosure. This embodiment is applicable to the case where the video codec process is protected according to the video codec protection device. The method can be executed by the video codec protection device, which can be connected to the video codec IP core and connected to the bus controller. The video codec protection device can be integrated in an electronic device. The electronic device can be a terminal device or a server device. The embodiment of the present disclosure does not limit the specific device type of the electronic device. Accordingly, Figure 6 As shown, the method includes the following operations:

[0096] S210: Acquire a working status signal of the video codec IP core and a codec control signal of the bus controller.

[0097] S220: Perform protection processing on the encoding and decoding control signal according to the current state of the working state signal.

[0098] S230: Control the video codec IP core to perform a video codec operation according to the protection processing result of the codec control signal.

[0099] Optionally, the protection processing of the codec control signal according to the current state of the working state signal may include: generating a codec protection signal corresponding to the codec control signal according to the type of the codec control signal; controlling the current signal state of the codec protection signal according to the current state of the working state signal; and controlling the video codec IP core to perform the video codec operation according to the protection processing result of the codec control signal may include: controlling the video codec IP core to perform the video codec operation according to the current signal state of the codec protection signal.

[0100] Optionally, controlling the current signal state of the codec protection signal according to the current state of the working state signal may include: when it is determined that the current state of the working state signal is the working state, controlling the current signal state of the codec protection signal to be a signal shielding state; when it is determined that the current state of the working state signal is the idle state, setting the current signal state of the codec protection signal to the current signal state of the codec control signal.

[0101] Optionally, the video codec protection device includes a flip module, a first AND gate module and a second AND gate module, and the codec control signal includes a chip select signal and a write control signal; the input end of the flip module is communicatively connected to the output end of the working status signal of the video codec IP core, the first output end of the flip module is communicatively connected to the first input end of the first AND gate module, and the first output end of the flip module is also communicatively connected to the first input end of the second AND gate module; the second input end of the first AND gate module is communicatively connected to the output end of the chip select signal of the bus controller, and the output end of the first AND gate module is communicatively connected to the first input end of the video codec IP core; the second input end of the second AND gate module is communicatively connected to the output end of the write control signal of the bus controller, and the output end of the second AND gate module is communicatively connected to the second input end of the video codec IP core.

[0102] Optionally, the video codec protection device also includes a counter, a first input end of the counter is communicatively connected to an output end of a working status signal of the video codec IP core, a second input end of the counter is communicatively connected to an output end of a chip select signal of the bus controller, and a third input end of the counter is communicatively connected to an output end of a write control signal of the bus controller; the method also includes: counting the number of erroneous write operations of the bus controller.

[0103] Optionally, counting the number of erroneous write operations of the bus controller may include: determining that the bus controller is currently performing an erroneous write operation when the current state of the working state signal is determined to be the working state and the current signal state of the encoding and decoding control signal is the write operation state; and triggering the counter to count the number of erroneous write operations.

[0104] Optionally, the above method may further include: in a case where it is determined that the bus controller has the erroneous write operation, controlling a target status flag bit of a target register in the video codec IP core to be enabled.

[0105] Optionally, the method may further include: when it is determined that the bus controller has the erroneous write operation, obtaining the data to be written sent by the bus controller via the encoded and decoded data signal; and storing the data to be written in the target memory.

[0106] Figure 7 FIG. 1 is a flow chart of a video codec protection device according to an embodiment of the present disclosure performing a video codec protection method based on protection logic. In a specific example, Figure 7 As shown, the process of the video codec protection device executing the video codec protection method based on the protection logic may include the following operations:

[0107] (1) The bus controller software (hereinafter referred to as the software) prepares the image data and related information to be encoded and decoded, then sets the registers of the video codec IP core and sends a start signal to notify the video codec IP core to start executing the task. The software then waits until the video codec IP core completes the encoding and decoding task of this frame;

[0108] (2) If the current busy signal of the video codec IP core is low, that is, the APB bus write operation is allowed, after the video codec IP core reads the start signal through the APB bus, the internal control logic will pull up the busy signal, and then use the configuration information of multiple registers transmitted by the APB bus to officially start encoding or decoding;

[0109] (3) During the period when the codec of the video codec IP core is executing tasks, that is, during the period when the busy signal is high, if the APB bus sends a signal again, the video codec protection device will shield these write register operations and record the wrong write operations of setting registers as wrong state. If the hardware logic is also designed with counting logic and logic for recording the specific data of the shielded write operations, it will also be performed at this time;

[0110] (4) When the hardware codec of the video codec IP core completes the encoding and decoding task of this frame, the control logic inside the video codec IP core will pull the busy signal low and query the wrong state at the same time. If there is a wrong state, the target state flag bit of the target register in the video codec IP core is enabled, that is, the target state flag bit of the target register is pulled high, indicating that there is an erroneous behavior trying to write to the register during this frame task;

[0111] (5) The encoding and decoding task has been completed, and the hardware reports the completion interrupt to notify the waiting software. The software can further check whether there is a wrong state and other debugging related information;

[0112] (6) The busy signal has been pulled low, and the next video encoding and decoding task can be started.

[0113] Currently, third-party IP core manufacturers do not pay attention to how to better protect the reliability of the video codec IP core itself at the level of complex software and hardware systems. And the integrators who integrate third-party video codec IP cores will not consider more mechanisms to protect the video codec IP cores. At the same time, hardware designers often ignore the complexity of software use. The disclosed embodiment is aimed at this kind of hardware integration based on third-party video codec IP cores, guides hardware protection design from the perspective of software use, and provides a hardware protection mechanism for the video codec IP core, thereby better regulating and limiting the correctness of the software control process of the video codec IP core. The design of the protection mechanism provided by the video codec protection device in the disclosed embodiment is very simple, and the video codec protection device hardly increases the additional chip area, while providing more guarantees for increasing the stability and reliability of the system-level video codec IP core.

[0114] The disclosed embodiment connects a video codec protection device between the bus controller and the video codec IP core, obtains the working status signal of the video codec IP core and the codec control signal of the bus controller through the video codec protection device, and performs protection processing on the codec control signal according to the current state of the working status signal, thereby controlling the video codec IP core to perform video codec operations according to the protection processing result of the codec control signal. This can solve the problems of low stability and reliability of the existing directly integrated video codec IP core when performing video codec processing, and can improve the stability and reliability of the video codec IP core application.

[0115] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0116] It should be noted that any arrangement and combination of the technical features in the above embodiments also falls within the protection scope of the present disclosure.

[0117] In one example, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0118] Figure 8A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0119] like Figure 8 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0120] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0121] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc.

[0122] The electronic device 800 may further include a video codec protection device ( Figure 8 Not shown), the video codec protection device and the video codec IP core ( Figure 8 The video codec protection device is also connected to the bus controller (not shown) of the electronic device 800 Figure 8The video codec protection device is used to perform the following video codec protection method:

[0123] Acquire the working status signal of the video codec IP core and the codec control signal of the bus controller;

[0124] Performing protection processing on the encoding and decoding control signal according to the current state of the working state signal;

[0125] The video codec IP core is controlled to perform video codec operations according to the protection processing result of the codec control signal.

[0126] For example, in some embodiments, the video codec protection method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the video codec protection method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the video codec protection method in any other suitable manner (e.g., by means of firmware).

[0127] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0128] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0129] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0130] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0131] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0132] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services. The server can also be a server of a distributed system, or a server combined with a blockchain.

[0133] The disclosed embodiment connects a video codec protection device between the bus controller and the video codec IP core, obtains the working status signal of the video codec IP core and the codec control signal of the bus controller through the video codec protection device, and performs protection processing on the codec control signal according to the current state of the working status signal, thereby controlling the video codec IP core to perform video codec operations according to the protection processing result of the codec control signal. This can solve the problems of low stability and reliability of the existing directly integrated video codec IP core when performing video codec processing, and can improve the stability and reliability of the video codec IP core application.

[0134] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0135] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A video codec protection device, the video codec protection device is connected to the video codec IP core in communication; the video codec protection device is also connected to the bus controller in communication; wherein, The video codec protection device is used for: Acquire the working status signal of the video codec IP core and the codec control signal of the bus controller; Performing protection processing on the encoding and decoding control signal according to the current state of the working state signal; The video codec IP core is controlled to perform video codec operations according to the protection processing result of the codec control signal.

2. The video codec protection device according to claim 1, wherein: The video codec protection device is also used for: generating a codec protection signal corresponding to the codec control signal according to the type of the codec control signal; Controlling the current signal state of the codec protection signal according to the current state of the working state signal; The video codec IP core is controlled to perform the video codec operation according to the current signal state of the codec protection signal.

3. The video codec protection device according to claim 2, wherein: The video codec protection device is also used for: When it is determined that the current state of the working state signal is the working state, controlling the current signal state of the coding and decoding protection signal to be a signal shielding state; In the case that it is determined that the current state of the working state signal is the idle state, the current signal state of the codec protection signal is set as the current signal state of the codec control signal.

4. The video codec protection device according to any one of claims 1 to 3, wherein the video codec protection device comprises a flip module, a first AND gate module and a second AND gate module, and the codec control signal comprises a chip select signal and a write control signal; wherein: The input end of the flip module is communicatively connected to the output end of the working status signal of the video codec IP core, the first output end of the flip module is communicatively connected to the first input end of the first AND gate module, and the second output end of the flip module is also communicatively connected to the first input end of the second AND gate module; The second input end of the first AND gate module is communicatively connected to the output end of the chip select signal of the bus controller, and the output end of the first AND gate module is communicatively connected to the first input end of the video codec IP core; The second input end of the second AND gate module is communicatively connected to the output end of the write control signal of the bus controller, and the output end of the second AND gate module is communicatively connected to the second input end of the video codec IP core.

5. The video codec protection device according to claim 4, further comprising a counter, wherein a first input terminal of the counter is communicatively connected to an output terminal of a working status signal of the video codec IP core, a second input terminal of the counter is communicatively connected to an output terminal of a chip select signal of the bus controller, and a third input terminal of the counter is communicatively connected to an output terminal of a write control signal of the bus controller; wherein: The counter is used to count the number of erroneous write operations of the bus controller.

6. The video codec protection device according to claim 5, further configured to: When it is determined that the current state of the working state signal is the working state, and when it is determined that the current signal state of the coding and decoding control signal is the writing operation state, it is determined that the bus controller is currently performing an erroneous write operation; The counter is triggered to count the number of operations of the erroneous write operation.

7. The video codec protection device according to claim 5 or 6, wherein the video codec protection device is further used for: When it is determined that the bus controller has the erroneous write operation, the target state flag bit of the target register in the video codec IP core is controlled to be enabled.

8. A video codec protection method, applied to a video codec protection device, wherein the video codec protection device is communicatively connected to a video codec IP core; The video codec protection device is also in communication connection with the bus controller; The video coding protection method comprises: Acquire the working status signal of the video codec IP core and the codec control signal of the bus controller; Performing protection processing on the encoding and decoding control signal according to the current state of the working state signal; The video codec IP core is controlled to perform video codec operations according to the protection processing result of the codec control signal.

9. The video codec protection method according to claim 8, wherein: The performing protection processing on the encoding and decoding control signal according to the current state of the working state signal includes: generating a codec protection signal corresponding to the codec control signal according to the type of the codec control signal; Controlling the current signal state of the codec protection signal according to the current state of the working state signal; The step of controlling the video codec IP core to perform a video codec operation according to the protection processing result of the codec control signal comprises: The video codec IP core is controlled to perform the video codec operation according to the current signal state of the codec protection signal.

10. The video codec protection method according to claim 9, wherein: The controlling the current signal state of the coding and decoding protection signal according to the current state of the working state signal includes: When it is determined that the current state of the working state signal is the working state, controlling the current signal state of the coding and decoding protection signal to be a signal shielding state; In the case that it is determined that the current state of the working state signal is the idle state, the current signal state of the codec protection signal is set as the current signal state of the codec control signal.

11. The video codec protection method according to any one of claims 8 to 10, wherein: The video codec protection device includes a flip module, a first AND gate module and a second AND gate module, and the codec control signal includes a chip selection signal and a write control signal; The input end of the flip module is communicatively connected to the output end of the working status signal of the video codec IP core, the first output end of the flip module is communicatively connected to the first input end of the first AND gate module, and the first output end of the flip module is also communicatively connected to the first input end of the second AND gate module; The second input end of the first AND gate module is communicatively connected to the output end of the chip select signal of the bus controller, and the output end of the first AND gate module is communicatively connected to the first input end of the video codec IP core; The second input end of the second AND gate module is communicatively connected to the output end of the write control signal of the bus controller, and the output end of the second AND gate module is communicatively connected to the second input end of the video codec IP core.

12. The video codec protection method according to claim 11, wherein the video codec protection device further comprises a counter, wherein a first input terminal of the counter is communicatively connected to an output terminal of a working status signal of the video codec IP core, a second input terminal of the counter is communicatively connected to an output terminal of a chip select signal of the bus controller, and a third input terminal of the counter is communicatively connected to an output terminal of a write control signal of the bus controller; the video codec protection method further comprises: The number of erroneous write operations of the bus controller is counted.

13. The video codec protection method according to claim 12, wherein: The counting of the number of erroneous write operations of the bus controller includes: When it is determined that the current state of the working state signal is the working state, and when it is determined that the current signal state of the coding and decoding control signal is the writing operation state, it is determined that the bus controller is currently performing an erroneous write operation; The counter is triggered to count the number of operations of the erroneous write operation.

14. The video codec protection method according to claim 12, further comprising: When it is determined that the bus controller has the erroneous write operation, the target state flag bit of the target register in the video codec IP core is controlled to be enabled.

15. An electronic device, comprising the video codec protection device according to any one of claims 1 to 7; the electronic device further comprising: at least one processor; as well as A memory is communicatively coupled to the at least one processor.

16. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the video codec protection method according to any one of claims 8 to 14.

17. A computer program product comprising a computer program / instructions, wherein: When the computer program / instruction is executed by a processor, the video codec protection method described in any one of claims 8-14 is implemented.

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