Semiconductor memory device including vertical cell transistor

Abstract

A semiconductor memory device includes a peripheral circuit structure and a cell array structure provided on the peripheral circuit structure and including a plurality of cell array regions and an upper peripheral region provided between the plurality of cell array regions. The cell array structure includes a vertical cell transistor, a first vertical peripheral transistor, and a second vertical peripheral transistor. Each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor has a channel extending in a third direction parallel to an arrangement direction of the peripheral circuit structure and the cell array structure. The vertical cell transistor is disposed in the cell array region and has a first polarity. A first vertical peripheral transistor is disposed in the upper peripheral region and has a first polarity. The second vertical peripheral transistor is disposed in the upper peripheral region and has a second polarity different from the first polarity.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical cell transistor. Background Art

[0002] Research is ongoing to reduce the size of components that make up semiconductor devices and to improve their performance. For example, in the field of dynamic random access memory (DRAM), research is ongoing to reliably and stably form components of reduced size. However, as the size of components decreases, it becomes increasingly difficult to achieve transistors with the desired performance. Summary of the invention

[0003] A semiconductor memory device includes a peripheral circuit structure and a cell array structure, wherein the cell array structure is arranged on the peripheral circuit structure and includes a plurality of cell array regions and an upper peripheral region arranged between the plurality of cell array regions. The cell array structure includes a vertical cell transistor, a first vertical peripheral transistor, and a second vertical peripheral transistor. Each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor has a channel extending in a third direction parallel to the arrangement direction of the peripheral circuit structure and the cell array structure. The vertical cell transistor is arranged in the cell array region and has a first polarity. The first vertical peripheral transistor is arranged in the upper peripheral region and has a first polarity. The second vertical peripheral transistor is arranged in the upper peripheral region and has a second polarity different from the first polarity.

[0004] A semiconductor memory device includes a peripheral circuit structure and a cell array structure arranged on the peripheral circuit structure. The peripheral circuit structure includes a horizontal peripheral transistor, which has a channel extending along a first direction intersecting the arrangement direction of the peripheral circuit structure and the cell array structure. The cell array structure includes a capacitor, a vertical cell transistor, a first vertical peripheral transistor, and a second vertical peripheral transistor. The capacitor is electrically connected to the vertical cell transistor. Each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor has a channel extending along a third direction parallel to the arrangement direction of the peripheral circuit structure and the cell array structure. The first vertical peripheral transistor and the second vertical peripheral transistor have a first polarity and a second polarity different from the first polarity, respectively.

[0005] A semiconductor memory device includes a substrate, the substrate includes a plurality of cell array areas and an upper peripheral area arranged between the plurality of cell array areas. A first conductive line extends along a first direction on the substrate and is arranged along a second direction intersecting the first direction. A vertical cell transistor, a first vertical peripheral transistor, and a second vertical peripheral transistor are provided on the first conductive line. A capacitor is provided on each vertical cell transistor. Each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor has a channel extending along a third direction perpendicular to the top surface of the substrate. The vertical cell transistor is an NMOS transistor arranged in the cell array area. The first vertical peripheral transistor is an NMOS transistor arranged in the upper peripheral area. The second vertical peripheral transistor is a PMOS transistor arranged in the upper peripheral area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects, features and elements of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a block diagram illustrating a semiconductor memory device according to an example embodiment;

[0008] Figure 2 is a schematic perspective view showing a semiconductor memory device according to an example embodiment;

[0009] Figure 3 It is shown Figure 2 A plan view of a cell array structure and a peripheral circuit structure;

[0010] Figure 4A and Figure 4B They are shown respectively Figure 3 A plan view of regions AA and BB of a cell array structure;

[0011] Figure 5A is a plan view of a cell array structure according to an example embodiment;

[0012] Figure 5B It is along Figure 5A A cross-sectional view taken along the lines AA' and BB';

[0013] Figure 5C It is along Figure 5A A cross-sectional view taken along lines C-C' and D-D';

[0014] Fig. 6A Shown include FIG. 5A to FIG. 5C an inverter circuit of a first vertical peripheral transistor and a second vertical peripheral transistor;

[0015] Figure 6B Shown include FIG. 5A to FIG. 5Ca latch circuit of a first vertical peripheral transistor and a second vertical peripheral transistor;

[0016] Figure 7 is a flow chart showing a method of manufacturing a cell array structure according to an embodiment;

[0017] Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A and Fig.13A It is shown Figure 7 A plan view of the manufacturing method shown;

[0018] Figure 8B , Figure 8C , Fig. 9B , Fig. 9C , Fig. 10B , Fig. 10C , Fig. 11B , Fig. 11C , Fig. 12B , Fig. 12C , Fig. 13B and Fig. 13C is with Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A and Fig.13A The cross-sectional views corresponding to the lines A-A', B-B', C-C' and D-D' in FIG. Figure 7 The manufacturing method shown; and

[0019] Fig.14 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, examples for implementing the present invention will be described clearly and specifically so that a person having ordinary skill in the technical field of the present invention can easily practice the present invention.

[0021] Figure 1 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0022] Reference Figure 1 , the semiconductor memory device SMD may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5. The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally (e.g., side by side with each other) or three-dimensionally (e.g., stacked with each other). Each memory cell MC may be connected between a word line WL and a bit line BL that cross each other.

[0023] Each memory cell MC includes a selection element TR and a data storage element DS, and the selection element TR and the data storage element DS can be electrically connected in series. The selection element TR can be controlled by a signal transmitted through a word line WL. For example, the selection element TR can be a field effect transistor (FET). The data storage element DS can be connected to a bit line BL through the selection element TR. For example, the data storage element DS can include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. The gate electrode of the selection element TR can be connected to the word line WL, and the drain / source terminal can be connected to the bit line BL and the data storage element DS, respectively.

[0024] The row decoder 2 may decode an externally input address and select one of the word lines WL of the memory cell array 1. The address decoded in the row decoder 2 may be provided to a row driver. The row driver may provide predetermined voltages to the selected word line WL and the unselected word line WL, respectively, in response to control of the control circuit.

[0025] The sense amplifier 3 may detect and amplify a voltage difference between a reference bit line and a bit line BL selected according to an address decoded from the column decoder 4 , and output the amplified voltage difference.

[0026] The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 may decode an externally input address and select one of the bit lines BL.

[0027] The control logic 5 may generate a control signal that controls a write operation of data to the memory cell array 1 or a read operation of data from the memory cell array 1 .

[0028] Figure 2 is a schematic perspective view of a semiconductor memory device according to example embodiments. Figure 3 It is shown Figure 2 A plan view of the cell array structure and peripheral circuit structure. Figure 4A and Figure 4B They are shown respectively Figure 3 A plan view of regions AA and BB of a cell array structure.

[0029] Reference Figures 2 to 4B , the semiconductor memory device SMD may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS. The peripheral circuit structure PS and the cell array structure CS may be arranged along a third direction DR3. For example, the peripheral circuit structure PS and the cell array structure CS may be bonded to each other by "copper to copper bonding", which is a technique for creating a stronger electrical connection between two pieces of copper (Cu).

[0030] The cell array structure CS may include a cell array region CAR and an upper peripheral region UPR. The cell array region CAR may be arranged along a first direction DR1 and a second direction DR2. Although the cell array region CAR is shown as being arranged in a 2×2 shape, this is illustrative. The arrangement form of the cell array region CAR may be determined as needed. The upper peripheral region UPR may be provided between the cell array regions CAR. For example, the upper peripheral region UPR may include a first upper peripheral region UPR1 (UPR) provided between the cell array regions CAR arranged along the first direction DR1. For example, the upper peripheral region UPR may include a second upper peripheral region UPR2 (UPR) provided between the cell array regions CAR arranged along the second direction DR2. The first upper peripheral region UPR1 (UPR) may extend along the second direction DR2. The first upper peripheral region UPR1 (UPR) may be spaced apart from each other by the second upper peripheral region UPR2. The second upper peripheral region UPR2 may extend along the first direction DR1.

[0031] The cell array region CAR may include Figure 1 The bit line BL in Figure 1 The word line WL in Figure 1 The memory cells MC and the back gate lines BGL in the memory cell MC. The bit lines BL may extend along the first direction DR1. The bit lines BL may be arranged along the second direction DR2 crossing the first direction DR1. The word lines WL may extend along the second direction DR2. The word lines WL may be arranged along the first direction DR1. The memory cells MC may be arranged two-dimensionally or three-dimensionally on a plane extending along the first direction DR1 and the second direction DR2. For example, the memory cells MC may be arranged along the first direction DR1 and the second direction DR2. Each memory cell MC may include Figure 1 The selection elements TR and Figure 1 In one embodiment, the selection element TR may be a vertical channel transistor (or a vertical cell transistor VCT). A vertical channel transistor may refer to a structure in which a channel length extends in a vertical direction (ie, a third direction DR3). In one embodiment, the data storage element DS may include a capacitor.

[0032] The back gate line BGL may extend along the second direction DR2. Each back gate line BGL may be provided between selection elements TR adjacent to each other along the first direction DR1. The back gate line BGL may be spaced apart from the word line WL along the first direction DR1, and the selection element TR is interposed between the back gate line BGL and the word line WL. In one embodiment, the back gate line BGL may be located at substantially the same height as the word line WL. The back gate line BGL may increase the threshold voltage of the selection element TR. Therefore, even if the selection element TR has a small size, a reduction in the threshold voltage and degradation of the leakage current characteristic may be prevented.

[0033] The upper peripheral region UPR may include at least some of the peripheral circuits. The peripheral circuits provided in the upper peripheral region UPR may include Figure 1 The control logic 5 in the upper peripheral region UPR. For example, the peripheral circuit provided in the upper peripheral region UPR may include a fuse box circuit, a mode resistor setting (MRS) circuit, a DC circuit, and other option-related circuits. The peripheral circuit provided in the upper peripheral region UPR may be implemented using, for example, an inverter circuit or a latch circuit. The upper peripheral region UPR may include a first vertical peripheral transistor VPT1, a second vertical peripheral transistor VPT2, a peripheral gate line GL, and a back gate line BGL. The first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2 may be vertical channel transistors. The first vertical peripheral transistor VPT1 may have a first polarity. The second vertical peripheral transistor VPT2 may have a second polarity different from the first polarity. When the first vertical peripheral transistor VPT1 is an NMOS transistor, the second vertical peripheral transistor VPT2 may be a PMOS transistor. When the first vertical peripheral transistor VPT1 is a PMOS transistor, the second vertical peripheral transistor VPT2 may be an NMOS transistor. The first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2 may be used to implement the first peripheral circuit provided in the upper peripheral region UPR. For example, the first and second vertical peripheral transistors VPT1 and VPT2 may be used to implement an inverter circuit, a latch circuit, etc. in the upper peripheral region UPR. The first and second vertical peripheral transistors VPT1 and VPT2 may be provided in the first and / or second upper peripheral regions UPR1 and UPR2.

[0034] The peripheral gate line GL may extend along the second direction DR2. The peripheral gate line GL may be arranged along the first direction DR1. The peripheral gate line GL may transmit a gate signal controlling the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2. In example embodiments, the peripheral gate line GL may be a gate electrode of the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2.

[0035] The back gate line BGL may extend along the second direction DR2. Each back gate line BGL may be provided between first vertical peripheral transistors VPT1 that are adjacent to each other along the first direction DR1 or between second vertical peripheral transistors VPT2 that are adjacent to each other along the first direction DR1. The back gate line BGL may be spaced apart from the peripheral gate line GL in the first direction DR1, and the first vertical peripheral transistor VPT1 or the second vertical peripheral transistor VPT2 is interposed between the back gate line BGL and the peripheral gate line GL. In one embodiment, the back gate line BGL may be located at substantially the same height as the peripheral gate line GL. The back gate line BGL may increase the threshold voltage of the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2. Therefore, even if the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2 have a micro size, the reduction of the threshold voltage may be prevented, thereby preventing the leakage current characteristic from being degraded.

[0036] The peripheral circuit structure PS may include a cell drive region CDR and a lower peripheral region LPR. The cell drive region CDR may be arranged along a first direction DR1 and a second direction DR2. As an embodiment, the cell drive region CDR is shown to be arranged in a 2×2 shape. The arrangement form of the cell drive region CDR may be determined as needed. The cell drive region CDR may at least partially overlap with the cell array region CAR along a third direction DR3. The cell drive region CDR may include another portion of the peripheral circuit. The peripheral circuit provided in the cell drive region CDR may be configured to control the cell array region CAR provided in the cell array region CAR. Figure 1 For example, the cell driving region CDR may include Figure 1 The row decoder in 2, Figure 1 The sense amplifier 3 and Figure 1 Column decoder 4 in.

[0037] The lower peripheral region LPR may include another portion of the peripheral circuit. In one embodiment, the lower peripheral region LPR and the cell driving region CDR may include a planar transistor. In an example embodiment, the horizontal conductive line and the vertical conductive line may be disposed between the peripheral circuit and the cell array structure CS. Figure 1 In an example embodiment, the horizontal conductive line and the vertical conductive line may be provided between the memory cells MC provided in the cell array structure CS. Figure 1 The horizontal conductive lines and the vertical conductive lines may provide the required electrical connections between the MC in the peripheral circuit structure PS and the peripheral circuits provided in the peripheral circuit structure PS.

[0038] Figure 5A is a plan view of a cell array structure according to an example embodiment. Figure 5B It is along Figure 5A A cross-sectional view taken along lines AA' and BB'. Figure 5C It is along Figure 5A Cross-sectional view taken along lines CC' and D-D'. Fig. 6A Shown include FIG. 5A to FIG. 5C An inverter circuit of a first vertical peripheral transistor and a second vertical peripheral transistor. Figure 6B Shown include FIG. 5A to FIG. 5C A latch circuit of a first vertical peripheral transistor and a second vertical peripheral transistor.

[0039] Reference FIG. 5A to FIG. 5C , a substrate 100 may be provided. The substrate 100 may be disposed in the cell array region CAR and the upper peripheral region UPR. The substrate 100 may include a first surface 100a and a second surface 100b facing opposite directions. The first surface 100a and the second surface 100b may extend along a first direction DR1 and a second direction DR2. The first surface 100a and the second surface 100b may be spaced apart from each other along a third direction DR3. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to each other. The substrate 100 may include a semiconductor material. For example, the substrate 100 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 100 may have a first conductivity type. For example, the first conductivity type may be p-type or n-type. When the conductivity type of the substrate 100 is p-type, the substrate 100 may be a silicon (Si) substrate containing a group III element or a group II element as an impurity. For example, the group III element may include boron (B), aluminum (Al), gallium (Ga), or indium (In). When the conductivity type of substrate 102 is n-type, it can be a silicon (Si) substrate containing a V group element, a VI group element, or a VII group element as an impurity. For example, the V group element may include phosphorus (P), arsenic (As), or antimony (Sb). When the first conductivity type is p-type or n-type, the second conductivity type may be n-type or p-type, respectively. Substrate 100 may be an epitaxial (epi) layer formed by an epitaxial growth process.

[0040] The first conductive line 102 may be provided on the substrate 100. The first conductive line 102 may extend along the first direction DR1. The first conductive line 102 may be arranged along the second direction DR2. For example, the first conductive lines 102 may be parallel to each other. The first conductive line 102 in the cell array region CAR may be a bit line. The first conductive line 102 in the upper peripheral region UPR may be a signal transmission line for a peripheral circuit. The first conductive line 102 may be electrically connected to the lower portion of the vertical cell transistor VCT, the first vertical peripheral transistor VPT1, and the second vertical peripheral transistor VPT2. In example embodiments, the first conductive line 102 electrically connected to the first vertical peripheral transistor VPT1 and the first conductive line 102 electrically connected to the second vertical peripheral transistor VPT2 may be electrically separated from each other (e.g., insulated). For example, the first conductive line 102 electrically connected to the first vertical peripheral transistor VPT1 and the first conductive line 102 electrically connected to the second vertical peripheral transistor VPT2 may be spaced apart from each other along the first direction DR1. In example embodiments, the first conductive line 102 electrically connected to the first vertical peripheral transistor VPT1 may be electrically separated from each other. For example, the first conductive lines 102 electrically connected to the first vertical peripheral transistors VPT1 that are adjacent to each other may be spaced apart from each other along the first direction DR1. In example embodiments, the first conductive lines 102 electrically connected to the second vertical peripheral transistors VPT2 may be electrically separated from each other. For example, the first conductive lines 102 electrically connected to the second vertical peripheral transistors VPT2 that are adjacent to each other may be spaced apart from each other along the first direction DR1. The first conductive lines 102 may include a conductive material. For example, the first conductive lines 102 may include doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, RuTiN), a conductive metal silicon nitride (e.g., TiSiN, TaSiN), a conductive metal silicide, and / or a conductive metal oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3 ), LSCo). The first conductive line 102 may have a single layer or a multi-layer structure. In one embodiment, the first conductive line 102 may include a two-dimensional semiconductor material. For example, the first conductive line 102 may include graphene, carbon nanotubes, or a combination thereof.

[0041] A lower insulating layer 104 may be provided on the substrate 100. The lower insulating layer 104 may be provided between the first conductive lines 102, respectively. The lower insulating layer 104 and the first conductive lines 102 may be arranged alternately along the second direction DR2. For example, the lower insulating layer 104 may at least partially fill the area between the first conductive lines 102. Although the lower insulating layer 104 is shown as being provided only on the side of the first conductive line 102, this is illustrative. In an example, the lower insulating layer 104 may extend between the substrate 100 and the first conductive line 102 and be connected to each other. The lower insulating layer 104 extends along the first direction DR1 and may be arranged along the second direction DR2. The lower insulating layer 104 may include an insulating material. For example, the lower insulating layer 104 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0042] The first semiconductor pattern SP1 may be provided in the cell array region CAR and the upper peripheral region UPR. The first semiconductor pattern SP1 may be provided on the first conductive line 102. The first semiconductor pattern SP1 may be arranged along the first direction DR1 and the second direction DR2. The first semiconductor pattern SP1 may be electrically connected to the first conductive line 102. For example, the first semiconductor pattern SP1 arranged along the first direction DR1 may be electrically connected to one first conductive line 102. The first semiconductor pattern SP1 disposed in the cell array region CAR and the first semiconductor pattern SP1 disposed in the upper peripheral region UPR may be electrically connected to different first conductive lines 102. The first semiconductor pattern SP1 may extend along the third direction DR3. The first semiconductor pattern SP1 may have a first conductivity type. The first semiconductor pattern SP1 of the cell array region CAR may be included in each vertical cell transistor VCT. The first semiconductor patterns SP1 of the upper peripheral region UPR may each be included in a first vertical peripheral transistor VPT1.

[0043] The second semiconductor pattern SP2 may be provided in the upper peripheral region UPR. The second semiconductor pattern SP2 may be provided on the first conductive line 102. The second semiconductor pattern SP2 may be arranged along the first direction DR1 and the second direction DR2. The second semiconductor pattern SP2 may be electrically connected to the first conductive line 102. For example, the second semiconductor pattern SP2 arranged along the first direction DR1 may be electrically connected to one first conductive line 102. In the upper peripheral region UPR, the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may be electrically connected to different first conductive lines 102. In an embodiment, in the upper peripheral region UPR, the first semiconductor patterns SP1 adjacent to each other along the first direction DR1 may be electrically connected to different first conductive lines 102. The second semiconductor pattern SP2 may extend along the third direction DR3. The second semiconductor pattern SP2 may have a second conductivity type. For example, the conductivity type of the first semiconductor pattern SP1 may be p-type, and the conductivity type of the second semiconductor pattern SP2 may be n-type. The second semiconductor patterns SP2 may each be included in the second vertical peripheral transistor VPT2.

[0044] The second conductive line 106 may be provided on the first conductive line 102. The second conductive line 106 may be spaced apart from the first conductive line 102 along the third direction DR3. The second conductive line 106 may extend along the second direction DR2. The second conductive line 106 may be arranged along the first direction DR1. For example, the second conductive lines 106 may be parallel to each other. The second conductive line 106 may face the first semiconductor pattern SP1 and the second semiconductor pattern SP2 along the first direction DR1. The second conductive line 106 may at least partially overlap the first semiconductor pattern SP1 and the second semiconductor pattern SP2 along the first direction DR1.

[0045] The second conductive lines 106 may be alternately disposed on one side and the other side of the first semiconductor pattern SP1 along the first direction DR1. The one side and the other side of the first semiconductor pattern SP1 may be both side surfaces of the first semiconductor patterns SP1 sequentially arranged along the first direction DR1. For example, one second conductive line 106 may be disposed on one side of one first semiconductor pattern SP1. For example, another second conductive line 106 may be provided on the other side of another first semiconductor pattern SP1 that is adjacent to the one first semiconductor pattern SP1 along the first direction DR1.

[0046] The second conductive lines 106 may be alternately disposed on one side and the other side of the second semiconductor pattern SP2 arranged along the first direction DR1. The one side and the other side of the second semiconductor pattern SP2 may be both sides of the second semiconductor patterns SP2 sequentially arranged along the first direction DR1. For example, one second conductive line 106 may be disposed on one side of one second semiconductor pattern SP2. For example, another second conductive line 106 may be provided on the other side of another second semiconductor pattern SP2 that is adjacent to the one second semiconductor pattern SP2 along the first direction DR1.

[0047] The second conductive line 106 in the cell array region CAR may be a word line. In example embodiments, the second conductive line 106 may be a gate electrode of a vertical cell transistor VCT, which turns on and / or off the vertical cell transistor VCT. The second conductive line 106 in the upper peripheral region UPR may be a gate electrode of a first vertical peripheral transistor VPT1 and a second vertical peripheral transistor VPT2. The second conductive line 106 may be configured to turn on and / or off the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2.

[0048] The second conductive line 106 may include a conductive material. For example, the second conductive line 106 may include doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, RuTiN), a conductive metal silicon nitride (e.g., TiSiN, TaSiN), a conductive metal silicide, and / or a conductive metal oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3 ), LSCo). The second conductive line 106 may have a single layer or a multi-layer structure. In one embodiment, the second conductive line 106 may include a two-dimensional semiconductor material. For example, the second conductive line 106 may include graphene, carbon nanotubes, or a combination thereof.

[0049] The first gate insulating layer 108 may be provided between the second conductive line 106 and the first semiconductor pattern SP1 and between the second conductive line 106 and the second semiconductor pattern SP2. The first gate insulating layer 108 may electrically separate the first semiconductor pattern SP1 and the second conductive line 106 that are adjacent to each other. The first gate insulating layer 108 may electrically separate the second semiconductor pattern SP2 and the second conductive line 106 that are adjacent to each other. The first gate insulating layer 108 may extend along the side surface of the first semiconductor pattern SP1 that faces the second conductive line 106. The first gate insulating layer 108 may extend along the side surface of the second semiconductor pattern SP2 that faces the second conductive line 106. The first gate insulating layer 108 may extend along the third direction DR3. The lower portion of the first gate insulating layer 108 may contact the first conductive line 102 and the lower insulating layer 104. The top of the first gate insulating layer 108 may contact the first pad 130 or the second pad 131. The first gate insulating layer 108 may be a gate insulating layer for the second conductive line 106 in the vertical cell transistor VCT, the first vertical peripheral transistor VPT1, and the second vertical peripheral transistor VPT2. The first gate insulating layer 108 may include a low-k dielectric material (e.g., a material having a dielectric constant smaller than that of silicon oxide), silicon oxide, and a high-k dielectric material (e.g., a material having a dielectric constant larger than that of silicon oxide). The high-k dielectric material may be a metal oxide or a metal oxynitride. For example, the first gate insulating layer 108 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 or a combination thereof.

[0050] The first insulating pattern 110 may be provided on the bottom surface of the second conductive line 106. The first insulating pattern 110 may extend along the bottom surface of the second conductive line 106. The first insulating pattern 110 may extend in the second direction DR2. The first insulating pattern 110 may be arranged along the first direction DR1. The first insulating pattern 110 may be provided on the side surface of the first gate insulating layer 108. The first insulating pattern 110 may contact the immediately adjacent first gate insulating layer 108. The first insulating pattern 110 may be provided on the first conductive line 102 and the lower insulating layer 104. The first insulating pattern 110 may be configured to electrically separate the first conductive line 102 and the second conductive line 106. The first insulating pattern 110 may include an insulating material. For example, the first insulating pattern 110 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0051] The second insulating pattern 112 may be provided between the first gate insulating layers 108. The second insulating pattern 112 may at least partially cover the second conductive line 106 and the first insulating pattern 110. The second insulating pattern 112 may at least partially fill the region between a pair of first gate insulating layers 108 adjacent to each other. The second insulating pattern 112 may extend along the second direction DR2. The second insulating pattern 112 may be arranged along the first direction DR1. The second insulating pattern 112 may extend along the third direction DR3. The second insulating pattern 112 may be configured to electrically separate a pair of second conductive lines 106 adjacent to each other. A pair of second conductive lines 106 adjacent to each other may be spaced apart from each other by the second insulating pattern 112. The second insulating pattern 112 may include an insulating material. For example, the second insulating pattern 112 may include silicon oxide, silicon nitride and / or silicon oxynitride.

[0052] The third conductive line 114 may be provided on the first conductive line 102. The third conductive line 114 may be provided on the opposite side of the second conductive line 106, and the first semiconductor pattern SP1 or the second semiconductor pattern SP2 is interposed between the third conductive line 114 and the second conductive line 106. The third conductive line 114 may be disposed between a pair of first semiconductor patterns SP1 adjacent to each other and between a pair of second semiconductor patterns SP2 adjacent to each other. The third conductive line 114 may extend along the second direction DR2. The third conductive line 114 may be arranged along the first direction DR1. For example, the third conductive lines 114 may be parallel to each other. The third conductive line 114 may at least partially overlap the first semiconductor pattern SP1 and the second semiconductor pattern SP2 along the first direction DR1. The third conductive line 114 may include a conductive material. For example, the third conductive line 114 may include doped polysilicon, metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, RuTiN), conductive metal silicon nitride (e.g., TiSiN, TaSiN), conductive metal silicide and / or conductive metal oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3), LSCo). The third conductive line 114 may have a single layer or a multilayer structure. In one embodiment, the third conductive line 114 may include a two-dimensional semiconductor material. For example, the third conductive line 114 may include graphene, carbon nanotubes, or a combination thereof. The third conductive line 114 may be a back gate electrode of the vertical cell transistor VCT, the first vertical peripheral transistor VPT1, and the second vertical peripheral transistor VPT2. The third conductive line 114 may increase the threshold voltage of the vertical cell transistor VCT, the first vertical peripheral transistor VPT1, and the second vertical peripheral transistor VPT2. Therefore, even if the vertical cell transistor VCT, the first vertical peripheral transistor VPT1, and the second vertical peripheral transistor VPT2 have a small size, the reduction of the threshold voltage and the degradation of the leakage current characteristic may be prevented.

[0053] The third insulating pattern 116 may be provided on the bottom surface of the third conductive line 114. The third insulating pattern 116 may extend along the bottom surface of the third conductive line 114. The third insulating pattern 116 may extend in the second direction DR2. The third insulating pattern 116 may be arranged along the first direction DR1. The third insulating pattern 116 may be provided on the first conductive line 102 and the lower insulating layer 104. The third insulating pattern 116 may be configured to electrically separate the first conductive line 102 and the third conductive line 114. The third insulating pattern 116 may include an insulating material. For example, the third insulating pattern 116 may include silicon oxide, silicon nitride and / or silicon oxynitride.

[0054] The fourth insulating pattern 118 may be provided on the third conductive line 114. The fourth insulating pattern 118 may be provided on the opposite side of the third insulating pattern 116, and the third conductive line 114 is interposed between the fourth insulating pattern 118 and the third insulating pattern 116. The fourth insulating pattern 118 may extend along the upper surface of the third conductive line 114. The fourth insulating pattern 118 may extend in the second direction DR2. The fourth insulating pattern 118 may be arranged along the first direction DR1. The fourth insulating pattern 118 may include an insulating material. For example, the fourth insulating pattern 118 may include silicon oxide, silicon nitride and / or silicon oxynitride.

[0055] The second gate insulating layer 120 may be provided between the third conductive line 114 and the first semiconductor pattern SP1 and between the third conductive line 114 and the second semiconductor pattern SP2. The second gate insulating layer 120 may extend along the second direction DR2. The second gate insulating layer 120 may electrically separate the first semiconductor pattern SP1 and the third conductive line 114 that are adjacent to each other. The second gate insulating layer 120 may electrically separate the second semiconductor pattern SP2 and the third conductive line 114 that are adjacent to each other. The second gate insulating layer 120 may be provided on the side surface of the first semiconductor pattern SP1 and the side surface of the second semiconductor pattern SP2. The second gate insulating layer 120 may extend along the third direction DR3. The lower portion of the second gate insulating layer 120 may contact the first conductive line 102 and the lower insulating layer 104. The top of the second gate insulating layer 120 may contact the upper insulating layer 132. The second gate insulating layer 120 may be a gate insulating layer for the third conductive line 114 in the vertical cell transistor (VCT), the first vertical peripheral transistor VPT1, and the second vertical peripheral transistor VPT2. The second gate insulating layer 120 may include a low-k dielectric material, silicon oxide, and / or a high-k dielectric material. The high-k dielectric material may be a metal oxide or a metal oxynitride. For example, the second gate insulating layer 120 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 and / or combinations thereof.

[0056] In the cell array region CAR, the first semiconductor pattern SP1, the second conductive line 106, the first gate insulating layer 108, the third conductive line 114 and the second gate insulating layer 120 may define a vertical cell transistor VCT. The vertical cell transistor VCT may have a first polarity. For example, the vertical cell transistor VCT may be an NMOS transistor.

[0057] In the upper peripheral region UPR, the first semiconductor pattern SP1, the second conductive line 106, the first gate insulating layer 108, the third conductive line 114 and the second gate insulating layer 120 may define a first vertical peripheral transistor VPT1. The first vertical peripheral transistor VPT1 may have a first polarity. For example, the first vertical peripheral transistor VPT1 may be an NMOS transistor.

[0058] In the upper peripheral region UPR, the second semiconductor pattern SP2, the second conductive line 106, the first gate insulating layer 108, the third conductive line 114 and the second gate insulating layer 120 may define a second vertical peripheral transistor VPT2. The second vertical peripheral transistor VPT2 may have a second polarity. For example, the second vertical peripheral transistor VPT2 may be a PMOS transistor.

[0059] At least some of the first peripheral circuits of the semiconductor memory device 10 may be implemented by the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2. Therefore, at least some of the first peripheral circuits of the semiconductor memory device 10 may be provided in the cell array structure CS. For example, the first vertical peripheral transistor VPT1 and the second vertical peripheral transistor VPT2 may form an inverter circuit and / or a latch circuit. The latch circuit may be used to implement, for example, a fuse box circuit or an MRS circuit.

[0060] The first pads 130 may be provided on the first semiconductor patterns SP1 of the cell array region CAR, respectively. For example, the first pads 130 may vertically overlap the first semiconductor patterns SP1, respectively, at least in part. The first pads 130 may be electrically connected to the first semiconductor patterns SP1, respectively. For example, the first pads 130 may directly contact the first semiconductor patterns SP1. The first pads 130 may be electrically separated from each other.

[0061] The second pad 131 may be provided on the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the upper peripheral region UPR. The second pad 131 may be connected to each other as needed. For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 that are adjacent to each other may be electrically connected to each other through one second pad 131. For example, the first vertical peripheral transistors VPT1 that are adjacent to each other may be electrically connected to each other through one second pad 131. The second pad 131 may extend in the first direction DR1 or the second direction DR2. One second pad 131 that electrically connects the first semiconductor pattern SP1 and the second semiconductor pattern SP2 that are adjacent to each other may be configured to at least partially overlap with the first semiconductor pattern SP1 and the second semiconductor pattern SP2 that are adjacent to each other along the third direction DR3. The electrical connection relationship between the second pad 131 and the first and second semiconductor patterns SP1 and SP2 may be selected to implement a desired circuit. As Fig. 6A As shown, a first vertical peripheral transistor VPT1 having a first polarity and a second vertical peripheral transistor VPT2 having a second polarity (e.g., a PMOS transistor) are electrically connected to form an inverter circuit. A circuit can be constructed. For example, the first vertical peripheral transistor VPT1 having a first polarity can be an NMOS transistor. For example, the second vertical peripheral transistor VPT2 having a second polarity can be a PMOS transistor. Figure 6BAs shown, a pair of first vertical peripheral transistors VPT1 having a first polarity and a pair of second vertical peripheral transistors VPT2 having a second polarity (e.g., PMOS transistors) can be electrically connected to form a latch circuit. For example, a pair of first vertical peripheral transistors VPT1 having a first polarity can be a pair of NMOS transistors. For example, a pair of second vertical peripheral transistors VPT2 having a second polarity can be a pair of PMOS transistors. The second pad 131 may include a conductive material. For example, the second pad 131 may include doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal and / or a metal alloy.

[0062] An upper insulating layer 132 may be provided between the first pad 130 and the second pad 131. The upper insulating layer 132 may at least partially fill the region between the first pad 130 and the region between the second pad 131. The upper insulating layer 132 may electrically separate the first pad 130 and the second pad 131 from each other. In an embodiment, the top surface of the upper insulating layer 132 is shown to be located at substantially the same height as the top surfaces of the first pad 130 and the second pad 131. In an example, the top surface of the upper insulating layer 132 may be located at a different height than the top surfaces of the first pad 130 and the second pad 131. The upper insulating layer 132 may include an insulating material. For example, the upper insulating layer 132 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0063] The lower electrode 142 may be provided in the cell array region CAR. The lower electrode 142 may be provided on the first pad 130, respectively. The lower electrode 142 may be arranged along the first direction DR1 and the second direction DR2. The lower electrode 142 may overlap the first pad 130 completely or partially in the third direction DR3. The lower electrode 142 may contact the first pad 130. The lower electrode 142 may contact all or part of the upper surface of the first pad 130. When viewed in a plane extending along the first direction DR1 and the second direction DR2, the lower electrode 142 may have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape. The lower electrode 142 may include a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, and / or a metal.

[0064] A capacitor dielectric layer 144 may be provided on the lower electrode 142. The capacitor dielectric layer 144 may extend along the surface of the lower electrode 142. The capacitor dielectric layer 144 may further extend from the surface of the lower electrode 142 and the upper surface of the first pad 130 to the upper surface of the upper insulating layer 132. The capacitor dielectric layer 144 may include a ferroelectric material, an antiferroelectric material, and / or a paraelectric material. For example, the capacitor dielectric layer 144 may be a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, and / or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0065] The upper electrode 146 may be provided on the capacitor dielectric layer 144. The upper electrode 146 may be electrically separated from the lower electrode 142, with the capacitor dielectric layer 144 interposed between the upper electrode 146 and the lower electrode 142. The upper electrode 146 may include a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, and / or a metal.

[0066] The lower electrode 142, the capacitor dielectric layer 144, and the upper electrode 146 may form a capacitor. Charge may be stored in the capacitor by a voltage difference applied to the lower electrode 142 and the upper electrode 146. The voltage applied to the lower electrode 142 may be controlled by a vertical cell transistor VCT. The voltage applied to the upper electrode 146 may be provided from a peripheral circuit disposed in a peripheral circuit structure. For example, the upper electrode 146 may be connected to a peripheral circuit disposed in a peripheral circuit structure via a vertical conductive line VCL and a horizontal conductive line HCL.

[0067] The upper peripheral region UPR may not include a capacitor. A capping layer 150 may be provided in the upper peripheral region UPR. The capping layer 150 may be provided on the upper insulating layer 132 and the second pad 131. A vertical conductive line VCL and a horizontal conductive line HCL providing electrical connection between the second pad 131 and other components may be provided in the capping layer 150. The capping layer 150 may include an insulating material. For example, the capping layer 150 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0068] In an embodiment, the semiconductor memory device 10 may include a variable resistance pattern instead of a capacitor, and the variable resistance pattern may be switched between two resistance states by an electric pulse. The variable resistance pattern may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes depending on the amount of current.

[0069] When the cell transistor is a planar transistor, the upper peripheral region UPR of the cell array structure CS may be a region where the peripheral circuit is placed. When a vertical channel transistor is used as the cell transistor, the peripheral circuit may be arranged at the bottom of the cell array structure CS. Figure 2 The cell array structure CS may be disposed in the peripheral circuit structure PS but may not be disposed in the upper peripheral region UPR of the cell array structure CS.

[0070] The peripheral circuits of the present invention can be divided into Figure 2 The cell array structure CS and the peripheral circuit structure PS are formed in part. Therefore, the peripheral circuit is only placed in Figure 2 As compared with the case of the peripheral circuit structure PS in FIG. 1 , the size of the semiconductor memory device 10 can be reduced or the integration degree of the semiconductor memory device 10 can be improved. As a result, the semiconductor memory device 10 with reduced size or improved integration can be provided.

[0071] Figure 7 is a flowchart illustrating a method of manufacturing a cell array structure according to an embodiment. Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A and Fig.13A It is shown Figure 7 A plan view of the manufacturing method. Figure 8B , Figure 8C , Fig. 9B , Fig. 9C , Fig. 10B , Fig. 10C , Fig. 11B , Fig. 11C , Fig. 12B , Fig. 12C , Fig. 13B and Fig. 13C is with Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A and Fig.13A The cross-sectional views corresponding to the lines A-A', B-B', C-C' and D-D' in FIG. Figure 7 Manufacturing method.

[0072] Reference Figure 7 , Fig. 8A , Figure 8B and Figure 8C, a first conductive line 102 and a lower insulating layer 104 and a preliminary gate insulating layer 121 may be provided on a substrate 100 provided in the cell array region CAR and the upper peripheral region UPR (S101). The substrate 100 may include a semiconductor material. For example, the substrate 100 may include silicon (Si), germanium (Ge) or silicon germanium (SiGe). The substrate 100 may include a first surface 100a and a second surface 100b facing opposite directions. The first surface 100a and the second surface 100b may extend along a first direction DR1 and a second direction DR2. The first surface 100a and the second surface 100b may be spaced apart from each other along a third direction DR3. The substrate 100 may have a first conductivity type. For example, the first conductivity type may be a p-type or an n-type. When the conductivity type of the substrate 100 is a p-type, the substrate 100 may be a silicon (Si) substrate containing a group III element (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or a group II element as an impurity. When the conductivity type of the substrate 100 is n-type, the substrate 100 may be a silicon (Si) substrate containing a group V element (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), a group VI element, or a group VII element as an impurity. Hereinafter, a region whose conductivity type is n-type may include impurities of a group V element, a group VI element, or a group VII element. When the first conductivity type is p-type or n-type, the second conductivity type may be n-type or p-type, respectively. The substrate 100 may be an epitaxial layer formed by an epitaxial growth process.

[0073] A lower insulating layer 104 may be disposed on the substrate 100. A groove 103 may be disposed between the lower insulating layers 104. The groove 103 may provide an area in which the first conductive line 102 is disposed. Although the groove 103 is shown as exposing the first surface 100a, this is illustrative. In an example, the groove 103 may be disposed on the top of the lower insulating layer 104 to expose the lower portion of the lower insulating layer 104. The groove 103 may extend along the first direction DR1. The grooves 103 may be spaced apart from each other in the second direction DR2. The lower insulating layer 104 may include an insulating material. For example, the lower insulating layer 104 may include silicon oxide, silicon nitride and / or silicon oxynitride. In one embodiment, the lower insulating layer 104 may be formed by patterning an insulating layer deposited on the substrate 100. For example, an insulating layer may be formed on the substrate 100 by chemical vapor deposition (CVD), physical vapor deposition (PVD) and / or atomic layer deposition (ALD).

[0074] A first conductive line 102 may be disposed in each trench 103. The first conductive line 102 may extend along a first direction DR1. The first conductive lines 102 may be spaced apart from each other in a second direction DR2. The first conductive line 102 may include a conductive material. For example, the first conductive line 102 may include doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, RuTiN), a conductive metal silicon nitride (e.g., TiSiN, TaSiN), a conductive metal silicide, and / or a conductive metal oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3 ), LSCo). The first conductive line 102 may have a single-layer or multi-layer structure. In one embodiment, the first conductive line 102 may include a two-dimensional semiconductor material. For example, the first conductive line 102 may include graphene, carbon nanotubes, or a combination thereof. The first conductive line 102 may be formed by at least partially filling the groove 103 with a conductive material. For example, at least partially filling the groove 103 with a conductive material may include depositing a conductive layer on the top surface of the lower insulating layer 104 and in the groove 103, and then removing the conductive layer on the top surface of the lower insulating layer 104. For example, the conductive layer may be disposed on the substrate 100 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0075] The preliminary gate insulating layer 121 may be disposed on the lower insulating layer 104 and the first conductive line 102. The preliminary gate insulating layer 121 may extend along the second direction DR2. The preliminary gate insulating layer 121 may be arranged along the first direction DR1. For example, the preliminary gate insulating layers 121 may be spaced apart from each other along the first direction DR1. The preliminary gate insulating layer 121 may include a low-k dielectric material, silicon oxide, and / or a high-k dielectric material. The high-k dielectric material may be a metal oxide or a metal oxynitride. For example, the preliminary gate insulating layer 121 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3or a combination thereof. In example embodiments, an etch stop layer having an etch selectivity with respect to the preliminary gate insulating layer 121 may be disposed on the bottom surface of the preliminary gate insulating layer 121. The preliminary gate insulating layer 121 may be formed by patterning a deposited insulating layer. For example, the insulating layer may be disposed on the lower insulating layer 104 and the first conductive line 102 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0076] Reference Figure 7 , Fig. 9A , Fig. 9B and Fig. 9C , a first preliminary semiconductor pattern SP1a may be formed (S102). The first preliminary semiconductor pattern SP1a may be formed on the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121 (S102). The first preliminary semiconductor pattern SP1a may extend along surfaces of the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121. For example, the first preliminary semiconductor pattern SP1a may be formed along contours of the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121. The first preliminary semiconductor pattern SP1a may be formed by depositing a semiconductor material layer on the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121. For example, depositing the semiconductor material layer may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0077] In one embodiment, before the first preliminary semiconductor pattern SP1a is provided, a mask pattern MP may be provided in a portion of the upper peripheral region UPR. The mask pattern MP may at least partially cover the preliminary gate insulating layer 121, the first conductive line 102, and the lower insulating layer 104 provided in a portion of the upper peripheral region UPR. A portion of the upper peripheral region UPR may be a region in which the second vertical peripheral transistor is provided.

[0078] The formation process of the first preliminary semiconductor pattern SP1a may be performed while forming a mask pattern MP on the preliminary gate insulating layer 121, the first conductive line 102, and the lower insulating layer 104. The mask pattern MP may be removed after the first preliminary semiconductor pattern SP1a is formed.

[0079] The first preliminary semiconductor pattern SP1a may include an oxide semiconductor. For example, the first preliminary semiconductor pattern SP1a may include In x Ga y Zn z O、In x Ga y Si z O、In x Sny Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O and / or In x Ga y O. As an example embodiment, the first preliminary semiconductor pattern SP1a may include indium gallium zinc oxide (IGZO). The first preliminary semiconductor pattern SP1a may include a single layer or a multi-layer oxide semiconductor. The first preliminary semiconductor pattern SP1a may include an amorphous, single crystal, or polycrystalline oxide semiconductor. In an example embodiment, the first preliminary semiconductor pattern SP1a may include a two-dimensional (2D) semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof. The first preliminary semiconductor pattern SP1a may have a first conductivity type. For example, the conductivity type of the first preliminary semiconductor pattern SP1a may be a p-type.

[0080] Reference Figure 7 , Fig. 10A , Fig. 10B and Fig. 10C, a second preliminary semiconductor pattern SP2a may be disposed in the upper peripheral region UPR (S103). The second preliminary semiconductor pattern SP2a may be disposed in a portion of the upper peripheral region UPR. A portion of the upper peripheral region UPR may be a region in which the first preliminary semiconductor pattern SP1a is not disposed. The second preliminary semiconductor pattern SP2a may be disposed on the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121 in a portion of the upper peripheral region UPR. The second preliminary semiconductor pattern SP2a may extend along the surface of the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121. For example, the second preliminary semiconductor pattern SP2a may be disposed along the contour of the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121. The second preliminary semiconductor pattern SP2a may be formed by depositing a semiconductor material layer on the first conductive line 102, the lower insulating layer 104, and the preliminary gate insulating layer 121. For example, depositing the semiconductor material layer may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0081] In one embodiment, before the second preliminary semiconductor pattern SP1a is set, a mask pattern MP may be set in another portion of the upper peripheral region UPR and the cell array region CAR. Another portion of the upper peripheral region UPR may be a region in which the first vertical peripheral transistor is set. The mask pattern MP may at least partially cover the first preliminary semiconductor pattern SP1a in another portion of the upper peripheral region UPR and the cell array region CAR. The process of forming the second preliminary semiconductor pattern SP2a may be performed while the mask pattern MP is formed on the first preliminary semiconductor pattern SP1a. The mask pattern MP may be removed after the second preliminary semiconductor pattern SP2a is formed.

[0082] The second preliminary semiconductor pattern SP2a may include an oxide semiconductor. For example, the second preliminary semiconductor pattern SP2a may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O,Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Snx O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O and / or In x Ga y O. As an example embodiment, the second preliminary semiconductor pattern SP2a may include indium gallium zinc oxide (IGZO). The second preliminary semiconductor pattern SP2a may include a single layer or a multi-layer oxide semiconductor. The second preliminary semiconductor pattern SP2a may include an amorphous, single crystal, or polycrystalline oxide semiconductor. In an example embodiment, the second preliminary semiconductor pattern SP2a may include a two-dimensional (2D) semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof. The second preliminary semiconductor pattern SP2a may have a second conductivity type. For example, the conductivity type of the second preliminary semiconductor pattern SP2a may be an n-type.

[0083] Reference Figure 7 , Fig.11A , Fig. 11B and Fig. 11C , a first semiconductor pattern SP1 and a second semiconductor pattern SP2 may be disposed on the first conductive line 102 ( S104 ).

[0084] The first semiconductor pattern SP1 may be provided on the side surface of the preliminary gate insulating layer 121. The first semiconductor pattern SP1 may be arranged on the side surface of the preliminary gate insulating layer 121 along the second direction DR2. For example, on the side surface of the preliminary gate insulating layer 121, the first semiconductor pattern SP1 may extend along the second direction DR2. The first semiconductor pattern SP1 may be arranged along the first conductive line 102. For example, the first semiconductor pattern SP1 may be arranged at regular intervals along the first direction DR1. In example embodiments, a pair of first semiconductor patterns SP1 adjacent to each other may be spaced apart along the first direction DR1, with the preliminary gate insulating layer 121 interposed between the pair of first semiconductor patterns SP1. One of the pair of first semiconductor patterns SP1 adjacent to each other may be disposed on one side of the preliminary gate insulating layer 121, and the other may be disposed on the other side of the preliminary gate insulating layer 121.

[0085] The second semiconductor pattern SP2 may be provided on the side surface of the preliminary gate insulating layer 121. The second semiconductor pattern SP2 may be arranged on the side surface of the preliminary gate insulating layer 121 along the second direction DR2. For example, on the side surface of the preliminary gate insulating layer 121, the second semiconductor pattern SP2 may extend along the second direction DR2. The second semiconductor pattern SP2 may be arranged along the first conductive line 102. For example, the second semiconductor pattern SP2 may be arranged at regular intervals along the first direction DR1. In example embodiments, a pair of second semiconductor patterns SP2 adjacent to each other may be spaced apart along the first direction DR1, with the preliminary gate insulating layer 121 interposed between the pair of second semiconductor patterns SP2. One of the pair of second semiconductor patterns SP2 adjacent to each other may be disposed on one side of the preliminary gate insulating layer 121, and the other may be disposed on the other side of the preliminary gate insulating layer 121.

[0086] The first and second semiconductor patterns SP1a and SP2a may be formed by patterning the first and second preliminary semiconductor patterns SP1a and SP2a so that top and side surfaces of the preliminary gate insulating layer 121, the top surface of the first conductive line 102, and the top surface of the lower insulating layer 104 may be exposed.

[0087] Reference Figure 7 , Fig. 12A , Fig. 12B and Fig. 12C , a first gate insulating layer 108, a second conductive line 106, a first insulating pattern 110 and a second insulating pattern 112 may be disposed on side surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the preliminary gate insulating layer 121 (S105). The first gate insulating layer 108 may extend along the side surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the preliminary gate insulating layer 121. For example, the first gate insulating layer 108 may be disposed along the contours of the side surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the preliminary gate insulating layer 121. The first gate insulating layer 108 may be arranged along the first direction DR1. The first gate insulating layer 108 may include a low-k dielectric material, silicon oxide and / or a high-k dielectric material. The high-k dielectric material may be a metal oxide or a metal oxynitride. For example, the first gate insulating layer 108 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3For example, the first gate insulating layer 108 may be formed using physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD) and / or atomic layer deposition (ALD).

[0088] The second conductive line 106 may be disposed on the first gate insulating layer 108. The second conductive line 106 may be spaced apart from the preliminary gate insulating layer 121, and the first gate insulating layer 108 is interposed between the second conductive line 106 and the preliminary gate insulating layer 121. The second conductive line 106 may extend along the first gate insulating layer 108. For example, the second conductive line 106 may extend along the second direction DR2. The second conductive line 106 may be arranged along the first direction DR1. The second conductive line 106 may include a conductive material. For example, the second conductive line 106 may include doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, RuTiN), a conductive metal silicon nitride (e.g., TiSiN, TaSiN), a conductive metal silicide and / or a conductive metal oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3 ), LSCo). The second conductive line 106 may have a single layer or a multilayer structure. In some embodiments, the second conductive line 106 may include a two-dimensional (2D) semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof. The second conductive line 106 may be formed by depositing a conductive layer on the side of the first gate insulating layer 108 and performing an anisotropic etching process on the deposited conductive layer. For example, depositing the conductive layer may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The second conductive line 106 may be spaced apart from the first conductive line 102 and the lower insulating layer 104.

[0089] A first insulating pattern 110 may be disposed on the bottom surface of the second conductive line 106. The first insulating pattern 110 may extend along the bottom surface of the second conductive line 106. For example, the first insulating pattern 110 may extend along the second direction DR2. The first insulating pattern 110 may at least partially overlap the second conductive line 106 along the third direction DR3. The first insulating pattern 110 may be disposed between the second conductive line 106 and the first conductive line 102 and between the second conductive line 106 and the lower insulating layer 104. For example, the first insulating pattern 110 may be formed by depositing an insulating layer on the side of the first gate insulating layer 108 located below the second conductive line 106 and performing an anisotropic etching process on the deposited insulating layer. For example, depositing the insulating layer may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The first insulating pattern 110 may include an insulating material. For example, the first insulating pattern 110 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0090] A second insulating pattern 112 may be disposed between the first gate insulating layers 108. The second insulating pattern 112 may at least partially cover the second conductive line 106 and the first insulating pattern 110. The second insulating pattern 112 may at least partially fill a region between the first gate insulating layers 108. The second insulating pattern 112 may include an insulating material. For example, the second insulating pattern 112 may include silicon oxide, silicon nitride, and / or silicon oxynitride. In example embodiments, the second insulating pattern 112 may be formed by depositing an insulating layer between the preliminary gate insulating layers 121. For example, depositing the insulating layer may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD).

[0091] Reference Figure 7 , Fig.13A , Fig. 13B and Fig. 13C , a third insulating pattern 116 , a third conductive line 114 , and a fourth insulating pattern 118 may be provided ( S106 ).

[0092] Forming the third insulating pattern 116, the third conductive line 114, and the fourth insulating pattern 118 may include forming a trench 121t penetrating the preliminary gate insulating layer 121 along the third direction DR3, and sequentially forming the third insulating pattern 116, the third conductive line 114, and the fourth insulating pattern 118 in each trench 121t. The trench 121t may be provided in the preliminary gate insulating layer 121 to form the second gate insulating layer 120. That is, the remaining portion of the preliminary gate insulating layer 121 after forming the trench 121t may be referred to as the second gate insulating layer 120. The third insulating pattern 116, the third conductive line 114, and the fourth insulating pattern 118 may extend along the second conductive line 106. For example, the third insulating pattern 116, the third conductive line 114, and the fourth insulating pattern 118 may extend along the second direction DR2. The third insulating pattern 116 and the fourth insulating pattern 118 may include an insulating material. For example, the third insulating pattern 116 and the fourth insulating pattern 118 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0093] The third conductive line 114 may include a conductive material. For example, the third conductive line 114 may include doped polysilicon, metal, conductive metal nitride, metal-semiconductor compound, conductive metal oxide, graphene, carbon nanotube and / or a combination thereof. For example, the third conductive line 114 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiAlC, TaAlC, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotube or a combination thereof. The third conductive line 114 may have a single layer or multilayer structure.

[0094] The third conductive line 114 may be Figure 4A The vertical unit transistor VCT, Figure 4B The first vertical peripheral transistor VPT1 and Figure 4B The third conductive line 114 may be raised to the back gate electrode of the second vertical peripheral transistor VPT2. Figure 4A The vertical unit transistor VCT, Figure 4B The first vertical peripheral transistor VPT1 and Figure 4B The threshold voltage of the second vertical peripheral transistor VPT2 in FIG. Figure 4A The vertical unit transistor VCT, Figure 4B The first vertical peripheral transistor VPT1 and Figure 4B The second vertical peripheral transistor VPT2 in the embodiment has a small size, and a reduction in threshold voltage and degradation in leakage current characteristics can also be prevented.

[0095] Reference Figure 7 , Figure 5A , Figure 5B and Figure 5C , an upper insulating layer 132, a first pad 130, a second pad 131, a lower electrode 142, a capacitor dielectric layer 144, an upper electrode 146, and a capping layer 150 may be disposed (S107). The upper insulating layer 132 may be disposed on the fourth insulating pattern 118. For example, the upper insulating layer 132 may be formed by depositing an insulating layer extending in the first direction DR1 and the second direction DR2 on the fourth insulating pattern 118 and patterning the insulating layer. For example, the deposition process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The pad hole 132h in which the pads 130 and 131 are disposed may be formed by patterning the insulating layer. The pad hole 132h may be disposed on the first semiconductor pattern SP1 and the second semiconductor pattern SP2, respectively. The pad hole 132h may expose the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The upper insulating layer 132 may include an insulating material. For example, the upper insulating layer 132 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0096] The first pad 130 may be disposed in each pad hole 132h of the cell array region CAR. Therefore, the first pads 130 may be disposed on the first semiconductor pattern SP1, respectively. The first pad 130 may at least partially overlap vertically with the first semiconductor pattern SP1. For example, the first pad 130 may be formed by depositing a conductive material into the pad hole 132h of the cell array region CAR. For example, the deposition process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The first pad 130 may be electrically connected to the first semiconductor pattern SP1. The first pad 130 may include a conductive material. For example, the first pad 130 may include doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal and / or a metal alloy.

[0097] The second pad 131 may be disposed in the pad hole 132h of the upper peripheral region UPR, respectively. Therefore, the second pad 131 may be disposed on the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the upper peripheral region UPR, respectively. The second pad 131 may at least partially overlap the first semiconductor pattern SP1 and the second semiconductor pattern SP2 vertically. For example, the second pad 131 may be formed by depositing a conductive material into the pad hole 132h of the upper peripheral region UPR. For example, the deposition process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The second pad 131 may be electrically connected to the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The second pad 131 may include a conductive material. For example, the second pad 131 may include doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal and / or a metal alloy.

[0098] The lower electrode 142, the capacitor dielectric layer 144, and the upper electrode 146 may be disposed in the cell array region CAR. The lower electrode 142, the capacitor dielectric layer 144, and the upper electrode 146 may form a capacitor. The lower electrode 142 may be arranged in a matrix form along the first direction DR1 and the second direction DR2. The lower electrode 142 may overlap the first pad 130 completely or partially in the third direction DR3. The lower electrode 142 may contact the first pad 130. When viewed in a plane extending along the first direction DR1 and the second direction DR2, the lower electrode 142 may have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape. The lower electrode 142 may include a conductive material. The lower electrode 142 may include, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, and / or a metal.

[0099] The capacitor dielectric layer 144 may be disposed on the surface of the lower electrode 142 and the upper surface of the upper insulating layer 132. For example, the capacitor dielectric layer 144 may extend along the surface of the lower electrode 142 and the upper surface of the upper insulating layer 132. The capacitor dielectric layer 144 may include a ferroelectric material, an antiferroelectric material, and / or a paraelectric material. For example, the capacitor dielectric layer 144 may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, and a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0100] The upper electrode 146 may be disposed on the capacitor dielectric layer 144. The upper electrode 146 may be spaced apart from the lower electrode 142 by the capacitor dielectric layer 144. The upper electrode 146 may include a conductive material. The upper electrode 146 may include, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, and / or a metal.

[0101] The cap layer 150 may be disposed in the upper peripheral region UPR. The upper peripheral region UPR may not include a capacitor. The cap layer 150 may be disposed on the second pad 131 and the upper insulating layer 132. For example, the cap layer 150 may be formed by depositing an insulating material on the second pad 131 and the upper insulating layer 132. For example, the deposition process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, the cap layer 150 may include silicon oxide, silicon nitride, or silicon oxynitride. The cap layer 150 may be disposed in the upper peripheral region UPR. Vertical conductive lines VCL and horizontal conductive lines HCL providing electrical connections between the second pad 131 and other components may be disposed in the cap layer 150.

[0102] In an example, a variable resistance pattern may be provided instead of a capacitor, and the variable resistance pattern may be switched between two resistance states by an electric pulse. For example, the variable resistance pattern may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes depending on the amount of current.

[0103] At least some of the peripheral circuits of the present invention may be disposed in the cell array structure CS. In example embodiments, a method of manufacturing a semiconductor memory device 10 having improved integration or reduced size may be provided.

[0104] Fig.14 is a cross-sectional view of a semiconductor memory device according to an example embodiment. To the extent that elements are not described in detail with respect to this figure, it can be assumed that these elements are at least similar to those already described with respect to FIG. 5A to FIG. 5C Corresponding elements as shown and described.

[0105] Reference Fig.14 , a peripheral circuit structure PS and a cell array structure CS may be provided. The cell array structure CS may be provided on the peripheral circuit structure PS. The peripheral circuit structure PS and the cell array structure CS may be arranged along a third direction DR3. FIG. 5A to FIG. 5CDifferent from the description, the cell array structure CS may further include a lower cover layer 160, a vertical conductive line VCL, and a horizontal conductive line HCL provided on the second surface 100b of the substrate 100. The lower cover layer 160 may at least partially cover the second surface 100b of the substrate 100. The lower cover layer 160 may include an insulating material. For example, the lower cover layer 160 may include silicon oxide, silicon nitride, or silicon oxynitride. In example embodiments, the lower cover layer 160 may have a multilayer structure in which a plurality of insulating layers are stacked.

[0106] The vertical conductive lines VCL and the horizontal conductive lines HCL may be configured to provide electrical connections between different components. Fig.14 The configuration of the vertical conductive lines VCL and the horizontal conductive lines HCL shown is for the purpose of providing an example. The configuration of the vertical conductive lines VCL and the horizontal conductive lines HCL can be determined as needed.

[0107] The peripheral circuit structure PS may include a peripheral substrate 200, a horizontal peripheral transistor 300, a peripheral insulating layer 210, a vertical conductive line VCL, and a horizontal conductive line HCL. A peripheral substrate 200 may be provided. The peripheral substrate 200 may be disposed in the cell drive region CDR and the lower peripheral region LPR. The peripheral substrate 200 may include a semiconductor material. For example, the peripheral substrate 200 may include silicon (Si), germanium (Ge), and / or silicon germanium (SiGe). The peripheral substrate 200 may have a first conductivity type. For example, the first conductivity type may be p-type or n-type. When the conductivity type of the peripheral substrate 200 is p-type, the peripheral substrate 200 may be a silicon (Si) substrate containing a group III element (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or a group II element as an impurity. When the conductivity type of the peripheral substrate 200 is n-type, the peripheral substrate 200 may be a silicon (Si) substrate containing a group V element (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), a group VI element, or a group VII element as an impurity. When the first conductivity type is p-type or n-type, the second conductivity type may be n-type or p-type, respectively. The peripheral substrate 200 may be an epitaxial layer formed by an epitaxial growth process.

[0108] The horizontal peripheral transistor 300 may include a planar transistor. Each horizontal peripheral transistor 300 may have a channel extending in a direction parallel to the top surface of the peripheral substrate 200 (e.g., a first direction DR1). The source / drain region 302 of the horizontal peripheral transistor 300 may be provided on the peripheral substrate 200. The channel of the horizontal peripheral transistor 300 may be provided between the source / drain region 302. The gate electrode 304 of the horizontal peripheral transistor 300 may be provided on the upper surface of the peripheral substrate 200. The gate insulating layer 306 of the horizontal peripheral transistor 300 may be provided between the gate electrode 304 of the horizontal peripheral transistor 300 and the upper surface of the peripheral substrate 200. When viewed along the third direction DR3, the source / drain region 302 may be spaced apart from each other, and the gate electrode 304 is interposed between the source / drain region 302. Although the source / drain region 302 is shown as being spaced apart from each other along the first direction DR1, this is merely illustrative. The separation direction of the source / drain regions 302 may be determined according to the shape of the horizontal peripheral transistor 300 .

[0109] A peripheral insulating layer 210 may be provided on the peripheral substrate 200. The peripheral insulating layer 210 may at least partially cover the horizontal peripheral transistor 300. The peripheral insulating layer 210 may include an insulating material. For example, the peripheral insulating layer 210 may include silicon oxide, silicon nitride, and / or silicon oxynitride. In example embodiments, the peripheral insulating layer 210 may have a multilayer structure in which a plurality of insulating layers are stacked.

[0110] The vertical conductive lines VCL and the horizontal conductive lines HCL may be configured to provide electrical connections between different components. Fig.14 The configuration of the vertical conductive line VCL and the horizontal conductive line HCL shown is for the purpose of providing an example. The configuration of the vertical conductive line VCL and the horizontal conductive line HCL can be determined as needed. For example, the vertical conductive line VCL and the horizontal conductive line HCL can be provided between the upper electrode 146 and the horizontal peripheral transistor 300 to provide an electrical connection.

[0111] Although the horizontal peripheral transistor 300 is shown as being provided in the cell driving region CDR and the lower peripheral region LPR, this is merely an example embodiment. In an example, the horizontal peripheral transistor 300 may be provided in the cell driving region CDR and not in the lower peripheral region LPR.

[0112] At least some of the peripheral circuits of the present invention may be provided in the cell array structure CS. In example embodiments, the integration degree of the semiconductor memory device 20 may be improved. In example embodiments, the size of the semiconductor memory device 20 may be reduced.

[0113] According to example embodiments, the present invention may provide a semiconductor memory device with improved integration.

[0114] According to example embodiments, the present invention may provide a semiconductor memory device having a reduced size.

[0115] Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure.

[0116] This application claims the priority of Korean Patent Application No. 10-2023-0158533 filed in the Korean Intellectual Property Office on November 15, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: Peripheral circuit structure; as well as a cell array structure disposed on the peripheral circuit structure and including a plurality of cell array regions and an upper peripheral region disposed between the cell array regions among the plurality of cell array regions, The cell array structure includes a vertical cell transistor, a first vertical peripheral transistor and a second vertical peripheral transistor. wherein each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor includes a channel extending in a third direction parallel to an arrangement direction of the peripheral circuit structure and the cell array structure, wherein the vertical cell transistor is disposed in the cell array region and has a first polarity, wherein the first vertical peripheral transistor is disposed in the upper peripheral region and has the first polarity, and The second vertical peripheral transistor is disposed in the upper peripheral region and has a second polarity different from the first polarity.

2. The semiconductor memory device according to claim 1, wherein: Each of the vertical cell transistor and the first vertical peripheral transistor includes a first semiconductor pattern extending in the third direction and having a first conductivity type and a first gate electrode facing the first semiconductor pattern, and Each of the second vertical peripheral transistors includes a second semiconductor pattern extending along the third direction and having a second conductivity type different from the first conductivity type and a second gate electrode facing the second semiconductor pattern.

3. The semiconductor memory device according to claim 2, wherein: The cell array structure further includes a first conductive line extending along a first direction, and Wherein, the first semiconductor pattern and the second semiconductor pattern are disposed on the first conductive line.

4. The semiconductor memory device according to claim 3, wherein: In the cell array region, the first semiconductor patterns arranged along the first direction are electrically connected to one of the first conductive lines.

5. The semiconductor memory device according to claim 3, wherein: In the upper peripheral region, the first semiconductor pattern and the second semiconductor pattern adjacent to each other along the first direction are electrically connected to different first conductive lines.

6. The semiconductor memory device according to claim 3, wherein: In the upper peripheral region, first semiconductor patterns immediately adjacent to each other along the first direction are electrically connected to different first conductive lines.

7. The semiconductor memory device according to claim 2, wherein: The cell array region and the upper peripheral region further include second conductive lines arranged along the first direction and extending along the second direction, and The second conductive line faces the first semiconductor pattern and the second semiconductor pattern, and includes the first gate electrode and the second gate electrode.

8. The semiconductor memory device according to claim 7, wherein: The cell array region and the upper peripheral region further include a third conductive line arranged along the first direction and extending along the second direction, and The third conductive line is disposed in a region between a pair of vertical unit transistors adjacent to each other, a region between a pair of first vertical peripheral transistors adjacent to each other, and a region between a pair of second vertical peripheral transistors adjacent to each other.

9. The semiconductor memory device according to claim 8, wherein: The third conductive line is configured to apply a back gate voltage that adjusts a threshold voltage to the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor, and Each of a pair of vertical unit transistors adjacent to each other, a pair of first vertical peripheral transistors adjacent to each other, and a pair of second vertical peripheral transistors adjacent to each other shares one of the third conductive lines.

10. The semiconductor memory device according to claim 1, wherein The cell array structure further comprises: first pads, respectively disposed on the vertical unit transistors; capacitors, respectively disposed on the first pads; and a second pad electrically connected to the first vertical peripheral transistor and the second vertical peripheral transistor, Wherein, in a plan view, the capacitor at least partially overlaps with the vertical cell transistor and is spaced apart from the first vertical peripheral transistor and the second vertical peripheral transistor.

11. The semiconductor memory device according to claim 10, wherein: The first vertical peripheral transistor and the second vertical peripheral transistor immediately adjacent to each other are electrically connected to each other through one of the second pads.

12. The semiconductor memory device according to claim 10, wherein: The first vertical peripheral transistors that are adjacent to each other are electrically connected to each other through one of the second pads.

13. The semiconductor memory device according to claim 12, wherein: The vertical cell transistor and the capacitor adjacent to each other are electrically connected to each other through a first pad disposed between the vertical cell transistor and the capacitor adjacent to each other.

14. The semiconductor memory device according to claim 10, wherein: The cell array structure further includes a vertical conductive line and a horizontal conductive line electrically connected to the second pad.

15. The semiconductor memory device according to claim 1, wherein: The first vertical peripheral transistor and the second vertical peripheral transistor are disposed in a region of the upper peripheral region arranged along the first direction from the cell array region.

16. A semiconductor memory device comprising: Peripheral circuit structure; as well as A cell array structure, arranged on the peripheral circuit structure; wherein the peripheral circuit structure includes a horizontal peripheral transistor having a channel extending in a first direction intersecting with an arrangement direction of the peripheral circuit structure and the cell array structure, The cell array structure includes a capacitor, a vertical cell transistor, a first vertical peripheral transistor and a second vertical peripheral transistor. wherein the capacitor is electrically connected to the vertical cell transistor, wherein each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor has a channel extending in a third direction parallel to the arrangement direction of the peripheral circuit structure and the cell array structure, and The first vertical peripheral transistor and the second vertical peripheral transistor respectively have a first polarity and a second polarity different from the first polarity.

17. The semiconductor memory device according to claim 16, wherein: The peripheral circuit structure and the cell array structure further include a vertical conductive line and a horizontal conductive line disposed between the capacitor and the horizontal peripheral transistor, and The capacitor and the horizontal peripheral transistor are electrically connected to each other through the vertical conductive line and the horizontal conductive line.

18. The semiconductor memory device according to claim 16, wherein: The cell array structure includes a plurality of cell array regions and an upper peripheral region disposed between the plurality of cell array regions. wherein the vertical cell transistor and the capacitor are arranged in the plurality of cell array regions, wherein the first vertical peripheral transistor and the second vertical peripheral transistor are disposed in the upper peripheral region, and Wherein, in a plan view, the horizontal peripheral transistor is disposed in a region at least partially overlapping with the plurality of cell array regions.

19. A semiconductor memory device comprising: A substrate including a plurality of cell array regions and an upper peripheral region disposed between the plurality of cell array regions; A first conductive line extending along a first direction on the substrate and arranged along a second direction intersecting the first direction; A vertical cell transistor, a first vertical peripheral transistor, and a second vertical peripheral transistor are disposed on the first conductive line; as well as a capacitor disposed on each of the vertical unit transistors, wherein each of the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor has a channel extending in a third direction perpendicular to a top surface of the substrate, The vertical cell transistor is an N-type metal oxide semiconductor (NMOS) transistor disposed in the cell array region. wherein the first vertical peripheral transistor is an NMOS transistor disposed in the upper peripheral region, and The second vertical peripheral transistor is a P-type metal oxide semiconductor (PMOS) transistor disposed in the upper peripheral region.

20. The semiconductor memory device according to claim 19, further comprising: a second conductive line arranged on the substrate along the first direction and extending along the second direction; as well as A third conductive line is disposed in a region between a pair of vertical unit transistors that are adjacent to each other among the vertical unit transistors, a region between a pair of first vertical peripheral transistors that are adjacent to each other among the first vertical peripheral transistors, and a region between a pair of second vertical peripheral transistors that are adjacent to each other among the second vertical peripheral transistors, wherein the second conductive line is configured to apply a gate voltage to the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor, The third conductive line is configured to apply a back gate voltage for adjusting a threshold voltage to the vertical cell transistor, the first vertical peripheral transistor, and the second vertical peripheral transistor.

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