Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes: a first connection region, a first memory block region, and a second connection region arranged in sequence; a first peripheral circuit region that vertically overlaps the first memory block region; a first memory cell in the first memory block region; a first word line extending through the first memory block region into the first connection region and the second connection region, and electrically connected to the first memory cell; a first sub word line driver in the first peripheral circuit region; and a first word line signal path electrically connecting the first word line and the first sub-word line driver. The first word line signal path includes at least one first wiring contact coupled to the first word line in the first connection region and at least one second wiring contact coupled to the first word line in the second connection region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a word line signal path. Background Art

[0002] Research is being conducted to reduce the size of elements constituting semiconductor devices and to improve the performance of elements constituting semiconductor devices. For example, in dynamic random access memory (DRAM), research is being conducted to reliably and stably form elements with reduced size, but as the size of the elements is reduced, the performance of the semiconductor device may deteriorate. Summary of the invention

[0003] An aspect of the present disclosure is to provide a semiconductor device that can increase integration and improve performance.

[0004] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a first structure, the first structure having a first connection region, a second connection region and a first storage block region, the first storage block region being located between the first connection region and the second connection region in a first direction; and a second structure, the second structure vertically overlapping the first structure. The first structure includes: a first storage cell, the first storage cell being located in the first storage block region; and a first word line, the first word line traversing the first storage block region and extending into the first connection region and the second connection region, and electrically connected to the first storage cell, the second structure having a first peripheral circuit region, at least a portion of the first peripheral circuit region vertically overlapping the first storage block region, the second structure including a first sub-word line driver in the first peripheral circuit region, the first structure and the second structure also including a first word line signal path electrically connecting the first word line and the first sub-word line driver, and the first word line signal path including at least one first wiring contact coupled to the first word line in the first connection region and at least one second wiring contact coupled to the first word line in the second connection region.

[0005] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a first connection region, a second connection region and a first storage block region, the first storage block region is located between the first connection region and the second connection region in a first direction; a first peripheral circuit region, the first peripheral circuit region vertically overlaps with the first storage block region; a first storage cell, the first storage cell is located in the first storage block region; a first word line, the first word line extends through the first storage block region to the first connection region and the second connection region, and is electrically connected to the first storage cell; a sub-word line driver, the sub-word line driver is located in the first peripheral circuit region; and a first word line signal path, the first word line signal path electrically connects the first word line and the sub-word line driver. The first word line signal path includes at least one first wiring contact coupled to the first word line in the first connection region and at least one second wiring contact coupled to the first word line in the second connection region.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a first structure, the first structure includes connection areas and storage block areas arranged alternately and repeatedly along a first direction; and a second structure, the second structure is arranged along the first direction and includes a peripheral circuit area, and the second structure overlaps the first structure vertically. The connection area includes a first edge connection area, a second edge connection area, and an intermediate connection area located between the first edge connection area and the second edge connection area, and each of the storage block areas is located between a pair of adjacent connection areas among the connection areas. The first structure includes: a storage cell located in each of the storage block areas; and a word line, the word line passes through the storage block area and extends into the connection area and is electrically connected to the storage cell. The second structure includes a sub-word line driver in each of the peripheral circuit areas. The first structure and the second structure also include a word line signal path electrically connecting the word line and the sub-word line driver. The word line signal path includes: a wiring interconnect line, which passes through the storage block area and extends into the connection area; a wiring contact located in each of the connection areas, which electrically connects the word line and the wiring interconnect line; and a wiring structure, which electrically connects the wiring interconnect line and the sub-word line driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A , Figure 1B , Figure 2A-2C , Figure 3 , Figure 4 , Figure 5A-Figure 5C , Figure 6 , Figure 7A-7D , Figure 8 , Fig.9A and Fig. 9B is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.10 , Fig.11A and Fig. 11B is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig. 12A , Fig. 12B and Fig. 12C is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.13 is a perspective view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.14 and Fig.15 is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.16 and Fig.17 is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.18A and Fig.18B is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.19A is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.19B is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.19C is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig. 20 is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.21 is a view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig. 22 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.23 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; Fig.24 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure; and Fig.25 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0008] Hereinafter, terms such as "upper", "middle" and "lower" may be replaced with other terms such as "first", "second" and "third" and may be used to describe elements of the specification. Terms such as "first", "second" and "third" may be used to describe various elements, but these elements are not limited thereto, and the "first element" can be referred to as the "second element".

[0009] In the specification, terms such as "lower", "upper", "top", and "bottom" may be terms based on description of the drawings.

[0010] In the drawings, marks in the form of “M(M1)” and “M(M2)” have multiple elements called “M”, and the multiple elements called “M” can be defined as including a first element called “M1” and a second element called “M2”.

[0011] First, refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 2C An example of a semiconductor device according to an example embodiment of the present disclosure is described. Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 2C middle, Figure 1A is a perspective view conceptually illustrating an example of a semiconductor device according to an example embodiment of the present disclosure, Figure 1B It is a conceptual illustration Figure 1A A perspective view of a portion of Figure 2A is a circuit diagram illustrating an example of a memory block in a memory block region of a semiconductor device according to an example embodiment of the present disclosure, Figure 2B is a circuit diagram illustrating an example of a sub word line driver in a peripheral circuit region of a semiconductor device according to an example embodiment of the present disclosure, and Figure 2C is a circuit diagram illustrating an example of a sense amplifier in a peripheral circuit region of a semiconductor device according to an example embodiment of the present disclosure.

[0012] First, refer to Figure 1A and Figure 1B, a semiconductor device 1 according to example embodiments may include a first structure ST1 and a second structure ST2 vertically overlapping the first structure ST1 (e.g., the first structure ST1 vertically overlaps thereon). As used herein, the phrase "A vertically overlaps B" means that A is above B (and a vertical line extends through both A and B). The first structure ST1 may be disposed on (e.g., above) the second structure ST2.

[0013] In example embodiments, the first structure ST1 may be a first chip structure including a memory cell, and the second structure ST2 may be a second chip structure including a peripheral circuit capable of operating the memory cell. The first structure ST1 and the second structure ST2 may be formed by bonding via a bonding process such as a wafer bonding process. Thus, the first structure ST1 may contact and bond to the second structure ST2.

[0014] The semiconductor device 1 may include a plurality of memory banks BA and a peripheral region PERI.

[0015] The peripheral region PERI may include a first peripheral region PERI1 in the first structure ST1 and a second peripheral region PERI2 in the second structure ST2. The peripheral region PERI may be a peripheral circuit region in which a peripheral circuit for input / output of data or commands or power / ground input is disposed.

[0016] Each of the plurality of memory banks BA may include a first memory bank region BA1 in a first structure ST1 and a second memory bank region BA2 in a second structure ST2 .

[0017] The first bank region BA1 in the first structure ST1 may include a block region CA and a connection region ER.

[0018] The storage block region CA may be arranged along a first direction (X direction) and a second direction (Y direction). The first direction (X direction) and the second direction (Y direction) may be perpendicular to each other. The connection region ER may be arranged on opposite (e.g., two) sides of each storage block region CA. For example, the storage block region CA and the connection region ER may be arranged alternately and repeatedly along the first direction (X direction). Among the storage block regions CA and the connection regions ER alternately and repeatedly arranged along the first direction (X direction), each storage block region CA may be arranged between a pair of connection regions ER adjacent in the first direction (X direction). The connection region ER may also be referred to as an extension region. The connection region ER may include a first edge connection region ERe1, a second edge connection region ERe2, and an intermediate connection region ER arranged between the first edge connection region ERe1 and the second edge connection region ERe2. Each storage block region CA may be arranged between a pair of adjacent connection regions ER among the connection regions ER.

[0019] The second memory body area BA2 in the second structure ST2 may include a peripheral circuit area PC. The peripheral circuit area PC may be arranged along a first direction (X direction) and a second direction (Y direction). The peripheral circuit area PC may overlap with the memory block area CA in a vertical direction (Z direction). Each peripheral circuit area PC may include a sense amplifier area SAR and a sub-word line driver area SWDR.

[0020] Next, refer to Figure 2A as well as Figure 1A and Figure 1B , the connection region ER may include a first connection region ER1 and a second connection region ER2 disposed on opposite (e.g., two) sides of one memory block region CA. The memory block region CA may include memory cells MC. The memory block region CA may include memory cells MC arranged along a first direction (X direction) and a second direction (Y direction), word lines WL connected to the memory cells MC and extending in the first direction (X direction), and bit lines BL connected to the memory cells MC and extending in the second direction (Y direction). The word lines WL may pass through the memory block region CA and may extend into the first connection region ER1 and the second connection region ER2.

[0021] Each memory cell MC may include a cell transistor cTR that may be used as a switch and a data storage structure DS that may be used as an information storage device. In a memory such as a DRAM, the data storage structure DS may be a cell capacitor that can store information.

[0022] Each memory block region CA may further include a back gate line BG. Each back gate line BG may be disposed between a pair of word lines WL adjacent to each other in the second direction (Y direction) among the word lines WL. Each back gate line BG may be disposed between the channel regions of the cell transistors cTR. The back gate line BG may pass through the memory block region CA and extend into the first connection region ER1 and the second connection region ER2.

[0023] Next, refer to Figure 2B as well as Figure 1A , Figure 1B and Figure 2A Each sub word line driver region SWDR may include a sub word line driver SWD. The sub word line driver SWD may be electrically connected to the word line WL.

[0024] The sub-word line driver SWD may include a PMOS transistor PT, a first NMOS transistor NT1, and a second NMOS transistor NT2. The drive signal PXID may be connected to the source terminal of the PMOS transistor PT, the word line WL may be electrically connected to the drain terminal of the PMOS transistor PT, and the word line enable signal NWEIB may be connected to the gate terminal of the PMOS transistor PT. The PMOS transistor PT may be a pull-up transistor. A precharge voltage corresponding to the reverse bias voltage VBB2 may be connected to the source terminal of the first NMOS transistor NT1, the word line WL may be electrically connected to the drain terminal of the first NMOS transistor NT1, and the word line enable signal NWEIB may be connected to the gate terminal of the first NMOS transistor NT1. The first NMOS transistor NT1 may be a pull-down transistor. The complementary drive signal PXIB may be connected to the gate terminal of the second NMOS transistor NT2, the precharge voltage corresponding to the reverse bias voltage VBB2 may be connected to the source terminal of the second NMOS transistor NT2, and the word line WL may be electrically connected to the drain terminal of the second NMOS transistor NT2. The second NMOS transistor NT2 may be a holding transistor for maintaining the word line WL at the level of the ground voltage when the word line WL is not selected. The second NMOS transistor NT2 may be connected in parallel with the first NMOS transistor NT1. The sub-word line driver SWD may drive the word line WL in response to the word line enable signal NWEIB and the drive signal PXID. The PMOS transistor PT may pull up the word line WL to the level of the drive signal PXID in response to the word line enable signal NWEIB. The first NMOS transistor NT1 may pull down the word line WL to the level of the negative voltage VBB2 in response to the word line enable signal NWEIB. When the word line WL is deactivated, the second NMOS transistor NT2, which may be a holding transistor, may maintain the word line WL at the level of the negative voltage VBB2. To this end, the second NMOS transistor NT2 may switch between a source provided with a negative voltage VBB2 and a drain electrically connected to the word line WL in response to a drive signal PXIB complementary to the drive signal PXID. The circuit of the sub word line driver SWD described above is an example embodiment, and the circuit of the sub word line driver SWD may be implemented in various circuit configurations.

[0025] Next, refer to Figure 2C as well as Figure 1A , Figure 1B , Figure 2A and Figure 2B, each sense amplifier region SAR may include a sense amplifier SA. The sense amplifier SA may include a plurality of transistors P1_a, P1_b, N1_a, and N1_b. The transistors P1_a, P1_b, N1_a, and N1_b may include a P1_a transistor and a P1_b transistor as PMOS transistors and an N1_a transistor and an N1_b transistor as NMOS transistors. The P1_a transistor and the P1_b transistor may be referred to as a pair of PMOS transistors, and the N1_a transistor and the N1_b transistor may be referred to as a pair of NMOS transistors. The source of the P1_a transistor and the source of the P1_b transistor may be connected to the first control line LA through a first node ND1_a. The source of the N1_a transistor and the source of the N1_b transistor may be connected to the second control line LAB through a second node ND1_b. The first node ND1_a and the second node ND1_b may be referred to as a first source node and a second source node, respectively. The drain of the P1_a transistor and the drain of the N1_a transistor can be connected to the first bit line BL1 among the bit lines BL through the first drain node ND1_c. The drain of the P1_b transistor and the drain of the N1_b transistor can be connected to the complementary bit line BL2 among the bit lines BL through the second drain node ND1_d. The sense amplifier SA can sense the voltage change of the first bit line BL1 and amplify the voltage change. When the sense amplifier SA performs the sensing and amplification operations, the internal power supply voltage can be applied to the first node ND1_a through the first control line LA, and the second node ND1_b can be connected to the ground terminal through the second control line LAB. The sense amplifier SA includes a pair of PMOS transistors and a pair of NMOS transistors, and is implemented in a cross-coupled circuit configuration between the transistors, but this is an example embodiment, and the embodiment is not limited thereto. For example, the circuit of the sense amplifier SA can be implemented in various circuit configurations.

[0026] Next, refer to Figure 3 , an electrical connection relationship between one memory block region CA among the memory block regions CA and a peripheral circuit region PC vertically overlapping with (eg, vertically overlapping with) the one memory block region CA will be described. Figure 3 2 is a diagram illustrating an electrical connection relationship between the first structure ST1 and the second structure ST2 described above.

[0027] refer to Figure 3 as well as Figures 1A to 2C ,like Figure 2A As described in the foregoing, the first connection region ER1 and the second connection region ER2 may be disposed on opposite (eg, two) sides of one memory block region CA. Therefore, the first structure ST1 may include the first connection region ER1, the memory block region CA, and the second connection region ER2 sequentially arranged along the first direction (X direction).

[0028] The first structure ST1 may include the above-mentioned memory cells MC, word lines WL, and bit lines BL. The memory cells MC may be disposed in the memory block region CA and may be sequentially arranged along the first direction (X direction). The word lines WL may pass through the memory block region CA and extend into the first connection region ER1 and the second connection region ER2. The word lines WL may be electrically connected to the memory cells MC. The bit lines BL may be electrically connected to the memory cells MC.

[0029] The second structure ST2 may include a peripheral circuit region PC having the above-described sub word line driver region SWDR and sense amplifier region SAR.

[0030] In the vertical direction (Z direction), at least a portion of the peripheral circuit region PC may overlap with the memory block region CA (e.g., the memory block region CA may overlap on at least a portion of the peripheral circuit region PC). According to example embodiments, a portion of the peripheral circuit region PC may vertically overlap with at least one of the first connection region ER1 and the second connection region ER2 (e.g., at least one of the first connection region ER1 and the second connection region ER2 may vertically overlap on a portion of the peripheral circuit region PC). As described above, the second structure ST2 may include a sub-word line driver SWD disposed in the sub-word line driver region SWDR and a sense amplifier SA disposed in the sense amplifier region SAR.

[0031] The first structure ST1 and the second structure ST2 may further include a word line signal path WSP electrically connecting the word line WL and the sub word line driver SWD.

[0032] The word line signal path WSP may include a wiring contact WC, a wiring interconnection line RL, and a lower wiring structure LRS, wherein the wiring contact WC is arranged in the connection region ER and connected to the word line WL, the wiring interconnection line RL is arranged at a height different from the word line WL and connected to the wiring contact WC, and the lower wiring structure LRS electrically connects the wiring interconnection line RL and the sub-word line driver SWD.

[0033] The routing interconnection line RL may cross the memory block area CA and extend into the first and second connection regions ER1 and ER2 .

[0034] A portion / region in which the lower wiring structure LRS and the wiring interconnection line RL are connected / coupled (eg, intersect and / or contact each other) may be disposed under the memory cell MC.

[0035] The wiring contact WC may include at least one first wiring contact WC1 connected to the word line WL in the first connection region ER1 and at least one second wiring contact WC2 connected to the word line WL in the second connection region ER2. In some embodiments, the at least one first wiring contact WC1 includes two or more first wiring contacts WC1 spaced apart from each other, and the at least one second wiring contact WC2 includes two or more second wiring contacts WC2 spaced apart from each other. The wiring contact WC may also be referred to as a word line contact or a gate contact.

[0036] The first structure ST1 may include an upper region of the lower wiring structure LRS, the wiring contacts WC, and the wiring interconnection lines RL, and the second structure ST2 may include a lower region of the lower wiring structure LRS.

[0037] The bit lines BL may cross the memory block area CA in one direction (eg, in the second direction (Y direction)) and intersect the word lines WL. The bit lines BL may be electrically connected to the memory cells MC.

[0038] The first structure ST1 and the second structure ST2 may further include a bit line signal path BSP electrically connecting the bit line BL and the sense amplifier SA in the sense amplifier region SAR. For example, the bit line signal path BSP may include a first bit line signal path BSP disposed between a first bit line BL electrically connected to one of the memory cells MC among the bit lines BL and the sense amplifier SA. The portion where the bit line signal path BSP is connected to the bit line BL may be disposed below the memory cell MC.

[0039] The first structure ST1 may include an upper region of the bit line signal path BSP, and the second structure ST2 may include a lower region of the bit line signal path BSP.

[0040] The sub word line driver SWD may be electrically connected to the word line WL through a word line signal path WSP. A voltage applied to the word line WL from the sub word line driver SWD may be applied to the word line WL in the memory block region CA through the first wiring contact WC1 of the first connection region ER1 and the second wiring contact WC2 of the second connection region ER2.

[0041] In an example embodiment, by providing the first connection region ER1 and the second connection region ER2 on opposite (e.g., both) sides of the memory block region CA, since a voltage can be applied to the word line WL in the memory block region CA, a resistance-capacitance delay (RC delay) can be reduced. For example, by providing the first connection region ER1 and the second connection region ER2, a voltage can be applied to the word line WL in the memory block region CA, so that the RC delay caused by the parasitic capacitance between the word lines WL adjacent to each other in the memory block region CA can be reduced. Therefore, the operating speed of the semiconductor device 1 can be improved.

[0042] Additionally, through the first and second connection regions ER1 and ER2 , a voltage may be applied to the word lines WL in the memory block region CA, and thus, a charge sharing time in the DRAM memory may be reduced, so that the performance of the semiconductor device 1 may be improved.

[0043] Additionally, even if a portion of the word line WL is cut off or a portion of the word line WL is thinned due to a trend of high integration as the width of the word line WL decreases, a voltage can be applied from opposite (e.g., both) sides of the word line WL through the first connection region ER1 and the second connection region ER2, and thus defects caused by the phenomenon that a portion of the word line WL is cut off or a portion of the word line WL is thinned can be reduced / prevented. That is, even if a portion of the word line WL is cut off or a portion of the word line WL is thinned, the word line WL can function normally.

[0044] Additionally, through the first connection region ER1 and the second connection region ER2, a voltage may be applied to the word line WL in the memory block region CA, thereby being able to reduce / minimize the time difference between the memory cell MC to which the word line voltage is applied the fastest and the memory cell MC to which the word line voltage is applied the most recently among the memory cells MC connected to the word line WL. Therefore, the operating speed and performance of the semiconductor device 1 may be improved.

[0045] Additionally, through the first connection region ER1 and the second connection region ER2, a voltage may be applied to the word line WL in the memory block region CA, thereby reducing the charge loss in the data storage structure DS that may function as a capacitor due to a phenomenon in which a voltage applied to the word line WL fluctuates (i.e., word line fluctuation (WL fluctuation) occurs). In this manner, the charge loss in the data storage structure DS may be reduced, thereby improving the performance of the semiconductor device 1.

[0046] Table 1:

[0047] In Table 1, the first sample, the second sample, the third sample, and the fourth sample may be samples according to example embodiments of the present disclosure.

[0048] The first sample can be from Figure 3 The word line signal path WSP omits the second wiring contact WC2 and is electrically connected to the sub word line driver SWD and the first reference sample of the word line WL through the first wiring contact WC1.

[0049] The second sample can be Figure 3The second reference sample is electrically connected to the sub word line driver SWD and the word line WL through the first wiring contact WC1 and the second wiring contact WC2 as illustrated.

[0050] The third sample and the fourth sample may be samples in which the driving capability of the sub-word line driver SWD is improved from the second sample. The third sample may be a sample in which the driving capability of the sub-word line driver SWD is improved by m times from the second sample, and the fourth sample may be a sample in which the driving capability of the sub-word line driver SWD is improved by n times from the second sample. For example, the third sample may have a sub-word line driver having a driving capability that is approximately 4 times that of the sub-word line driver SWD of the second sample, and the fourth sample may have a sub-word line driver (SWD) having a driving capability that is approximately 8 times that of the sub-word line driver (SWD) of the second sample.

[0051] In Table 1 above, B millivolt (mV) may be less than A mV. For example, B mV may be 40% to about 60% of A mV. C mV may be less than B mV. D mV may be less than C mV. E % may be less than F %. For example, E % may be 1 / 2 to 1 / 5 of F %. F % may be less than E %. For example, E % may be 1 / 2 to 1 / 8 of F %. G % may be less than H %.

[0052] From Table 1 above, in terms of word line fluctuation, it can be seen that the word line fluctuation becomes smaller (eg, decreases) in the order of the first sample, the second sample, the third sample, and the fourth sample.

[0053] In terms of word line fluctuation, it can be seen that the performance of the semiconductor device of the second sample is improved compared to that of the semiconductor device of the first sample. Therefore, it can be seen that the performance of the semiconductor device of the second sample in which the sub word line driver SWD and the word line WL are electrically connected through the first wiring contact WC1 and the second wiring contact WC2 can be further improved compared to the performance of the semiconductor device of the first sample in which the second wiring contact WC2 is omitted from the word line signal path WSP and the sub word line driver SWD and the word line WL are electrically connected through the first wiring contact WC1.

[0054] In terms of word line fluctuation, like the third and fourth samples, it can be seen that the performance of the semiconductor device improves as the driving capability of the sub word line driver SWD increases.

[0055] In terms of charge loss of the data storage structure DS, it can be seen that the performance of the semiconductor device of the second sample is improved compared to the performance of the semiconductor device of the first sample.

[0056] In terms of the charge loss of the data storage structure DS, like the third and fourth samples, it can be seen that the performance of the semiconductor device is improved as the driving capability of the sub word line driver SWD is improved.

[0057] Next, we will refer to Figure 4 , Figure 5A , Figure 5B and Figure 5C The planar shape and the cross-sectional shape of the above-mentioned semiconductor device 1 are described. Figure 4 It is schematically shown Figure 3 A plan view of the first connection region ER1, the storage block region CA, and the second connection region ER2 in FIG. Figure 5A It is a diagram showing the Figure 4 A cross-sectional view of the region cut by lines II-I' and II-II', Figure 5B Is Figure 5A The area indicated by “A” is a partial enlarged view, and Figure 5C Is Figure 5A A partial enlarged view of the area indicated by "B".

[0058] refer to Figures 1A to 3 as well as Figure 4 , Figure 5A , Figure 5B and Figure 5C , the first structure ST1 may further include an active pattern ACTc. The active pattern ACTc may include a material that can be used as a channel of a transistor, such as a semiconductor material. For example, each active pattern ACTc may include at least one of a silicon layer, an oxide semiconductor layer, and a two-dimensional material layer having semiconductor properties, which may be used as a channel region of a transistor. For example, each active pattern ACTc may include single crystal silicon or polycrystalline silicon. The active patterns ACTc may be arranged along a first direction (X direction) and a second direction (Y direction). Each active pattern ACTc may be in the shape of a strip extending in the first direction (X direction).

[0059] Each active pattern ACTc may include a first source / drain region SDc1 , a second source / drain region SDc2 disposed at a higher level than the first source / drain region SDc1 , and a channel region CHc located in the vertical direction Z between the first and second source / drain regions SDc1 and SDc2 .

[0060] Each cell transistor cTR may include a first source / drain region SDc1, a second source / drain region SDc2 disposed at a height higher than the first source / drain region SDc1, a channel region CHc between the first source / drain region SDc1 and the second source / drain region SDc2, a gate dielectric layer GOc in contact with a side surface of the channel region CHc, and a word line WL in contact with the gate dielectric layer GOc. In the word line WL, a portion facing the channel region CHc (and / or in contact with the gate dielectric layer GOc) may be a gate electrode. The vertical length of each word line WL may be greater than its width in the second direction (Y direction). Here, the vertical length may be the length from the lower surface to the upper surface of the word line WL. The word line WL may have a side surface facing the side surface of the active pattern ACTc.

[0061] In such Figure 4 In the illustrated plane, the word line WL may include a first word line WL1 and a second word line WL2 adjacent to each other in the second direction (Y direction), the active pattern ACTc may include a first active pattern ACTc1 adjacent to the first word line WL1 and a second active pattern ACTc2 adjacent to the second word line WL2 between the first word line WL1 and the second word line WL2, and the back gate line BG (see Figure 4 , Figure 5A and Figure 5B ) may include a first back gate line BG1 disposed between the first word line WL1 and the second word line WL2 and passing between the first active pattern ACTc1 and the second active pattern ACTc2. The back gate line BG may be a back gate electrode.

[0062] The first structure ST1 may include a back gate dielectric layer BGO between the back gate line BG and the active pattern ACTc. The back gate line BG may have a side surface facing a side surface of the channel region CHc of the active pattern ACTc. Each active pattern ACTc may be disposed between one word line WL and one back gate line BG adjacent to each other.

[0063] The back gate line BG may control the charges accumulated in the channel region CHc. The channel region CHc may be a floating body disposed between the first source / drain region SDc1 and the second source / drain region SDc2, and the back gate line BG may suppress or prevent the performance of the cell transistor cTR from being degraded due to the floating body effect, thereby improving the performance of the cell transistor cTR. For example, during the operation of the cell transistor cTR, the back gate line BG may minimize or prevent the threshold voltage variation of the cell transistor cTR by accumulating charges (e.g., holes) in the floating body of the channel region CHc.

[0064] The word line WL may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but the disclosure is not limited thereto. Each word line WL may include a single layer or multiple layers of the above-mentioned conductive materials. The back gate line BG may include at least one conductive material. For example, each back gate line BG may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but the disclosure is not limited thereto. Each back gate line BG may include a single layer or multiple layers of the above-mentioned materials.

[0065] The first structure ST1 may further include contact structures 127 connected to the second source / drain region SDc2. Each of the contact structures 127 may include a plug portion 115 contacting the active pattern ACTc and a pad portion 125 on the plug portion 115.

[0066] The data storage structure DS may include first electrodes 130 disposed on the pad portion 125 and extending in a vertical direction (Z direction), second electrodes 140 located on side surfaces and an upper surface of each first electrode 130, and a dielectric layer 135 located between the first electrodes 130 and the second electrodes 140. The data storage structure DS may be a capacitor capable of storing information.

[0067] The first electrode 130 may be connected to the pad portion 125 of the contact structure 127. The first electrode 130 may be electrically connected to the second source / drain region SDc2 through the contact structure 127. Thus, the cell transistor cTR may be electrically connected to the data storage structure DS through the contact structure 127.

[0068] The data storage structure DS may be a unit capacitor capable of storing information in a memory such as a DRAM, but example embodiments are not limited thereto. For example, the data storage structure DS may be an information storage structure of an MRAM or an information storage structure of a FeRAM.

[0069] The bit line BL may be connected to the active pattern ACTc under the active pattern ACTc. For example, the bit line BL may be electrically connected to the first source / drain region SDc1 of the active pattern ACTc. Thus, the bit line BL may be electrically connected to the cell transistor cTR.

[0070] The first structure ST1 may further include a shielding conductive structure BS including line portions BS_L alternately arranged with the bit lines BL and connection portions BS_C connecting the line portions BS_L. The shielding conductive structure BS may shield the capacitive coupling between the bit lines BL. For example, the shielding conductive structure BS may reduce or block the parasitic capacitance between the bit lines BL, thereby reducing / minimizing the resistance-capacitance delay RC of the bit lines BL.

[0071] The first structure ST1 may include a first insulating structure 150, a second insulating structure 105 on the first insulating structure 150, a third insulating layer 110 on the second insulating structure 105, a fourth insulating layer 120 on the third insulating layer 110, and an upper insulating structure 145 on the fourth insulating layer 120. The bit line BL may be disposed in the first insulating structure 150. A structure including an active pattern ACTc, a word line WL, a back gate line BG, a gate dielectric layer GOc, and a back gate dielectric layer BGO may penetrate the second insulating structure 105. The contact structure 127 may penetrate the third insulating layer 110 and the fourth insulating layer 120. The upper insulating structure 145 may be disposed on the fourth insulating layer 120 and the data storage structure DS.

[0072] The first structure ST1 may include conductive structures WC, RL, 160w, 170w, 170b, and 162b disposed under the word lines WL and the bit lines BL.

[0073] The conductive structure may include a wiring contact WC arranged below the word line WL and in the connection region ER, a wiring interconnection line RL connected to the wiring contact WC and arranged at a height lower than the bit line BL, a word line under-interconnection structure 160w electrically connected to the wiring interconnection line RL below the wiring interconnection line RL, a bit line under-interconnection structure 162b electrically connected to the bit line BL below the bit line BL, and first bonding pads 170w and 170b connected to the word line under-interconnection structure 160w and the bit line under-interconnection structure 162b.

[0074] The word line interconnect structure 160w may include horizontal portions 160wH disposed at different heights and vertical portions 160wV connected to the horizontal portions 160wH. Here, the horizontal portions 160wH may be interconnect lines or pads, and the vertical portions 160wV may be conductive paths. The bit line interconnect structure 162b may include horizontal portions 162bH disposed at different heights and vertical portions 162bV connected to the horizontal portions 162bH. Here, the horizontal portions 162wH may be interconnect lines or pads, and the vertical portions 162bV may be conductive paths.

[0075] The first bonding pads 170w and 170b may have a lower surface coplanar with a lower surface of the first insulating structure 150. The first bonding pads 170w and 170b may include a first wordline bonding pad 170w connected to a wordline under interconnection structure 160w and a first bitline bonding pad 170b connected to a bitline under interconnection structure 162b.

[0076] The second structure ST2 may further include a substrate 3 and a device isolation region 6 defining an active region 9 on the substrate 3. The substrate 3 may be a semiconductor substrate. The second structure ST2 may further include a peripheral transistor PTR disposed on the substrate 3 and peripheral interconnect structures 15w and 15b.

[0077] The peripheral transistor PTR may include transistors PT, NT1, and NT2 of the sub-word line driver SWD (see Figure 2B ) and transistors P1_a, P1_b, N1_a and N1_b of the sense amplifier SA (see Figure 2C ).

[0078] In an exemplary embodiment, transistors PT, NT1, and NT2 (see Figure 2B ) may be provided in the sub word line driver region SWDR, and the transistors P1_a, P1_b, N1_a, and N1_b of the sense amplifier SA (see Figure 2C ) may be disposed in the sense amplifier region SAR. As an example, in the drawings, the peripheral transistor PTR is illustrated as a first peripheral transistor TR1 and a second peripheral transistor TR2, the first peripheral transistor TR1 may be the transistors PT, NT1 and NT2 of the sub-word line driver SWD (see Figure 2B ), the second peripheral transistor TR2 may be one of the transistors P1_a, P1_b, N1_a and N1_b of the sense amplifier SA (see Figure 2C )one.

[0079] The first peripheral transistor TR1 may include a first peripheral gate structure GE1 and GO1 disposed on the active region 9 disposed in the sub word line driver region SWDR, and a first peripheral source / drain region SD1 disposed in the active region 9 disposed on opposite (e.g., both) sides of the first peripheral gate structures GE1 and GO1. The first peripheral gate structures GE1 and GO1 may include a first peripheral gate dielectric layer GO1 and a first peripheral gate electrode GE1 stacked sequentially. The second peripheral transistor TR2 may include a second peripheral gate structure GE2 and GO2 disposed on the active region 9 disposed in the sense amplifier region SAR, and a second peripheral source / drain region SD2 disposed in the active region 9 disposed on opposite (e.g., both sides) of the second gate structures GE2 and GO2. The second peripheral gate structures GE2 and GO2 may include a second peripheral gate dielectric layer GO2 and a second peripheral gate electrode GE2 stacked sequentially.

[0080] The peripheral interconnect structures 15w and 15b may include a word line peripheral interconnect structure 15w and a bit line peripheral interconnect structure 15b.

[0081] The word line peripheral interconnect structure 15w may include horizontal portions 15wH disposed at different heights and vertical portions 15wV connected to the horizontal portions 15wH. Here, the horizontal portions 15wH may be interconnects or pads, and the vertical portions 15wV may be conductive paths. The bit line peripheral interconnect structure 15b may include horizontal portions 15bH disposed at different heights and vertical portions 15bV connected to the horizontal portions 15bH. Here, the horizontal portions 15wH may be interconnects or pads, and the vertical portions 15bV may be conductive paths.

[0082] The number of horizontal portions 15wH of the wordline peripheral interconnect structure 15w may be greater than the number of horizontal portions 160wH of the wordline under-interconnect structure 160w. The number of horizontal portions 15bH of the bitline peripheral interconnect structure 15b may be greater than the number of horizontal portions 162bH of the bitline under-interconnect structure 162b. The number of horizontal portions 115wH of the wordline peripheral interconnect structure 15w may be the same as the number of horizontal portions 15bH of the bitline peripheral interconnect structure 15b.

[0083] The second structure ST2 may include a lower insulating structure 20 disposed on the substrate 3 and covering the peripheral transistor PTR and the peripheral interconnect structures 15w and 15b, and second bonding pads 25w and 25b having upper surfaces coplanar with the upper surface of the lower insulating structure 20. The second bonding pads 25w and 25b may include a second word line bonding pad 25w connected to the word line peripheral interconnect structure 15w and a second bit line bonding pad 25b connected to the bit line peripheral interconnect structure 15b.

[0084] The first bonding pads 170w and 170b and the second bonding pads 25w and 25b may include the same metal material that may be bonded to each other. For example, the first bonding pads 170w and 170b and the second bonding pads 25w and 25b may include copper.

[0085] The lower surfaces of the first bonding pads 170w and 170b may be in direct contact with and bonded to the upper surfaces of the second bonding pads 25w and 25b, and the lower surface of the first insulating structure 150 may be in direct contact with and bonded to the upper surface of the lower insulating structure 20. The upper surface of the second word line bonding pad 25w may be in contact with and bonded to the upper surface of the first word line bonding pad 170w, and the upper surface of the second bit line bonding pad 25b may be in contact with and bonded to the lower surface of the first bit line bonding pad 170b.

[0086] like Figure 3 As depicted in FIG. 1 , the first structure ST1 and the second structure ST2 may include a word line signal path WSP and a bit line signal path BSP.

[0087] Hereinafter, the description will focus on one word line WL, one word line signal path WSP, and one bit line signal path BSP.

[0088] The bit line signal path BSP connected to the bit line BL may include a first bit line interconnect structure BSP_U disposed in the first structure ST1 and a second bit line interconnect structure BSP_L disposed in the second structure ST2. The first bit line interconnect structure BSP_U may include a bit line lower interconnect structure 162b and a first bit line bonding pad 170b. The first bit line interconnect structure BSP_U may include a bit line peripheral interconnect structure 15b and a second bit line bonding pad 25b.

[0089] The word line signal path WSP connected to the word line WL may include a wiring contact WC, a wiring interconnection line RL, and a lower wiring structure LRS.

[0090] The wiring contact WC may be in contact with the word line WL below the word line WL and connected to the word line WL. The word line WL may be set at a height higher than the bit line BL, and the upper surface of the wiring contact WC may be set at a height higher than the bit line BL and may be in contact with the lower surface of the word line WL. The lower surface of the wiring contact WC may be set at a height lower than the bit line BL. The wiring contact WC may include at least one first wiring contact WC1 connected to the word line WL in the first connection region ER1 and at least one second wiring contact WC2 connected to the word line WL in the second connection region ER2.

[0091] The wiring interconnection line RL may be in the shape of a line that crosses the memory block area CA in the first direction X and extends into the first connection area ER1 and the second connection area ER2. The wiring interconnection line RL may overlap vertically with the word line WL (for example, the word line WL may overlap vertically on the wiring interconnection line RL). The wiring interconnection line RL may be set at a height lower than the bit line BL. In the memory block area CA, the wiring interconnection line RL may overlap vertically with the memory cell MC (for example, the memory cell MC may overlap vertically on the wiring interconnection line RL). The wiring interconnection line RL may contact at least one first wiring contact WC1 and at least one second wiring contact WC2 at the same time and be connected to at least one first wiring contact WC1 and at least one second wiring contact WC2. For example, a first portion of the wiring interconnection line RL may be adjacent to at least one first wiring contact WC1, a second portion of the wiring interconnection line RL may be adjacent to at least one second wiring contact WC2, and the wiring interconnection line RL may extend continuously from the first portion to the second portion. The upper surface of the wiring interconnection line RL may contact at least one first wiring contact WC1 and at least one second wiring contact WC2.

[0092] The lower wiring structure LRS may include an upper structure LRS_U disposed in the first structure ST1 and a lower structure LRS_L disposed in the second structure ST2. The upper structure LRS_U may include a wordline under-interconnection structure 160w and a first wordline bonding pad 170w. The lower structure LRS_L may include a wordline peripheral interconnection structure 15w and a second wordline bonding pad 25w.

[0093] The first peripheral transistor TR1 of the sub word line driver SWD can be electrically connected to the word line WL through the word line signal path WSP. The voltage applied from the sub word line driver SWD can be applied to the word line WL in the memory block area CA through the first wiring contact WC1 of the first connection area ER1 and the second wiring contact WC2 of the second connection area ER2.

[0094] Next, we will refer to Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Figure 8 Illustrative examples of semiconductor devices according to example embodiments of the present disclosure are described. Figure 6 1 is a top view illustrating a shape in which the memory block regions CA are arranged in various forms along the first direction (X direction) and the word lines WL are arranged in various forms, Fig. 7A It's a picture. Figure 6 A conceptual cross-sectional view of the electrical connection relationship of the first word line WL1 among the word lines WL in FIG. Figure 7B It's a picture. Figure 6A conceptual cross-sectional view of the electrical connection relationship of the second word line WL2 among the word lines WL in FIG. Figure 7C It's a picture. Figure 6 A conceptual cross-sectional view of the electrical connection relationship of the third word line WL3 among the word lines WL in FIG. Fig.7D It's a picture. Figure 6 A conceptual cross-sectional diagram of the electrical connection relationship of the fourth word line WL4 among the word lines WL in FIG. 1 , and Figure 8 is a schematic perspective view illustrating the relationship between the wiring interconnection lines RL, the wiring contacts WC, and the word lines WL.

[0095] refer to Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Figure 8 as well as Figures 1A to 5B , the storage block area CA includes a first storage block area CA1, a second storage block area CA2, a third storage block area CA3, and a fourth storage block area CA4 sequentially arranged along a first direction (X direction). The connection area ER may include a first connection area ER1, a second connection area ER2, a third connection area ER3, a fourth connection area ER4, and a fifth connection area ER5 sequentially arranged along the first direction (X direction). The first storage block area CA1 may be arranged between the first connection area ER1 and the second connection area ER2. The second storage block area CA2 may be arranged between the second connection area ER2 and the third connection area ER3. The third storage block area CA3 may be arranged between the third connection area ER3 and the fourth connection area ER4. The fourth storage block area CA4 may be arranged between the fourth connection area ER4 and the fifth connection area ER5.

[0096] In an example, the word line WL may cross the memory block region CA and the intermediate connection region ER between the first edge connection region ERe1 and the second edge connection region ERe2 , and may extend into the first edge connection region ERe1 and the second edge connection region ERe2 .

[0097] The word lines WL may include first, second, third, and fourth word lines WL1, WL2, WL3, and WL4 sequentially arranged in the second direction (Y direction). The first and third word lines WL1 and WL3 may be odd word lines, and the second and fourth word lines WL2 and WL4 may be even word lines.

[0098] In one example, each word line WL may continuously and seamlessly cross the first to fourth memory block regions CA1, CA2, CA3, and CA4 and the first to fifth connection regions ER1, ER2, ER3, ER4, and ER5. For example, the first word line WL may continuously and seamlessly cross the first to fourth memory block regions CA1, CA2, CA3, and CA4 and the first to fifth connection regions ER1, ER2, ER3, ER4, and ER5.

[0099] A memory cell group MCG may be disposed in each memory block area CA. Each memory cell group MCG may include memory cells MC regularly arranged along a first direction (X direction). Each memory cell group MCG may include memory cells MC arranged at regular intervals along a first direction (X direction).

[0100] The memory cell group MCG may include a first memory cell group MCG1 connected to the first word line WL1, a second memory cell group MCG2 connected to the second word line WL2, a third memory cell group MCG3 connected to the third word line WL3, and a fourth memory cell group MG4 connected to the fourth word line WL4.

[0101] The peripheral circuit region PC may include a first peripheral circuit region PC1 , a second peripheral circuit region PC2 , a third peripheral circuit region PC3 , and a fourth peripheral circuit region PC4 sequentially arranged along the first direction (X direction).

[0102] The first peripheral circuit region PC1 may vertically overlap the first storage block region CA1, the second peripheral circuit region PC2 may vertically overlap the second storage block region CA2, the third peripheral circuit region PC3 may vertically overlap the third storage block region CA3, and the fourth peripheral circuit region PC4 may vertically overlap the fourth storage block region CA4.

[0103] As described above, each peripheral circuit region PC may include the sub word line driver region SWDR and the sense amplifier region SAR.

[0104] The sense amplifier region SAR may include sense amplifiers SA.

[0105] The odd word lines WL1 and WL3 and the odd sub-word line drivers SWD1 and SDW3 electrically connected through the word line signal path WSP may be disposed in the first peripheral circuit region PC1 and the third peripheral circuit region PC3, and the even word lines WL2 and WL4 and the even sub-word line drivers SWD2 and SDW4 electrically connected through the word line signal path WSP may be disposed in the second peripheral circuit region PC2 and the fourth peripheral circuit region PC4. For example, the first sub-word line driver SWD1 disposed in the first peripheral circuit region PC1 and the third peripheral circuit region PC3 may be electrically connected to the first word line WL1 through the word line signal path WSP, and the third sub-word line driver SWD3 disposed in the first peripheral circuit region PC1 and the third peripheral circuit region PC3 may be electrically connected to the third word line WL3 through the word line signal path WSP. The second sub-word line driver SWD2 set in the second peripheral circuit area PC2 and the fourth peripheral circuit area PC4 can be electrically connected to the second word line WL2 through the word line signal path WSP, and the fourth sub-word line driver SWD4 set in the second peripheral circuit area PC2 and the fourth peripheral circuit area PC4 can be electrically connected to the fourth word line WL4 through the word line signal path WSP.

[0106] In one example, in each word line signal path WSP, a wiring contact WC disposed in each connection region ER and connected to a word line may be provided in a plurality of forms. For example, in the second connection region ER2 between the first memory block region CA1 and the second memory block region CA2, the first word line WL1 may be in contact with and connected to a plurality of wiring contacts WC.

[0107] The wiring interconnection lines RL of the word line signal path WSP may include a first wiring interconnection line RL1 electrically connected to the first word line WL1 and the wiring contact WC, a second wiring interconnection line RL1 electrically connected to the second word line WL2 and the wiring contact WC, a third wiring interconnection line RL3 electrically connected to the third word line WL3 and the wiring contact WC, and a fourth wiring interconnection line RL4 electrically connected to the fourth word line WL4 and the wiring contact WC. The wiring interconnection lines RL may vertically overlap the word lines WL (e.g., the word lines WL may vertically overlap on the wiring interconnection lines RL).

[0108] In one example, each wiring interconnection line RL may continuously and seamlessly cross the first to fourth memory block regions CA1, CA2, CA3, and CA4 and the first to fifth connection regions ER1, ER2, ER3, ER4, and ER5. For example, the first wiring interconnection line RL1 may continuously and seamlessly cross the first to fourth memory block regions CA1, CA2, CA3, and CA4 and the first to fifth connection regions ER1, ER2, ER3, ER4, and ER5.

[0109] Next, refer to Fig.9A and Fig. 9B , we will now describe Figures 6 to 7D The cross-sectional structure of the first connection region ER1, the first storage block region CA1, the second connection region ER2, the second storage block region CA2 and the third connection region ER3 sequentially arranged along the first direction (X direction) and the cross-sectional structure of the first peripheral circuit region PC1 and the second peripheral circuit region PC2 sequentially arranged along the first direction (X direction) are described in the. Fig.9A and Fig. 9B middle, Fig.9A So Fig. 7A A cross-sectional view centered on the first word line WL1, and Fig. 9B So Figure 7B A cross-sectional view centered on the second word line WL2.

[0110] refer to Fig.9A and Fig. 9B as well as FIG. 1A to FIG. 7D In addition to the word line signal path WSP, the cross-sectional structure of the first memory block region CA1 and the first peripheral circuit region PC1 may also be the same as that along Figure 5A The cross-sectional structure taken along the line II' in FIG. 1 is the same as that taken along the line II' in FIG. 1 , and except for the word line signal path WSP, the cross-sectional structure of the second memory block region CA2 and the second peripheral circuit region PC2 may also be the same as that taken along the line II' in FIG. 1 . Figure 5A The cross-sectional structure taken along line II' is the same.

[0111] like Fig. 7A The illustrated first sub word line driver SWD1 may be disposed in the sub word line driver region SWDR of the first peripheral circuit region PC1, and as shown in FIG. Figure 7B The illustrated second sub word line driver SWD2 may be provided in the sub word line driver region SWDR of the second peripheral circuit region PC2 .

[0112] The first sub-word line driver SWD1 may vertically overlap with the first storage block region CA1 (e.g., the first storage block region CA1 may vertically overlap on the first sub-word line driver SWD1). For example, the first sub-word line driver SWD1 may vertically overlap with the data storage structure DS of the first storage block region CA1 (e.g., the data storage structure DS of the first storage block region CA1 may vertically overlap on the first sub-word line driver SWD1). The second sub-word line driver SWD2 may vertically overlap with the second storage block region CA2 (e.g., the second storage block region CA2 may vertically overlap on the second sub-word line driver SWD2). For example, the second sub-word line driver SWD2 may vertically overlap with the data storage structure DS of the second storage block region CA2 (e.g., the data storage structure DS of the second storage block region CA2 may vertically overlap on the second sub-word line driver SWD2).

[0113] Each of the first sub word line driver SWD1 and the second sub word line driver SWD2 may include Figure 2B Transistors PT, NT1 and NT2 are described.

[0114] The transistors PT, NT1 and NT2 (see Figure 2B ) may be disposed in the sub word line driver region SWDR of the first peripheral circuit region PC1 and may serve as transistors PT, NT1, and NT2 of the second sub word line driver SWD2 (see Figure 2B ) may be disposed in the sub word line driver region SWDR of the second peripheral circuit region PC2. The first peripheral transistor TR1 may vertically overlap the data storage structure DS of the first memory block region CA1 (e.g., the data storage structure DS of the first memory block region CA1 may vertically overlap on the first peripheral transistor TR1). The second peripheral transistor TR1a may vertically overlap the data storage structure DS of the second memory block region CA2 (e.g., the data storage structure DS of the second memory block region CA2 may vertically overlap on the second peripheral transistor TR1a).

[0115] The lower wiring structure LRS may contact and be connected to the first wiring interconnection line RL1 in the first memory block region CA1 in a word line signal path WSP electrically connecting the first word line WL1 and the first peripheral transistor TR1 .

[0116] The lower wiring structure LRS may contact and be connected to the second wiring interconnection line RL2 in the second memory block region CA2 in the word line signal path WSP electrically connecting the second word line WL2 and the second peripheral transistor TR1a.

[0117] Various modifications of the elements of the above-described example embodiments will be described. The various modifications of the elements of the above-described embodiments described below will be described focusing on the modified or replaced elements. Here, the above-described elements may be directly referenced without separate detailed description, or the description may be omitted. In addition, the following elements that may be modified or replaced are described below with reference to the accompanying drawings, but the elements that may be modified or replaced may be combined with each other or with the above-described elements to form a semiconductor device according to an example embodiment of the present disclosure.

[0118] Next, we will refer to Fig.10 , Fig.11A and Fig. 11B An example of a semiconductor device according to an example embodiment of the present disclosure is described. Fig.10 It's a picture. Figure 8 A perspective view of a modified example of the odd-numbered wiring interconnections RL1 and RL3 and the even-numbered wiring interconnections RL2 and RL4 described in FIG. Fig.11A It's a picture. Fig.9A is a cross-sectional view of a modified example of the first wiring interconnection line RL1, and Fig. 11B It's a picture. Fig. 9B FIG. 1 is a cross-sectional view of a modified example of the second wiring interconnection line RL2.

[0119] refer to Fig.10 , Fig.11A and Fig. 11B , Figure 8 The odd-numbered wiring interconnections RL1 and RL3 described in may be replaced with odd-numbered wiring interconnections RL1a and RL3a separated from the second connection region ER2 and the fourth connection region ER4 in the first direction (X direction).

[0120] Figure 8 The first wiring interconnect lines RL1 in the first direction (X direction) may be replaced with first wiring interconnect lines RL1a that are separated and spaced apart from each other in the first direction (X direction). One of the first wiring interconnect lines RL1a arranged along the first direction (X direction) may continuously cross the second storage block region CA2, the third connection region ER3, and the third storage block region CA3, and may extend into the second connection region ER2 and the fourth connection region ER4. Fig.9A The first wiring interconnections RL1 in the second connection region ER2 may be replaced with first wiring interconnections RL1a separated and spaced apart from each other in the second connection region ER2.

[0121] Figure 8 The second wiring interconnect lines RL2 in the first direction (X direction) may be replaced with second wiring interconnect lines RL2a that are separated and spaced apart from each other in the first direction (X direction). One of the second wiring interconnect lines RL2a arranged along the first direction (X direction) may continuously cross the first storage block region CA1, the second connection region ER2, and the second storage block region CA2, and may extend into the first connection region ER1 and the third connection region ER3. Fig. 9B The second wiring interconnection line RL2 in FIG. 1 may be replaced with a second wiring interconnection line RL2a separated from the first connection region ER1 and the third connection region ER3.

[0122] Next, we will refer to Fig. 12A , Fig. 12B and Fig. 12C An example of a semiconductor device according to an example embodiment of the present disclosure is described. Fig. 12A It's a picture. Fig.10 A perspective view of a modified example of the odd word lines WL1 and WL3 and the even word lines WL2 and WL4 in FIG. Fig. 12B It's a picture. Fig.11A is a cross-sectional view of a modified example of the first word line WL1, and Fig. 12C It's a picture. Fig. 11B 2 is a cross-sectional view of a modified example of the second word line WL2.

[0123] refer to Fig. 12A , Fig. 12B and Fig. 12C , Fig.10 The odd word lines WL1 and WL3 and the even word lines WL2 and WL4 in the connection region ER may be replaced with the odd word lines WL1a and WL3a and the even word lines WL2a and WL4a separated and spaced apart from each other in the connection region ER. Fig.10 and Fig.11A The first word lines WL1 in the connection region ER may be replaced with first word lines WL1a that are separated and spaced apart from each other in the connection region ER and sequentially arranged along the first direction (X direction), and Fig.10 and Fig. 11B The second word lines WL2 in FIG. 4 may be replaced with second word lines WL2 a that are separated and spaced apart from each other in the connection region ER and sequentially arranged along the first direction (X direction).

[0124] Next, refer to Fig.13 , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig.13 It's a picture. Fig.10 2 is a perspective view of a modified example of the odd word lines WL1 and WL3 and the even word lines WL2 and WL4 in FIG.

[0125] refer to Fig.13 , Fig.10 The odd word line WL1 in may be replaced with an odd word line WL1b divided at the same position as the odd wiring interconnect line RL1a, the odd word line WL3 may be replaced with an odd word line WL3b divided at the same position as the odd wiring interconnect line RL3a, and Fig.10 The even wordline WL2 in may be replaced with an even wordline WL2b divided at the same position as the even wiring interconnection line RL2a, and the even wordline WL4 may be replaced with an even wordline WL4b divided at the same position as the even wiring interconnection line RL4a.

[0126] Fig.10 The first word lines WL1 in the first direction (X direction) may be replaced with first word lines WL1b that are separated and spaced apart from each other in the first direction (X direction). One of the first word lines WL1b arranged along the first direction (X direction) may continuously cross the second storage block region CA2, the third connection region ER3, and the third storage block region CA3, and may extend into the second connection region ER2 and the fourth connection region ER4. The first word lines WL1b arranged along the first direction (X direction) may be separated and spaced apart from each other in the even connection regions ER2 and ER4.

[0127] Fig.10 The second word lines WL2 in the first direction (X direction) may be replaced with second word lines WL2b separated and spaced apart from each other in the first direction (X direction). One of the second word lines WL2b arranged along the first direction (X direction) may continuously cross the first storage block region CA1, the second connection region ER2, and the second storage block region CA2, and may extend into the first connection region ER1 and the third connection region ER3. The second word lines WL2b arranged along the first direction (X direction) may be separated and spaced apart from each other in the odd connection regions ER1 and ER3.

[0128] Next, refer to Fig.14 and Fig.15 , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig.14 It's a picture. 7A to 7D A conceptual cross-sectional view of a modified example of the wiring contact WC in FIG. Fig.15 It's a picture. Fig.9A sectional view of a modified example of the wiring contact WC in FIG.

[0129] refer to Fig.14 and Fig.15 In each connection region ER, a plurality of wiring contacts WC may be disposed on one word line WL, but example embodiments are not limited thereto. Fig.14 and Fig.15In each connection region ER, one wiring contact WCs may be set on one word line WL. Therefore, the first word line WL1 crossing the first storage block region CA1, the second connection region ER2, and the second storage block region CA2 may contact and be connected to one wiring contact WCs in the first connection region ER1, may contact and be connected to one wiring contact WCs in the second connection region ER2, and may contact and be connected to one wiring contact WCs in the third connection region ER3.

[0130] Next, refer to Fig.16 and Fig.17 , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig.16 It's a picture. Figure 3 A conceptual cross-sectional view of a modified example of a sub-word line driver SWD and a word line signal path WSP in FIG. 1 , and Fig.17 It's a picture. Figure 5A A conceptual cross-sectional view of a modified example of a sub word line driver SWD and a word line signal path WSP in a cross-sectional structure taken along line II′.

[0131] refer to Fig.16 and Fig.17 , Figure 3 The sub-word line driver (SWD) described in the above may be replaced with a plurality of sub-word line drivers SWDa and SWDb, which are electrically connected to a word line WL crossing the memory block region CA in a sub-word line driver region SWDR of a peripheral circuit region PC vertically overlapping with (e.g., a memory block region CA vertically overlaps thereon). For example, in order to improve the driving capability of the sub-word line driver, a plurality of sub-word line drivers SWDa and SWDb may be electrically connected to a word line WL. For example, the plurality of sub-word line drivers SWDa and SWDb may include a first sub-word line driver SWDa and a second sub-word line driver SWDb electrically connected to a word line WL. The first sub-word line driver SWDa and the second sub-word line driver SWDb may be adjacent to each other or may be spaced apart from each other.

[0132] Each of the first sub-word line driver SWDa and the second sub-word line driver SWDb may include Figure 2B The transistors PT, NT1 and NT2 are described. Therefore, Figure 5A The described peripheral transistor PTR may include transistors PT, NT1, and NT2 each of which may function as a first sub-word line driver SWD (see Figure 2B). The first peripheral transistor TR1 and the second peripheral transistor TRb may vertically overlap the memory block area CA (e.g., the memory block area CA may vertically overlap the first peripheral transistor TR1 and the second peripheral transistor TRb). The first peripheral transistor TR1 and the second peripheral transistor TRb may vertically overlap the data storage structure DS (e.g., the data storage structure DS may vertically overlap the first peripheral transistor TR1 and the second peripheral transistor TRb).

[0133] In a word line signal path WSP electrically connecting a plurality of sub word line drivers SWDa and SWDb with one word line WL, a wiring interconnection line RL may be divided into a first wiring interconnection line RLa connected to a first wiring contact WC1 in a first connection region ER1 and a second wiring interconnection line RLb connected to a second wiring contact WC2 in a second connection region ER2, and a lower wiring structure LRS may be divided into a first lower wiring structure LRSa electrically connecting the first wiring interconnection line RLa and the first sub word line driver SWDa and a second lower wiring structure LRSb electrically connecting the second wiring interconnection line RLb and the second sub word line driver SWDb. Each of the first lower wiring structure LRSa and the second lower wiring structure LRSb may include a word line peripheral interconnection structure 15w, a second word line bonding pad 25w, a first word line bonding pad 170w, and a word line under-interconnection structure 160w, as shown in FIG. Figure 5A As shown.

[0134] Next, refer to Fig.18A and Fig.18B , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig.18A It's a picture. Fig.16 A conceptual cross-sectional view of a modified example of a wiring interconnection line RL of a word line signal path WSP in FIG. Fig.18B It's a picture. Fig.17 FIG. 2 is a view of a modified example of the wiring interconnection line RL of the word line signal path WSP in FIG.

[0135] refer to Fig.18A and Fig.18B ,exist Fig.16 and Fig.17The first wiring interconnection line RLa and the second wiring interconnection line RLb separated from each other in the first connection region ER1 may be replaced with one wiring interconnection line RL. For example, the wiring interconnection line RL may extend continuously from a portion in contact with the first wiring contact WC1 in the first connection region ER1 to a portion in contact with the second wiring contact WC2 in the second connection region ER2. Therefore, the one wiring interconnection line RL may be electrically connected to the first sub-word line driver SWDa through the first lower wiring structure LRSa, and may be electrically connected to the second sub-word line driver SWDb through the second lower wiring structure LRSb.

[0136] In the above Figures 16 to 18B In an example embodiment of , one word line WL may be electrically connected to a plurality of sub word line drivers SWDa and SWDb disposed in a sub word line driver region SWDR that vertically overlaps (eg, vertically overlaps) one memory block region CA. Fig.19A , Fig.19B and Fig.19C In the description Figures 16 to 18B Examples of memory block areas CA in example embodiments are arranged in various forms. Fig.19A , Fig.19B and Fig.19C is a diagram illustrating first to fourth memory block regions CA1, CA2, CA3, and CA4 and first to fifth connection regions ER1, ER2, ER3, ER4, and ER5, and FIG. 12A to FIG. 12C The first word line WL1a and the second word line WL2a among the first to fourth word lines WL1a, WL2a, WL3a, and WL4a described above, and the FIG. 12A to FIG. 12C The first wiring interconnection line RL1a and the second wiring interconnection line RL2a among the first to fourth wiring interconnection lines RL1a, RL2a, RL3a, and RL4a are described and the Figures 16 to 18B A conceptual perspective view of the electrical connection relationship between the first wiring interconnection line RL1a and the second wiring interconnection line RL2a and the sub-word line drivers SWDa and SWDb described in an exemplary embodiment of FIG. FIG. 12A to FIG. 12C The first word line WL1a and the second word line WL2a in FIG. 1 , but the first word line WL1a and the second word line WL2a may be replaced by Figure 8 The first word line WL1 and the second word line WL2 shown in the figure or Fig.13 A first word line WL1b and a second word line WL2b are illustrated.

[0137] First, refer to Figures 16 to 18B as well as FIG. 12A to FIG. 12C and Fig.19AIn any of the embodiments of the present invention, the peripheral circuit region PC may include first to fourth peripheral circuit regions PC1, PC2, PC3 and PC4 vertically overlapping the first to fourth memory block regions CA1, CA2, CA3 and CA4, respectively (e.g., the first to fourth memory block regions CA1, CA2, CA3 and CA4 are vertically overlapped thereon, respectively). Each of the first to fourth peripheral circuit regions PC1, PC2, PC3 and PC4 may include Fig.16 and Fig.17 The first wiring interconnect line RLa and the second wiring interconnect line RLb described in the example embodiment of the present invention. Each of the first wiring interconnect line RLa and the second wiring interconnect line RLb may be electrically connected to a corresponding one of the first sub-word line driver SWDa and the second sub-word line driver SWDb. Each of the first to fourth peripheral circuit regions PC1, PC2, PC3, and PC4 may include a first sub-word line driver SWDa and a second sub-word line driver SWDb.

[0138] like Fig.19A As shown, one of the first wiring interconnection lines RL1a that continuously crosses the second storage block area CA2, the second connection area ER2, and the third storage block area CA3 and extends to the second connection area ER2 and the fourth connection area ER4 can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb that do not vertically overlap with the second storage block area CA2 (for example, the second storage block area CA2 does not vertically overlap thereon) but vertically overlap with the third storage block area CA3 (for example, the third storage block area CA3 vertically overlaps thereon). As described above, this one first wiring interconnection line RL1a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb through the first lower wiring structure LRSa and the second lower wiring structure LRSb. Therefore, the first word line WL1a electrically connected to the first wiring interconnection line RL1a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb. Therefore, the first word line WL1a may be electrically connected to the first and second sub word line drivers SWDa and SWDb through the wiring contacts WC, the first wiring interconnection lines RL1a, and the first and second lower wiring structures LRSa and LRSb.

[0139] One of the second wiring interconnection lines RL2a that continuously crosses the first storage block area CA1, the second connection area ER2, and the second storage block area CA2 and extends to the first connection area ER1 and the third connection area ER3 can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb that do not vertically overlap with the first storage block area CA1 (for example, the first storage block area CA1 does not vertically overlap thereon) but vertically overlap with the second storage block area CA2 (for example, the second storage block area CA2 vertically overlaps thereon). As described above, this second wiring interconnection line RL2a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb through the first lower wiring structure LRSa and the second lower wiring structure LRSb. Therefore, the second word line WL2a electrically connected to the second wiring interconnection line RL2a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb. Therefore, the second word line WL2a may be electrically connected to the first and second sub word line drivers SWDa and SWDb through the wiring contacts WC, the second wiring interconnection lines RL2a, and the first and second lower wiring structures LRSa and LRSb.

[0140] Next, refer to Fig.19B , will describe Fig.19A A modified example of the electrical connection relationship between the word line WL and the sub word line drivers SWDa and SWDb described in FIG.

[0141] refer to Fig.19B , Fig.19A The first lower wiring structure LRSa and the second lower wiring structure LRSb described in Fig.19A ) can be replaced by Fig.19B The lower wiring structure LRS' is shown.

[0142] One of the first wiring interconnection lines RL1a that continuously crosses the second storage block area CA2, the third connection area ER3, and the third storage block area CA3 and extends to the second connection area ER2 and the fourth connection area ER4 can be electrically connected to the first sub-word line driver SWDa vertically overlapping with the third storage block area CA3 (for example, the third storage block area CA3 vertically overlaps thereon) and the second sub-word line driver SWDb vertically overlapping with the second storage block area CA2 (for example, the second storage block area CA2 vertically overlaps thereon). The lower wiring structure LRS' can electrically connect the first wiring interconnection line RL1a and the first sub-word line driver SWDa, and can electrically connect the first wiring interconnection line RL1a and the second sub-word line driver SWDb. Therefore, the first word line WL1a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb through the wiring contact WC, the first wiring interconnection line RL1a, and the lower wiring structure LRS'.

[0143] One of the second wiring interconnection lines RL2a that continuously crosses the first storage block area CA1, the second connection area ER2, and the third storage block area CA3 and extends into the first connection area ER1 and the third connection area ER3 can be electrically connected to the first sub-word line driver SWDa vertically overlapping with the second storage block area CA2 (for example, the second storage block area CA2 vertically overlaps thereon) and the second sub-word line driver SWDb vertically overlapping with the first storage block area CA1 (for example, the first storage block area CA1 vertically overlaps thereon). The lower wiring structure LRS' can electrically connect the second wiring interconnection line RL2a electrically connected to the second word line WL2a to the first sub-word line driver SWDa, and can electrically connect the second wiring interconnection line RL2a to the second sub-word line driver SWDb. Therefore, the second word line WL2a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb through the wiring contact WC, the second wiring interconnection line RL2a, and the lower wiring structure LRS'.

[0144] Next, refer to Fig.19C , will describe about Fig.19A A modified example of the electrical connection relationship between the word line WL and the sub word line drivers SWDa and SWDb is described.

[0145] refer to Fig.19C , Fig.19A The first lower wiring structure LRSa and the second lower wiring structure LRSb described in Fig.19A ) can be replaced by Fig.19C The lower wiring structure LRS'' is shown.

[0146] One of the first wiring interconnection lines RL1a that continuously crosses the second storage block area CA2, the third connection area ER3, and the third storage block area CA3 and extends to the second connection area ER2 and the fourth connection area ER4 can be electrically connected to the second sub-word line driver SWDb vertically overlapping with the third storage block area CA3 (for example, the third storage block area CA3 vertically overlaps thereon) and the first sub-word line driver SWDa vertically overlapping with the fourth storage block area CA4 (for example, the fourth storage block area CA4 vertically overlaps thereon). The lower wiring structure LRS'' can electrically connect the first wiring interconnection line RL1a and the first sub-word line driver SWDa, and can electrically connect the first wiring interconnection line RL1a and the second sub-word line driver SWDb. Therefore, the first word line WL1a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb through the wiring contact WC, the first wiring interconnection line RL1a, and the lower wiring structure LRS''.

[0147] One of the second wiring interconnection lines RL2a that continuously crosses the first storage block region CA1, the second connection region ER2, and the second storage block region CA2 and extends to the first connection region ER1 and the third connection region ER3 can be electrically connected to the first sub-word line driver SWDa vertically overlapping with the second storage block region CA2 (for example, the second storage block region CA2 vertically overlaps thereon) and the second sub-word line driver SWDb vertically overlapping with the first storage block region CA1 (for example, the first storage block region CA1 vertically overlaps thereon). The lower wiring structure LRS'' can electrically connect the second wiring interconnection line RL2a electrically connected to the second word line WL2a to the first sub-word line driver SWDa, and can electrically connect the second wiring interconnection line RL2a and the second sub-word line driver SWDb. Therefore, the second word line WL2a can be electrically connected to the first sub-word line driver SWDa and the second sub-word line driver SWDb through the wiring contact WC, the second wiring interconnection line RL2a, and the lower wiring structure LRS''.

[0148] Next, refer to Fig. 20 , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig. 20 It's a picture. Figure 5A A conceptual cross-sectional view of a modified example of a word line signal path WSP in a cross-sectional structure taken along line II′.

[0149] refer to Fig. 20, in the word line signal path WSP, the wiring contact WC may further include at least one third wiring contact WC3 disposed between the wiring interconnect line RL and the word line WL in the memory block region CA and passing between the bit lines BL. The word line WL passing through one memory block region CA may contact the first wiring contact WC1 and the second wiring contact WC2 in the connection region ER and the third wiring contact WC3 in the memory block region CA.

[0150] Next, refer to Fig.21 , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig.21 It's a picture. Figure 1B A conceptual perspective view of a modified example of the memory block area CA provided in the first memory bank area BA1.

[0151] refer to Fig.21 , Figure 1B At least one middle storage block region CAa of the storage block regions CA arranged along the first direction (X direction) described in the embodiment may have a width different from other storage block regions CA. Here, the middle storage block region CAa may be defined as a second storage block region CAa, and the remaining storage block regions CA may be defined as a first storage block region CA. The second storage block region CAa may be disposed between the first storage block regions CA.

[0152] The width W2 of the second storage block region CAa in the first direction (X direction) may be smaller than the width W1 of each first storage block region CA in the first direction (X direction). The widths of the first storage block region CA and the second storage block region CAa in the second direction (Y direction) may be the same. Therefore, "m" storage cells MC arranged sequentially along the first direction (X direction) may be arranged in the second storage block region CAa, and "n" storage cells (MC) arranged sequentially along the first direction (X direction) may be arranged in one of the first storage block regions CA in the first storage block region CA. "n" and "m" are natural numbers, and "n" may be a natural number greater than "m".

[0153] Next, we will refer to Fig. 22 , Fig.23 and Fig.24 An example of a semiconductor device according to an example embodiment of the present disclosure is described. Fig. 22 , Fig.23 and Fig.24 It's a picture. Figure 5A 2 is a cross-sectional view of a modified example of the first structure ST1 and the second structure ST2 in the cross-sectional structure taken along the line II′.

[0154] First, refer to Fig. 22 ,according to Figures 1A to 21The first structure ST1 of the embodiment can be replaced by Fig. 22 The first structure ST1a shown in the figure. For example, the first structure ST1a can be obtained by Figures 1A to 21 The first structure ST1 of the exemplary embodiment omits the first bonding pad 170w and uses Fig. 22 The illustrated under-wordline interconnection structure 260 is formed to replace the under-wordline interconnection structure 160w. The under-wordline interconnection structure 260 may include at least one horizontal portion and at least one vertical portion. The under-wordline interconnection structure 260 may be connected to a wiring interconnection line RL.

[0155] according to Figures 1A to 21 The second structure ST2 of the exemplary embodiment may be replaced as follows Fig. 22 The second structure ST2a shown in the figure may include a substrate 203 and a device isolation region 206 defining an active region 209 below the substrate 203. The substrate 203 may be a semiconductor substrate.

[0156] The second structure ST2a may include a peripheral circuit transistor PTR disposed below the substrate 203, a peripheral interconnect structure 215 electrically connected to the peripheral circuit transistor PTR below the peripheral circuit transistor PTR, a lower insulating structure 220 covering the peripheral transistor PTR and the substrate 203 below the substrate 203 (for example, on the bottom surface of the substrate 203), and a bonding insulating layer 250 disposed on the substrate 203 and in contact with and bonded to the first insulating structure 150 of the first structure ST1a.

[0157] Each peripheral circuit transistor PTR may include a peripheral gate structure GE1 and GO1 disposed below the active region 209, and a peripheral source / drain region SD1 disposed in the active region 209 on opposite (e.g., two) sides of the peripheral gate structure GE1 and GO1. The peripheral gate structure GE1 and GO1 may include a peripheral gate dielectric layer GO1 and a peripheral gate electrode GE1 located below the peripheral gate dielectric layer GO1.

[0158] The second structure ST2a may include the same peripheral circuit region PC as described above. Among the peripheral circuit transistors PTR, the first peripheral transistor TR1 disposed in the sub word line driver region SWDR may be the transistors PT, NT1, and NT2 of the sub word line driver SWD (see Figure 2B ).

[0159] The first structure ST1a and the second structure ST2a may further include through-electrode structures 270 and 272. For example, any one of the through-electrode structures 270 and 272 may include a through-electrode 272 extending downward by penetrating the substrate 203 and connected to the peripheral interconnection structure 215 and extending upward by penetrating the substrate 203 and connected to the wordline under-interconnection structure 260, and an insulating spacer 270 surrounding a side surface of the through-electrode 272.

[0160] Above Figures 1A to 21 The lower wiring structure LRS in the example embodiment may be replaced with a lower wiring structure LRSaa including the peripheral interconnection structure 215 , the through-electrode 272 , and the wordline under-interconnection structure 260 .

[0161] Above Figures 1A to 21 The word line signal path WSP in the example embodiment of can be replaced by a word line signal path WSP including a lower wiring structure LRSaa, a wiring interconnect line RL and a wiring contact WC. Therefore, it can be used as a sub-word line driver ( Figure 2B The first peripheral transistor TR1 of the SWD in FIG. 1 may be electrically connected to the word line WL through the lower wiring structure LRSaa, the wiring interconnection line RL, and the wiring contact WC.

[0162] Next, refer to Fig.23 ,according to Figures 1A to 21 The first structure ST1 of the exemplary embodiment may be replaced by Fig.23 For example, the first structure ST1b may be replaced according to Figures 1A to 21 In the first structure ST1 of the example embodiment, the wiring contact WC may be replaced with a wiring contact WC' disposed on the word line WL in the connection region ER, the wiring interconnect line RL may be replaced with a wiring interconnect line RL'' connected to the upper surface of the wiring contact WC' and crossing the storage block region CA at a height higher than the data storage structure DS, the word line lower interconnect structure 160w may be replaced with a word line upper wiring structure 360w disposed on the wiring interconnect line RL'', and the first bonding pad 170w may be replaced with a first bonding pad 370w connected to the word line upper wiring structure 360w and having an upper surface coplanar with the upper surface of the upper insulating structure 145. The wiring contact WC' may include a first wiring contact WC1' that contacts and is connected to the upper surface of the word line WL in the first connection region ER1, and a second wiring contact WC2' that is connected to and is in contact with the upper surface of the word line WL in the second connection region ER2. Therefore, Figures 1A to 21 The upper structure LRS_U in the embodiment of FIG. 3 may be replaced with an upper structure LRS_Ua including a word line upper wiring structure 360w and a first bonding pad 370w.

[0163] according to Figures 1A to 21 The second structure ST2 of the exemplary embodiment may be replaced as follows Fig.23 The illustrated second structure ST2b may be disposed on the first structure ST1b.

[0164] The second structure ST2b may further include a substrate 303 and a device isolation region 306 defining an active region 309 below the substrate 303. The substrate 303 may be a semiconductor substrate. The second structure ST2b may include a peripheral circuit transistor PTR disposed below the substrate 303, a peripheral interconnect structure 315w electrically connected to the peripheral circuit transistor PTR below the peripheral circuit transistor PTR, a lower insulating structure 320 covering the peripheral transistor PTR and the substrate 303 below the substrate 303 (e.g., on its bottom surface), and a second bonding pad 325w connected to the peripheral interconnect structure 315w and having a lower surface coplanar with a lower surface of the lower insulating structure 320. The peripheral transistor PTR may be connected to the substrate 303. Fig. 22 The peripheral transistor PTR described in is the same. Figures 1A to 21 The lower structure LRS_L in the example embodiment may be replaced with a lower structure LRS_La including a peripheral interconnection structure 315w and a second bonding pad 325w.

[0165] Above Figures 1A to 21 The lower wiring structure LRS in the example embodiment may be replaced with a lower wiring structure LRSab including a lower structure LRS_La and an upper structure LRS_Ua.

[0166] Above Figures 1A to 21 The word line signal path WSP in the example embodiment of can be replaced by a word line signal path WSP including a lower wiring structure LRSab, a wiring interconnection line RL'' and a wiring contact WC'. Therefore, it can be used as a sub-word line driver SWD (see Figure 2B ) may be electrically connected to the word line WL through the lower wiring structure LRSab, the wiring interconnection line RL″, and the wiring contact WC′.

[0167] Next, refer to Fig.24 , Fig.23 The first structure ST1b in can be replaced by Fig.24 The first structure ST1c shown in the figure. For example, the first structure ST1c can be obtained by Fig.23 The first structure ST1b in the embodiment omits the first bonding pad 370w and uses Fig.24The wordline interconnection structure 460 shown is formed to replace the wordline interconnection structure 360w. The wordline interconnection structure 460 may include at least one horizontal portion and at least one vertical portion. The wordline interconnection structure 460 may be connected to the wiring interconnection line RL″.

[0168] Fig.23 The second structure ST2b in can be replaced by Fig.24 The second structure ST2c shown. The second structure ST2c may include a substrate 403 and a device isolation region 406 defining an active region 409 on the substrate 403. The substrate 403 may be a semiconductor substrate. The second structure ST2c may include a peripheral transistor PTR disposed on the substrate 403, a peripheral interconnect structure 415 electrically connected to the peripheral circuit transistor PTR on the peripheral transistor PTR, a lower insulating structure 420 covering the peripheral transistor PTR and the substrate 403 on the substrate 403, and a bonding insulating layer 450 disposed below the substrate 403 and contacting and bonding to the upper insulating structure 145 of the first structure ST1c. Each peripheral circuit transistor PTR may include peripheral gate structures GE1 and GO1 disposed on the active region 409, and peripheral source / drain regions SD1 disposed in the active region 409 on opposite (e.g., two) sides of the peripheral gate structures GE1 and GO1.

[0169] The second structure ST2c may include the same peripheral circuit region PC as described above. The first peripheral transistor TR1 disposed in the sub word line driver region SWDR among the peripheral circuit transistors PTR may be the transistors PT, NT1 and NT2 of the sub word line driver SWD (see Figure 2B ).

[0170] The first structure ST1c and the second structure ST2c may further include through-electrode structures 470 and 472. For example, any one of the through-electrode structures 470 and 472 may include a through-electrode 472 extending upward by penetrating the substrate 403 and connected to the peripheral interconnection structure 415 and extending downward through the substrate 403 and connected to the wordline upper interconnection structure 460, and an insulating spacer 470 surrounding a side surface of the through-electrode 472.

[0171] Above Figures 1A to 21 The lower wiring structure LRS in the example embodiment may be replaced with a lower wiring structure LRSac including the peripheral interconnection structure 415 , the through-electrode 472 , and the wordline upper interconnection structure 460 .

[0172] Above Figures 1A to 21The word line signal path WSP in the example embodiment of can be replaced by a word line signal path WSP including a lower wiring structure LRSac, a wiring interconnection line RL'' and a wiring contact WC'. Therefore, it can be used as a sub-word line driver SWD (see Figure 2B ) may be electrically connected to the word line WL through the lower wiring structure LRSac, the wiring interconnection line RL″, and the wiring contact WC′.

[0173] Next, refer to Fig.25 , an example of a semiconductor device according to an example embodiment of the present disclosure will be described. Fig.25 It's a picture. Fig.9A FIG. 4 is a cross-sectional view of a modified example of the data storage structure DS in the cross-sectional structure of FIG.

[0174] refer to Fig.25 The data storage structure DS may include a first data storage structure DS1 disposed in the first storage block area CA1 and a second data storage structure DS2 disposed in the second storage block area CA2. Fig.25 In an example, the second electrode 140 of the first data storage structure DS1 and the second electrode 140 of the second data storage structure DS2 may extend into the connection region ER and may be connected to (eg, in contact with) each other. Figure 1B The second electrode 140 of the data storage structure DS disposed in the first memory body region BA1 as illustrated may have an extension portion 140e extending into the connection region ER, and the second electrode 140 of the data storage structure DS disposed in the first memory body region BA1 may be one second electrode 140 continuously connected to each other. Since the second electrodes 140 of the data storage structure DS are connected to each other, the same voltage Vp may be applied to the second electrode 140 more effectively. Therefore, the data storage structure DS may store information more stably and reliably. The wiring contact WC may overlap the second electrode 140 of the data storage structure DS in the vertical direction (Z direction) (e.g., the second electrode 140 of the data storage structure DS overlaps thereon).

[0175] According to example embodiments, since a voltage may be applied to a word line WL in a memory block region through a first connection region and a second connection region disposed at opposite (eg, both) sides of the memory block region, performance of a semiconductor device may be improved.

[0176] The advantages and effects of the present application are not limited to the foregoing and can be more easily understood in the course of describing specific exemplary embodiments of the present disclosure.

[0177] Although the exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will appreciate that the present disclosure can be implemented in other specific forms without changing its scope. Therefore, it should be understood that the exemplary embodiments described above are merely examples and are not intended to be limiting.

Claims

1. A semiconductor device, comprising: a first structure, the first structure having a first connection region, a second connection region and a first storage block region, the first storage block region being located between the first connection region and the second connection region in a first direction; as well as a second structure, the second structure vertically overlapping the first structure, Wherein, the first structure includes: a first storage unit, the first storage unit being located in the first storage block area; and a first word line, the first word line traversing the first memory block region and extending into the first connection region and the second connection region, and being electrically connected to the first memory cell, wherein the second structure has a first peripheral circuit region, at least a portion of the first peripheral circuit region vertically overlaps with the first memory block region, wherein the second structure includes a first sub-word line driver in the first peripheral circuit region, The first structure and the second structure further include a first word line signal path electrically connecting the first word line and the first sub-word line driver, and The first word line signal path includes at least one first wiring contact coupled to the first word line in the first connection region and at least one second wiring contact coupled to the first word line in the second connection region.

2. The semiconductor device according to claim 1, in, The first word line signal path further includes a first wiring interconnect line electrically connected to the at least one first wiring contact and the at least one second wiring contact, wherein the first wiring interconnect line comprises a first portion adjacent to the at least one first wiring contact and a second portion adjacent to the at least one second wiring contact, and The first wiring interconnection line extends continuously from the first portion to the second portion and crosses the first memory block region.

3. The semiconductor device according to claim 2, in, The first word line signal path further includes a first lower wiring structure electrically connecting the first wiring interconnect line and the first sub word line driver, and The first lower wiring structure and the first wiring interconnection line are coupled to each other below the first memory cell.

4. The semiconductor device according to claim 1, wherein: Each of the first memory cells includes a cell transistor and a data storage structure electrically connected to the cell transistor, Wherein, the unit transistor comprises: a first source / drain region and a second source / drain region at a higher elevation than the first source / drain region; a channel region, the channel region being located between the first source / drain region and the second source / drain region; a gate dielectric layer, the gate dielectric layer being in contact with a side surface of the channel region; and the first word line, the first word line is in contact with the gate dielectric layer, and Wherein, the data storage structure includes: a first electrode electrically connected to the second source / drain region; a second electrode located on an upper surface and a side surface of the first electrode; and A dielectric layer is located between the first electrode and the second electrode.

5. The semiconductor device according to claim 1, further comprising: a first bit line, the first bit line traversing the first storage block region in a second direction, intersecting the first word line, and being electrically connected to at least one of the first storage cells; a first sense amplifier located in the first peripheral circuit region; as well as A first bit line signal path electrically connects the first bit line and the first sense amplifier.

6. The semiconductor device according to claim 1, further comprising: a second storage block region and a third connection region, wherein the second storage block region is located between the second connection region and the third connection region in the first direction; a second peripheral circuit region vertically overlapping the second memory block region; a second storage unit, the second storage unit being located in the first storage block area; a third storage unit and a fourth storage unit, wherein the third storage unit and the fourth storage unit are located in the second storage block area; a second word line, the second word line traversing the first storage block region, the second connection region, and the second storage block region, extending into the first connection region and the third connection region, and electrically connected to the second storage cell and the fourth storage cell; a second sub word line driver, the second sub word line driver being located in the second peripheral circuit region; and A second word line signal path electrically connects the second word line and the second sub word line driver.

7. The semiconductor device according to claim 6, wherein: The first word line extends in the first direction, crosses the second memory block region and extends into the third connection region, and is electrically connected to the third memory cell.

8. The semiconductor device according to claim 7, wherein: The first word line signal path also includes at least one third wiring contact coupled to the first word line in the third connection region.

9. The semiconductor device according to claim 6, wherein: The second word line signal path comprises: at least one fourth wiring contact coupled to the second word line in the first connection region; at least one fifth wiring contact coupled to the second word line in the second connection region; and At least one sixth wiring contact is coupled to the second word line in the third connection region.

10. A semiconductor device, comprising: a first connection region, a second connection region, and a first storage block region, wherein the first storage block region is located between the first connection region and the second connection region in a first direction; a first peripheral circuit region vertically overlapping the first memory block region; a first storage unit, the first storage unit being located in the first storage block area; a first word line, the first word line extending through the first storage block region into the first connection region and the second connection region, and being electrically connected to the first storage cell; a sub-word line driver, the sub-word line driver being located in the first peripheral circuit region; as well as a first word line signal path electrically connecting the first word line and the sub word line driver, The first word line signal path includes at least one first wiring contact coupled to the first word line in the first connection region and at least one second wiring contact coupled to the first word line in the second connection region.

11. The semiconductor device according to claim 10, in, The first word line signal path further includes a first wiring interconnect line electrically connected to the at least one first wiring contact and the at least one second wiring contact, wherein the first wiring interconnect line comprises a first portion adjacent to the at least one first wiring contact and a second portion adjacent to the at least one second wiring contact, and The first wiring interconnection line extends continuously from the first portion to the second portion and crosses the first memory block region.

12. The semiconductor device according to claim 10, in, The at least one first wiring contact is two or more first wiring contacts spaced apart from each other, and The at least one second wiring contact is two or more second wiring contacts spaced apart from each other.

13. The semiconductor device according to claim 10, further comprising: a first bit line, the first bit line traversing the first memory block region in a second direction, intersecting the first word line, and being electrically connected to a first memory cell in the first memory cells; a first sense amplifier located in the first peripheral circuit region; as well as A first bit line signal path electrically connects the first bit line and the first sense amplifier.

14. A semiconductor device, comprising: A first structure, the first structure comprising connection areas and storage block areas alternately and repeatedly arranged along a first direction; as well as a second structure, the second structure is arranged along the first direction and includes a peripheral circuit area, and the second structure vertically overlaps the first structure, The connection area includes a first edge connection area, a second edge connection area, and an intermediate connection area between the first edge connection area and the second edge connection area. Each of the storage block regions is located between a pair of adjacent connection regions among the connection regions. Wherein, the first structure includes: a storage unit located in each of the storage block regions; and a word line that passes through the memory block region and extends into the connection region to be electrically connected to the memory cell, wherein the second structure includes a sub-word line driver in each of the peripheral circuit regions, The first structure and the second structure further include a word line signal path electrically connecting the word line and the sub-word line driver, and Wherein, the word line signal path includes: a wiring interconnect line that passes through the memory block region and extends into the connection region; a wiring contact located in each of the connection regions, the wiring contact electrically connecting the word line and the wiring interconnect line; and A wiring structure electrically connects the wiring interconnection line and the sub-word line driver.

15. The semiconductor device according to claim 14, in, The storage block area includes a first storage block area and a second storage block area located between the first storage block areas, Each of the first storage block areas includes "n" storage units, Wherein, the second storage block area includes "m" storage units, Where "n" and "m" are natural numbers, and Here, "n" is a natural number greater than "m".

16. The semiconductor device according to claim 14, in, The first structure also includes a bit line electrically connected to the memory cell, Wherein, the second structure further includes sense amplifiers respectively located in the peripheral circuit area, and The first structure and the second structure further include a bit line signal path electrically connecting the bit line and the sub-word line driver.

17. The semiconductor device according to claim 14, wherein: Each of the memory cells includes a cell transistor and a data storage structure electrically connected to the cell transistor, and Wherein, the unit transistor comprises: a vertical active pattern, the vertical active pattern comprising a first source / drain region, a second source / drain region at a higher height than the first source / drain region, and a channel region between the first source / drain region and the second source / drain region; a gate dielectric layer, the gate dielectric layer contacting the channel region of the vertical active pattern; and a word line among the word lines that contacts the gate dielectric layer, Wherein, the word line includes a gate electrode, and Wherein, the data storage structure includes: a first electrode electrically connected to the second source / drain region; a second electrode located on an upper surface and a side surface of the first electrode; and A dielectric layer is located between the first electrode and the second electrode.

18. The semiconductor device according to claim 17, wherein: The second electrodes of the data storage structure of the memory block region extend into the intermediate connection region and contact each other.

19. The semiconductor device according to claim 17, further comprising: a back gate line, wherein the back gate line is located between the word lines, Each of the back gate lines is located between a pair of word lines that are adjacent to each other among the word lines, and passes between a pair of vertical active patterns that are adjacent to each other among the vertical active patterns.

20. The semiconductor device according to claim 14, wherein The word line crosses the memory block region and the middle connection region and extends into the first edge connection region and the second edge connection region.

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