Phase change memory and forming method thereof

Abstract

The invention provides a phase change memory and a forming method thereof. The phase change memory comprises a first conductive wire, a second conductive wire and a memory unit located between the first conductive wire and the second conductive wire in a first direction, the storage unit extends along the first direction; the first conductive wire extends along a second direction and is connected with the plurality of storage units arranged along the second direction; the second conductive wire extends along a third direction and is connected with the plurality of storage units arranged along the third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; the first isolation structure is positioned between the two adjacent storage units in the second direction, and is positioned between the second conductive wires which are respectively connected with the two adjacent storage units in the second direction; the thermal conductivity of the first isolation structure ranges from 0.3 W / (m.K) to 0.45 W / (m.K).

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a phase change memory and a method for forming the same. Background Art

[0002] Phase-Change Memory (PCM), as an emerging non-volatile memory device, has great advantages in read and write speed, read and write times, data retention time, unit area, multi-value realization, etc. However, with the improvement of the integration density of PCM, the reliability of data storage and data reading of PCM needs to be further improved. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a phase change memory and a method for forming the same.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a phase change memory, including:

[0006] A first conductive line, a second conductive line, and a storage unit located between the first conductive line and the second conductive line in a first direction; the storage unit extends along the first direction; the first conductive line extends along the second direction and is connected to a plurality of the storage units arranged along the second direction; the second conductive line extends along a third direction and is connected to a plurality of the storage units arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction;

[0007] A first isolation structure, wherein the first isolation structure is located between two of the storage units adjacent to each other in the second direction, and between the second conductive lines respectively connected to the two storage units adjacent to each other in the second direction; the thermal conductivity of the first isolation structure ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

[0008] In an optional embodiment, the first isolation structure includes low temperature silicon oxide.

[0009] In an optional implementation, the phase change memory further includes:

[0010] A second isolation structure, wherein the second isolation structure is located between two adjacent storage units in the third direction and between the first conductive lines respectively connected to the two adjacent storage units in the third direction; the thermal conductivity of the second isolation structure is less than the thermal conductivity of the first isolation structure.

[0011] In an optional embodiment, the thermal conductivity of the second isolation structure is in a range of 0.11 W / (m·K) to 0.2 W / (m·K).

[0012] In an optional implementation, the first isolation structure extends along the third direction and is located between two adjacent second isolation structures in the second direction.

[0013] In an optional implementation, the storage unit includes:

[0014] A first electrode, a gating element, a second electrode, a phase change element and a third electrode are stacked and arranged in sequence along the first direction; the first electrode is located between the gating element and the first conductive line; the third electrode is located between the phase change element and the second conductive line.

[0015] In an optional implementation, the phase change memory further includes:

[0016] A third isolation structure and a fourth isolation structure; the third isolation structure covers the phase change element of the storage unit, the third electrode and the second conductive line connected to the storage unit on the same side of the two opposite sides in the second direction; the fourth isolation structure covers the third isolation structure, the second electrode, the selection element and the same side of the first electrode on the two opposite sides in the second direction; the fourth isolation structure is located between the first isolation structure and the third isolation structure.

[0017] In an optional embodiment, the third isolation structure includes a first dielectric layer and a second dielectric layer; the fourth isolation structure includes a third dielectric layer and a fourth dielectric layer; the second dielectric layer is located between the first dielectric layer and the third dielectric layer; the first dielectric layer and the third dielectric layer include silicon nitride; the second dielectric layer and the fourth dielectric layer include silicon oxide.

[0018] In a second aspect, an embodiment of the present disclosure provides a method for forming a phase change memory, comprising:

[0019] forming a first conductive line extending along a second direction;

[0020] A storage unit is formed on one side of two opposite sides of the first conductive line along the first direction; the storage unit extends along the first direction; one of the first conductive lines is connected to a plurality of the storage units arranged along the second direction;

[0021] A second conductive line extending along a third direction is formed on one side of the storage unit that is away from the first conductive line among two opposite sides along the first direction; one of the second conductive lines is connected to a plurality of the storage units arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction;

[0022] A first isolation structure is formed; the first isolation structure is located between two adjacent storage units in the second direction, and between the second conductive lines respectively connected to the two adjacent storage units in the second direction; the thermal conductivity of the first isolation structure ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

[0023] In an optional embodiment, the memory cell includes a first electrode, a gating element, a second electrode, a phase change element and a third electrode stacked and arranged in sequence along the first direction; the first electrode is located between the gating element and the first conductive line; and the forming of the first isolation structure includes:

[0024] Filling an isolation material between two adjacent storage cells in the second direction by a low temperature atomic layer deposition process to form a first initial isolation structure; the top surface of the first initial isolation structure is located between the top surface and the bottom surface of the third electrode in the first direction;

[0025] Etching the first initial isolation structure to form a second initial isolation structure, wherein a top surface of the second initial isolation structure is located between the top surface and the bottom surface of the phase change element in the first direction;

[0026] The isolation material is filled on the second initial isolation structure by the low temperature atomic layer deposition process to form the first isolation structure.

[0027] In the technical solution provided in the present disclosure, the phase change memory includes a first isolation structure located between two adjacent storage cells in a second direction and between second conductive lines connected to the two adjacent storage cells in the second direction, and the thermal conductivity of the first isolation structure ranges from 0.3W / (m·K) to 0.45W / (m·K), and is greater than the thermal conductivity of the second isolation structure located between two adjacent storage cells in a third direction. Thus, the degree of heat transfer along the second direction when a reset operation is performed on a selected storage cell can be increased, thereby reducing the degree of heat transfer along the third direction to balance the heat in the two directions and reduce thermal crosstalk to non-selected storage cells adjacent to the selected storage cell in the third direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1A schematic diagram of a three-dimensional structure of a part of the structure of a phase change memory provided by an embodiment of the present disclosure;

[0029] Figure 2 A top view of a partial structure of a phase change memory provided in the disclosed embodiment;

[0030] Figure 3 for Figure 2 Cross-section along line AA';

[0031] Figure 4 for Figure 3 A magnified schematic diagram of the structure in the middle;

[0032] Figure 5 for Figure 2 Cross-section along line BB';

[0033] Figure 6 A schematic diagram of a process of forming a phase change memory provided by an embodiment of the present disclosure;

[0034] Figures 7 to 11 A structural schematic diagram of a phase change memory formation process provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0037] In the drawings, like reference numerals refer to like elements throughout.

[0038] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Phase-Change Memory (PCM), as an emerging non-volatile memory device, has great advantages in read and write speed, read and write times, data retention time, unit area, multi-value realization, etc. However, with the improvement of the integration density of PCM, the reliability of data storage and data reading of PCM needs to be further improved.

[0041] Figure 1 A three-dimensional schematic diagram of a partial structure of a phase change memory provided by an embodiment of the present disclosure, such as Figure 1 As shown, the phase change memory includes a first conductive line 121, a second conductive line 122, and a storage unit 100 located between the first conductive line 121 and the second conductive line 122 in a first direction, the storage unit 100 extends along the first direction, the first conductive line 121 extends along the second direction and is connected to a plurality of storage units 100 arranged along the second direction, and the second conductive line 122 extends along the third direction and is connected to a plurality of storage units 100 arranged along the third direction. Here, the first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction as an example.

[0042] In some embodiments, the storage unit 100 includes a first electrode 101, a selection element 102, a second electrode 103, a phase change element 104 and a third electrode 105 stacked in sequence along a first direction, wherein the first electrode 101 is located between the first conductive line 121 and the selection element 102, and the third electrode 105 is located between the phase change element 104 and the second conductive line 122.

[0043] In some specific examples, the first conductive line 121 may be a bit line (BL), the third electrode 105 is connected to the second conductive line 122, and the second conductive line 122 may be a word line (WL).

[0044] In some specific examples, the first conductive line 121 and the second conductive line 122 may include a conductive material. Here, the conductive material may be at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0045] In some specific examples, the first electrode 101 , the second electrode 103 , and the third electrode 105 may include a conductive material and may serve as a conductive path.

[0046] In some specific examples, the second electrode 103 may further include a thermal insulation material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0047] In some specific examples, the resistance of the gating element 102 may change in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may include a material having an Ovonic Threshold Switch (OTS) property, and the material having the OTS property may include at least one element of oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn x Te y ,Ge x Te y , Nb x O y 、Si x As y Te zWhen the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 may be in a high resistance state that prevents current from flowing, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 may be in a low resistance state that allows current to flow.

[0048] In some specific examples, the phase change element 104 may include a chalcogenide component, such as binary compounds such as GaSb, InSb, InSe, SbTe and GeTe, ternary compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe and InSbGe, and quaternary compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and TeGeSbS.

[0049] In some specific examples, the phase change element 104 can be reversibly switched between a crystalline state and an amorphous state, and the difference in resistivity between the crystalline state and the amorphous state can be used to achieve data storage. Specifically, the crystal phase of the phase change element 104 can be changed by the Joule heat generated by the voltage applied between the second electrode 103 and the third electrode 105, so that it can be crystallized or amorphized to change the resistance of the phase change element 104, thereby changing the data stored in the phase change memory cell 100. When the phase change element 104 is in the crystalline state, the memory cell 100 is in the set (SET) state, and the data stored in the memory cell 100 can be one of "0" and "1". When the phase change element 104 is in the amorphous state, the memory cell 100 is in the reset (RESET) state, and the data stored in the memory cell 100 can be the other of "0" and "1".

[0050] Since amorphization of the phase change element 104 requires a higher temperature, when the memory cell 100 needs to be converted to a reset state, a larger voltage needs to be applied between the second electrode 103 and the third electrode 105 to generate a larger current and more heat. During this process, heat may be transferred to the non-selected memory cell adjacent to the selected memory cell, which may cause thermal crosstalk to the non-selected memory cell adjacent to the selected memory cell, resulting in changes in the crystal phase of the phase change element in the non-selected memory cell. For example, if the non-selected memory cell is in a reset state, the portion of the phase change element in the amorphous state close to the selected memory cell may be converted into a crystalline state after being heated, which may cause misreading when a subsequent read operation is performed on the non-selected memory cell, thereby reducing the reliability of data stored in the phase change memory.

[0051] Therefore, it is necessary to reduce the thermal crosstalk between adjacent memory cells to improve the reliability of the phase change memory. To this end, the present disclosure proposes the following implementations.

[0052] Figure 2 A top view of a partial structure of a phase change memory provided in the disclosed embodiment, Figure 3 for Figure 2 The cross-section along line AA' is Figure 4 for Figure 3 The enlarged schematic diagram of the middle part of the structure, combined with reference Figures 1 to 4 The phase change memory includes: a first conductive line 121, a second conductive line 122 and a storage unit 100 located between the first conductive line 121 and the second conductive line 122 in a first direction; the storage unit 100 extends along the first direction; the first conductive line 121 extends along the second direction and is connected to a plurality of storage units 100 arranged along the second direction; the second conductive line 122 extends along a third direction and is connected to a plurality of storage units 100 arranged along the third direction; a first isolation structure 201, the first isolation structure 201 is located between two adjacent storage units 100 in the second direction, and is located between the second conductive lines 122 respectively connected to the two adjacent storage units 100 in the second direction; the thermal conductivity of the first isolation structure 201 ranges from 0.3W / (m·K) to 0.45W / (m·K).

[0053] In the embodiment of the present disclosure, the second direction intersects with the third direction and is perpendicular to the first direction. Here, the first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction.

[0054] In some specific examples, the first isolation structure 201 includes low temperature silicon oxide. Here, the low temperature silicon oxide is silicon oxide formed by a low temperature atomic layer deposition (LP ALD) process, and the process temperature of the low temperature atomic layer deposition ranges from 45°C to 55°C.

[0055] In a specific example, the process temperature of the low-temperature atomic layer deposition is 50° C., and the thermal conductivity of the low-temperature silicon oxide is about 0.39 W / (m·K).

[0056] In some embodiments, Figure 5 for Figure 2 Cross-section along line BB', combined with reference Figure 2 and Figure 5 The phase change memory also includes: a second isolation structure 202, the second isolation structure 202 is located between two adjacent storage units 100 in the third direction, and is located between the first conductive lines 121 respectively connected to the two adjacent storage units 100 in the third direction; the thermal conductivity of the second isolation structure 202 is less than the thermal conductivity of the first isolation structure 201.

[0057] In some embodiments, reference Figure 2The first isolation structure 201 extends along the third direction and is located between two adjacent second isolation structures 202 in the second direction.

[0058] In some specific examples, the thermal conductivity of the second isolation structure 202 ranges from 0.11 W / (m·K) to 0.2 W / (m·K).

[0059] In a specific example, the second isolation structure 202 includes SixOyCz, wherein the ratio of x, y, and z makes the thermal conductivity of the second isolation structure 202 about 0.14 W / (m·K).

[0060] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The memory cell 100 includes: a first electrode 101, a gating element 102, a second electrode 103, a phase change element 104 and a third electrode 105 which are stacked and arranged in sequence along a first direction; the first electrode 101 is located between the gating element 102 and the first conductive line 121; the third electrode 105 is located between the phase change element 104 and the second conductive line 122. Here, the specific material composition of the memory cell 100 can refer to the aforementioned Figure 1 For the sake of brevity, the description is not repeated here.

[0061] In some specific examples, combined with reference Figure 3 and Figure 4 The phase change memory further includes a first adhesion layer 106 located between the first conductive line 121 and the first electrode 101 and a second adhesion layer 107 located between the second conductive line 122 and the third electrode 105. The first adhesion layer 106 and the second adhesion layer 107 may both include metal nitrides, such as titanium nitride, and the first adhesion layer 106 may improve the adhesion between the first conductive line 121 and the first electrode 101 and reduce the contact resistance, and the second adhesion layer 107 may improve the adhesion between the second conductive line 122 and the third electrode 105 and reduce the contact resistance.

[0062] In some embodiments, reference Figure 4The phase change memory further includes: a third isolation structure 203 and a fourth isolation structure 204, wherein the third isolation structure 203 covers the phase change element 104 of the memory cell 100, the third electrode 105, and the second conductive line 122 connected to the memory cell 100 on the same side of the two opposite sides in the second direction; the fourth isolation structure 204 covers the third isolation structure 203, the second electrode 103, the gating element 102, and the first electrode 101 on the same side of the two opposite sides in the second direction; the fourth isolation structure 204 is located between the first isolation structure 201 and the third isolation structure 203. Here, the memory cell 100 and the second conductive line 122 connected to the memory cell 100 are both provided with the third isolation structure 203 and the fourth isolation structure 204 on the two opposite sides along the second direction, and the third isolation structure 203 and the fourth isolation structure 204 both include dielectric materials and can play a role in sidewall protection to avoid mutual contamination between different material layers.

[0063] In some specific examples, such as Figure 4 As shown, the third isolation structure 203 includes a first dielectric layer 2031 and a second dielectric layer 2032, and the fourth isolation structure 204 includes a third dielectric layer 2041 and a fourth dielectric layer 2042. The first dielectric layer 2031 and the third dielectric layer 2041 may include silicon nitride, and the second dielectric layer 2032 and the fourth dielectric layer 2042 may include silicon oxide.

[0064] In some specific examples, refer to Figure 5 The phase change memory also includes a fifth isolation structure 205 and a sixth isolation structure 206. Both the fifth isolation structure 205 and the sixth isolation structure 206 include dielectric materials and can play a role in sidewall protection to prevent mutual contamination between different material layers. Specifically, the fifth isolation structure 205 covers the same side of the phase change element 104 and the third electrode 105 of the memory cell 100 in the third direction, and the sixth isolation structure 206 covers the same side of the third isolation structure 203, the second electrode 103, the gating element 102, the first electrode 101 and the first conductive line 121 connected to the memory cell 100 in the third direction, and the sixth isolation structure 206 is located between the second isolation structure 202 and the fifth isolation structure 205. The fifth isolation structure 205 includes a fifth dielectric layer 2051 and a sixth dielectric layer 2052, and the sixth isolation structure 206 is a single-layer structure, wherein the fifth dielectric layer 2051 and the sixth isolation structure 206 may include silicon nitride, and the sixth dielectric layer 2052 may include silicon oxide.

[0065] In some specific examples, combined with reference Figure 4 and Figure 5The second conductive line 122 is covered with four dielectric layers on the side walls on the two opposite sides in the second direction and the storage unit 100 is covered with four dielectric layers on the side walls on the two opposite sides in the second direction, and the thermal conductivity of the dielectric layers is relatively high, while the first conductive line 121 is covered with only one dielectric layer on the side walls on the two opposite sides in the third direction. When a reset operation is performed on the selected storage unit, heat is easily transferred along the third direction to the non-selected storage unit adjacent to the selected storage unit in the third direction.

[0066] In a related embodiment, the first isolation structure and the second isolation structure include materials with similar thermal conductivity. In this case, when a reset operation is performed on a selected storage cell, most of the heat will be transferred along a third direction, that is, the extension direction of the second conductive line, to a non-selected storage cell adjacent to the selected storage cell in the third direction, and cause more serious thermal crosstalk to the non-selected storage cell, resulting in a partial transformation of the crystal phase of the phase change element in the non-selected storage cell, thereby reducing the reliability of its stored data.

[0067] In the embodiment of the present disclosure, the phase change memory includes a first isolation structure 201 located between two adjacent memory cells 100 in the second direction and between second conductive lines 122 connected to the two adjacent memory cells 100 in the second direction. The thermal conductivity of the first isolation structure 201 ranges from 0.3W / (m·K) to 0.45W / (m·K), and is greater than the thermal conductivity of the second isolation structure 202 located between two adjacent memory cells 100 in the third direction. Thus, the degree of heat transfer along the second direction when a reset operation is performed on the selected memory cell 100 can be increased, thereby reducing the degree of heat transfer along the third direction and reducing thermal crosstalk to non-selected memory cells adjacent to the selected memory cell in the third direction.

[0068] It should be noted that in the embodiment of the present disclosure, the thermal conductivity of the first isolation structure 201 is greater than a lower limit value but less than an upper limit value. This is because the excessive thermal conductivity of the first isolation structure 201 may cause thermal crosstalk to the non-selected storage unit adjacent to the selected storage unit in the second direction. By limiting the thermal conductivity of the first isolation structure 201 to a suitable range and appropriately increasing the thermal conductivity of the first isolation structure 201, the heat transfer in the second direction and the third direction can be balanced, thereby reducing the thermal crosstalk between the storage units in the phase change memory and improving the reliability of the phase change memory.

[0069] In the above-mentioned embodiments, a phase change memory includes a layer of storage cells arranged in an array along the second direction and the third direction as an example. In other embodiments, the phase change memory may include a plurality of storage layers stacked and arranged along the first direction, and each storage layer includes a first conductive line, a second conductive line, and a storage cell located between the first conductive line and the second conductive line in the first direction, and a first isolation structure located between two adjacent storage cells and between the first conductive lines respectively connected to the two adjacent storage cells, and the thermal conductivity of the first isolation structure ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

[0070] Based on a concept similar to the above-mentioned phase change memory, the present disclosure also provides a method for forming a phase change memory. Figure 6 A schematic diagram of a process flow of forming a phase change memory provided by an embodiment of the present disclosure, such as Figure 6 As shown, the method for forming a phase change memory includes the following steps:

[0071] Step S10: forming a first conductive line extending along a second direction;

[0072] Step S20: forming a storage unit on one side of two opposite sides of the first conductive line along the first direction; the storage unit extends along the first direction; one of the first conductive lines is connected to a plurality of the storage units arranged along the second direction;

[0073] Step S30: forming a second conductive line extending along a third direction on one side of the storage unit that is away from the first conductive line among two opposite sides along the first direction; one second conductive line is connected to a plurality of the storage units arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction;

[0074] Step S40: forming a first isolation structure; the first isolation structure is located between two of the storage units adjacent to each other in the second direction, and between the second conductive lines respectively connected to the two storage units adjacent to each other in the second direction; the thermal conductivity of the first isolation structure ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

[0075] Figures 7 to 11 The structural diagram of the formation process of the phase change memory provided by the embodiment of the present disclosure is as follows. Figures 6 to 11 A method for forming a phase change memory provided by an embodiment of the present disclosure is described.

[0076] In some embodiments, reference Figure 7, the specific process of performing step S10 may include: forming a first conductive line 121 extending along the second direction on the substrate 300, wherein the substrate 300 may include a contact structure and a pad connected to the contact structure, and the contact structure 301 may include a bit line contact structure connected to the first conductive line 121. Here, the structure of the substrate 300 is only an example, and the present disclosure does not specifically limit this.

[0077] In some embodiments, the specific process of performing step S20 may include: forming a storage unit 100 on one side away from the substrate 300 on two opposite sides of the first conductive line 121 along the first direction, the storage unit 100 extending along the first direction and including a first electrode 101, a selection element 102, a second electrode 103, a phase change element 104 and a third electrode 105 stacked in sequence along the first direction, and a first conductive line 121 is connected to a plurality of storage units 100 arranged along the second direction.

[0078] In some specific examples, the specific process of forming the first conductive line 121 may include: forming a conductive layer on the substrate 300, etching the conductive layer to divide the conductive layer into a plurality of first conductive lines 121 extending along the second direction and arranged along the third direction. The specific process of forming the memory cell 100 may include: forming a stacked structure by a deposition process, the stacked structure including a plurality of material layers stacked along the first direction, etching the stacked structure along the second direction and the third direction respectively, to divide the stacked structure into a plurality of memory cells 100 arranged in an array along the second direction and the third direction.

[0079] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0080] In the embodiment of the present disclosure, the etching process can be a dry etching process, including but not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0081] In some embodiments, before executing step S30, the method for forming a phase change memory may further include: forming a second isolation structure 202, the second isolation structure 202 being located between two adjacent storage units 100 in a third direction, and being located between first conductive lines 121 respectively connected to the two adjacent storage units 100 in the third direction; the thermal conductivity of the second isolation structure 202 is less than the thermal conductivity of the first isolation structure 201.

[0082] In some specific examples, the second isolation structure 202 may be formed by a spin coating process, and the thermal conductivity of the second isolation structure may be in a range of 0.11 W / (m·K) to 0.2 W / (m·K).

[0083] In a specific example, the second isolation structure 202 includes SixOyCz, wherein the ratio of x, y, and z makes the thermal conductivity of the second isolation structure 202 about 0.14 W / (m·K).

[0084] In some embodiments, reference Figure 7 The specific process of executing step S30 may include: forming a second conductive line 122 extending along a third direction and a blocking layer 123 located on the second conductive line 122 on one side of the storage unit 100 that is away from the first conductive line 121 on two opposite sides along the first direction; a second conductive line 122 is connected to a plurality of storage units 100 arranged along the third direction.

[0085] In some embodiments, in conjunction with reference Figure 4 and Figure 7 The method for forming a phase change memory also includes: forming a third isolation structure 203, the third isolation structure 203 covers the blocking layer 123, the phase change element 104 of the memory cell 100, the third electrode 105 and the second conductive line 122 connected to the memory cell 100 on the same side of the two opposite sides in the second direction; forming a fourth isolation structure 204, the fourth isolation structure 204 covers the third isolation structure 203, the second electrode 103, the selection element 102 and the first electrode 101 on the same side of the two opposite sides in the second direction.

[0086] In some embodiments, in conjunction with reference Figure 7 and Figure 8 The specific process of executing step S40 may include: filling isolation material between two adjacent storage units 100 in the second direction through a low-temperature atomic layer deposition process to form a first initial isolation structure 210; the top surface of the first initial isolation structure 210 is located between the top surface and the bottom surface of the third electrode 105 in the first direction.

[0087] In some embodiments, in conjunction with reference Figure 8 and Fig. 9The specific process of performing step S40 may include: etching the first initial isolation structure 210 to form a second initial isolation structure 211, wherein the top surface of the second initial isolation structure 211 is located between the top surface and the bottom surface of the phase change element 104 in the first direction.

[0088] In some embodiments, in conjunction with reference Figures 7 to 9 The specific process of performing step S40 may include: filling the isolation material on the second initial isolation structure 211 by a low temperature atomic layer deposition process to form the first isolation structure 201. Specifically, as Fig.10 As shown, in order to allow the isolation material to fully fill the gap between two adjacent memory cells 100 in the second direction, after the isolation material is filled on the second initial isolation structure 211, a third initial isolation structure 212 may be formed, and the top surface of the third initial isolation structure 212 may be higher than the top surface of the barrier layer 123. Fig.11 As shown, the excess isolation material and the barrier layer 123 on the second conductive line 122 can be removed by a chemical mechanical polishing process and / or an etching process, and the remaining isolation material constitutes the first isolation structure 201 .

[0089] In some specific examples, the thermal conductivity of the first isolation structure 201 formed by the above method ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

[0090] In a specific example, the first isolation structure 201 includes low temperature silicon oxide, and the process temperature of the low temperature atomic layer deposition is in a range of 45° C. to 55° C.

[0091] In the embodiment of the present disclosure, return to reference Figure 8 and Fig. 9 When the isolation material is filled between two adjacent storage units 100 by low-temperature atomic layer deposition, due to the small spacing between the adjacent storage units 100, voids may be generated because the growth rate of the thickness of the material layer deposited close to the opening is higher than the growth rate of the thickness of the material layer deposited far from the opening. In this case, by first forming a first initial isolation structure 210 and then etching the first initial isolation structure 210, the void in the first initial isolation structure 210 can be opened, and then the isolation material is continued to be filled on the second initial isolation structure 211, thereby reducing the void in the finally formed first isolation structure 201 and improving the reliability of the first isolation structure 201.

[0092] In an embodiment of the present disclosure, a phase change memory formed by the above-mentioned formation method includes a first isolation structure located between two adjacent storage cells in the second direction and between second conductive lines connected to the two adjacent storage cells in the second direction, and the thermal conductivity of the first isolation structure ranges from 0.3W / (m·K) to 0.45W / (m·K), and is greater than the thermal conductivity of the second isolation structure located between two adjacent storage cells in the third direction. Thus, the degree of heat transfer along the second direction when a reset operation is performed on a selected storage cell can be increased, thereby reducing the degree of heat transfer along the third direction to balance the heat in the two directions and reduce thermal crosstalk to non-selected storage cells adjacent to the selected storage cell in the third direction.

[0093] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0094] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0095] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A phase change memory, characterized in that: include: A first conductive line, a second conductive line, and a storage unit located between the first conductive line and the second conductive line in a first direction; The storage unit extends along the first direction; The first conductive line extends along a second direction and is connected to a plurality of the storage units arranged along the second direction; The second conductive line extends along a third direction and is connected to a plurality of the storage units arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction; A first isolation structure, wherein the first isolation structure is located between two of the storage units adjacent to each other in the second direction, and between the second conductive lines respectively connected to the two storage units adjacent to each other in the second direction; the thermal conductivity of the first isolation structure ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

2. The phase change memory according to claim 1, characterized in that: The first isolation structure includes low temperature silicon oxide.

3. The phase change memory according to claim 1, characterized in that: The phase change memory further comprises: A second isolation structure, wherein the second isolation structure is located between two adjacent storage units in the third direction and between the first conductive lines respectively connected to the two adjacent storage units in the third direction; the thermal conductivity of the second isolation structure is less than the thermal conductivity of the first isolation structure.

4. The phase change memory according to claim 3, characterized in that: The thermal conductivity of the second isolation structure ranges from 0.11 W / (m·K) to 0.2 W / (m·K).

5. The phase change memory according to claim 3, characterized in that: The first isolation structure extends along the third direction and is located between two adjacent second isolation structures in the second direction.

6. The phase change memory according to claim 1, characterized in that: The storage unit comprises: A first electrode, a gating element, a second electrode, a phase change element and a third electrode are stacked and arranged in sequence along the first direction; the first electrode is located between the gating element and the first conductive line; the third electrode is located between the phase change element and the second conductive line.

7. The phase change memory according to claim 6, characterized in that: The phase change memory further comprises: A third isolation structure and a fourth isolation structure; the third isolation structure covers the phase change element of the storage unit, the third electrode and the second conductive line connected to the storage unit on the same side of the two opposite sides in the second direction; the fourth isolation structure covers the third isolation structure, the second electrode, the selection element and the same side of the first electrode on the two opposite sides in the second direction; the fourth isolation structure is located between the first isolation structure and the third isolation structure.

8. The phase change memory according to claim 7, characterized in that: The third isolation structure includes a first dielectric layer and a second dielectric layer; the fourth isolation structure includes a third dielectric layer and a fourth dielectric layer; the second dielectric layer is located between the first dielectric layer and the third dielectric layer; the first dielectric layer and the third dielectric layer include silicon nitride; the second dielectric layer and the fourth dielectric layer include silicon oxide.

9. A method for forming a phase change memory, characterized in that: include: forming a first conductive line extending along a second direction; forming a memory cell on one side of two opposite sides of the first conductive line along a first direction; The storage unit extends along the first direction; one of the first conductive lines is connected to a plurality of the storage units arranged along the second direction; forming a second conductive line extending along a third direction on one side of the storage unit that is away from the first conductive line among two opposite sides along the first direction; One of the second conductive lines is connected to a plurality of the storage units arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction; A first isolation structure is formed; the first isolation structure is located between two adjacent storage units in the second direction, and between the second conductive lines respectively connected to the two adjacent storage units in the second direction; the thermal conductivity of the first isolation structure ranges from 0.3 W / (m·K) to 0.45 W / (m·K).

10. The method for forming a phase change memory according to claim 9, characterized in that: The memory cell comprises a first electrode, a gating element, a second electrode, a phase change element and a third electrode which are sequentially stacked and arranged along the first direction; The first electrode is located between the gating element and the first conductive line; The forming of the first isolation structure comprises: Filling an isolation material between two adjacent storage cells in the second direction by a low temperature atomic layer deposition process to form a first initial isolation structure; the top surface of the first initial isolation structure is located between the top surface and the bottom surface of the third electrode in the first direction; Etching the first initial isolation structure to form a second initial isolation structure, wherein a top surface of the second initial isolation structure is located between the top surface and the bottom surface of the phase change element in the first direction; The isolation material is filled on the second initial isolation structure by the low temperature atomic layer deposition process to form the first isolation structure.

Images