A memory chip, logic chip, chip stack structure and memory

Abstract

The embodiments of the present disclosure provide a storage chip, a logic chip, a chip stack structure and a memory, wherein a center point of an active surface of the storage chip and a region adjacent to the center point are defined as a global signal region; the global signal region is penetrated by n conductive via groups, each of the conductive via groups comprises a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; for the same conductive via group, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory chip, a logic chip, a chip stacking structure, and a memory. Background Technology

[0002] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limitations of existing development techniques, and limits of stored electron density. Against this backdrop, to address the difficulties encountered in two-dimensional semiconductor devices and to pursue lower production costs per unit memory cell, bonding processes (e.g., hybrid bonding, bumping, wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still suffers from problems such as large parasitic capacitance and resistance, affecting signal transmission quality. Summary of the Invention

[0003] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a memory chip, wherein the center point of the active surface of the memory chip and its adjacent area are defined as a global signal region, and the center point of the global signal region coincides with the center point of the active surface;

[0005] The global signal region is penetrated by n groups of conductive vias, where n is a positive integer. Each group of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0006] For the same group of conductive vias, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis;

[0007] The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip.

[0008] In some embodiments, the memory chip further includes n first driving circuits, and the n first driving circuits are coupled one-to-one with the first conductive vias in the n conductive via groups.

[0009] The first driving circuit is used to send the global signal transmitted through the corresponding coupled first conductive via to the internal circuit of the memory chip; or, to send the global signal generated by the internal circuit of the memory chip to the corresponding coupled first conductive via.

[0010] In some embodiments, the conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip are electrically isolated from each other.

[0011] Secondly, this disclosure provides a logic chip in which the center point of the active surface of the logic chip and its adjacent area are defined as a global signal region, and the center point of the global signal region coincides with the center point of the active surface.

[0012] The global signal region is penetrated by n groups of conductive vias, where n is a positive integer. Each group of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0013] For the same group of conductive vias, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis;

[0014] The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the logic chip, and the second axis is parallel to the second side of the logic chip.

[0015] In some embodiments, the logic chip further includes 4n second driving circuits, and the 4n second driving circuits are coupled one-to-one with the 4n conductive vias;

[0016] The second driving circuit is used to send the global signal transmitted through the corresponding coupled conductive via to the internal circuit of the logic chip; or, to send the global signal generated by the internal circuit of the logic chip to the corresponding coupled conductive via.

[0017] In some embodiments, the logic chip further includes n second driving circuits, each of the n second driving circuits corresponding to one of the n conductive via groups, and each second driving circuit being coupled to each conductive via in the corresponding conductive via group;

[0018] The second driving circuit is used to send the global signal transmitted by each of the correspondingly coupled conductive vias to the internal circuit of the logic chip; or, to send the global signal generated by the internal circuit of the logic chip to each of the correspondingly coupled conductive vias.

[0019] In some embodiments, the conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same logic chip are electrically isolated from each other.

[0020] Thirdly, embodiments of this disclosure provide a chip stacking structure, the chip stacking structure including logic chips and at least one stacking unit stacked sequentially along a third direction, each stacking unit including a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked sequentially along the third direction, the third direction being perpendicular to the top surface of each memory chip; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips as described in any one of the first aspects, and the logic chip is a logic chip as described in any one of the second aspects;

[0021] The first memory chip and the second memory chip are stacked face-to-face, the second memory chip and the third memory chip are stacked back-to-back, and the third memory chip and the fourth memory chip are stacked face-to-face.

[0022] The first memory chip and the logic chip in the first stacking unit are stacked back-to-back, or the first memory chip and the logic chip in the first stacking unit are stacked back-to-back; the n conductive via groups in the logic chip correspond one-to-one with the n conductive via groups in each of the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip, and are aligned along the third direction, where n is a positive integer.

[0023] In some embodiments, where the logic chip and the first memory chip are stacked back-to-back,

[0024] The fourth conductive via in the i-th conductive via group of the logic chip, the first conductive via in the i-th conductive via group of each first memory chip, the second conductive via in the i-th conductive via group of each second memory chip, the third conductive via in the i-th conductive via group of each third memory chip, and the fourth conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0025] The third conductive via in the i-th conductive via group of the logic chip, the second conductive via in the i-th conductive via group of each first memory chip, the first conductive via in the i-th conductive via group of each second memory chip, the fourth conductive via in the i-th conductive via group of each third memory chip, and the third conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0026] The second conductive via in the i-th conductive via group of the logic chip, the third conductive via in the i-th conductive via group of each first memory chip, the fourth conductive via in the i-th conductive via group of each second memory chip, the first conductive via in the i-th conductive via group of each third memory chip, and the second conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0027] The first conductive via in the i-th conductive via group of the logic chip, the fourth conductive via in the i-th conductive via group of each first memory chip, the third conductive via in the i-th conductive via group of each second memory chip, the second conductive via in the i-th conductive via group of each third memory chip, and the first conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0028] Where i is a positive integer less than or equal to n.

[0029] In some embodiments, where the logic chip and the first memory chip are stacked back-to-back,

[0030] The second conductive via in the i-th conductive via group of the logic chip, the first conductive via in the i-th conductive via group of each first memory chip, the second conductive via in the i-th conductive via group of each second memory chip, the third conductive via in the i-th conductive via group of each third memory chip, and the fourth conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0031] The first conductive via in the i-th conductive via group of the logic chip, the second conductive via in the i-th conductive via group of each first memory chip, the first conductive via in the i-th conductive via group of each second memory chip, the fourth conductive via in the i-th conductive via group of each third memory chip, and the third conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0032] The fourth conductive via in the i-th conductive via group of the logic chip, the third conductive via in the i-th conductive via group of each first memory chip, the fourth conductive via in the i-th conductive via group of each second memory chip, the first conductive via in the i-th conductive via group of each third memory chip, and the second conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0033] The third conductive via in the i-th conductive via group of the logic chip, the fourth conductive via in the i-th conductive via group of each first memory chip, the third conductive via in the i-th conductive via group of each second memory chip, the second conductive via in the i-th conductive via group of each third memory chip, and the first conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel.

[0034] In some embodiments, for two chips connected face-to-face, the conductive vias aligned along the third direction are electrically connected using a hybrid bonding process; for two chips connected back-to-back or back-to-face, the conductive vias aligned along the third direction are electrically connected using a conductive bump bonding process; or...

[0035] For two chips connected face-to-face, or two chips connected back-to-back, or two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected using the hybrid bonding process; or,

[0036] For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected through the conductive bump bonding process.

[0037] In some embodiments, the global signal generated by the internal circuit of the logic chip enters the fourth conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each first memory chip via the corresponding signal transmission channel, and is transmitted to the internal circuit of each first memory chip via the corresponding connected first driving circuit.

[0038] The global signal generated by the internal circuit of the logic chip enters the third conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the second memory chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the second memory chips via the corresponding connected first driving circuit.

[0039] The global signal generated by the internal circuit of the logic chip enters the second conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the third memory chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the third memory chips via the corresponding connected first driving circuit.

[0040] The global signal generated by the internal circuit of the logic chip enters the first conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the fourth memory chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the fourth memory chips via the corresponding connected first driving circuit.

[0041] In some embodiments, the global signal generated by the internal circuit of the logic chip enters the second conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each first memory chip via the corresponding signal transmission channel, and is transmitted to the internal circuit of each first memory chip via the corresponding connected first driving circuit.

[0042] The global signal generated by the internal circuit of the logic chip enters the first conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the fourth memory chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the fourth memory chips via the corresponding connected first driving circuit.

[0043] The global signal generated by the internal circuit of the logic chip enters the fourth conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the third memory chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the third memory chips via the corresponding connected first driving circuit.

[0044] The global signal generated by the internal circuit of the logic chip enters the third conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the second memory chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the second memory chips via the corresponding connected first driving circuit.

[0045] Fourthly, embodiments of this disclosure provide a memory comprising a chip stacking structure as described in any one of the third aspects.

[0046] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory. By utilizing conductive vias with special symmetry, it not only reduces the number of driving circuits and data selectors, thereby reducing parasitic capacitance, but also achieves signal rotation transmission through the direct connection configuration of the conductive vias in the chip stack structure formed by the memory chip and the logic chip, further reducing parasitic resistance. Furthermore, the conductive via configuration enables point-to-point connections without redundant conductive vias, thus achieving point-to-point connections of global signals with a minimal number of conductive vias, reducing the occupied area of ​​the global signal region, and further reducing the area of ​​the memory chip. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of a chip;

[0048] Figure 2A A schematic diagram of signal transmission in a chip stacking structure. Figure 1 ;

[0049] Figure 2B Schematic diagram 2 of a chip stacking structure for signal transmission;

[0050] Figure 3 A schematic diagram of an active surface in a memory chip provided in an embodiment of this disclosure;

[0051] Figure 4 A schematic diagram of the composition structure of a memory chip provided in this embodiment of the present disclosure. Figure 1 ;

[0052] Figure 5 A schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure is shown below;

[0053] Figure 6 A schematic diagram of an active surface in a logic chip provided in an embodiment of this disclosure;

[0054] Figure 7 A schematic diagram of the composition structure of a logic chip provided in this embodiment of the disclosure. Figure 1 ;

[0055] Figure 8 A schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure is shown below;

[0056] Figure 9 A schematic diagram of the composition structure of a logic chip provided in this embodiment of the disclosure. Figure 3 ;

[0057] Figure 10 This is a schematic diagram of the composition of a chip stacking structure provided in an embodiment of the present disclosure;

[0058] Figure 11A / Figure 11B A specific illustration of a chip stacking structure provided in this embodiment of the present disclosure. Figure 1 ;

[0059] Figure 12A / Figure 12B A second schematic diagram of a chip stacking structure provided in this embodiment of the present disclosure;

[0060] Figure 13 This invention provides a schematic diagram of signal transmission in a chip stacking structure according to an embodiment of the present disclosure. Figure 1 ;

[0061] Figure 14A / Figure 14B A specific illustration of a chip stacking structure provided in this embodiment of the present disclosure. Figure 3 ;

[0062] Figure 15A / Figure 15B A specific illustration of a chip stacking structure provided in this embodiment of the present disclosure. Figure 4 ;

[0063] Figure 16 This is a schematic diagram of signal transmission for a chip stacking structure provided in an embodiment of the present disclosure;

[0064] Figure 17 This invention provides a schematic diagram of signal transmission in a chip stacking structure according to an embodiment of the present disclosure. Figure 3 ;

[0065] Figure 18 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0066] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0068] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0069] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0070] Before introducing the embodiments of this disclosure, we first define three directions that may be used in the plane to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0071] Please see Figure 1 A semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two mutually perpendicular directions are defined, namely a first direction and a second direction, where the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0072] Please see Figure 1 A semiconductor chip includes a substrate. One side of the substrate used to fabricate devices (such as transistors and capacitors) forms the active surface (the side of the substrate opposite to the active surface is the non-active surface, i.e., ...). Figure 1 The bottom surface has multiple metal layers distributed between its substrate and top surface, such as M1, M2, M3, etc. Figure 1The diagram also shows two types of conductive vias (e.g., through-silicon vias), both used to enable signal connections between different stacked chips.

[0073] like Figure 1 As shown, for a type 1 conductive via, it penetrates the bottom surface and the top surface in a third direction, and the conductive via is connected to the internal circuitry of the chip through a metal layer.

[0074] like Figure 1 As shown, for type 2 conductive vias, which penetrate the substrate only along a third direction (penetrating both the active surface and the bottom surface), signal transmission is achieved in conjunction with a contact structure that penetrates the top surface along the third direction. The contact structure and the conductive via are not directly electrically connected, but rather indirectly connected through a metal layer. For example: Figure 1 The contact structure in the middle is connected to M4, and M4 is connected to M1 via M3 and M2 in sequence. M1 is then connected to the conductive via; or... Figure 1 The conductive vias in the chip are connected to the internal circuitry via M1-M4. Figure 1 The input terminal of the device in the substrate, the output signal processed by the internal circuitry of the chip, is then output to the corresponding contact structure via metal layers M1-M4. Similarly, Figure 1 The contact structure in the chip can also be connected to the internal circuitry via M1-M4. Figure 1 The input terminal of the device in the substrate, after being processed by the internal circuitry of the chip, is then output to the corresponding conductive via M1-M4. Of course, in other embodiments, the contact structure and conductive via can also be designed to be directly electrically connected.

[0075] Furthermore, the types of conductive vias are not limited to the two types mentioned above; the examples are merely illustrative. In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the drawings are not necessarily drawn to scale.

[0076] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0077] In one embodiment, a memory chip and a logic chip are provided. Both the memory chip and the logic chip include multiple conductive vias extending through the chip in a third direction. These conductive vias are used to enable signal transmission between different chips, and all conductive vias can be located at any position. Specifically, every four conductive vias can be functionally considered as a group of conductive vias, but the individual positions of these four conductive vias are not limited.

[0078] In one specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. Simultaneously, the conductive vias of the eight memory chips are aligned along a third direction, and the nine aligned conductive vias along the third direction are connected to form an electrical path. See also... Figure 2A It illustrates a signal transmission diagram of a chip stacking structure. Figure 1 .like Figure 2A As shown, the chip stacking structure includes memory chips 0-7 and logic chips. Figure 2A For each memory chip, only 4 conductive vias D0 to D3 are shown, and these 4 conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in 8 memory chips and 1 logic chip are aligned to form a single electrical path, and the conductive vias D1 in 8 memory chips and 1 logic chip are aligned to form a single electrical path... The remaining conductive vias are similar.

[0079] At the same time, each memory chip and logic chip is also equipped with multiple driver circuits. Figure 2A Only one driving circuit is shown in the image (the rest are not shown), and each conductive via is connected to one driving circuit; each memory chip also has multiple data selectors (e.g., Figure 2A In the configuration (mux0~7), each via group corresponds to one data selector. That is, all the vias in a via group are connected to the data port of the data selector through their respective drive circuits. In other words, the data selector can choose which via transmits a signal to the memory chip or which via inputs a signal output from the memory chip.

[0080] For the overall storage device, different regions in different memory chips will be managed by different channels (e.g., CH0, CH1, CH4, CH5). The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "conductive via D0 in logic chip 0, conductive via D0 in memory chip 0, conductive via D0 in memory chip 1, conductive via D0 in memory chip 2, conductive via D0 in memory chip 3, conductive via D0 in memory chip 4, conductive via D0 in memory chip 5, conductive via D0 in memory chip 6, and conductive via D0 in memory chip 7". The selection signal of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 is SEL_C0. That is, the signal Signal_CH0 can enter memory chip 0 and memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0081] As can be seen from the above, memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1, and so on. That is, each memory chip only needs to obtain signals from one of the conductive vias in a group of conductive vias. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with the exact same structure during manufacturing (to maximize cost and labor savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using… Figure 2A In the chip stacking structure shown, each conductive via corresponds to a driving circuit. During the operation of this chip stacking structure, it is necessary to drive all the driving circuits of all memory chips in the same channel. This results in a large load and large parasitic capacitance, which seriously affects the performance of the chips, restricts the transmission efficiency, increases power consumption, and also limits the number of chips stacked in the three-dimensional device.

[0082] In another embodiment, please refer to Figure 2B The diagram illustrates a signal transmission schematic of a chip stacking structure. Specifically, Figure 2B Only some conductive vias (D0~D3) are marked; others are omitted. However, for... Figure 2B For example, the markings for conductive vias aligned along a third direction are the same. Figure 2B As shown, the chip stack structure also includes eight memory chips and one logic chip aligned along a third direction. However, the conductive vias in each memory chip are rotatably connected to another conductive via at a different position in another memory chip, achieving a spiral upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through “conductive via D0 in logic chip 0 – conductive via D1 in memory chip 0 – conductive via D2 in memory chip 1 – conductive via D3 in memory chip 2 – conductive via D0 in memory chip 3 – conductive via D1 in memory chip 4 – conductive via D2 in memory chip 5 – conductive via D3 in memory chip 6 – conductive via D0 in memory chip 7”, and the other signals are similar.

[0083] In this way, memory chip 0 can obtain the signal Signal_CH0 through the output terminal of the conductive via D0 in the logic chip, memory chip 1 can obtain the signal Signal_CH1 through the input terminal of the conductive via D0 in memory chip 0, memory chip 2 can obtain the signal Signal_CH4 through the input terminal of the conductive via D0 in memory chip 1, memory chip 3 can obtain the signal Signal_CH5 through the input terminal of the conductive via D0 in memory chip 2, and so on. For each memory chip, only one conductive via is needed to connect to the driving circuit in each group of conductive vias, and no data selector is required, which reduces the number of devices and thus reduces parasitic capacitance. However, compared to Figure 2A The conductive via direct connection configuration. Figure 2B The process of rotary connection of through-holes in medium-voltage systems is more complex, specifically... Figure 2B A horizontal interconnect structure needs to be set between adjacent conductive vias in each memory chip. Figure 2B (Only one is marked with a pentagram in the image). The signal interconnect structure can be a metal interconnect, a conductive via, etc. To achieve the rotating connection of the conductive via, the input signal signal_CH0 must first be transmitted upwards from the conductive via D0 of the logic chip to the interconnect structure below the conductive via D0 of the memory chip 0 (not directly connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnect structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is: Figure 2B The structure shown requires the signal to pass through the interconnect structure in each memory chip during the signal transmission process, and the output signal is similar. This inevitably leads to an increase in parasitic resistance and also increases the complexity of the manufacturing process.

[0084] In particular, Figure 2A and Figure 2B In the chip stacking structure, all chips are active-facing, meaning that different memory chips are stacked back-to-back, and memory chips and logic chips are also stacked back-to-back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0085] In summary, on the one hand, Figure 2A The chip stacking structure requires numerous conductive vias to transmit the corresponding signals. Combined with the associated driver circuitry and data selectors, this results in a large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to its rotational configuration; on the other hand... Figure 2A and Figure 2BAll existing stacking structures have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if we want to further realize face-to-face chip stacking structures, one approach is to use two sets of masks to create two different chips, one as the active-facing chip and the other as the active-facing chip. This approach has high process complexity and uncontrollable costs. Another approach is to create an additional set of conductive vias and connect both sets of conductive vias to the same driving circuit within the memory chip. However, this leads to complex internal wiring of the memory chip, increasing both process complexity and power consumption.

[0086] Therefore, embodiments of this disclosure propose a memory chip, a logic chip, a chip stacking structure, and a memory. The chip stacking structure not only has small parasitic capacitance and parasitic resistance, but also realizes a face-to-face stacking method. In particular, embodiments of this disclosure also provide a related mechanism for global signal transmission under this structure.

[0087] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0088] In one embodiment of this disclosure, see [link to embodiment]. Figure 3 This illustration shows a schematic diagram of the active surface of a memory chip according to an embodiment of the present disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. Figure 3 As shown, the memory chip 10 includes m channels (m is a positive integer). Figure 3 (Taking m=4 as an example for illustration), m channels are arranged sequentially along the first direction. Each channel includes a first storage array region, a channel signal region, and a second storage array region distributed sequentially along the second direction. The center of each channel signal region coincides with the center of its respective channel.

[0089] It should be noted that, in order to distinguish different channels of the chip during the chip manufacturing process, a positioning structure can be made on the reference channel (e.g., the first channel) of the memory chip 10 so that the position of the reference channel can be identified through the positioning structure during subsequent packaging, and other channels can be identified in combination with the orientation of the active surface of the chip.

[0090] Figure 3 The example shown is m=4, and the following explanation will also use m=4 as an example, but m can be any positive integer.

[0091] like Figure 3 As shown, the center point of the active surface of the memory chip 10 and its adjacent area are defined as the global signal region 11, and the center point of the global signal region 11 coincides with the center point of the active surface; the m channels are symmetrical about the global signal region 11.

[0092] It should be noted that both the global signal region 11 and the channel signal region are penetrated by a plurality of conductive vias along a third direction, and the third direction is perpendicular to the active surface. Here, the conductive vias can be through-silicon vias (TSVs), specifically a vertical interconnect structure that penetrates a silicon wafer / chip, or, in other embodiments, other conductive vias with conductive functions, without specific limitation. In addition, the conductive vias can take the form of type 1 mentioned above, or take the form of type 2 mentioned above.

[0093] For the global signal region 11, each conductive via is used to transmit a global signal, which is shared by all regions of the corresponding memory chip 10. Global signals include, but are not limited to: data signal DQ, power-related signal Voltage Monitor, and timing-related signal Timing Aligner. In some cases, the global signal region 11 may also refer to the pad region. Global signals can be Design For Test (DFT) test signals, through which the operating status of the internal circuitry and the transmission status of related signals can be determined. Furthermore, because the DFT pin pads in the memory chip 10 are generally located in the middle of the chip, the conductive vias for global signals such as DFT are preferably located in a narrower area in the middle of the chip, i.e., such as... Figure 3 The location of the global signal region 11 shown.

[0094] For the channel signal region, each conductive via is used to transmit the channel signal, and the signal transmitted in each channel signal region is only used by its respective channel. The conductive via in each channel signal region is for its own channel signal region, and only a local part of the memory chip 10 (the corresponding channel) will use the conductive via; while the conductive via in the global signal region 11 located in the middle of the memory chip 10 is used to test the entire memory chip 10, and the signal transmitted in the global signal region 11 is shared by m channels of the memory chip 10.

[0095] Please see Figure 3 For the active surface of the memory chip 10, there exists a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. The first axis AA' is parallel to the first side of the memory chip 10, and the second axis BB' is parallel to the second side of the memory chip 10. Figure 3 In this embodiment, the first axis AA' can extend along the first direction, and the second axis BB' can extend along the second direction. In other embodiments, the first axis AA' can also extend along the second direction, and the second axis BB' can extend along the first direction. There is no specific limitation on this.

[0096] Further, see Figure 4 It illustrates a schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure. Figure 1 .like Figure 4 As shown, in the memory chip 10, the global signal region is divided by n conductive vias 20 ( Figure 4 Only one conductive via group 20 is shown in the figure, and the rest are omitted. n is a positive integer. Each conductive via group 20 includes a first conductive via D0, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3.

[0097] In particular, Figure 4 This can be viewed as a cross-sectional view of the memory chip 10 along its active surface. Please refer to [reference needed]. Figure 4 For the same group of conductive vias 20, the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB'.

[0098] It should be noted that the number and position of the conductive via groups 20 in the global signal region can be adjusted according to the actual situation, and there is no specific limitation. However, the number of conductive vias in each conductive via group 20 must be the same, and the symmetrical distribution rule mentioned above must be followed. The following example illustrates this with the global signal region being penetrated by a conductive via group 20, and the number of conductive vias in the conductive via group 20 being 4.

[0099] Understandably, the numbering order of the conductive vias in each conductive via group 20 does not constitute any restriction.

[0100] exist Figure 4 Based on this, see Figure 5 This illustrates a schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure. For example... Figure 5 As shown, in some embodiments, the memory chip 10 further includes n first driving circuits 30 ( Figure 5 Only one first driving circuit 30 is shown in the diagram, the rest are omitted), n first driving circuits 30 and n conductive via groups 20 ( Figure 5 Only one conductive via group 20 is shown in the figure, and the rest are omitted. The first conductive via D0 in the figure corresponds to the coupling.

[0101] The first driving circuit 30 is used to send the global signal transmitted through the corresponding coupled first conductive via D0 to the internal circuit of the memory chip 10; or, to send the global signal generated by the internal circuit of the memory chip 10 to the corresponding coupled first conductive via D0.

[0102] Specifically, the first driving circuit 30 can be coupled to the active surface portion of the first conductive via D0 in the conductive via group 20. That is, for each memory chip 10, only one conductive via in each conductive via group 20 needs to be connected to the first driving circuit 30, and only the global signal transmitted by this conductive via will enter the memory chip 10 or be output from the memory chip 10.

[0103] It should be noted that each driver circuit includes an input driver branch (Receive, RX) and an output driver branch (Transmit, TX). For example, such as... Figure 5 As shown, the input drive branch of the first drive circuit 30 sends the global signal output from the corresponding coupled first conductive via D0 to the internal circuit of the memory chip 10. Specifically, the input drive branches and output drive branches in the other figures will not be labeled further; please refer to the diagram. Figure 5 To achieve an adaptive understanding.

[0104] It should also be noted that the conductive vias mentioned above can at least be categorized as through-silicon vias (TSVs), specifically a vertical interconnect structure that penetrates a silicon wafer / memory chip, for example... Figure 1 Type 1 in the above; of course, conductive vias can also be used. Figure 1 Type 2 in the diagram, together with the contact structure, enables signal transmission. In other embodiments, other electrical connection structures can also be selected as conductive vias.

[0105] In some embodiments, each conductive via in the memory chip 10 can be fabricated by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip 10 are electrically isolated from each other.

[0106] Pre-via technology refers to a via fabrication process where vias are created before the fabrication of devices, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Intermediate via technology involves creating vias during the manufacturing process, often after device fabrication but before the fabrication of stacked layers. Back-via technology involves creating vias from the front side of the wafer after the back-end of line (BEOL) process. Rear-side via technology involves creating vias from the back side of the wafer after the BEOL process. In other words, pre-via technology can refer to creating vias first, then fabricating the circuitry, for example... Figure 1 Type 1 conductive vias; intermediate via fabrication can refer to first fabricating the circuit and part of the metal layer, then fabricating the via, and finally fabricating the remaining vias, for example... Figure 1 Type 2 conductive vias; back-through-hole and reverse-through-hole processes can refer to fabricating the circuitry and metal layers first, and then fabricating the vias last, for example... Figure 1 Type 2 conductive via.

[0107] This disclosure provides a memory chip in which the conductive vias have a special symmetry, allowing direct application to stacked structures configured in any manner, such as face-to-face, back-to-back, or face-to-back, without requiring two sets of masks or two sets of conductive vias. Furthermore, only one conductive via in each group is connected to the first driving circuit, and no data selector is needed for via selection, reducing the number of components compared to... Figure 1 The reduced parasitic capacitance in the memory chip not only saves circuit area but also reduces chip manufacturing costs; subsequently, when the memory chip 10 is formed into a stacked structure, it can also be compared to... Figure 2A and Figure 2B The memory chip reduces parasitic resistance (see subsequent explanation for the specific reasons).

[0108] In another embodiment of this disclosure, see Figure 6 This illustrates a schematic diagram of an active surface in a logic chip provided by an embodiment of this disclosure. For example... Figure 6 As shown, the center point of the active surface of the logic chip 40 and its adjacent signal area are defined as the global signal region 11. The center point of the global signal region 11 coincides with the center point of the active surface, and channel signal regions are distributed on both sides of the global signal region 11.

[0109] Both the global signal region 11 and the channel signal region are traversed by numerous conductive vias along a third direction, and this third direction is perpendicular to the active surface. Furthermore, since the DFT pin pads (PADs) in the logic chip 40 are generally located in the center of the chip, the conductive vias for global signals such as DFT are preferably located in a narrower region in the center of the chip, i.e., ... Figure 6 The location of the global signal region 11 shown.

[0110] In addition, the areas of the logic chip 40 and the memory chip 10 may be the same or different, and no specific limitation is made. However, the global signal regions of both are located in the middle of their respective chips, and the areas of the two global signal regions are the same.

[0111] Please see Figure 6For the active surface of the logic chip 40, there exists a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. The first axis AA' is parallel to the first side of the logic chip 40, and the second axis BB' is parallel to the second side of the logic chip 40. Figure 6 In this example, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation.

[0112] See Figure 7 It illustrates a schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure. Figure 1 .like Figure 7 As shown, in logic chip 40, the global signal region is divided by n conductive vias 50 ( Figure 7 Only one conductive via group 50 is shown in the figure, and the rest are omitted. n is a positive integer. Each conductive via group 50 includes a first conductive via D0, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3.

[0113] In particular, Figure 7 This can be viewed as a cross-sectional view of logic chip 40 along its active surface. Please refer to [reference needed]. Figure 7 For the same group of conductive vias 50, the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB'.

[0114] It should be noted that the number and position of the conductive via groups 50 in the global signal region can be adjusted according to the actual situation, and there is no specific limitation. However, the number of conductive vias in each conductive via group 50 must be the same, and the symmetrical distribution rule mentioned above must be followed. The following example illustrates this with the global signal region being penetrated by a conductive via group 50, and the number of conductive vias in the conductive via group 50 being 4.

[0115] Understandably, the numbering order of the conductive vias in each conductive via group 50 does not constitute any restriction.

[0116] exist Figure 7 Based on this, see Figure 8 This illustrates a schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure. For example... Figure 8 As shown, in some embodiments, the logic chip 40 further includes 4n second driving circuits 60 ( Figure 8 Only four second drive circuits 60 are shown; the rest are omitted. Figure 8Only one of the second driving circuits 60 is shown in the dashed box; the rest of the second driving circuits 60 are not shown in the box. There are 4n second driving circuits 60 and 4n conductive vias. Figure 8 (Only four conductive vias in one conductive via group 50 are shown in the figure; the rest are omitted.) The one-to-one coupling is shown.

[0117] The second driving circuit 60 is used to send the global signal transmitted through the corresponding coupled conductive via to the internal circuit of the logic chip 40; or, to send the global signal generated by the internal circuit of the logic chip 40 to the corresponding coupled conductive via.

[0118] For example, such as Figure 8 As shown, the output drive branch of the second drive circuit 60 outputs the global signal generated by the internal circuit of the logic chip 40 to the corresponding coupled conductive via.

[0119] Specifically, the second driving circuit 60 can be coupled to the active surface portion of a corresponding conductive via in the conductive via group 50. That is, for the logic chip 40, each conductive via in its conductive via group 50 is connected to the second driving circuit 60, and the global signal transmitted by each conductive via will either enter the logic chip 40 or be output from the logic chip 40.

[0120] It should be noted that, in this embodiment, for the same group of conductive vias 50 of the logic chip 40, each conductive via transmits the same type of signal and will further transmit it to different memory chips 10; or, different memory chips 10 transmit the same type of signal to the logic chip 40. Here, although each conductive via in the same group of conductive vias 50 transmits the same type of signal, the signal value transmitted by each conductive via to each memory chip or to the conductive vias therein can be different; it can be logic "1" or logic "0", and there is no specific limitation on this.

[0121] like Figure 9 As shown, in some other embodiments, the logic chip 40 may further include n second driving circuits 60. Figure 9 (Only one second driving circuit 60 is shown in the figure, and the rest are omitted.) The n second driving circuits 60 correspond one-to-one with the n conductive via groups 50, and each second driving circuit 60 is coupled to each conductive via in the corresponding conductive via group 50.

[0122] The second driving circuit 60 is used to send the global signal transmitted through each correspondingly coupled conductive via to the internal circuit of the logic chip 40; or, to send the global signal generated by the internal circuit of the logic chip 40 to each correspondingly coupled conductive via.

[0123] Specifically, the second driving circuit 60 can be coupled to the active surface portion of each conductive via in the corresponding conductive via group 50. That is, for the logic chip 40, each conductive via in its conductive via group 50 is connected to the same second driving circuit 60, and the global signal transmitted by each conductive via will either enter the logic chip 40 or be output from the logic chip 40.

[0124] It should be noted that, in this embodiment, for the same group of conductive vias 50 of the logic chip 40, each conductive via transmits the exact same signal, that is, a signal of the same type and value, and will further transmit it to different memory chips 10; or, different memory chips 10 transmit the exact same signal to the logic chip 40. Therefore, in this case, each group of conductive vias 50 only needs one second driving circuit 60 to drive the signal.

[0125] In some embodiments, each conductive via in the logic chip 40 can be fabricated by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last. Different conductive vias in the same logic chip 40 are electrically isolated from each other.

[0126] This disclosure provides a logic chip, in which the conductive vias are arranged in the same positions as those in the aforementioned memory chip. For details not disclosed in this disclosure, please refer to the description of the foregoing embodiments for clarification.

[0127] In another embodiment of this disclosure, see [reference needed]. Figure 10 This illustrates a schematic diagram of the composition of a chip stacking structure provided in an embodiment of this disclosure. For example... Figure 10 As shown, the chip stacking structure 70 includes logic chips 40 stacked sequentially along a third direction and at least one stacking unit. Figure 10 Only two stacking units are shown (the rest are omitted). Each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13, and a fourth memory chip 14 stacked sequentially along a third direction, with the third direction perpendicular to the top surface of each memory chip. The structures of the first memory chip 11, the second memory chip 12, the third memory chip 13, and the fourth memory chip 14 are all the same as the aforementioned memory chip 10, and the structure of the logic chip 40 is the same as the aforementioned logic chip 40. In particular, in Figure 10 The portion shown is only the global signal region 11 of each chip, not the entire active surface.

[0128] For each stacking unit, the first memory chip 11 and the second memory chip 12 are stacked face to face, the second memory chip 12 and the third memory chip 13 are stacked back to back, and the third memory chip 13 and the fourth memory chip 14 are stacked face to face; the first memory chip 11 and the logic chip 40 in the first stacking unit are stacked back to face, or the first memory chip 11 and the logic chip 40 in the first stacking unit are stacked back to back.

[0129] In this embodiment of the disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned along a third direction, and the center points of the two chips, the first axis AA' and the second axis BB' of the top surfaces are also aligned along a third direction; back-to-back stacking means that the bottom surfaces of two chips are approximately aligned along a third direction; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along a third direction. Unless otherwise specified, "chip" can refer to either a logic chip or a memory chip.

[0130] n conductive via groups in logic chip 40 Figure 10 Only one conductive via group is shown in the figure, and the rest are omitted. It corresponds one-to-one with the n conductive via groups in each first memory chip 11, each second memory chip 12, each third memory chip 13, and each fourth memory chip 14 and is aligned along the third direction, where n is a positive integer.

[0131] It should also be noted that due to process errors, "alignment" in this article is not absolute alignment; deviations within a reasonable range can be considered as alignment.

[0132] In this embodiment, the chip stack structure 70 can specifically be a high-bandwidth memory (HBM) stack product. Particularly, it relates to a situation where each chip is symmetrical in four quadrants (i.e., the via groups are symmetrical about both the first and second axes). The vias in the global signal regions of each chip can enable point-to-point connections between every four layers of memory chips and logic chips. Utilizing the face-to-face and back-to-back symmetry between multiple vias and chips, this is applied to signal transmission in point-to-point designs vias, such as data signals (DQ), power-related signals (Voltage Monitor), and timing-related signals (Timing Aligner), etc., without specific limitations. Here, memory chips can be represented as core dies, and logic chips as base dies.

[0133] It should be noted that, in one possibility, for two chips connected face-to-face, the bonding surfaces (the positions where the conductive vias are aligned along the third direction) are electrically connected using a hybrid bonding process (also known as bonding pillars); for two chips connected back-to-back or back-to-face, the bonding surfaces (the positions where the conductive vias are aligned along the third direction) are electrically connected using a conductive bump bonding process (also known as microbumps).

[0134] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the bonding surfaces (positions where the conductive vias are aligned along a third direction) of both are electrically connected using a hybrid bonding process.

[0135] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the bonding surfaces (positions where the conductive vias are aligned along a third direction) of both are electrically connected through a conductive bump bonding process.

[0136] Here, the above chip can refer to either logic chip 40 or memory chip 10.

[0137] It should be noted that compared to conductive bump bonding, face-to-face bonding using hybrid bonding technology allows for a tighter fit between adjacent memory chips, virtually eliminating gaps. This significantly reduces the height of the chip stack structure, which is one of the advantages of face-to-face stacking. Of course, two memory chips connected back-to-back can also be electrically connected using hybrid bonding, but its connection performance is weaker than that achieved through conductive bump bonding. Thus, in this embodiment, the chip stack structure supports face-to-face stacking, resulting in better performance.

[0138] It should be understood that logic chip 40 or each memory chip can be divided into a high-order transmission area and a low-order transmission area, and the subsequent... Figures 11A to 12B , Figures 14A to 15B The arrows are uniformly located in the high-order transmission area of ​​the chip. Specifically, in this embodiment, the high-order transmission area and the low-order transmission area merely distinguish two areas of the logic chip 40 or each memory chip, and do not have any additional restrictions. They may not be directly related to the high-order and low-order data commonly referred to in data transmission. Furthermore, Figures 10 to 17 This example illustrates only one group of conductive vias within the global signal region. However, there are actually multiple groups of conductive vias in the global signal region, and different groups of conductive vias have similar alignment characteristics. The alignment of other conductive vias is not shown here; please refer to the following text description. Figures 10 to 17 To achieve an adaptive understanding.

[0139] It should be noted that the top surface of the logic chip 40 or each memory chip is divided into 2×2 signal regions, namely the first signal region, the second signal region, the third signal region, and the fourth signal region, denoted by C, D, E, and F. Among them, the first signal region (C) and the second signal region (D) are symmetrical along their own first axis AA', the first signal region (C) and the fourth signal region (F) are symmetrical along their own second axis BB', and the third signal region (E) and the fourth signal region (F) are symmetrical along their own first axis AA'. The first axis AA' of the logic chip 40 and each memory chip are aligned along a third direction, and the second axis BB' of the logic chip 40 and each memory chip are aligned along a third direction.

[0140] It should be noted that the first conductive via D0 in each conductive via group is located in the first signal region (C), the second conductive via D1 in each conductive via group is located in the second signal region (D), the third conductive via D2 in each conductive via group is located in the third signal region (E), and the fourth conductive via D3 in each conductive via group is located in the fourth signal region (F).

[0141] When the logic chip 40 and the first memory chip 11 are stacked back-to-back and the logic chip 40 and the fourth memory chip 14 are arranged in the same way, a first specific implementation method and a second specific implementation method are provided; when the logic chip 40 and the first memory chip 11 are stacked back-to-back and the logic chip 40 and the second memory chip 12 are arranged in the same way, a third specific implementation method and a fourth specific implementation method are provided, as detailed below.

[0142] In the first specific embodiment, such as Figure 11A As shown, assuming that the logic chip 40 and each memory chip's respective first axis AA' divides the chip into a high-order transmission region and a low-order transmission region (i.e., the first axis AA' extends along the first direction), the high-order transmission region of the logic chip 40, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the low-order transmission region of the logic chip 40, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0143] In the second specific embodiment, such as Figure 12AAs shown, assuming that the second axis BB' of each logic chip 40 and each memory chip divides the chip into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the high-order transmission region of the logic chip 40, the low-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the low-order transmission regions of the logic chip 40, the high-order transmission regions of the first memory chip 11, the high-order transmission regions of the second memory chip 12, the low-order transmission regions of the third memory chip 13, and the low-order transmission regions of the fourth memory chip 14 are aligned along the third direction.

[0144] Please see Figure 11A or Figure 12A For the first and second specific embodiments, each signal region has the following alignment relationship:

[0145] (1) The fourth signal area (F) of the logic chip 40, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along a third direction.

[0146] (2) The third signal area (E) of the logic chip 40, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction.

[0147] (3) The second signal area (D) of the logic chip 40, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction;

[0148] (4) The first signal area (C) of the logic chip 40, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0149] It should also be noted that each conductive via group of the logic chip 40 and each memory chip includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3 arranged in a 2×2 array.

[0150] Please see Figure 11B or Figure 12BFor the first and second specific embodiments, only for multiple signal regions aligned along a third direction, each conductive via has the following alignment relationship:

[0151] (1) The fourth conductive via D3 in the i-th conductive via group of logic chip 40, the first conductive via D0 in the i-th conductive via group of each first memory chip 11, the second conductive via D1 in the i-th conductive via group of each second memory chip 12, the third conductive via D2 in the i-th conductive via group of each third memory chip 13, and the fourth conductive via D3 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0152] (2) The third conductive via D2 in the i-th conductive via group of logic chip 40, the second conductive via D1 in the i-th conductive via group of each first memory chip 11, the first conductive via D0 in the i-th conductive via group of each second memory chip 12, the fourth conductive via D3 in the i-th conductive via group of each third memory chip 13, and the third conductive via D2 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0153] (3) The second conductive via D1 in the i-th conductive via group of logic chip 40, the third conductive via D2 in the i-th conductive via group of each first memory chip 11, the fourth conductive via D3 in the i-th conductive via group of each second memory chip 12, the first conductive via D0 in the i-th conductive via group of each third memory chip 13, and the second conductive via D1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0154] (4) The first conductive via D0 in the i-th conductive via group of logic chip 40, the fourth conductive via D3 in the i-th conductive via group of each first memory chip 11, the third conductive via D2 in the i-th conductive via group of each second memory chip 12, the second conductive via D1 in the i-th conductive via group of each third memory chip 13, and the first conductive via D0 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel.

[0155] It should be noted that i is a positive integer less than or equal to n.

[0156] exist Figures 11A to 12B Based on this, see Figure 13 It illustrates a signal transmission diagram of a chip stacking structure provided in an embodiment of this disclosure. Figure 1 .like Figure 13As shown, in one specific embodiment, the global signal generated by the internal circuitry of the logic chip 40 is transmitted via the second driving circuit 60. Figure 13 Only one of the second driving circuits is shown in the dashed box; the remaining second driving circuits are not shown. It enters the fourth conductive via D3 in the i-th conductive via group of the logic chip 40, and reaches the first conductive via D0 in the i-th conductive via group of the first memory chip 11 via the corresponding signal transmission channel, and then passes through the corresponding connected first driving circuit 30. Figure 13 (Only one of the first driving circuits is shown in the dashed box; the remaining first driving circuits are not shown in the box.) The transmission to the internal circuit of each first memory chip 11 is transmitted.

[0157] The global signal generated by the internal circuit of the logic chip 40 enters the third conductive via D2 in the i-th conductive via group of the logic chip 40 via the second driving circuit 60, and reaches the first conductive via D0 in the i-th conductive via group of the second memory chip 12 via the corresponding signal transmission channel, and is transmitted to the internal circuit of each second memory chip 12 via the corresponding connected first driving circuit 30.

[0158] The global signal generated by the internal circuit of the logic chip 40 enters the second conductive via D1 in the i-th conductive via group of the logic chip 40 via the second driving circuit 60, and reaches the first conductive via D0 in the i-th conductive via group of the third memory chip 13 via the corresponding signal transmission channel, and is transmitted to the internal circuit of the third memory chip 13 via the corresponding connected first driving circuit 30.

[0159] The global signal generated by the internal circuit of the logic chip 40 enters the first conductive via D0 in the i-th conductive via group of the logic chip 40 via the second driving circuit 60, and reaches the first conductive via D0 in the i-th conductive via group of the fourth memory chip 14 via the corresponding signal transmission channel, and is transmitted to the internal circuit of the fourth memory chip 14 via the corresponding connected first driving circuit 30.

[0160] Figure 13 The signal transmission path is illustrated using only one conductive via group and two stacked units (i.e., eight memory chips). However, in reality, chip stacking structures can have three, four, or more stacked units, and each stacked unit has similar signal transmission characteristics. The signal transmission situations of other stacked units are not shown here. Please refer to the above text and... Figure 13 To achieve an adaptive understanding.

[0161] like Figure 13As shown, every four layers of memory chips are connected once for transmitting global signals. The global signals transmitted by the memory chips enter the internal circuitry of the corresponding memory chips spaced four layers apart. The intermediate memory chips are only connected but not connected to their internal circuitry. For example, the first memory chip 11 in the first stacking unit is connected to the first memory chip 11 in the second stacking unit (e.g., ...). Figure 13 (As shown by the black dots in the diagram), the first memory chip 11 in the first stacking unit sends the transmitted global signal to the first memory chip 11 in the second stacking unit, but does not enter the second memory chip 12 to the fourth memory chip 14 in the first stacking unit; the second memory chip 12 in the first stacking unit is connected to the second memory chip 12 in the second stacking unit, and the second memory chip 12 in the first stacking unit sends the transmitted global signal to the second memory chip 12 in the second stacking unit, but does not enter the third memory chip 13, the fourth memory chip 14 in the first stacking unit and the first memory chip 11 in the second stacking unit... the remaining memory chips are similar.

[0162] In the third specific embodiment, such as Figure 14A As shown, assuming that the logic chip 40 and each memory chip's respective first axis AA' divides the chip into a high-order transmission region and a low-order transmission region (i.e., the first axis AA' extends along the first direction), the low-order transmission region of the logic chip 40, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the high-order transmission region of the logic chip 40, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0163] In the fourth specific embodiment, such as Figure 15A As shown, assuming that the second axis BB' of each logic chip 40 and each memory chip divides the chip into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the low-order transmission region of logic chip 40, the low-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the high-order transmission region of logic chip 40, the high-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0164] Please see Figure 14A or Figure 15A For the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0165] (1) The second signal area (D) of the logic chip 40, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction;

[0166] (2) The first signal area (C) of the logic chip 40, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction.

[0167] (3) The fourth signal area (F) of the logic chip 40, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction.

[0168] (4) The third signal area (E) of the logic chip 40, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0169] Please see Figure 14B or Figure 15B For the third and fourth specific embodiments, only for multiple signal regions aligned along a third direction, each conductive via has the following alignment relationship:

[0170] (1) The second conductive via D1 in the i-th conductive via group of logic chip 40, the first conductive via D0 in the i-th conductive via group of each first memory chip 11, the second conductive via D1 in the i-th conductive via group of each second memory chip 12, the third conductive via D2 in the i-th conductive via group of each third memory chip 13, and the fourth conductive via D3 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0171] (2) The first conductive via D0 in the i-th conductive via group of logic chip 40, the second conductive via D1 in the i-th conductive via group of each first memory chip 11, the first conductive via D0 in the i-th conductive via group of each second memory chip 12, the fourth conductive via D3 in the i-th conductive via group of each third memory chip 13, and the third conductive via D2 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0172] (3) The fourth conductive via D3 in the i-th conductive via group of logic chip 40, the third conductive via D2 in the i-th conductive via group of each first memory chip 11, the fourth conductive via D3 in the i-th conductive via group of each second memory chip 12, the first conductive via D0 in the i-th conductive via group of each third memory chip 13, and the second conductive via D1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0173] (4) The third conductive via D2 in the i-th conductive via group of logic chip 40, the fourth conductive via D3 in the i-th conductive via group of each first memory chip 11, the third conductive via D2 in the i-th conductive via group of each second memory chip 12, the second conductive via D1 in the i-th conductive via group of each third memory chip 13, and the first conductive via D0 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel.

[0174] exist Figures 14A to 15B Based on this, see Figure 16 This illustrates a second schematic diagram of signal transmission for a chip stacking structure provided in an embodiment of this disclosure. Figure 16 As shown, in another specific embodiment, the global signal generated by the internal circuitry of the logic chip 40 is transmitted via the second driving circuit 60. Figure 16 Only one of the second driving circuits is shown in the dashed box; the remaining second driving circuits are not shown. It enters the second conductive via D1 in the i-th conductive via group of the logic chip 40, and reaches the first conductive via D0 in the i-th conductive via group of the first memory chip 11 via the corresponding signal transmission channel, and then passes through the corresponding connected first driving circuit 30. Figure 16 (Only one of the first driving circuits is shown in the dashed box; the remaining first driving circuits are not shown in the box.) The transmission to the internal circuit of each first memory chip 11 is transmitted.

[0175] The global signal generated by the internal circuit of the logic chip 40 enters the first conductive via D0 in the i-th conductive via group of the logic chip 40 via the second driving circuit 60, and reaches the first conductive via D0 in the i-th conductive via group of the fourth memory chip 14 via the corresponding signal transmission channel, and is transmitted to the internal circuit of the fourth memory chip 14 via the corresponding connected first driving circuit 30.

[0176] The global signal generated by the internal circuit of the logic chip 40 enters the fourth conductive via D3 in the i-th conductive via group of the logic chip 40 via the second driving circuit 60, and reaches the first conductive via D0 in the i-th conductive via group of the third memory chip 13 via the corresponding signal transmission channel, and is transmitted to the internal circuit of the third memory chip 13 via the corresponding connected first driving circuit 30.

[0177] The global signal generated by the internal circuit of the logic chip 40 enters the third conductive via D2 in the i-th conductive via group of the logic chip 40 via the second driving circuit 60, and reaches the first conductive via D0 in the i-th conductive via group of the second memory chip 12 via the corresponding signal transmission channel, and is transmitted to the internal circuit of the second memory chip 12 via the corresponding connected first driving circuit 30.

[0178] Figure 16 The signal transmission path is illustrated using only one conductive via group and two stacked units (i.e., eight memory chips). However, in reality, chip stacking structures can have three, four, or more stacked units, and each stacked unit has similar signal transmission characteristics. The signal transmission situations of other stacked units are not shown here. Please refer to the above text and... Figure 16 To achieve an adaptive understanding.

[0179] Similarly, in Figure 16 In this system, every four layers of memory chips are connected once to transmit global signals. The global signals transmitted by the memory chips enter the internal circuits of the corresponding memory chips spaced four layers apart, while the memory chips in the middle are only connected but not connected to their internal circuits.

[0180] In some embodiments, see Figure 17 It illustrates a signal transmission diagram of a chip stacking structure provided in an embodiment of this disclosure. Figure 3 In particular, Figure 17 It is aimed at Figures 11A to 12B The chip stacking structure shown is illustrated. Additionally, Figure 17 This is only an abstract circuit schematic. The driving circuits (first driving circuit and second driving circuit) are simply placed next to the conductive vias connected to them, without showing the specific connection relationships. Please refer to the text description for a more accurate understanding.

[0181] Please refer to the following: Figure 17 For the chip stack structure 70, the bottom-up signal transmission path will be similar to the following: the fourth conductive via D3 in the logic chip 40 — the first conductive via D0 in the first memory chip 11 — the second conductive via D1 in the second memory chip 12 — the third conductive via D2 in the third memory chip 13 — the fourth conductive via D3 in the fourth memory chip 14… and so on. Other signals are transmitted similarly. That is to say, from a physical perspective, the conductive vias in the chip stack structure 70 are still in a direct-connect configuration. However, from the perspective of the absolute position of the conductive vias on the active surface, the conductive vias can also be considered as a functionally rotating configuration, that is, achieving a similar… Figure 2B The signal transmission effect (i.e., the rotational transmission effect of conductive via D0-conductive via D1-conductive via D2-conductive via D3...). Simply put, Figure 2B The chip stacking structure in the present invention requires a physical spiral structure, which necessarily includes lateral interconnection structures. However, the chip stacking structure 70 in this embodiment is physically a direct connection structure, which does not require lateral interconnection structures. This significantly reduces parasitic resistance and greatly improves transmission speed and transmission performance.

[0182] As can be seen from the above, the memory chip provided in this embodiment not only reduces the number of driving circuits and data selectors, thereby reducing parasitic capacitance, but also reduces parasitic resistance by achieving signal rotation transmission through the direct connection configuration of conductive vias in the chip stack structure formed by the memory chips. Furthermore, for point-to-point connections of global signals, every four layers of memory chips (i.e., one stacking unit) are effective. Utilizing the symmetrical conductive via design in the four quadrants of each chip, only four conductive vias are needed to output point-to-point signals between four memory chips and logic chips. This allows for point-to-point connections of global signals to be achieved with a minimal number of conductive vias, reducing the occupied area of ​​the global signal region and further minimizing the area of ​​the memory chip.

[0183] In another embodiment of this disclosure, see Figure 18 This illustration shows a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. For example... Figure 18 As shown, the memory 80 includes the chip stacking structure 70 described in the foregoing embodiments.

[0184] In some embodiments, the chip stack structure 70 can be applied to the memory 80. The memory 80 can be, for example, Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDR SDRAM), etc., and is not specifically limited here.

[0185] In this embodiment of the disclosure, the chip area of ​​the memory 80 can be reduced, thereby reducing the chip manufacturing cost.

[0186] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0187] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0188] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0189] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0190] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0191] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0192] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0193] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory chip, characterized by, A center point of an active surface of the memory chip and a region adjacent to the center point are defined as a global signal region, and a center point of the global signal region coincides with the center point of the active surface; The global signal region is penetrated by n groups of conductive vias, n is a positive integer, each of the groups of conductive vias includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; For the same group of conductive vias, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis; The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side edge of the memory chip, and the second axis is parallel to a second side edge of the memory chip.

2. The memory chip of claim 1, wherein, The memory chip further includes n first driving circuits, and the n first driving circuits are coupled to the first conductive vias in the n groups of conductive vias one by one; The first driving circuit is configured to send a global signal transmitted by the corresponding first conductive via to an internal circuit of the memory chip, or send the global signal generated by the internal circuit of the memory chip to the corresponding first conductive via.

3. The memory chip of claim 2, wherein: The conductive vias are prepared by any one of a via-first process, a via-middle process, a via-last process, a back side via-last process, or a plurality of processes, and different conductive vias in the same memory chip are electrically isolated from each other.

4. A logic chip, characterized by A center point of an active surface of the logic chip and a region adjacent to the center point are defined as a global signal region, and a center point of the global signal region coincides with the center point of the active surface; The global signal region is penetrated by n groups of conductive vias, n is a positive integer, each of the groups of conductive vias includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; For the same group of conductive vias, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis; The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side edge of the memory chip, and the second axis is parallel to a second side edge of the memory chip.

5. The logic chip of claim 4, wherein, The logic chip further includes 4n second driving circuits, and the 4n second driving circuits are coupled to the 4n conductive vias one by one; The second driving circuit is configured to transmit a global signal transmitted by the corresponding conductive via to an internal circuit of the logic chip, or transmit the global signal generated by the internal circuit of the logic chip to the corresponding conductive via.

6. The logic chip of claim 4, wherein, The logic chip further comprises n second driving circuits, and each of the n second driving circuits is coupled to each of the conductive vias in the corresponding conductive via group. The second driving circuit is configured to transmit a global signal transmitted by each of the corresponding conductive vias to an internal circuit of the logic chip, or transmit the global signal generated by the internal circuit of the logic chip to each of the corresponding conductive vias.

7. The logic chip of claim 5 or 6, wherein The conductive vias are prepared by any one of a via-first process, a via-middle process, a via-last process, a back side via-last process, or a combination of multiple processes, and the conductive vias in the same logic chip are electrically isolated from each other.

8. A chip stack structure, characterized by The chip stacking structure comprises logic chips and at least one stacking unit stacked in a third direction, each stacking unit comprises first, second, third and fourth storage chips stacked in the third direction, and the third direction is perpendicular to the top surface of each storage chip. The first, second, third and fourth storage chips are any one of the storage chips of claims 1-3, and the logic chip is any one of the logic chips of claims 4-7. The first and second storage chips are stacked in a face-to-face manner, the second and third storage chips are stacked in a back-to-back manner, and the third and fourth storage chips are stacked in a face-to-face manner. The first storage chip and the logic chip in the first stacking unit are stacked in a back-to-face manner, or the first storage chip and the logic chip in the first stacking unit are stacked in a back-to-back manner. The n conductive via groups in the logic chip correspond to the n conductive via groups in each of the first, second, third and fourth storage chips one by one and are aligned in the third direction, and n is a positive integer.

9. The chip stacking structure of claim 8, wherein In the case where the logic chip and the first storage chip are stacked in a back-to-back manner, the fourth conductive via in the i-th conductive via group in the logic chip, the first conductive via in the i-th conductive via group in each of the first memory chips, the second conductive via in the i-th conductive via group in each of the second memory chips, the third conductive via in the i-th conductive via group in each of the third memory chips, and the fourth conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a signal transmission channel; the third conductive via in the i-th conductive via group in the logic chip, the second conductive via in the i-th conductive via group in each of the first memory chips, the first conductive via in the i-th conductive via group in each of the second memory chips, the fourth conductive via in the i-th conductive via group in each of the third memory chips, and the third conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a signal transmission channel; the second conductive via in the i-th conductive via group in the logic chip, the third conductive via in the i-th conductive via group in each of the first memory chips, the fourth conductive via in the i-th conductive via group in each of the second memory chips, the first conductive via in the i-th conductive via group in each of the third memory chips, and the second conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a signal transmission channel; the first conductive via in the i-th conductive via group in the logic chip, the fourth conductive via in the i-th conductive via group in each of the first memory chips, the third conductive via in the i-th conductive via group in each of the second memory chips, the second conductive via in the i-th conductive via group in each of the third memory chips, and the first conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a signal transmission channel. wherein i is a positive integer less than or equal to n.

10. The chip stack structure according to claim 8, wherein, in the case where the logic chip and the first memory chip are stacked in a back-to-back manner, the second conductive via in the i-th conductive via group in the logic chip, the first conductive via in the i-th conductive via group in each of the first memory chips, the second conductive via in the i-th conductive via group in each of the second memory chips, the third conductive via in the i-th conductive via group in each of the third memory chips, and the fourth conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a signal transmission channel. the first conductive via in the i-th conductive via group in the logic chip, the second conductive via in the i-th conductive via group in each of the first memory chips, the first conductive via in the i-th conductive via group in each of the second memory chips, the fourth conductive via in the i-th conductive via group in each of the third memory chips, and the third conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a signal transmission channel; the fourth conductive via in the i-th conductive via group in the logic chip, the third conductive via in the i-th conductive via group in each of the first memory chips, the fourth conductive via in the i-th conductive via group in each of the second memory chips, the first conductive via in the i-th conductive via group in each of the third memory chips, and the second conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a signal transmission channel; the third conductive via in the i-th conductive via group in the logic chip, the fourth conductive via in the i-th conductive via group in each of the first memory chips, the third conductive via in the i-th conductive via group in each of the second memory chips, the second conductive via in the i-th conductive via group in each of the third memory chips, and the first conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a signal transmission channel.

11. The chip stack structure according to any one of claims 8-10, wherein, for two chips connected face-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by a hybrid bonding process; for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by a conductive bump bonding process; or, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by the hybrid bonding process; or, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by the conductive bump bonding process.

12. The chip stack structure according to claim 9, wherein, a global signal generated by the internal circuit of the logic chip enters the fourth conductive via in the i-th conductive via group in the logic chip via a second driving circuit, reaches the first conductive via in the i-th conductive via group in each of the first memory chips via a corresponding signal transmission channel, and is transmitted to the internal circuit of each of the first memory chips via a corresponding connected first driving circuit; The global signal generated by the internal circuit of the logic chip enters the third conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the third storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the third storage chips via the corresponding connected first driving circuit. The global signal generated by the internal circuit of the logic chip enters the second conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the third storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the third storage chips via the corresponding connected first driving circuit. The global signal generated by the internal circuit of the logic chip enters the first conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the fourth storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the fourth storage chips via the corresponding connected first driving circuit.

13. The chip stack structure according to claim 10, wherein The global signal generated by the internal circuit of the logic chip enters the second conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the first storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the first storage chips via the corresponding connected first driving circuit. The global signal generated by the internal circuit of the logic chip enters the first conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the fourth storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the fourth storage chips via the corresponding connected first driving circuit. The global signal generated by the internal circuit of the logic chip enters the fourth conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the third storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the third storage chips via the corresponding connected first driving circuit. The global signal generated by the internal circuit of the logic chip enters the third conductive via in the i-th conductive via group in the logic chip via the second driving circuit, and reaches the first conductive via in the i-th conductive via group in each of the second storage chips via the corresponding signal transmission channel, and is transmitted to the internal circuit of each of the second storage chips via the corresponding connected first driving circuit.

14. A memory, comprising: The memory comprises the chip stack structure according to any one of claims 8-13.

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