Preparation method of high-stability oxide semiconductor field effect transistor

Abstract

The invention discloses a preparation method of a high-stability oxide semiconductor field effect transistor, and belongs to the technical field of information materials and devices. According to the method, the oxide semiconductor transistor device covered by the barrier layer material is subjected to high-temperature annealing, and the hydrogen in a channel is effectively released and the proportion of oxygen is maintained by utilizing the difference of the barrier layer material on diffusion coefficients of hydrogen and oxygen, so that the concentration of oxygen vacancies is controlled, and the stability of the oxide semiconductor transistor is improved. Compared with oxide semiconductor field effect transistors prepared by other traditional processes, the oxide semiconductor field effect transistor prepared by the method has better electrical stability and high-temperature stability, and threshold voltage and on-state current are maintained at the same time.

Description

Technical Field

[0001] The invention belongs to the technical field of information materials and devices, and specifically relates to a method for preparing a high-stability oxide semiconductor field effect transistor. Background Art

[0002] Oxide semiconductor materials have high electron mobility (10-100cm 2 / V·s), wide bandgap (~3.0eV), and low process temperature (<300℃). In recent years, with the continuous optimization of materials and preparation processes, the performance of oxide semiconductor transistors has been significantly improved, and they have gradually shown great application potential in display, logic, and storage. However, due to the unique permeation conduction mechanism of oxide semiconductors and their sensitivity to hydrogen and oxygen introduced during the preparation process and the environment, the stability of oxide semiconductor transistors has become a key factor limiting their industrial applications.

[0003] One of the common methods to improve the stability of oxide semiconductor transistors is to adjust the composition of metal elements in the oxide semiconductor film and introduce doping to form a more stable metal-oxygen bond. However, this method will also reduce the carrier concentration of the oxide semiconductor material, reduce the mobility and increase the contact resistance, resulting in the degradation of the on-state current of the transistor. In addition, high-temperature annealing is also an effective method to improve the stability of oxide semiconductors. The high-temperature annealing process can passivate the trap states in the oxide semiconductor channel and the medium, and reduce the hydrogen content. However, this method will also lead to an increase in oxygen vacancies in the oxide semiconductor material, causing the threshold voltage to shift negatively. Therefore, the present invention proposes a barrier layer material for the annealing process of oxide semiconductor transistors, that is, high-temperature annealing is performed under the coverage of the barrier layer. Due to the obvious difference in the diffusion coefficients of hydrogen and oxygen in the barrier layer, hydrogen is diffused outward during the annealing process while blocking the diffusion of oxygen, thereby improving the stability of the device. Summary of the invention

[0004] In order to improve oxide semiconductor transistor devices, the present invention proposes a novel method for preparing a high-stability oxide semiconductor field effect transistor.

[0005] The technical solution of the present invention is as follows:

[0006] A method for preparing a high-stability oxide semiconductor field effect transistor, the steps comprising:

[0007] 1) preparing an oxide semiconductor field effect transistor device, wherein the dielectric layer, insulating layer or passivation layer respectively disposed on and below the oxide semiconductor transistor channel layer of the transistor device are all barrier materials, or barrier material layers are respectively disposed on and below the oxide semiconductor transistor channel layer of the transistor device, and the barrier material is SiO2, SiNx , HfO2, HfSiO or HfLaO;

[0008] 2) Placing the transistor device prepared in step 1) in an annealing furnace for high temperature annealing, wherein the annealing temperature is 300 to 500 degrees Celsius and the annealing time is 1 to 2 hours.

[0009] Furthermore, the structure of the transistor device includes but is not limited to a planar back gate, a top gate, a double gate structure or a three-dimensional fin gate, a surround gate, a ring channel, a stacked nanosheet structure and a vertical channel structure.

[0010] Furthermore, the oxide semiconductor transistor channel material includes but is not limited to In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO, etc., as well as all oxide semiconductor films of various doping components and proportions and composite films of multi-layer oxide film stacks, which can be prepared by processes such as magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition, with a thickness ranging from 1 to 20 nanometers.

[0011] Furthermore, the source and drain contact electrode layers should be made of metal or alloy materials that can form good contact with the oxide channel layer and can withstand subsequent annealing temperatures, including but not limited to oxide materials such as ITO and ZnO or metals such as Pt, Pd, Au, Mo, W, TiN, TaN and their alloy materials, with a thickness ranging from 10 to 60 nanometers.

[0012] Furthermore, the gate dielectric material includes but is not limited to HfO2, HfLaO x 、HfSiO x 、ZrO2、Al2O3、SiN x , SiO2 and other materials can be prepared by chemical vapor deposition, molecular beam epitaxy or atomic layer deposition, with a thickness reference range of 3 to 50 nanometers.

[0013] Furthermore, the barrier material layer is prepared by magnetron sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition, ion beam deposition, laser pulse deposition or atomic layer deposition, and the reference thickness range is 5 to 50 nanometers.

[0014] Furthermore, the annealing gas atmosphere is nitrogen or argon, and is maintained in a low pressure environment of 10 to 50 torr during annealing, and the gas flows evenly through the annealing furnace at a flow rate of 100 to 500 mL / min.

[0015] The beneficial effects of the present invention are as follows:

[0016] The present invention performs high temperature annealing on the oxide semiconductor transistor device covered by the barrier layer material, and utilizes the difference in diffusion coefficients of hydrogen and oxygen in the barrier layer material to effectively release hydrogen in the channel while maintaining the proportion of oxygen, thereby controlling the concentration of oxygen vacancies and improving the stability of the oxide semiconductor transistor. Compared with oxide semiconductor field effect transistors prepared by other traditional processes, the oxide semiconductor field effect transistor prepared by the present invention has better electrical stability and high temperature stability, while the threshold voltage and on-state current are maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A top-gate structure oxide semiconductor field effect transistor device provided in a specific embodiment of the present invention;

[0018] Figure 2 The present invention is a flow chart of a preparation method according to a specific embodiment of the present invention.

[0019] Figure 3 These are the relevant measurement data of the improvement effect of the present invention on the reliability and threshold voltage of oxide semiconductor transistor devices.

[0020] Wherein: 1-substrate, 2-insulating layer, 3-oxide semiconductor channel layer, 4-source / drain metal electrode layer, 5-top gate dielectric layer (blocking layer), 6-top gate electrode layer. DETAILED DESCRIPTION

[0021] The present invention proposes a method for preparing a highly stable oxide semiconductor field effect transistor. The following will be combined with the accompanying drawings and take a top gate structure as an example. Figure 1 As shown, the oxide semiconductor field effect transistor comprises, from bottom to top, a substrate, an insulating layer, an oxide semiconductor channel layer, a source-drain metal electrode layer, a top gate dielectric layer, and a top gate electrode layer. In the embodiment of the present invention, the insulating layer and the top gate dielectric layer of the top gate transistor are both made of blocking materials, which act as blocking layers.

[0022] A method for preparing a highly stable oxide semiconductor field effect transistor provided in a specific embodiment of the present invention comprises the following steps:

[0023] S001: Substrate cleaning. In this embodiment, a high-resistance silicon substrate with 100 nanometers of SiO2 on the surface is selected, and impurities on the substrate are cleaned using a standard RCA1 process. After cleaning, high-purity nitrogen is used to blow dry the substrate. Figure 2 As shown in (1), the silicon oxide layer on the surface serves as an insulating layer.

[0024] S002: Define an oxide semiconductor channel layer on the barrier layer using process steps including magnetron sputtering, coating, baking, photolithography, development, wet etching, and stripping. In this embodiment, the oxide semiconductor channel layer is 3 nanometers of indium tin oxide (ITO), such as Figure 2 As shown in (2).

[0025] S003: Use process steps including coating, baking, photolithography, development, electron beam evaporation, etc. to prepare 5 / 25 nanometer Pt / Au as the metal electrode layer of the source and drain, and use the lift-off technology to complete the definition of the source and drain electrodes. Figure 2 As shown in (3).

[0026] S004: Prepare a top gate dielectric layer using an atomic layer deposition process. In this embodiment, the top gate dielectric layer is 5 nanometers of HfSiO x , the growth temperature is 300 degrees Celsius, such as Figure 2 As shown in (4).

[0027] S005: Use process steps including coating, baking, photolithography, development, electron beam evaporation, etc. to prepare 5 / 25 nanometer Pt / Au as the top gate electrode, and use lift-off technology to complete the definition of the top gate electrode. Figure 2 As shown in (5).

[0028] S006: High temperature annealing. In this embodiment, a tube furnace is used for annealing. The device is placed in the center of the tube furnace and argon gas is introduced at a rate of 100 ml / min. The pressure is 10-50 Torr. The prepared oxide semiconductor transistor is annealed at 500 degrees Celsius for 2 hours.

[0029] like Figure 3 As shown, the transistor prepared by the specific embodiment of the present invention significantly improves the stability of the transistor compared with the prior art, and at the same time achieves more stable electrical performance than the traditional indium tin oxide semiconductor transistor while maintaining a high on-state current.

[0030] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for preparing a high-stability oxide semiconductor field effect transistor, the steps comprising: 1) preparing an oxide semiconductor field effect transistor device, wherein the dielectric layer, insulating layer or passivation layer respectively disposed on and below the oxide semiconductor transistor channel layer of the transistor device are all barrier materials, or barrier material layers are respectively disposed on and below the oxide semiconductor transistor channel layer of the transistor device, and the barrier material is SiO2, SiN x , HfO2, HfSiO or HfLaO; 2) Placing the transistor device prepared in step 1) in an annealing furnace for high temperature annealing, wherein the annealing temperature is 300 to 500 degrees Celsius and the annealing time is 1 to 2 hours.

2. The method for preparing a high-stability oxide semiconductor field effect transistor according to claim 1, characterized in that: The structure of the transistor device is a planar back gate, top gate, double gate structure or a three-dimensional fin-type gate, surround gate, ring channel, stacked nanosheet structure and vertical channel structure.

3. The method for preparing a high-stability oxide semiconductor field effect transistor according to claim 1, characterized in that: The channel material of the oxide semiconductor transistor is In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO and all oxide semiconductor films of various doping components and proportions and composite films of multi-layer oxide film stacks.

4. The method for preparing a high-stability oxide semiconductor field effect transistor according to claim 3, characterized in that: The oxide semiconductor transistor channel material is prepared by magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition technology, and has a thickness ranging from 1 to 20 nanometers.

5. The method for preparing a high-stability oxide semiconductor field effect transistor according to claim 1, characterized in that: The source and drain contact electrode layers of the oxide semiconductor transistor are made of ITO, ZnO oxide materials or Pt, Pd, Au, Mo, W, TiN, TaN metals and alloy materials thereof, with a thickness ranging from 10 to 60 nanometers.

6. The method for preparing a high-stability oxide semiconductor field effect transistor according to claim 1, characterized in that: The gate dielectric material of the oxide semiconductor transistor is HfO2, HfLaO x 、HfSiO x 、ZrO2、Al2O3、SiN x , SiO2 materials, prepared by chemical vapor deposition, molecular beam epitaxy or atomic layer deposition, with a thickness ranging from 3 to 50 nanometers.

7. The method for preparing a high stability oxide semiconductor field effect transistor according to claim 1, characterized in that: The barrier layer is prepared by magnetron sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition, ion beam deposition, laser pulse deposition or atomic layer deposition, and has a thickness ranging from 5 to 50 nanometers.

8. The method for preparing a high-stability oxide semiconductor field effect transistor according to claim 1, characterized in that: The annealing gas atmosphere is nitrogen or argon, and is maintained in a low pressure environment of 10 to 50 torr during annealing, and the gas flows evenly through the annealing furnace at a flow rate of 100 to 500 mL / min.

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