Ferroelectric field effect transistor, memory array and method, memory and electronic equipment

Abstract

The invention provides a ferroelectric field effect transistor, a memory array and method, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the leakage current of the ferroelectric field effect transistor. And the FeFET is a double-gate type transistor. The ferroelectric field effect transistor comprises a substrate, and a first insulating dielectric layer, a first conductive material layer, a second insulating dielectric layer, a ferroelectric material layer and a second conductive material layer which are arranged on the substrate. The substrate comprises a source electrode region and a drain electrode region, a channel between the source electrode region and the drain electrode region is divided into a first channel part and a second channel part, a switch of the first channel part is controlled by the first conductive material layer, and a switch of the second channel part is controlled by the second conductive material layer. The ferroelectric material layer and the second conductive material layer are in lap joint on the side, away from the substrate, of the first conductive material layer. The double-gate FeFET can improve the electric leakage condition of the FeFET, and the ferroelectric material layer is located above the first conductive material layer, so that the interference of the first conductive material layer on the polarization direction of the ferroelectric material layer can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a ferroelectric field effect transistor, a storage array and method, a memory and an electronic device. Background Art

[0002] In recent years, with the development and popularization of semiconductor technology, many new transistors have emerged. Ferroelectric field effect transistors (FeFETs) have attracted widespread attention in the industry due to their advantages such as fast switching speed, high storage density, non-volatile storage, radiation resistance, small size, and low power consumption.

[0003] The working principle of FeFET is to change the threshold voltage of FeFET by changing the direction of the polarization strength of the ferroelectric material layer in FeFET to change the drain current. By reading the size of the drain current, it is possible to determine whether the originally stored information is 0 or 1. However, the current mainstream FeFET has problems of large leakage and high power consumption when the ferroelectric polarity is facing downward due to the variability of the threshold voltage. Summary of the invention

[0004] The embodiments of the present application provide a ferroelectric field effect transistor, a storage array and method, a memory and an electronic device for reducing leakage current in a ferroelectric field effect transistor storage process.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a ferroelectric field effect transistor is provided, and the ferroelectric field effect transistor is a dual-gate transistor. The ferroelectric field effect transistor comprises a substrate and a first insulating dielectric layer, a first conductive material layer, a second insulating dielectric layer, a ferroelectric material layer and a second conductive material layer arranged on the same side of the substrate. The substrate comprises a first doped region and a second doped region, and the first doped region and the second doped region are mutually a source region and a drain region. There is a gap between the first doped region and the second doped region, and the gap serves as a channel of the ferroelectric field effect transistor. Along the direction from the first doped region to the second doped region, the gap is divided into a first part and a second part adjacent to each other; that is, the channel of the ferroelectric field effect transistor is divided into a first part channel and a second part channel, the switch of the first part channel is controlled by the first conductive material layer, and the switch of the second part channel is controlled by the second conductive material layer. The first conductive material layer is arranged on the side of the first insulating dielectric layer away from the substrate and above the first part, and the first conductive material layer is used to control the opening and closing of the first part channel. The first insulating dielectric layer is between the first conductive material layer and the first part. The second insulating dielectric layer is arranged on one side of the substrate, covers the second part, and extends above the first conductive material layer. The ferroelectric material layer is arranged on the side of the second insulating medium layer away from the substrate and covers the second insulating medium layer. The second conductive material layer is arranged on the side of the ferroelectric material layer away from the substrate and covers the ferroelectric material layer. The second conductive material layer is used to control the opening and closing of the second channel.

[0007] The ferroelectric field effect transistor provided by the embodiment of the present application is provided with a first conductive material layer and a second conductive material layer above the gap between the first doped region and the second doped region in the ferroelectric field effect transistor, so that the conduction of the first part of the channel of the ferroelectric field effect transistor is controlled by the first conductive material layer, and the conduction of the second part of the channel of the ferroelectric field effect transistor is controlled by the second conductive material layer, and the ferroelectric field effect transistor is turned on only when the first part of the channel and the second part of the channel are turned on together. In this way, during the data writing and data retention stages, when the ferroelectric polarity is facing downward, even if the second part of the channel is turned on, since the first part of the channel is always kept closed, the first doped region and the second doped region will still not be turned on, thereby greatly reducing the leakage of the ferroelectric field effect transistor to reduce static power consumption. After the leakage of the ferroelectric field effect transistor is reduced, the requirements for the accuracy of the write voltage in the data writing stage can also be reduced, shortening the time of the write operation. Moreover, due to the large leakage of traditional ferroelectric field effect transistors, the traditional ferroelectric field effect transistors need to strictly control the write voltage, so that the polarization intensity can only go through an inner iron hysteresis loop (minor loop) inside the saturated iron hysteresis loop, and the value range of the polarization intensity of the ferroelectric material layer is relatively small. In the present application, after the leakage of the ferroelectric field effect transistor is reduced, the polarization intensity can directly go through the saturated iron hysteresis loop, which can increase the value range of the polarization intensity of the ferroelectric material layer in the ferroelectric field effect transistor. Furthermore, since the ferroelectric material layer is located on the side of the first conductive material layer away from the substrate, then when the first conductive material layer is working, it will not affect the polarization direction of the ferroelectric material layer, reduce the interference of the ferroelectric material layer, and improve the accuracy of stored information.

[0008] In a possible implementation, the first part is close to the first doping region, and the second part is close to the second doping region; the first doping region is the drain region, and the second doping region is the source region. By placing the second conductive material layer close to the source region, when writing, after applying a write voltage to the second conductive material layer, the second conductive material layer directly forms a current loop with the source region through the second part in the channel, thereby completing the control of the polarization reversal of the ferroelectric material layer, without passing through the first part under the first conductive material layer, and therefore, there is no need to pay attention to the voltage applied to the first conductive material layer. However, if the second conductive material layer is placed close to the drain region, not only the second part under the second conductive material layer needs to be turned on, but also the first part under the first conductive material layer needs to be turned on, so it is necessary to control the voltage of the first conductive material layer, which increases the complexity of control.

[0009] In a possible implementation, the gap is divided into a first part and a second part, so that the design can be simplified.

[0010] In a possible implementation, the projection of the second conductive material layer on the substrate does not cover the projection of the first conductive material layer on the substrate. In this way, the first part of the channel below the first conductive material layer is controlled by the first conductive material layer, but not by the second conductive material layer, thereby ensuring the performance of the ferroelectric field effect transistor. Moreover, when forming a via hole electrically connected to the back-end process wiring layer above the first conductive material layer, it is not necessary to pass through the second conductive material layer, thereby simplifying the process difficulty.

[0011] In a possible implementation, the material of the ferroelectric material layer includes perovskite, hafnium oxide-based material or sphalerite. The ferroelectric field effect transistor provided in the present application can directly use existing ferroelectric material layer materials without the need to develop new materials, and the production cost is low.

[0012] In a possible implementation, the materials of the first insulating dielectric layer and the second insulating dielectric layer include silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide or niobium pentoxide. In this application, a technically mature insulating dielectric material can be directly selected without developing a new insulating dielectric material.

[0013] In a possible implementation, the materials of the first conductive material layer and the second conductive material layer include metal or polysilicon. In the present application, a conductive material with mature technology can be directly selected without developing a new conductive material.

[0014] According to a second aspect of an embodiment of the present application, a storage array is provided, comprising: a plurality of first word lines, all extending in a first direction; a plurality of second word lines, all extending in the first direction; a plurality of bit lines, all extending in a second direction, the second direction intersecting with the first direction; a reference ground terminal; a plurality of ferroelectric field effect transistors of any one of the first aspects; a plurality of ferroelectric field effect transistors arranged in a plurality of rows and columns, the row direction being parallel to the first direction; a first conductive material layer of the ferroelectric field effect transistors in the same row being electrically connected to the same first word line, and a second conductive material layer of the ferroelectric field effect transistors in the same row being electrically connected to the same second word line; a first doped region of the ferroelectric field effect transistors in the same column being electrically connected to the same bit line; and second doped regions of the plurality of ferroelectric field effect transistors being electrically connected to the reference ground terminal.

[0015] According to a third aspect of the embodiments of the present application, a memory is provided, including: a controller; and the memory array of the second aspect; the controller is electrically connected to the memory array.

[0016] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising: a circuit board; and the memory of the third aspect; the circuit board and the memory are electrically connected.

[0017] The fifth aspect of the embodiment of the present application provides a method for reading and writing a storage array, wherein the storage array includes the storage array of the second aspect; the method for reading and writing includes: a data writing phase: applying a reference ground voltage to a first doped region of a ferroelectric field effect transistor, applying a reference ground voltage to a second doped region of the ferroelectric field effect transistor, applying a reference ground voltage to a first conductive material layer of the ferroelectric field effect transistor, and applying a write voltage to the second conductive material layer of the ferroelectric field effect transistor. A data retention phase: applying a reference ground voltage to the first doped region, the second doped region, the first conductive material layer, and the second conductive material layer. A data reading phase: applying a power supply voltage to the first doped region, applying a reference ground voltage to the second doped region, applying a reference voltage to the second conductive material layer, applying a read voltage to the first conductive material layer, and reading a signal from the first doped region.

[0018] In a possible implementation, the absolute value of the write voltage is greater than the coercive voltage, and the read voltage is equal to the power supply voltage.

[0019] According to a sixth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes computer instructions. When the computer instructions are executed on a device, the device executes the reading and writing method of the fifth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 An architecture diagram of an electronic device provided in an embodiment of the present application;

[0022] Figure 2 A framework diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 3 An architectural diagram of a storage device provided in an embodiment of the present application;

[0024] Figure 4A A schematic diagram of the structure of a MOSFET according to an embodiment of the present application;

[0025] Figure 4B A switching characteristic curve diagram of a MOSFET illustrated in an embodiment of the present application;

[0026] Figure 4CA schematic diagram of the structure of a FeFET illustrated in an embodiment of the present application;

[0027] Figure 4D A polarization intensity curve diagram of a dielectric material illustrated in an embodiment of the present application;

[0028] Figure 4E A ferroelectric hysteresis loop diagram of a ferroelectric material illustrated in an embodiment of the present application;

[0029] Figure 4F A schematic diagram of a FeFET with its polarization direction facing downwards, as shown in an embodiment of the present application;

[0030] Figure 4G A schematic diagram of an FeFET with its polarization direction facing upwards, as shown in an embodiment of the present application;

[0031] Figure 4H A curve diagram of drain current of a FeFET in different polarization directions illustrated in an embodiment of the present application;

[0032] Figure 5A A schematic diagram of the structure of a FeFET provided in an embodiment of the present application;

[0033] Figure 5B A schematic diagram of the structure of another FeFET provided in an embodiment of the present application;

[0034] Fig. 6A A schematic diagram of an equivalent circuit structure of a FeFET provided in an embodiment of the present application;

[0035] Figure 6B A schematic diagram of an equivalent circuit structure of another FeFET provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of a FeFET provided in an embodiment of the present application;

[0037] Figure 8A-8L A schematic diagram of a preparation process of a FeFET provided in an embodiment of the present application;

[0038] Fig. 9 A schematic diagram of the structure of a storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0040] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0041] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0042] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0043] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0044] An electronic device is provided in an embodiment of the present application. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product. Among them, consumer electronic products are such as mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products are such as smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (such as soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc. Financial terminal products are such as automated teller machines (ATMs), self-service terminals, etc. Communication electronic products are such as communication equipment such as servers, storage devices, radars, and base stations.

[0045] Figure 1 An architectural diagram of an electronic device provided in an embodiment of the present application.

[0046] An example of an electronic device such as Figure 1 As shown, an electronic device is exemplified, such as Figure 1 As shown, the electronic device 1 includes: a memory 11, a processor 12, an input device 13, an output device 14 and other components. Those skilled in the art can understand that Figure 1 The architecture of the electronic device 1 shown in the figure does not constitute a limitation on the electronic device 1, and the electronic device 1 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0047] The memory 11 is used to store software programs and modules. The memory 11 mainly includes a program storage area and a data storage area. The program storage area can store and back up an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc.

[0048] The processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect various parts of the entire electronic device 1. By running or executing software programs and / or modules stored in the memory 11, and calling data stored in the memory 11, it executes various functions of the electronic device 1 and processes data, thereby monitoring the electronic device 1 as a whole. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), etc. Among them, different processing units may be independent devices or integrated into one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 12. The above-mentioned application processor may be, for example, a central processing unit (CPU).

[0049] The input device 13 is used to receive input digital or character information, and to generate key signal input related to user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. A touch screen, also known as a touch panel, can collect user touch operations on or near the touch screen (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen), and drive corresponding connection devices according to a pre-set program.

[0050] The output device 14 is used to output the input of the input device 13 and the signal corresponding to the data stored in the memory 11. For example, the output device 14 outputs a sound signal or a video signal.

[0051] Continue to refer Figure 1 The memory 11 includes a controller and a storage array. The controller is electrically connected to the storage array, and the controller is used to control the reading and writing of the storage array.

[0052] The storage array includes a plurality of storage units arranged in an array, and the storage density of the storage units directly affects the storage density of the storage array.

[0053] In order to further explain the structure of the electronic device 1 , the following is an exemplary introduction using the electronic device 1 as a mobile phone as an example.

[0054] Figure 2 A framework diagram of an electronic device provided in an embodiment of the present application.

[0055] like Figure 2 As shown, the electronic device 1 may further include a middle frame 15, a rear shell 16, and a display screen 17. The rear shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15, and the middle frame 15 and the display screen 17 are arranged in the rear shell 16. The middle frame 15 includes a carrier plate 150 for carrying the display screen 17, and a frame 151 surrounding the carrier plate 150.

[0056] Continue to see Figure 2 The electronic device 1 may further include a circuit board 18 , which is disposed on a side of the carrier board 150 close to the rear shell 16 . The memory 11 in the electronic device 1 may be disposed on the circuit board 18 , and the memory 11 is electrically connected to the circuit board 18 .

[0057] Memories can be divided into volatile memories and non-volatile memories. Dynamic random access memory (DRAM) occupies a large market due to its advantages of fast read and write speed and strong durability. However, with the rapid development of the Internet of Things, big data and artificial intelligence, its small storage capacity and high power consumption can no longer meet the requirements.

[0058] As a new type of memory, ferroelectric memory has become one of the mainstream internal memories due to its non-volatility of stored data, fast access rate, low read and write voltage, low power consumption, small device size, good durability, non-volatility, good cycle performance and radiation resistance.

[0059] Figure 3 An architectural diagram of a memory provided in an embodiment of the present application.

[0060] like Figure 3 As shown, the memory 11 includes a memory array 210, a decoder 220, a driver 230, a timing controller 240, a buffer 250 and an input / output driver 260. The memory array 210 includes a plurality of memory cells 200 arranged in an array.

[0061] Ferroelectric field effect transistor (FeFET) has gradually become a mainstream transistor due to its advantages such as fast switching speed, high storage density, non-volatile storage, radiation resistance, small size, and low power consumption. Therefore, ferroelectric memory based on FeFET has also gradually become a mainstream memory.

[0062] Metal-oxide-semiconductor field-effect transistor (MOSFET) is the basic unit device of integrated circuits. According to the different carrier types, MOSFET is divided into N-channel type (NMOS) and P-channel type (PMOS). Figure 4A As shown, taking MOSFET as NMOS as an example, MOSFET includes source S, drain D, gate G and body terminal B, body terminal B can be coupled to the reference ground voltage terminal, and a gate insulating dielectric layer is provided under gate G. By changing the voltage of gate G, the resistance between source S and drain D is controlled, and then the current flowing through source S and drain D is controlled to realize the switching characteristics of MOSFET. The voltage of the on-state and off-state transition is called the threshold voltage Vt. Figure 4B As shown in the figure, when the threshold voltage Vt is about 2V, no matter the drain voltage Vd is 1V, 2V, 3V or 4V, when the voltage of the gate G is greater than the threshold voltage Vt, the MOSFET is turned on, and there is a drain current between the source S and the drain D, but the drain current is different when the drain voltage Vd is different. When the voltage of the gate G is less than the threshold voltage Vt, the MOSFET is turned off, and the drain current between the source S and the drain D is almost zero.

[0063] like Figure 4C As shown, FeFET is based on MOSFET, and the gate insulating dielectric layer under the gate G is changed to a ferroelectric material layer.

[0064] When an electric field (voltage) is applied to the gate insulating dielectric layer, an electric dipole is generated due to the relative movement of polarized charges inside the gate insulating dielectric layer. Its electric dipole moment is called the electric dipole moment. The (electric) polarization intensity is defined as the density of the electric dipole moment. Figure 4D As shown in , the relationship between the polarization intensity (polarization, P) of the dielectric material and the external electric field E is a linear relationship. When the external electric field E is 0, the polarization intensity P is 0. Figure 4E As shown in Figure 2, the relationship between the polarization intensity P of the ferroelectric material and the applied electric field E is nonlinear, which is usually called the ferrohysteresis loop ( Figure 4E The figure shows the saturated iron hysteresis loop. Figure 4EIn it, Pr is the residual polarization intensity, and Ec is the coercive electric field. The residual polarization intensity Pr is the intersection of the saturated iron hysteresis loop and the vertical axis (P axis). There are two intersection points +Pr and -Pr in the saturated iron hysteresis loop, which are used to indicate that when the external electric field E is 0, the residual polarization intensity Pr may be positive or negative. The positive and negative signs of Pr can be used to define whether the stored information is 0 or 1. Ec is the intersection of the saturated iron hysteresis loop and the horizontal axis (E axis). There are two intersection points +Ec and -Ec in the saturated iron hysteresis loop. The stored information can be changed by applying a positive or negative electric field with an absolute value greater than the coercive electric field Ec.

[0065] The saturated iron hysteresis loop moves according to the following rules: When the external positive electric field is greater than Ec, the polarization intensity P is positive and is in the first quadrant. As the external electric field E decreases, the polarization intensity P decreases accordingly. When the external electric field E decreases to 0, the polarization intensity P is +Pr. Then, when the external electric field E changes direction (changes to negative), the polarization intensity P starts to decrease from +Pr and enters the second quadrant. If the absolute value of the external electric field E is less than Ec, the external electric field E disappears and the polarization intensity P returns to Pr. When the absolute value of the external electric field E is greater than Ec and continues to increase, the polarization intensity P will change from positive to negative and enter the third quadrant. At this point, the reversal of the polarity of the ferroelectric material from positive to negative is completed. The reversal of the polarity of the ferroelectric material from negative to positive is similar. If the applied positive electric field does not exceed Ec, then when the electric field disappears, the polarization intensity P is -Pr. If the applied positive electric field exceeds Ec, it enters the first quadrant.

[0066] The non-volatility of ferroelectric materials comes from the ferrohysteresis loop. When the external electric field disappears, the polarization intensity of the material is either at +Pr or -Pr, thus achieving the characteristic of not losing information when the power is off.

[0067] During the information writing process, the source S and drain D of the FeFET are grounded GND, and a write voltage Vwrite with an absolute value greater than the coercive voltage Vc is applied to the gate G to flip the polarity of the ferroelectric material layer. If the voltage polarity applied to the gate G is positive (negative), the polarity of the information stored in the ferroelectric material layer is upward (downward).

[0068] When information needs to be retained (not in the reading or writing process), the gate G, source S and drain D are all grounded to GND. From the saturated ferroelectric hysteresis loop, it can be seen that when the external electric field E is 0, the ferroelectric material has +Pr or -Pr, and the information is preserved.

[0069] During the information reading process, the source S is grounded GND, the gate G applies an appropriate reference voltage Vref, and the drain D applies a read voltage Vread. Due to the effect of ferroelectric polarity, the positive (negative) polarity will increase (decrease) the threshold voltage Vt of the FeFET accordingly. Figure 4F and Figure 4HAs shown in Figure 1, under the appropriate reference voltage Vref, when the ferroelectric polarity is facing upward, the drain current Id is almost zero. Figure 4G and Figure 4H As shown, when the ferroelectric polarity is downward, the drain current Id is not 0. By reading the size of the drain current Id, it is possible to determine whether the originally stored information is 0 or 1.

[0070] Based on this, Figure 3 The decoder 220 in the memory array 210 can decode according to the received address to determine the memory cell 200 in the memory array 210 that needs to be accessed. The driver 230 is used to generate a control signal according to the decoding result output by the decoder 220, and the control signal is transmitted to the gate G of the FeFET through the word line WL to control the FeFET to be turned on or off, thereby realizing access to the specified memory cell 200. The bit line BL is coupled to the drain D of the FeFET to read the drain current of the FeFET. The buffer 250 receives the data signal output by the memory cell 200 through the bit line BL, and is used to cache the data signal, for example, first-in first-out (FIFO) can be used for caching. The timing controller 240 is used to control the timing of the buffer 250, and control the driver 230 to drive the memory array 210. The input and output driver 260 is used to transmit data signals, such as receiving data signals or sending data signals.

[0071] From the above description, it can be seen that the working principle of FeFET is to change the direction of the polarization intensity of the ferroelectric material layer (upward or downward), thereby changing the threshold voltage Vt of FeFET (increase or decrease). When the ferroelectric polarity is downward, the threshold voltage Vt of FeFET will decrease and the leakage will increase. In some scenarios, such as when the absolute value of the polarization intensity P is large, the threshold voltage Vt of FeFET will become very small or even a negative threshold voltage. At this time, the leakage of FeFET will become very large, causing the power consumption of the memory to increase. When the ferroelectric polarity is downward and the threshold voltage is negative, FeFET will also become a depletion-type transistor. When the gate voltage Vg is 0, FeFET will be in the on state, causing greater leakage and high energy consumption.

[0072] The state of the write operation is closely related to the polarization intensity (absolute value) of the ferroelectric material. If you want to ensure that the threshold voltage Vt of the FeFET is not too small by precisely adjusting the polarization intensity to reduce leakage, you need to precisely adjust the write operation process, which requires a high level of write voltage accuracy. Figure 4E The minor loop shown in FIG. 1 takes longer for write operations.

[0073] Based on this, an embodiment of the present application provides a new FeFET for reducing the leakage current of the FeFET.

[0074] Figure 5A-Figure 5B A schematic diagram of the structure of a FeFET provided in an embodiment of the present application.

[0075] like Figure 5A As shown, the FeFET provided in the embodiment of the present application includes a substrate 20, a first insulating dielectric layer 30, a first conductive material layer 40, a second insulating dielectric layer 50, a ferroelectric material layer 60, and a second conductive material layer 70. The first conductive material layer 40 and the second conductive material layer 70 are both used as the gate of the FeFET provided in the embodiment of the present application. The FeFET provided in the embodiment of the present application can be understood as a ferroelectric field effect transistor with a discrete gate (split-gate-FeFET). Hereinafter, the FeFET provided in the embodiment of the present application is referred to as a split-gate-FeFET to distinguish it from the FeFET in the related art.

[0076] For example, the substrate 20 includes a first doping region 21 and a second doping region 22, and the first doping region 21 and the second doping region 22 are the source region and the drain region of the split-gate-FeFET. Figure 5A As shown, the first doped region 21 is the drain region D', and the second doped region 22 is the source region S'. Figure 5B As shown, the first doped region 21 is the source region S', and the second doped region 22 is the drain region D'.

[0077] There is a gap between the first doped region 21 and the second doped region 22, and the gap can be understood as the channel of the split-gate-FeFET. Along the direction from the first doped region 21 to the second doped region 22 (the length direction of the channel), the gap is divided into adjacent first parts W1 and second parts W2. The boundary line between the first part W1 and the second part W2 can, for example, coincide. The boundary line between the first part W1 and the second part W2 extends along the width direction of the channel, and the boundary line can be a straight line or a curve, which is not limited in the embodiments of the present application. The dimensions of the first part W1 and the second part W2 in the channel width direction can be equal, for example, both are equal to the width of the channel.

[0078] In some embodiments, the gap is equally divided into a first portion W1 and a second portion W2. Alternatively, the size of the first portion W1 along the channel length direction is equal to the size of the second portion W2 along the channel length direction. In this way, the design can be simplified.

[0079] In other embodiments, the gap may be unequally divided into the first part W1 and the second part W2 according to the requirements of the process node. For example, the size of the first part W1 along the channel length direction is greater or smaller than the size of the second part W2 along the channel length direction.

[0080] The substrate 20 is, for example, a semiconductor substrate, and the material of the substrate 20 can be, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, etc. A well region (well) is also provided on the substrate 20, and the first doping region 21 and the second doping region 22 are doping regions of the same type, and the first doping region 21 and the second doping region 22 are N-type doping regions and P-type doping regions with the well region. When the first doping region 21 and the second doping region 22 are N-type doping regions and the well region is a P-type doping region, the split-gate-FeFET is an N-type transistor. When the first doping region 21 and the second doping region 22 are P-type doping regions and the well region is an N-type doping region, the split-gate-FeFET is a P-type transistor. Among them, the doping type of the channel region is the same as the doping type of the well region, or the portion of the well region between the first doping region 21 and the second doping region 22 is used as the channel region of the split-gate-FeFET.

[0081] The first insulating dielectric layer 30 is disposed on one side of the substrate 20 and covers the first portion W1. For example, the projection of the first insulating dielectric layer 30 on the substrate 20 overlaps with the first portion W1. The first insulating dielectric layer 30 can be understood as a gate insulating dielectric layer, and the material of the first insulating dielectric layer 30 can include, for example, silicon oxide, silicon nitride, etc.

[0082] The first conductive material layer 40 is disposed on the side of the first insulating dielectric layer 30 away from the substrate 20 and covers the first insulating dielectric layer 30. For example, the projection of the first conductive material layer 40 on the substrate 20 overlaps with the first portion W1. The first conductive material layer 40 can be understood as a select gate (SG), which is equivalent to a selector switch of a memory cell. The material of the first conductive material layer 40 can be, for example, a conductive material such as metal or polysilicon.

[0083] The second insulating dielectric layer 50 and the first insulating dielectric layer 30 are disposed on the same side of the substrate 20 . The second insulating dielectric layer 50 covers the second portion W2 and extends to above the first conductive material layer 40 (away from the substrate 20 ).

[0084] For example, the second insulating dielectric layer 50 overlaps with the first conductive material layer 40, the second insulating dielectric layer 50 does not completely cover the first conductive material layer 40, and the second insulating dielectric layer 50 exposes a portion of the first conductive material layer 40. Alternatively, it can be understood that the projection of the second insulating dielectric layer 50 on the substrate 20 overlaps with the projection of the first conductive material layer 40 on the substrate 20, but the projection of the second insulating dielectric layer 50 on the substrate 20 does not cover the projection of the first conductive material layer 40 on the substrate 20. For example, the projection of the second insulating dielectric layer 50 on the substrate 20 covers the second portion W2 and overlaps with the first portion W1. The material of the second insulating dielectric layer 50 may include, for example, silicon oxide, silicon nitride, etc.

[0085] The ferroelectric material layer 60 is disposed on the side of the second insulating dielectric layer 50 away from the substrate 20 and covers the second insulating dielectric layer 50. For example, the projection of the ferroelectric material layer 60 on the substrate 20 coincides with the projection of the second insulating dielectric layer 50 on the substrate 20. Then, the second insulating dielectric layer 50 is spaced between the ferroelectric material layer 60 and the first conductive material layer 40, and the ferroelectric material layer 60 does not contact the first conductive material layer 40.

[0086] The material of the ferroelectric material layer 60 includes, for example, perovskite, hafnium oxide-based material, zinc blende, and the like.

[0087] For example, the hafnium oxide-based material can be a ferroelectric material based on the hafnium oxide (HfO) material system. For example, the material of the ferroelectric material layer 60 can be zirconium (Zr)-doped hafnium dioxide (HfO2), silicon (Si)-doped HfO2, aluminum (Al)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, gadolinium (Gd)-doped HfO2, strontium (Sr)-doped HfO2, etc.

[0088] Alternatively, the hafnium oxide-based material may also be a ferroelectric material of the hafnium zirconium oxide (HZO) material system. For example, the material of the ferroelectric material layer 60 may be lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium-lanthanum (Gd / La) co-doped HZO, etc. The doping element may also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, and carbon.

[0089] Alternatively, the hafnium oxide-based material may also be a ferroelectric material from a material system such as hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium zirconium yttrium oxide, or hafnium zirconium gadolinium oxide.

[0090] The second conductive material layer 70 is disposed on the side of the ferroelectric material layer 60 away from the substrate 20 and covers the ferroelectric material layer 60. For example, the projection of the second conductive material layer 70 on the substrate 20 coincides with the projection of the ferroelectric material layer 60 on the substrate 20. The second conductive material layer 70 can be understood as a ferroelectric gate (FEG), which is equivalent to a memory switch of a memory cell. The material of the second conductive material layer 70 can be, for example, a conductive material such as metal or polysilicon.

[0091] For example, the projection of the second conductive material layer 70 on the substrate 20 does not cover the projection of the first conductive material layer 40 on the substrate 20 .

[0092] In this way, the first part W1 channel below the first conductive material layer 40 is controlled by the first conductive material layer 40, but not by the second conductive material layer 70, thereby ensuring the performance of the split-gate-FeFET. Moreover, when forming a via hole electrically connected to the back-end process wiring layer above the first conductive material layer 40, it is not necessary to pass through the second conductive material layer 70, which can simplify the process difficulty.

[0093] In some embodiments, Figure 5A As shown, the first portion W1 is close to the first doping region 21 , and the second portion W2 is close to the second doping region 22 .

[0094] For example, the first doped region 21 is a drain region D', and the second doped region 22 is a source region S'. Then, the first conductive material layer 40 is disposed close to the drain region D', and the second conductive material layer 70 is disposed close to the source region S'.

[0095] In some other embodiments, the first portion W1 is close to the second doping region 22 , and the second portion W2 is close to the first doping region 21 .

[0096] For example, the first doped region 21 is a source region S', and the second doped region 22 is a drain region D'. Then, the first conductive material layer 40 is disposed close to the drain region D', and the second conductive material layer 70 is disposed close to the source region S'.

[0097] It can be understood that the term "close" in the embodiment of the present application is relative, and the first conductive material layer 40 is close to the drain region D', which can be understood as the first conductive material layer 40 is closer to the drain region D' than the second conductive material layer 70. Similarly, the second conductive material layer 70 is close to the source region S', which can be understood as the second conductive material layer 70 is closer to the source region S' than the first conductive material layer 40.

[0098] By placing the second conductive material layer 70 close to the source region S', when writing, after applying a write voltage to the second conductive material layer 70, the second conductive material layer 70 directly forms a current loop with the source region S' through the second portion W2 in the channel, thereby completing the control of the polarization reversal of the ferroelectric material layer 60, without passing through the first portion W1 under the first conductive material layer 40, and therefore, there is no need to pay attention to the voltage applied to the first conductive material layer 40. However, if the second conductive material layer 70 is placed close to the drain region D', not only the second portion W2 under the second conductive material layer 70 needs to be turned on, but also the first portion W1 under the first conductive material layer 40 needs to be turned on, and the voltage of the first conductive material layer 40 needs to be controlled, which increases the complexity of control.

[0099] In some embodiments, Figure 5B As shown, the first portion W1 is close to the first doping region 21 , and the second portion W2 is close to the second doping region 22 .

[0100] For example, the first doped region 21 is a source region S', and the second doped region 22 is a drain region D'. Then, the first conductive material layer 40 is disposed close to the source region S', and the second conductive material layer 70 is disposed close to the drain region D'.

[0101] In some other embodiments, the first portion W1 is close to the second doping region 22 , and the second portion W2 is close to the first doping region 21 .

[0102] For example, the first doped region 21 is the drain region D', and the second doped region 22 is the source region S'. Then, the first conductive material layer 40 is disposed close to the source region S', and the second conductive material layer 70 is disposed close to the drain region D'.

[0103] Fig. 6A and Figure 6B A schematic diagram of an equivalent circuit structure of a split-gate-FeFET provided in an embodiment of the present application.

[0104] like Fig. 6A and Figure 6B As shown, the split-gate-FeFET provided in the embodiment of the present application includes a first conductive material layer 40 as a selection gate SG, a second conductive material layer 70 as a ferroelectric gate FEG, and a first doped region 21 and a second doped region 22 which are source regions S' and drain regions D' to each other. The selection gate SG and the ferroelectric gate FEG share the same set of source regions S' and drain regions D', and the channel between the source region S' and the drain region D' is divided into two parts, one part corresponds to the selection gate SG, and the other part corresponds to the ferroelectric gate FEG.

[0105] Figure 7 A schematic diagram of the structure of a split-gate-FeFET provided in an embodiment of the present application.

[0106] In some embodiments, Figure 7 As shown, the split-gate-FeFET further includes a planar layer 80 , a first conductive via 91 , a second conductive via 92 , a third conductive via 93 and a fourth conductive via 94 .

[0107] The planarization layer 80 is disposed on the substrate 20 and covers the first doping region 21 , the second doping region 22 , the first conductive material layer 40 , and the second conductive material layer 70 .

[0108] The first via hole 91 penetrates the flat layer 80 and is in ohmic contact with the first doped region 21. The first via hole 91 is, for example, a drain via hole. The second via hole 92 penetrates the flat layer 80 and is in ohmic contact with the second doped region 22. The second via hole 92 is, for example, a source via hole. The third via hole 93 penetrates the flat layer 80 and is coupled to the first conductive material layer 40. The third via hole 93 is, for example, a select gate via hole. The fourth via hole 94 penetrates the flat layer 80 and is coupled to the second conductive material layer 70. The fourth via hole 94 is, for example, a ferroelectric gate via hole.

[0109] The material of the first via 91 , the second via 92 , the third via 93 , and the fourth via 94 may be tungsten, for example.

[0110] The first doped region 21, the second doped region 22, the first insulating dielectric layer 30, the first conductive material layer 40, the second insulating dielectric layer 50, the ferroelectric material layer 60 and the second conductive material layer 70 in the split-gate-FeFET are, for example, prepared by a front end of line (FEOL) process. The planar layer 80, the first via 91, the second via 92, the third via 93 and the fourth via 94 are, for example, prepared by a middle end of line (MEOL) process.

[0111] Below, the preparation method of the split-gate-FeFET provided in the embodiment of the present application is schematically described.

[0112] Figure 8A-8L A schematic diagram of the preparation process of a split-gate-FeFET provided in an embodiment of the present application.

[0113] like Fig. 8A As shown, a well region (well) is formed in the substrate 20. The split-gate-FeFET is an N-type transistor, and the well region is a P-well region. The split-gate-FeFET is a P-type transistor, and the well region is an N-well region.

[0114] like Figure 8B As shown, a first dielectric film 30' and a first conductive film 40' are deposited on the surface of the substrate 20 to cover the well region.

[0115] like Figure 8C As shown, photolithography and development are performed, and the photoresist is retained at the location where the first conductive material layer 40 is to be formed, and the remaining area is exposed.

[0116] like Fig.8DAs shown, the first dielectric film 30' and the first conductive film 40' outside the photoresist protection position are etched away by etching, and the remaining parts are used as the first insulating dielectric layer 30 and the first conductive material layer 40. Then the photoresist is removed.

[0117] like Fig. 8E As shown, a second dielectric film 50', a ferroelectric film 60' and a second conductive film 70' are deposited. The second dielectric film 50' is used to isolate the first conductive material layer 40, the ferroelectric film 60' is used as the core material of the split-gate-FeFET, and the second conductive film 70' is used to prepare a conductive gate.

[0118] like Fig.8F As shown, photolithography and development are performed, and the photoresist is retained at the location where the second conductive material layer 70 is to be formed, and the remaining area is exposed.

[0119] like Figure 8G As shown, the second dielectric film 50', the ferroelectric film 60' and the second conductive film 70' outside the photoresist protection position are etched away by etching, and the remaining parts are used as the second insulating dielectric layer 50, the ferroelectric material layer 60 and the second conductive material layer 70. Then the photoresist is removed.

[0120] like Figure 8H As shown, ion implantation is performed to form a first doping region 21 and a second doping region 22 to form a source region S' and a drain region D'.

[0121] like Figure 8I As shown, a planar film 80' is deposited.

[0122] like Figure 8J As shown, photolithography and development are performed to remove the photoresist corresponding to the positions of the first conductive material layer 40, the second conductive material layer 70, the first doping region 21 and the second doping region 22, and the photoresist is retained in the remaining parts.

[0123] like Figure 8K As shown, the planar film 80' at the positions of the first conductive material layer 40, the second conductive material layer 70, the first doping region 21 and the second doping region 22 is etched away by etching to expose the first conductive material layer 40, the second conductive material layer 70, the first doping region 21 and the second doping region 22 to form a planar layer 80. Then the photoresist is removed.

[0124] like Figure 8L As shown, a conductive material layer 90 is deposited as the material of the via hole.

[0125] like Figure 7As shown, by chemical-mechanical planarization (CMP), the excess conductive material layer 90 is polished away, and the portion located in the planar layer 80 is retained as the first conductive hole 91, the second conductive hole 92, the third conductive hole 93 and the fourth conductive hole 94, and the surface is flattened.

[0126] At this point, a split-gate-FeFET having a source region S', a drain region D', a ferroelectric gate FEG, and a select gate SG is formed, and the split-gate-FeFET is used as a memory unit 200 (bit cell). Subsequently, through the backend of line (BEOL) process, metal interconnection is performed to connect the split-gate-FeFET in an array to form a memory array 210 (memory array).

[0127] Fig. 9 A schematic diagram of the structure of a storage array provided in an embodiment of the present application.

[0128] The present application also provides a storage array, such as Fig. 9 As shown, the memory array 210 includes a plurality of any of the above split-gate-FeFETs, and one split-gate-FeFET serves as a memory unit 200. The plurality of split-gate-FeFETs are arranged in multiple rows and columns, the row direction is parallel to the first direction X, the column direction is parallel to the second direction Y, and the second direction Y intersects the first direction X. Of course, considering the process error, the deviation of ±5° belongs to the parallelism in the embodiment of the present application.

[0129] The memory array further includes a plurality of first word lines WL1, a plurality of second word lines WL2, a plurality of bit lines BL, and a reference ground terminal GND. The plurality of first word lines WL1 all extend along a first direction X, the plurality of second word lines WL2 all extend along the first direction X, and the plurality of bit lines BL all extend along a second direction Y. The first word lines WL1 and the second word lines WL2 may be arranged in the same layer, for example, and the first word lines WL1 and the bit lines BL may be located in different layers, for example.

[0130] The first conductive material layer 40 of the split-gate-FeFET located in the same row is electrically connected to the same first word line WL1, and the first conductive material layer 40 is electrically connected to the first word line WL1, for example, through the third conductive hole 93. The first word line WL1 can be understood as a read word line (wordline-read). The second conductive material layer 70 of the split-gate-FeFET located in the same row is electrically connected to the same second word line WL2, and the second conductive material layer 70 is electrically connected to the second word line WL2, for example, through the fourth conductive hole 94. The second word line WL2 can be understood as a write word line (worldline-write).

[0131] The first doped regions 21 of the split-gate-FeFETs in the same column are electrically connected to the same bit line BL, and the first doped regions 21 are electrically connected to the bit line BL, for example, through the first via 91. The second doped regions 22 of the plurality of split-gate-FeFETs are all electrically connected to the reference ground terminal GND, and the second doped regions 22 are electrically connected to the reference ground terminal GND, for example, through the second via 92.

[0132] The embodiment of the present application further provides a memory, which includes a controller and the above-mentioned memory array 210, and the controller is electrically connected to the memory array 210. The memory is, for example, a memory chip, and the memory can be applied to any electronic device provided in the embodiment of the present application.

[0133] The present application also provides a method for reading and writing a storage array, including:

[0134] Data writing phase:

[0135] A reference ground voltage gnd is applied to the first doping region 21 of the split-gate-FeFET, a reference ground voltage gnd is applied to the second doping region 22 of the split-gate-FeFET, a reference ground voltage gnd is applied to the first conductive material layer 40 of the split-gate-FeFET, and a write voltage Vwrite is applied to the second conductive material layer 70 of the split-gate-FeFET.

[0136] A reference ground voltage gnd is applied to the first conductive material layer 40 of the split-gate-FeFET, and a reference ground voltage gnd is applied to the second doping region 22 of the split-gate-FeFET, which is equivalent to Vgs=0V, and the first part W1 channel under the first conductive material layer 40 is not turned on. A write voltage Vwrite is applied to the second conductive material layer 70 to flip the polarity of the ferroelectric material layer 60. This is equivalent to the second conductive material layer 70 controlling the polarity flip of the ferroelectric material layer 60 during the data writing phase, and the first conductive material layer 40 controlling the split-gate-FeFET to be turned off.

[0137] The polarity of the write voltage Vwrite is different to control the polarity flipping of the ferroelectric material layer 60, and 0 or 1 is written to the split-gate-FeFET. The positive or negative write voltage Vwrite can control the polarity flipping of the ferroelectric material layer 60 to face up or face down to represent "0" or "1". The polarity facing up can be defined as "1", and the corresponding polarity facing down can be defined as "0". The polarity facing up can also be defined as "0", and the corresponding polarity facing down can be defined as "1".

[0138] For example, the absolute value of the write voltage Vwrite is greater than the coercive voltage Vc.

[0139] For example, when the write voltage Vwrite is positive and greater than the coercive voltage Vc, the polarity of the ferroelectric material layer 60 is upward, which is defined as storing "1". When the write voltage Vwrite is negative and less than the negative coercive voltage Vc, the polarity of the ferroelectric material layer 60 is downward, which is defined as storing "0".

[0140] Data retention phase:

[0141] A reference ground voltage gnd is applied to the first doping region 21 , the second doping region 22 , the first conductive material layer 40 , and the second conductive material layer 70 of the split-gate-FeFET.

[0142] Due to the non-volatility of the split-gate-FeFET, data can still be retained after power failure. When the split-gate-FeFET is not subjected to read and write operations, the first doped region 21, the second doped region 22, the first conductive material layer 40 and the second conductive material layer 70 all receive the reference ground voltage gnd.

[0143] Then, during the data retention process, no matter whether the polarity of the ferroelectric material layer is upward or downward, due to the existence of the first conductive material layer 40 (selection gate SG), when the voltage received by the first conductive material layer 40 is the reference ground voltage gnd, the first part W1 channel can be closed, which is equivalent to closing the entire channel of the split-gate-FeFET, thereby reducing leakage.

[0144] Data reading phase:

[0145] A power supply voltage vdd is applied to the first doping region 21 of the split-gate-FeFET, a reference ground voltage gnd is applied to the second doping region 22 of the split-gate-FeFET, a reference voltage Vref is applied to the second conductive material layer 70, and a read voltage Vread is applied to the first conductive material layer 40 to read the signal of the first doping region 21.

[0146] A read voltage Vread is applied to the first conductive material layer 40 of the split-gate-FeFET, and a reference ground voltage gnd is applied to the second doping region 22 of the split-gate-FeFET. By controlling the magnitude of the read voltage Vread, the first portion W1 channel below the first conductive material layer 40 can be controlled to be turned on. A reference voltage Vref is applied to the second conductive material layer 70 of the split-gate-FeFET, and a reference ground voltage gnd is applied to the second doping region 22 of the split-gate-FeFET. By controlling the magnitude of the reference voltage Vref, the second portion W2 channel below the second conductive material layer 70 can be controlled to be turned on.

[0147] For example, the second portion W2 channel under the second conductive material layer 70 is an open channel, and the reference voltage Vref is, for example, the reference ground voltage gnd. The second portion W2 channel under the second conductive material layer 70 is a closed channel, and the reference voltage Vref is, for example, the power supply voltage vdd.

[0148] Illustratively, the read voltage Vread is equal to the power supply voltage vdd.

[0149] During the data reading process, due to the characteristics of the ferroelectric hysteresis loop, the ferroelectric polarity pointing upward will increase the threshold voltage Vt of the split-gate-FeFET accordingly, and the ferroelectric polarity pointing downward will reduce the threshold voltage Vt of the split-gate-FeFET accordingly. Under the appropriate reference voltage Vref, when the ferroelectric polarity points upward, the drain current Id is almost 0. When the ferroelectric polarity points downward, the drain current Id is not 0. By reading the size of the current Id of the first doped region 21, it is possible to determine whether the originally stored information is "0" or "1".

[0150] For example, the polarity of the ferroelectric material layer 60 is upward, which is defined as storing "1". The polarity of the ferroelectric material layer 60 is downward, which is defined as storing "0". Then, when the current Id of the first doping region 21 is almost 0, it means that the threshold voltage Vt has increased, and it is judged that the ferroelectric polarity is upward, and the stored information is "1". When the current Id of the first doping region 21 is not 0, it means that the threshold voltage Vt has decreased, and it is judged that the ferroelectric polarity is downward, and the stored information is "0".

[0151] In actual operation, for example, the read current Id can be compared with a reference current to determine whether the current Id read from the split-gate-FeFET is a large current or a small current, so as to determine the stored information.

[0152] The split-gate-FeFET provided in the embodiment of the present application is provided with a first conductive material layer 40 and a second conductive material layer 70 above the gap between the first doping region 21 and the second doping region 22 in the split-gate-FeFET, so that the conduction of the first part W1 channel of the split-gate-FeFET is controlled by the first conductive material layer 40, and the conduction of the second part W2 channel of the split-gate-FeFET is controlled by the second conductive material layer 70, and the split-gate-FeFET is turned on only when the first part W1 channel and the second part W2 channel are turned on together. In this way, during the data writing and data retention stages, when the ferroelectric polarity is facing downward, even if the second part of the channel is turned on, since the first part W1 channel is always kept closed, the first doping region 21 and the second doping region 22 will still not be turned on, thereby greatly reducing the leakage of the split-gate-FeFET to reduce static power consumption. After the leakage of the split-gate-FeFET is reduced, the requirements for the accuracy of the write voltage Vwrite in the data writing stage can also be reduced, shortening the time of the write operation. Moreover, due to the large leakage of the traditional split-gate-FeFET, the traditional split-gate-FeFET needs to strictly control the write voltage, so that the polarization intensity P can only go through an inner iron hysteresis loop (minor loop) inside the saturated iron hysteresis loop, and the value range of the polarization intensity of the ferroelectric material layer 60 is small. In the present application, after the leakage of the split-gate-FeFET is reduced, the polarization intensity can directly go through the saturated iron hysteresis loop, which can increase the value range of the polarization intensity of the ferroelectric material layer 60 in the split-gate-FeFET. Furthermore, since the ferroelectric material layer 60 is located on the side of the first conductive material layer 40 away from the substrate 20, then when the first conductive material layer 40 is working, it will not affect the polarization direction of the ferroelectric material layer 60, reduce the interference of the ferroelectric material layer 60, and improve the accuracy of the stored information.

[0153] An embodiment of the present application also provides a computer-readable storage medium, which includes computer instructions. When the computer instructions are executed on a device, the device executes the above-mentioned reading and writing method.

[0154] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A ferroelectric field effect transistor, characterized in that: include: A substrate, comprising a first doping region and a second doping region, wherein a gap is formed between the first doping region and the second doping region; Along a direction from the first doping region to the second doping region, the gap is divided into adjacent first and second parts; A first conductive material layer is disposed on a side of the first insulating medium layer away from the substrate and above the first portion; a first insulating dielectric layer, disposed between the first conductive material layer and the first portion; A second insulating dielectric layer, disposed on one side of the substrate, covers the second portion and extends above the first conductive material layer; a ferroelectric material layer, disposed on a side of the second insulating dielectric layer away from the substrate and covering the second insulating dielectric layer; The second conductive material layer is arranged on a side of the ferroelectric material layer away from the substrate and covers the ferroelectric material layer.

2. The ferroelectric field effect transistor according to claim 1, characterized in that: The first portion is close to the first doping region, and the second portion is close to the second doping region; the first doping region is a drain region, and the second doping region is a source region.

3. The ferroelectric field effect transistor according to claim 1 or 2, characterized in that: The gap is equally divided into the first portion and the second portion.

4. The ferroelectric field effect transistor according to any one of claims 1 to 3, characterized in that: A projection of the second conductive material layer on the substrate does not cover a projection of the first conductive material layer on the substrate.

5. The ferroelectric field effect transistor according to any one of claims 1 to 4, characterized in that: The material of the ferroelectric material layer includes perovskite, hafnium oxide-based material or zinc blende.

6. The ferroelectric field effect transistor according to any one of claims 1 to 5, characterized in that: The materials of the first insulating dielectric layer and the second insulating dielectric layer include silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide or niobium pentoxide.

7. The ferroelectric field effect transistor according to any one of claims 1 to 6, characterized in that: The materials of the first conductive material layer and the second conductive material layer include metal or polysilicon.

8. A storage array, characterized in that: include: A plurality of first word lines, all extending along a first direction; A plurality of second word lines, all extending along the first direction; a plurality of bit lines, all extending along a second direction, the second direction intersecting the first direction; Reference ground terminal; A plurality of ferroelectric field effect transistors according to any one of claims 1 to 7; the plurality of ferroelectric field effect transistors are arranged in a plurality of rows and columns, the row direction being parallel to the first direction; The first conductive material layer of the ferroelectric field effect transistors located in the same row is electrically connected to the same first word line, and the second conductive material layer of the ferroelectric field effect transistors located in the same row is electrically connected to the same second word line; the first doped regions of the ferroelectric field effect transistors located in the same column are electrically connected to the same bit line; the second doped regions of multiple ferroelectric field effect transistors are all electrically connected to the reference ground terminal.

9. A memory, characterized in that: include: Controller; and the storage array as claimed in claim 8; The controller is electrically connected to the storage array.

10. An electronic device, characterized in that: include: Circuit boards; And the memory as claimed in claim 9; the circuit board and the memory are electrically connected.

11. A method for reading and writing a storage array, characterized in that: The storage array comprises the storage array according to claim 8; The reading and writing method comprises: Data writing phase: Applying a reference ground voltage to a first doped region of a ferroelectric field effect transistor, applying the reference ground voltage to a second doped region of the ferroelectric field effect transistor, applying the reference ground voltage to a first conductive material layer of the ferroelectric field effect transistor, and applying a write voltage to a second conductive material layer of the ferroelectric field effect transistor; Data retention phase: applying the reference ground voltage to the first doped region, the second doped region, the first conductive material layer, and the second conductive material layer; Data reading phase: The power supply voltage is applied to the first doping region, the reference ground voltage is applied to the second doping region, a reference voltage is applied to the second conductive material layer, a read voltage is applied to the first conductive material layer, and a signal of the first doping region is read.

12. The reading and writing method according to claim 11, characterized in that: The absolute value of the write voltage is greater than the coercive voltage, and the read voltage is equal to the power supply voltage.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes computer instructions, and when the computer instructions are executed on a device, the device executes the reading and writing method according to claim 11 or 12.

Images