Semiconductor power device, preparation method, power module, conversion circuit and vehicle

Abstract

The invention discloses a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor power device comprises a semiconductor body; a trench gate structure; a gate located in a gate trench on the surface of the first region of the semiconductor body; the semiconductor body comprises a first contact region and a body region; the first contact region comprises a first sub-contact region and a second sub-contact region which respectively extend into the semiconductor body from the first surface, and the first sub-contact region is arranged along the side wall of the gate trench and is in contact with the trench gate structure; the second sub-contact region is located at one side, far away from the trench gate structure, of the first sub-contact region; the length of the first sub-contact region is greater than or equal to the thickness of the body region along the direction from the first surface to the second surface; and the contact metal layer is located on the surface of the second region of the semiconductor body and forms Schottky contact with the surface of the second region of the semiconductor body. According to the technical scheme provided by the invention, the preparation difficulty of the semiconductor power device is simplified, and the energy loss of the device in a reverse follow current state is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle. Background Art

[0002] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] Power metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor-Field-Effect-Transistor, MOSFET) is widely used in the field of high speed and high power. The MOS device of SiC material commonly used in the related art is an enhancement device. The enhancement device is not conductive under normal conditions, and a positive voltage needs to be applied to the gate to make the device conduction. The depletion MOS device is conductive under normal conditions, and a negative voltage needs to be applied to Vgs to cut off the device channel in the cut-off state. Therefore, the depletion MOS device can respond faster and control the current flow, and the conduction loss is small, which is more suitable for high-frequency circuits and switching circuits. In the current preparation method of the depletion type trench MOS device, an external anti-parallel diode of the depletion type trench MOS is usually used for reverse freewheeling. However, the external anti-parallel diode of the depletion type trench MOS device increases the difficulty of device preparation, and the conduction voltage drop of the diode is large, and the energy loss of the device in the reverse freewheeling state is large, which affects the performance of the device. Summary of the invention

[0004] Embodiments of the present invention provide a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle to simplify the preparation difficulty of the semiconductor device and reduce the energy loss of the device in a reverse freewheeling state.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] A semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the first surface comprises a first region surface and a second region surface, and the first region surface is provided with a gate trench;

[0007] A trench gate structure; the trench gate structure is located in the gate trench;

[0008] The semiconductor body comprises a first contact region and a body region; the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is arranged along the sidewall of the gate trench and contacts the trench gate structure; the second sub-contact region contacts the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure;

[0009] The body region is located on a side of the first sub-contact region away from the trench gate structure, and on a side of the second sub-contact region close to the second surface; along the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region;

[0010] A first electrode, located on a surface of the first region of the semiconductor body and in contact with the second sub-contact region;

[0011] The contact metal layer is located on the surface of the second region of the semiconductor body, and the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

[0012] Optionally, the semiconductor device further includes: a gate electrode, located on the surface of the first region of the semiconductor body and in contact with the trench gate structure; wherein the first electrode, the gate electrode and the contact metal layer are arranged in the same layer.

[0013] Optionally, the semiconductor body also includes: a second contact region, the second contact region is located on a side of the first sub-contact region away from the trench gate structure, and is located on a side of the body region away from the second surface; the second contact region and the first sub-contact region have different conductivity types; the first electrode is in contact with the second sub-contact region and the second contact region.

[0014] Optionally, the first surface also includes a third region surface; the semiconductor body also includes a body diode, and the second conductivity type region of the body diode is located on the third region surface.

[0015] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0016] forming a semiconductor body; the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region surface and a second region surface, and a gate trench is arranged on the first region surface;

[0017] A trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure; wherein the first contact region includes a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface to the semiconductor body, the first sub-contact region is arranged along the sidewall of the gate trench and contacts the trench gate structure; the second sub-contact region contacts the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure; along the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region;

[0018] Forming a contact metal layer on the surface of the second region of the semiconductor body; the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body;

[0019] A first electrode is formed on the surface of the first region of the semiconductor body and is in contact with the second sub-contact region.

[0020] Optionally, the method for preparing the semiconductor device further includes: forming a gate electrode in contact with the gate structure.

[0021] Optionally, a trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure, comprising:

[0022] forming a first mask layer on the first surface of the semiconductor body, and patterning the first mask layer to form a first opening in the first mask layer that exposes the surface of the first region;

[0023] Based on the patterned first mask layer, implanting second conductive type ions into the surface of the first region of the semiconductor body to form an initial body region;

[0024] removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form at least one second opening in the second mask layer to expose the initial body region; the width of the second opening is smaller than the width of the first opening;

[0025] Based on the patterned second mask layer, implanting first conductive type ions into the initial body region to form at least one first sub-region on a surface of the initial body region away from the second surface;

[0026] The second mask layer is removed, a third mask layer is formed on the first surface of the semiconductor body, and the third mask layer is patterned to form a third opening in the third mask layer that exposes a preset position of the trench gate structure; wherein the third opening exposes the initial body region and an area of ​​the first sub-region adjacent to the initial body region;

[0027] forming a spacer layer on the sidewall of the third opening adjacent to the first sub-region, so as to form a fourth opening in the third mask layer whose width is smaller than that of the third opening; wherein the width of the fourth opening is greater than or equal to the width of the initial body region exposed by the third opening;

[0028] forming a gate trench on the surface of the first region exposed by the fourth opening, and forming a first blocking layer in the gate trench;

[0029] The spacer layer located on the side wall of the third opening is removed, and the first conductive type ions are implanted into the exposed surface of the first region to form a first sub-contact region; wherein the first sub-region retained after the first sub-contact region is formed serves as the second sub-contact region, and the initial body region into which the first conductive type ions are not implanted serves as the body region;

[0030] The first barrier layer is removed, and a trench gate structure is formed in the gate trench.

[0031] Optionally, the semiconductor body also includes a second contact region; the method for preparing the semiconductor device also includes: forming a second contact region on at least one side of the trench gate structure; the second contact region is located on a side of the first contact region away from the trench gate structure, and is located on a side of the body region away from the second surface.

[0032] Optionally, a second contact region is formed on at least one side of the trench gate structure, including: forming a second barrier layer on the surface of the first barrier layer and the first surface of the semiconductor body; patterning the second barrier layer to form an opening in the second barrier layer that exposes a preset position of the second contact region; based on the patterned second barrier layer, implanting second conductive type ions into the preset position of the second contact region to form a second contact region; and removing the second barrier layer.

[0033] Optionally, forming a second contact region on at least one side of the trench gate structure comprises: after forming the first sub-contact region, removing the third mask layer and removing the first barrier layer; forming an etch stop layer on the groove wall of the gate trench and the first surface of the semiconductor body; forming a third barrier layer having a thickness greater than that of the etch stop layer on the surface of the etch stop layer; patterning the third barrier layer to form an opening in the third barrier layer to expose the etch stop layer at a preset position of the second contact region; based on the patterned third barrier layer, implanting second conductive type ions into a preset position of the second contact region to form a second contact region;

[0034] Before forming the trench gate structure in the gate trench, the method further includes: removing the third barrier layer and the etching stop layer.

[0035] Optionally, a trench gate structure is formed in the gate trench, including: forming a gate insulating layer on the wall of the gate trench; and forming a polysilicon gate on the surface of the gate insulating layer.

[0036] Optionally, the first surface further includes a third region surface, and while forming the initial body region, the process further includes: implanting second conductive type ions into the third region surface to form a second conductive type region of the body diode;

[0037] While forming the second sub-contact region, the method further includes: implanting the second conductive type ions into the second conductive type region of the body diode again to increase the ion doping concentration on the surface of the second conductive type region of the body diode.

[0038] Optionally, before forming a gate electrode in contact with the gate structure and a first electrode in contact with the second sub-contact region on the surface of the first region of the semiconductor body, the method further includes:

[0039] A passivation layer is formed on the surface of the first region of the semiconductor body, and a first electrode connection port exposing the second sub-contact region and a gate connection port exposing the gate structure are formed in the passivation layer.

[0040] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0041] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0042] The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0043] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0044] The technical solution provided by the embodiment of the present invention integrates a Schottky barrier diode (SBD) in the body of a semiconductor device. Compared with a diode connected in anti-parallel outside the semiconductor device body for reverse freewheeling, a Schottky barrier diode can be formed while preparing a MOS device, thereby simplifying the device preparation process and avoiding the increase in device packaging cost and stray inductance caused by an external parallel SBD, thereby preventing the device switching characteristics from being degraded. In addition, during reverse freewheeling, since the turn-on voltage of the Schottky diode is lower than that of the PN junction diode, the integrated Schottky diode is turned on before the body diode, and current flows through the Schottky junction, thereby greatly reducing the energy loss of the device in the reverse freewheeling state.

[0045] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0048] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 3 is a structural schematic diagram corresponding to step S110 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0050] Figure 4 is a structural schematic diagram corresponding to step S120 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0051] Figure 5is a structural schematic diagram corresponding to step S210 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0052] Figure 6 is a structural schematic diagram corresponding to step S220 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0053] Figure 7 is a structural schematic diagram corresponding to step S230 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0054] Figure 8 is a structural schematic diagram corresponding to step S240 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0055] Fig. 9 is a structural schematic diagram corresponding to step S250 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0056] Figure 10-11 is a structural schematic diagram corresponding to step S260 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0057] Figure 12-13 is a structural schematic diagram corresponding to step S270 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0058] Figure 14-15 is a structural schematic diagram corresponding to step S280 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0059] Fig.16 It is a structural schematic diagram corresponding to step S2811 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0060] Fig.17 It is a structural schematic diagram corresponding to step S2812 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0061] Fig.18 It is a structural schematic diagram corresponding to step S2813 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0062] Fig.19 It is a structural schematic diagram corresponding to step S2822 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0063] Fig. 20 It is a structural schematic diagram corresponding to step S2823 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0064] Fig.21 It is a structural schematic diagram corresponding to step S2824 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0065] Fig. 22 It is a structural schematic diagram corresponding to step S290 in a method for preparing a semiconductor device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0067] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] An embodiment of the present invention further provides a semiconductor device, Figure 1 is a schematic diagram of a semiconductor device provided by an embodiment of the present invention, with reference to Figure 1 , semiconductor devices include:

[0069] The semiconductor body 1 comprises a first surface 11 and a second surface 12 arranged opposite to each other, the first surface 11 comprises a first region surface and a second region surface, and a gate trench is arranged on the first region surface;

[0070] A trench gate structure 30; the trench gate structure 30 is located in the gate trench; wherein the semiconductor body 1 includes a first contact region and a body region 21; the first contact region 22 includes a first sub-contact region 222 and a second sub-contact region 221, the first sub-contact region 222 and the second sub-contact region 221 respectively extend from the first surface 11 into the semiconductor body 1, the first sub-contact region 222 is arranged along the sidewall of the gate trench and contacts the trench gate structure 30; the second sub-contact region 221 contacts the first sub-contact region 222 and is located on a side of the first sub-contact region 222 away from the trench gate structure 30;

[0071] The body region 21 is located on a side of the first sub-contact region 222 away from the trench gate structure 30 and on a side of the second sub-contact region 221 close to the second surface 12; along the direction from the first surface 11 to the second surface 12, the length of the first sub-contact region 222 is greater than or equal to the thickness of the body region 21;

[0072] A first electrode is located on the surface of the first region of the semiconductor body 1 and contacts the second sub-contact region 221;

[0073] The contact metal layer 81 is located on the surface of the second region of the semiconductor body 1 , and the contact metal layer 81 forms a Schottky contact with the surface of the second region of the semiconductor body 1 .

[0074] The semiconductor device of the embodiment of the present invention is a trench-type and depletion-type semiconductor device. The depletion-type device is normally turned on, and current flows in through the second surface 12 of the semiconductor body 1, and flows through the drift region 24 along the contact region (first sub-contact region 222) of the sidewall of the trench gate structure 30 to the first surface 11 of the semiconductor body 1. When the depletion-type device is switched to the cut-off state, a negative voltage needs to be applied to the trench gate structure 30 to cut off the device channel, so the depletion-type semiconductor device can respond faster and control the current flow, with small conduction loss, and is more suitable for high-frequency circuits and switching circuits.

[0075] In addition, the technical solution provided by the embodiment of the present invention integrates the Schottky diode 103 in the semiconductor device body. Compared with the diode connected in anti-parallel outside the semiconductor device body for reverse freewheeling, the Schottky diode 102 can be formed at the same time as the MOS device is prepared, which simplifies the device preparation process and avoids the increase of packaging cost and stray inductance caused by external parallel SBD, thereby preventing the switching characteristics of the device from being degraded. In addition, during reverse freewheeling, since the turn-on voltage of the Schottky diode 103 is lower than that of the PN junction diode, the integrated Schottky diode 103 is turned on before the body diode 102, and the current flows through the Schottky junction, so the energy loss of the device in the reverse freewheeling state is greatly reduced.

[0076] Optionally, the semiconductor device further includes: a gate electrode G, located on the surface of the first region of the semiconductor body 1 and in contact with the trench gate structure 30; wherein the first electrode, the gate electrode G and the contact metal layer 81 are disposed in the same layer. The first electrode may be a source electrode S.

[0077] Optionally, the semiconductor body 1 also includes a second contact region 23, which is located on a side of the first contact region 22 away from the trench gate structure 30 and on a side of the body region 21 away from the second surface 12; the second contact region 23 has a different conductivity type from the first contact region 22; the first electrode is in contact with the second sub-contact region 221 and the second contact region 23.

[0078] Optionally, the first surface 11 further includes a third region surface; the semiconductor body 1 further includes a body diode 102, and the second conductivity type region of the body diode 102 is located on the third region surface.

[0079] The embodiment of the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device described in any embodiment of the present invention. Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 2 , a method for preparing a semiconductor device comprises:

[0080] S10, forming a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the first surface comprises a first region surface and a second region surface.

[0081] Specifically, the semiconductor body can be formed by one epitaxy or multiple epitaxys. That is, the semiconductor body can be a semiconductor epitaxial layer or a stacked structure formed by multiple semiconductor epitaxial layers. The semiconductor body can also include a substrate, that is, the semiconductor body includes a substrate and at least one semiconductor epitaxial layer formed on one side of the substrate. The material of the substrate can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate can be different from the material of the semiconductor epitaxial layer.

[0082] refer to Figure 3 Optionally, the material of the semiconductor body 1 may be SiC, that is, the semiconductor device in the embodiment of the present invention may be a trench SiC power device. The semiconductor body 1 includes a substrate 10 and a semiconductor epitaxial layer 20 formed on one side of the substrate 10. SiC has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, and have the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0083] The semiconductor body 1 includes a first surface 11 and a second surface 12 that are arranged opposite to each other. When the semiconductor body 1 includes only the semiconductor epitaxial layer 20, the second surface 12 is the surface of the semiconductor body 1 on the side close to the substrate 10, and the first surface 11 is the surface of the semiconductor body 1 on the side away from the substrate 10. When the semiconductor body 1 includes the substrate 10 and at least one semiconductor epitaxial layer 20, the second surface 12 is the surface of the substrate 10 on the side away from the semiconductor epitaxial layer 20, and the first surface 11 is the surface of the semiconductor epitaxial layer 20 that is farthest from the substrate 10 and is away from the substrate 10.

[0084] The first surface 11 includes a first region surface Q1 and a second region surface Q2, and the first region surface Q1 and the second region surface Q2 may be adjacent or spaced apart. It can be understood that the semiconductor body 1 includes a first region and a second region, the first region surface Q1 is the first surface 11 of the semiconductor body 1 located in the first region, and the second region surface Q2 is the first surface 11 of the semiconductor body 1 located in the second region. The semiconductor body 1 located in the first region is used to prepare a MOS device, and the semiconductor body 1 located in the second region is used to form a Schottky diode.

[0085] S20. A gate trench is set on the surface of the first region, and a trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure; wherein the first contact region includes a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface to the semiconductor body, the first sub-contact region is set along the side wall of the gate trench and contacts the trench gate structure; the second sub-contact region contacts the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure; along the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region.

[0086] Specifically, refer to Figure 4The body region 21 can be formed by implanting ions of the second conductivity type on the surface of the semiconductor epitaxial layer 20 after forming the semiconductor epitaxial layer; the first contact region 22 is formed by implanting ions in the body region 21. The first contact region 22 includes a first sub-contact region 222 and a second sub-contact region 221. The first sub-contact region 222 is located on the first region surface of the semiconductor body 1 and the sidewall of the trench gate structure 30. Along the direction from the first surface 11 to the second surface 12, the length of the first sub-contact region 222 located on the sidewall of the trench gate structure 30 is greater than or equal to the thickness of the body region 21. The second sub-contact region 221 is located on the side of the first sub-contact region 222 away from the trench gate structure 30, and on the side of the body region 21 away from the second surface 12. The first sub-contact region 222 and the second sub-contact region 231 have the same conductivity type. The first electrode contacts the second sub-contact region 221. Before the trench gate structure 30 is formed on the first region surface Q1 of the semiconductor body 1, a gate trench can be formed on the first region surface Q1 of the semiconductor body 1. The number of gate trenches corresponds to the number of trench gate structures 30. The gate trench can be formed by etching the first sub-contact region 222, the body region 21 and the drift region 24 of a partial thickness from the first surface 11 of the semiconductor body 1. Forming the trench gate structure 30 in the gate trench includes: forming a gate insulating layer 32 on the groove wall of the gate trench; forming a polysilicon gate 31 on the surface of the gate insulating layer 32. The trench gate structure 30 includes a polysilicon gate 31 and a gate insulating layer 32 located between the polysilicon gate 31 and the gate trench 301. The material of the gate insulating layer 32 may include at least one of aluminum oxide and silicon oxide.

[0087] The trench gate structure 30 formed on the first region surface Q1 of the semiconductor body 1 may be one or more. That is, the semiconductor device of the embodiment of the present invention includes at least one trench SiC power device. Among them, at least one side of each trench gate structure 30 is provided with a first sub-contact region 222 and a body region 21, and the first sub-contact region 222 is located on the first region surface Q1 of the semiconductor body 1 and the side wall of the trench gate structure 30, and along the direction from the first surface 11 to the second surface 12, the length of the first sub-contact region 222 is greater than or equal to the thickness of the body region 21; that is, the semiconductor device of the embodiment of the present invention is a depletion-type device. The depletion-type device is turned on in normal state, and the current flows in through the second surface 12 of the semiconductor body 1, and flows through the drift region 24 along the first sub-contact region 22 of the side wall of the trench gate structure 30 to the first surface 11 of the semiconductor body 1 (the first sub-contact region 222 located on the first surface 11). When the depletion-mode device switches to the cut-off state, a negative voltage is applied to the trench gate structure 30 to cut off the device channel. Therefore, the depletion-mode semiconductor device can respond faster and control the current flow, has small conduction loss, and is more suitable for high-frequency circuits and switching circuits.

[0088] The conductivity type of the first sub-contact region 222 is the same as that of the semiconductor body 1, and both are doped with ions of the first conductivity type, and the ion doping concentration of the first sub-contact region 222 is greater than the ion doping concentration of the semiconductor body 1. The conductivity type of the body region 21 is different from that of the semiconductor body 1, and ions of the second conductivity type are doped in the body region 21. The semiconductor epitaxial layer 20 between the body region 21 and the second surface 12 is used as a drift region 24. The ions of the first conductivity type may be N-type doped ions, and the ions of the second conductivity type may be P-type doped ions; or, the ions of the first conductivity type may be P-type doped ions, and the ions of the second conductivity type may be N-type doped ions. The N-type doped ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doped ions may be Al (aluminum) ions or B (boron) ions. In the embodiment of the present invention, the ions of the first conductivity type are N-type doped ions, and the ions of the second conductivity type are P-type doped ions.

[0089] S30, forming a contact metal layer on the surface of the second area of ​​the semiconductor body; the contact metal layer forms a Schottky contact with the surface of the second area of ​​the semiconductor body, and forming a first electrode in contact with the second sub-contact area on the surface of the first area of ​​the semiconductor body.

[0090] Specifically, a Schottky diode is a low-power, high-current, ultra-high-speed semiconductor device made using the metal-semiconductor junction principle formed by the contact between metal and semiconductor. A Schottky diode generally includes a cathode metal layer, a first conductive type substrate, a first conductive type epitaxial layer, a barrier metal or metal silicide, and an anode metal layer; the barrier metal or metal silicide and the first conductive type epitaxial layer form a Schottky contact. Figure 1 In the embodiment of the present invention, the semiconductor body 1 is a semiconductor layer of the first conductivity type, and only ions of the first conductivity type are doped in the semiconductor body 1 located in the second region. At least a portion of the contact metal layer 81 adjacent to the semiconductor body 1 is a barrier metal or a metal silicide. A contact metal layer 81 is formed on the surface Q2 of the second region of the semiconductor body 1, and the contact metal layer 81 is annealed, so that the contact metal layer 81 forms a Schottky contact with the surface Q2 of the second region of the semiconductor body 1, thereby forming a Schottky diode 103. The first electrode can be a source electrode S.

[0091] Optionally, the contact metal layer 81 includes not only the barrier metal or metal silicide but also an anode metal layer of the Schottky diode 103 .

[0092] Optional, please continue to refer to Figure 1While forming the contact metal layer 81 on the second area surface Q2 of the semiconductor body 1, it also includes: forming a first electrode in contact with the second contact sub-area 221 on the first area surface Q1 of the semiconductor body 1, and forming a gate electrode G in contact with the gate structure, thereby simplifying the preparation process of the semiconductor device.

[0093] Exemplarily, the first electrode, the gate electrode G and the contact metal layer 81 can be prepared and formed simultaneously by sequentially depositing a Ti layer, a TiN layer and an Al layer, and then undergoing a metal etching process. A second electrode is also provided on the side of the semiconductor body 1 away from the first surface 11. The first electrode can be a source electrode S, and the second electrode can be a drain electrode D; or the first electrode can be a drain electrode D, and the second electrode can be a source electrode S. Figure 1 The first electrode is exemplarily shown as a source electrode S, and the second electrode is a drain electrode D. The cathode metal layer of the Schottky diode 103 may be electrically connected to or shared with the second electrode; the anode metal layer of the Schottky diode 103 may be electrically connected to or shared with the first electrode.

[0094] The technical solution provided by the embodiment of the present invention can form a Schottky barrier diode while preparing a depletion-mode MOS device by integrating a Schottky barrier diode in the body of a semiconductor device, thereby simplifying the preparation process of the semiconductor device and avoiding the problem of increasing packaging cost and stray inductance due to an external parallel SBD, thereby preventing the switching characteristics of the device from being degraded; in addition, during reverse freewheeling, since the turn-on voltage of the Schottky diode 103 is lower than that of the PN junction diode, the integrated Schottky diode 103 is turned on before the body diode 102, and the current flows through the Schottky junction, so the energy loss of the device in the reverse freewheeling state is greatly reduced.

[0095] On the basis of the above embodiments, step S20 forms a trench gate structure on the surface of the first region of the semiconductor body, and forms a first contact region and a body region on at least one side of the trench gate structure, including:

[0096] S210 , forming a first mask layer on a first surface of the semiconductor body, and patterning the first mask layer to form a first opening in the first mask layer that exposes a surface of the first region.

[0097] Specifically, refer to Figure 5PECVD (Plasma Enhanced Chemical Vapor Deposition) can be used to deposit SiO2 to form the first mask layer 100; the first mask layer 100 is patterned by photolithography. The photolithography process is an important step in the semiconductor device manufacturing process. This step uses exposure and development to depict geometric structures on the photoresist layer, and then the pattern of the photoresist layer is transferred to the first mask layer 100 by an etching process to achieve patterning of the first mask layer 100. The width of the first opening 01 located on the first region surface Q1 can just expose the entire first region surface Q1.

[0098] S220 , based on the patterned first mask layer, implant second conductive type ions into the surface of the first region of the semiconductor body to form an initial body region.

[0099] Specifically, refer to Figure 6 , based on the patterned first mask layer 100, the second conductive type ions are implanted into the first region surface Q1 of the semiconductor body 1 to form an initial body region 211. The initial body region 211 located on the first region surface Q1 is a film layer formed during the preparation of the semiconductor device, and the body region 21 is formed on the basis of the initial body region 211. In the embodiment of the present invention, the initial body region 211 is a doped region formed by implanting the second conductive type ions into the surface of the semiconductor epitaxial layer 20 after the semiconductor epitaxial layer 20 is formed; compared with the method of doping the second conductive type ions into the epitaxial material during the epitaxial process, the embodiment of the present invention can make the semiconductor epitaxial layer 20 used to prepare the initial body region 211 and the semiconductor epitaxial layer 20 used to prepare the Schottky diode 103 be formed in the same epitaxial process, thereby simplifying the preparation process of the semiconductor device.

[0100] S230, removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form at least one second opening in the second mask layer that exposes the initial body region; the width of the second opening is smaller than the width of the first opening.

[0101] Specifically, refer to Figure 7, after the first mask layer 100 of silicon dioxide material can be etched away with a hydrofluoric acid solution; SiO2 is deposited by a PECVD process to form a second mask layer 200, and the second mask layer 200 is patterned by a photolithography process to form at least one second opening 02 exposing the initial body region 211 in the second mask layer 200. The width of the second opening 02 is smaller than the width of the first opening 01. The position of the second opening 02 corresponds to the position of the first sub-region a1 of the first conductivity type formed in step S240. When a trench gate structure 30 is formed in the first region of the semiconductor body 1, one or two second openings 02 can be formed. When multiple trench gate structures 30 are formed in the first region of the semiconductor body 1, at least the same number of second openings 02 as the trench gate structures 30 are formed. Adjacent second openings 02 are spaced apart.

[0102] S240 , based on the patterned second mask layer, implanting first conductive type ions into the initial body region to form at least one first sub-region on a surface of the initial body region away from the second surface.

[0103] Specifically, refer to Figure 8 Based on the patterned second mask layer 200, the initial body region 211 is implanted with first conductive type ions to form at least one first conductive type first sub-region a1 on the surface of the initial body region 211 away from the second surface 12. The thickness of the first sub-region a1 is less than that of the initial body region 211.

[0104] S250, removing the second mask layer, forming a third mask layer on the first surface of the semiconductor body, and patterning the third mask layer to form a third opening in the third mask layer that exposes a preset position of the trench gate structure.

[0105] Specifically, refer to Fig. 9 , after the second mask layer 200 of silicon dioxide material is etched away by hydrofluoric acid solution, SiO2 is deposited by PECVD process to form a third mask layer 300, and the third mask layer 300 is patterned by photolithography process to form at least one third opening 03 in the third mask layer 300. The third opening 03 exposes the preset position of the trench gate structure 30, and the number of the third openings 03 is the same as the number of the trench gate structures 30. Among them, the third opening 03 exposes the initial body region 211 and the area adjacent to the first sub-region a1 and the initial body region 211. Fig. 9 It is exemplarily shown that the third opening 03 exposes the initial body region 211 between two adjacent first sub-regions a1 and partial regions of the two adjacent first sub-regions a1.

[0106] S260, forming a spacer layer on the sidewall of the third opening adjacent to the first sub-region to form a fourth opening in the third mask layer whose width is smaller than the third opening; wherein the width of the fourth opening is greater than or equal to the width of the initial body region exposed by the third opening.

[0107] Specifically, refer to Fig.10 and Fig.11 , SiN material can be deposited to form a spacer layer 40 on the surface of the third mask layer 300 away from the semiconductor body 1, the sidewall of the third opening 03, and the first surface 11 of the semiconductor body 1 exposed by the third opening 03; and then the spacer layer 40 located on the surface of the third mask layer 300 away from the semiconductor body 1 and the spacer layer 40 located on the first surface 11 of the semiconductor body 1 exposed by the third opening 03 are removed by a dry etching process, thereby forming a spacer layer 40 on the sidewall of the third opening 03. In the embodiment of the present invention, the first sub-regions a1 are provided on both opposite sides of the third opening 03, so the spacer layers 40 on the opposite sides of the third opening 03 can be retained.

[0108] S270, forming a gate trench on the surface of the first region exposed by the fourth opening, and forming a first barrier layer in the gate trench.

[0109] Specifically, refer to Fig.12 and Fig.13 A gate trench 301 is formed on the first region surface Q1 exposed by the fourth opening 04, and a first barrier layer 51 is formed in the gate trench 301. The width of the fourth opening 04 is greater than or equal to the width of the initial body region 211 between two adjacent first conductive type first sub-regions 221, so that the sidewall of the gate trench 301 formed by etching the semiconductor body 1 based on the fourth opening 04 is in contact with the first conductive type first sub-region 221.

[0110] S280, remove the spacer layer located on the side wall of the third opening, and inject the first conductive type ions into the exposed surface of the first region to form a first sub-contact region; wherein the first sub-region retained after the first sub-contact region is formed serves as the second sub-contact region, and the initial body region into which the first conductive type ions are not injected serves as the body region.

[0111] Specifically, refer to Fig.14 and Fig.15, remove the spacer layer 40 located on the side wall of the third opening 03, and implant the first conductive type ions into the initial body region 211 below the spacer layer 40 to form the first sub-contact region 222. The material of the spacer layer 40 is different from the material of the third mask layer 300, and is different from the material of the first barrier layer 51. Thus, it can be ensured that the third mask layer 300 is prevented from being damaged when the spacer layer 40 is removed, and the first barrier layer 51 is prevented from being damaged. Optionally, the material of the spacer layer 40 can be SiN, and the material of the first barrier layer 51 can be polysilicon. The spacer layer 40 located on the side wall of the third opening 03 can be removed by a phosphoric acid solution.

[0112] After removing the spacer layer 40 located on the side wall of the third opening 03, a portion of the first sub-region 221 located below the spacer layer 40 is exposed, and the first conductive type ions are implanted again to form the first sub-contact region 222 along the side wall of the gate trench 301, thereby completing the preparation of the first sub-contact region 222. Among them, the first sub-region a1 retained after the first sub-contact region 222 is formed is used as the second sub-contact region 221. The first blocking layer 51 is used to block the first conductive type ions from being implanted into the bottom of the gate trench 301 when forming the first sub-contact region 222. The initial body region 221 into which the first conductive type ions are not implanted forms the body region 21. The ion doping concentration in the first sub-contact region 222 is greater than the ion doping concentration in the second sub-contact region 221.

[0113] S290, removing the first barrier layer, and forming a trench gate structure in the gate trench.

[0114] Specifically, the first barrier layer 51 may be removed by using a nitric acid solution, thereby exposing the sidewall and the bottom of the gate trench 301 , so as to form a trench gate structure 30 in the gate trench 301 .

[0115] On the basis of the above embodiments, the semiconductor device further includes a second contact region located on a side of the first contact region away from the trench gate structure and located on a side of the body region away from the second surface. The method for preparing the semiconductor device further includes: forming a second contact region on at least one side of the trench gate structure; the second contact region is located on a side of the first contact region away from the trench gate structure and located on a side of the body region away from the second surface.

[0116] On the basis of the above embodiments, in one embodiment of the present invention, a second contact region is formed on at least one side of the trench gate structure 30, including:

[0117] After forming the first sub-contact region 222 in step S280, the method further includes:

[0118] S2811, remove the third mask layer 300, and form a second barrier layer 52 on the surface of the first barrier layer 51 and the first surface 11 of the semiconductor body 1. (Refer to Fig.16)

[0119] S2812, patterning the second barrier layer 52 to form an opening 521 in the second barrier layer 52 that exposes a predetermined position of the second contact region 23. (Refer to Fig.17 )

[0120] S2813, based on the patterned second barrier layer 52, implant the second conductive type ions into the preset position of the second contact region 23 to form the second contact region 23. (Refer to Fig.18 )

[0121] The second contact region 23 is doped with ions of the second conductive type, and the offline doping concentration in the second contact region 23 is greater than the ion doping concentration in the body region 21 .

[0122] Before forming the trench gate structure 30 in the gate trench 301, the second barrier layer 52 is further removed. That is, before forming the trench gate structure 30 in the gate trench 301, both the second barrier layer 52 and the first barrier layer 51 need to be removed. The first barrier layer 51 and the second barrier layer 52 may be made of the same material, so that they can be removed in the same removal process, thereby simplifying the preparation process of the semiconductor device.

[0123] Based on the above embodiments, in another embodiment of the present invention, a second contact region is formed on at least one side of the trench gate structure, including:

[0124] After forming the first sub-contact region 222 in step S280, the following steps are included:

[0125] S2821 , removing the third mask layer 300 , and removing the first barrier layer 51 .

[0126] S2822, forming an etch stop layer 60 on the wall of the gate trench 301 and the first surface 11 of the semiconductor body 1, and forming a third barrier layer 53 having a thickness greater than that of the etch stop layer 60 on the surface of the etch stop layer 60. (Refer to Fig.19 )

[0127] Specifically, the etch stop layer 60 can be provided to prevent the surface of the semiconductor body 1 from being damaged during the patterning of the third barrier layer 53 in step S2823. The thickness of the etch stop layer 60 is set to be smaller than the thickness of the third barrier layer 53, which can reduce the impact on the implantation of the second conductive type ions in step S2824. The material of the etch stop layer 60 can be silicon dioxide, and the material of the third barrier layer 53 can be polysilicon.

[0128] S2823, patterning the third barrier layer 53 to form an opening 531 in the third barrier layer 53 that exposes the etching barrier layer at a predetermined position of the second sub-contact region 23. (Refer to Fig. 20 )

[0129] S2824, based on the patterned third barrier layer 53, implant the second conductive type ions into the preset position of the second contact region 23 to form the second contact region 23. (Refer to Fig.21 )

[0130] Before forming the trench gate structure 30 in the gate trench 301 , the process further includes: removing the third barrier layer 53 and the etching stop layer 60 .

[0131] On the basis of the above embodiments, in step S290, a trench gate structure 30 is formed in the gate trench 301, including:

[0132] S2910 , forming a gate insulating layer 32 on the wall of the gate trench 301 .

[0133] S2920 , forming a gate insulating layer 32 on the wall of the gate trench 301 .

[0134] Specifically, refer to Fig. 22 A gate insulating layer 32 can be formed on the sidewall and bottom of the gate trench 301 and the first surface 11 of the semiconductor body 1 by a thermal oxidation process. Doped Poly-Si is deposited, and then etched back to fill the gate trench with Poly-Si to form a polysilicon gate 31, thereby completing the preparation of the trench gate structure 30.

[0135] Furthermore, before forming the trench gate structure 30 in the gate trench 301 in step S290, the step further includes: sputtering a layer of carbon film on the first surface 11 of the semiconductor body 1 and the wall of the gate trench 301, annealing in an annealing furnace, and then removing the carbon film. Specifically, since ion implantation may generate some lattice defects in the semiconductor, these defects may be eliminated by low temperature annealing or laser annealing after ion implantation.

[0136] Furthermore, after removing the carbon film, the method further includes: forming a sacrificial oxide layer on the first surface 11 of the semiconductor body 1 and the wall surface of the gate trench 301 by a thermal oxidation process to repair the lattice on the surface of the semiconductor body 1; and then removing the sacrificial oxide layer.

[0137] Based on the above embodiments, optionally, the first surface 11 further includes a third region surface Q3, and while forming the initial body region 211 in step S220, the step also includes: implanting second conductive type ions into the third region surface Q3 to form a second conductive type region 1021 of the body diode 102. (See Figure 6 )

[0138] While forming the second contact region 23 in step S2813 and step S2824, the process further includes: implanting the second conductive type ions into the second conductive type region of the body diode 102 again to increase the ion doping concentration on the surface of the second conductive type region 1021 of the body diode 102. (Refer to Fig.18 and Fig.21 )

[0139] Based on the above embodiments, optionally, refer to Figure 1 Before a gate electrode in contact with the gate structure and a first electrode in contact with the second sub-contact region 221 are formed on the first region surface Q1 of the semiconductor body 1, the method further includes: forming a passivation layer 70 on the first region surface Q1 of the semiconductor body 1, and forming a first electrode connection port exposing the second sub-contact region 221 and a gate connection port exposing the trench gate structure 3 in the passivation layer 70.

[0140] The first electrode is also in contact with the second contact region 23 .

[0141] The embodiment of the present invention further provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. The power module has the same technical effect and will not be described in detail here.

[0142] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. It has the same technical effect and is not repeated here.

[0143] The embodiment of the present invention further provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. The same technical effects are achieved, which will not be described in detail here.

[0144] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the first surface comprises a first region surface and a second region surface, and the first region surface is provided with a gate trench; A trench gate structure; the trench gate structure is located in the gate trench; The semiconductor body comprises a first contact region and a body region; the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is arranged along the sidewall of the gate trench and contacts the trench gate structure; the second sub-contact region contacts the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure; The body region is located on a side of the first sub-contact region away from the trench gate structure, and on a side of the second sub-contact region close to the second surface; along the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region; A first electrode, located on a surface of the first region of the semiconductor body and in contact with the second sub-contact region; The contact metal layer is located on the surface of the second region of the semiconductor body, and the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

2. The semiconductor device according to claim 1, wherein: Also includes: A gate electrode, located on the surface of the first region of the semiconductor body and in contact with the trench gate structure; Wherein, the first electrode, the gate electrode and the contact metal layer are arranged in the same layer.

3. The semiconductor device according to claim 2, characterized in that The semiconductor body further comprises: a second contact region, the second contact region being located on a side of the first contact region away from the trench gate structure and on a side of the body region away from the second surface; the second contact region and the first contact region have different conductivity types; The first electrode contacts the second sub-contact region and the second contact region.

4. The semiconductor device according to claim 1, wherein: The first surface also includes a third zone surface; The semiconductor body also includes a body diode, and the second conductivity type region of the body diode is located on the surface of the third region.

5. A method for preparing a semiconductor device, characterized in that: include: forming a semiconductor body; the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region surface and a second region surface, and a gate trench is arranged on the first region surface; A trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure; wherein the first contact region includes a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface to the semiconductor body, the first sub-contact region is arranged along the sidewall of the gate trench and contacts the trench gate structure; the second sub-contact region contacts the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure; along the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region; Forming a contact metal layer on the surface of the second region of the semiconductor body; the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body; A first electrode is formed on the surface of the first region of the semiconductor body and is in contact with the second sub-contact region.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: Also includes: A gate electrode is formed in contact with the gate structure.

7. The method for preparing a semiconductor device according to claim 5, characterized in that: A trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure, comprising: forming a first mask layer on the first surface of the semiconductor body, and patterning the first mask layer to form a first opening in the first mask layer that exposes the surface of the first region; Based on the patterned first mask layer, implanting second conductive type ions into the surface of the first region of the semiconductor body to form an initial body region; removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form at least one second opening in the second mask layer to expose the initial body region; the width of the second opening is smaller than the width of the first opening; Based on the patterned second mask layer, implanting first conductive type ions into the initial body region to form at least one first sub-region on a surface of the initial body region away from the second surface; The second mask layer is removed, a third mask layer is formed on the first surface of the semiconductor body, and the third mask layer is patterned to form a third opening in the third mask layer that exposes a preset position of the trench gate structure; wherein the third opening exposes the initial body region and an area of ​​the first sub-region adjacent to the initial body region; forming a spacer layer on the sidewall of the third opening adjacent to the first sub-region, so as to form a fourth opening in the third mask layer whose width is smaller than that of the third opening; wherein the width of the fourth opening is greater than or equal to the width of the initial body region exposed by the third opening; forming a gate trench on the surface of the first region exposed by the fourth opening, and forming a first blocking layer in the gate trench; The spacer layer located on the side wall of the third opening is removed, and the first conductive type ions are implanted into the exposed surface of the first region to form a first sub-contact region; wherein the first sub-region retained after the first sub-contact region is formed serves as the second sub-contact region, and the initial body region into which the first conductive type ions are not implanted serves as the body region; The first barrier layer is removed, and a trench gate structure is formed in the gate trench.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The semiconductor body further includes a second contact region; and the method for preparing the semiconductor device further includes: A second contact region is formed on at least one side of the trench gate structure; the second contact region is located on a side of the first contact region away from the trench gate structure and on a side of the body region away from the second surface.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: A second contact region is formed on at least one side of the trench gate structure, comprising: forming a second barrier layer on a surface of the first barrier layer and a first surface of the semiconductor body; patterning the second barrier layer to form an opening in the second barrier layer that exposes a predetermined position of the second contact region; Based on the patterned second barrier layer, implanting second conductive type ions into a preset position of the second contact region to form a second contact region; The second barrier layer is removed.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: A second contact region is formed on at least one side of the trench gate structure, comprising: After forming the first sub-contact region, removing the third mask layer and removing the first barrier layer; forming an etch stop layer on the trench wall of the gate trench and the first surface of the semiconductor body; forming a third barrier layer on a surface of the etch stop layer, the third barrier layer having a thickness greater than that of the etch stop layer; Patterning the third barrier layer to form an opening in the third barrier layer that exposes the etch barrier layer at a predetermined position of the second contact region; Based on the patterned third barrier layer, implanting second conductive type ions into a preset position of the second contact region to form a second contact region; Before forming a trench gate structure in the gate trench, the method further includes: The third barrier layer and the etch stop layer are removed.

11. The method for preparing a semiconductor device according to claim 9 or 10, characterized in that: Forming a trench gate structure in the gate trench, comprising: forming a gate insulating layer on the groove wall of the gate groove; A polysilicon gate is formed on the surface of the gate insulating layer.

12. The method for preparing a semiconductor device according to claim 9 or 10, characterized in that: The first surface also includes a third region surface, and while forming the initial body region, it also includes: Implanting second conductive type ions into the surface of the third region to form a second conductive type region of the body diode; While forming the second sub-contact region, the method further includes: The second conductive type ions are implanted again into the second conductive type region of the body diode to increase the ion doping concentration on the surface of the second conductive type region of the body diode.

13. The method for preparing a semiconductor device according to claim 6, characterized in that: Before forming a gate electrode in contact with the gate structure and a first electrode in contact with the second sub-contact region on the surface of the first region of the semiconductor body, the method further includes: A passivation layer is formed on the surface of the first region of the semiconductor body, and a first electrode connection port exposing the second sub-contact region and a gate connection port exposing the gate structure are formed in the passivation layer.

14. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 4, wherein the substrate is used for carrying the semiconductor power device.

15. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor power device according to any one of claims 1 to 4, wherein the semiconductor power device is electrically connected to the circuit board.

16. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 15, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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