Method for improving capacitance between source and drain of shield gate trench device

Abstract

The invention provides a method for improving capacitance between a source and a drain of a shield gate trench device, which comprises the following steps of: providing a substrate, forming a deep trench on the substrate, forming a first gate dielectric layer on the substrate and the deep trench, then forming a source polycrystalline silicon layer which covers the substrate, fills the residual deep trench and is of a first conduction type, and etching the source polycrystalline silicon layer to a required height; doping the source polycrystalline silicon layer by utilizing ion implantation of the first conduction type so as to improve the doping concentration of the source polycrystalline silicon layer; the first gate dielectric layer is etched to form a shallow trench located between the source polycrystalline silicon layer and the substrate, a second gate dielectric layer is deposited in the shallow trench, and the second gate dielectric layer on the source polycrystalline silicon layer is thicker than other parts; and forming a gate polycrystalline silicon layer for filling the shallow trench. According to the invention, the thickness of the second gate dielectric layer between the gate polysilicon layer and the source polysilicon layer can be increased, and the output capacitance can be reduced.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving the source-drain capacitance of a shielded gate trench device. Background Art

[0002] Power devices require lower and lower switching losses and shorter turn-off times, and an important measure is to reduce the output capacitance Coss of the device.

[0003] For Figure 1 and 2 In the LRSGT (shielded gate trench device) shown, the overlapping portion Cgs of the source polysilicon and the gate is an important component of the output capacitance Coss.

[0004] The IPO (inter-gate dielectric layer) is grown simultaneously with the GOX (gate oxide layer) through furnace oxidation, so how to increase the thickness of the IPO becomes a top priority.

[0005] In order to solve the above problems, it is necessary to propose a new method for improving the source-drain capacitance of the shielded gate trench device. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the source-drain capacitance of a shielded gate trench device, so as to solve the problem in the prior art that the inter-gate dielectric layer of the overlapping portion of the source polysilicon and the gate affects the output capacitance.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving the source-drain capacitance of a shielded gate trench device, comprising:

[0008] Step 1, providing a substrate, forming a deep trench on the substrate, forming a first gate dielectric layer on the substrate and the deep trench, then forming a source polysilicon layer of the first conductivity type covering the substrate and filling the remaining deep trench, and etching the source polysilicon layer to a desired height;

[0009] Step 2: doping the source polysilicon layer by ion implantation of the first conductivity type to increase the doping concentration of the source polysilicon layer;

[0010] Step 3: etching the first gate dielectric layer to form a shallow trench between the source polysilicon layer and the substrate, and depositing a second gate dielectric layer in the shallow trench, wherein the second gate dielectric layer on the source polysilicon layer is thicker than that at other locations;

[0011] Step 4: forming a gate polysilicon layer filling the shallow trench.

[0012] Preferably, in step one, the deep trench is formed by photolithography and etching.

[0013] Preferably, the first conductivity type in step 1 is N type.

[0014] Preferably, in step one, the source polysilicon layer is wet etched to a desired height.

[0015] Preferably, the material of the first gate dielectric layer in step 1 is silicon dioxide.

[0016] Preferably, the ion source of the ion implantation in step 2 is As, the implantation energy is 30-100 keV, and the implantation dose is 1E15-1E17.

[0017] Preferably, the etching method in step three is wet etching.

[0018] Preferably, the material of the second gate dielectric layer in step three is silicon dioxide.

[0019] Preferably, in step four, the source polysilicon layer filling the shallow trench is formed by deposition and polysilicon back etching.

[0020] Preferably, the method further comprises: forming a body region on the substrate at one side of the source polysilicon; forming a source region on the body region and a source metal leading out of the source region; and forming a drain metal on the back side of the substrate.

[0021] As described above, the method for improving the source-drain capacitance of a shielded gate trench device of the present invention has the following beneficial effects:

[0022] The present invention can increase the thickness of the second gate dielectric layer between the gate polysilicon layer and the source polysilicon layer, thereby reducing the output capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic cross-sectional structure diagram of a shielded gate trench device of the prior art;

[0024] Figure 2 Shown is a circuit schematic diagram of a prior art shielded gate trench device;

[0025] Figure 3 Shown is a schematic diagram of the process flow of the present invention;

[0026] Figure 4 It is a schematic diagram of etching the source polysilicon layer of the present invention;

[0027] Figure 5 It is a schematic diagram showing ion implantation into a source polysilicon layer according to the present invention;

[0028] Figure 6 It is a schematic diagram of forming a second gate dielectric layer according to the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] See also Figure 3 The present invention provides a method for improving the source-drain capacitance of a shielded gate trench device, comprising:

[0031] Step 1: providing a substrate 101, forming a deep trench on the substrate 101, forming a first gate dielectric layer 102 on the substrate 101 and the deep trench, and then forming a source polysilicon layer 103 of the first conductivity type covering the substrate 101 and filling the remaining deep trench, and etching the source polysilicon layer 103 to a desired height, usually the upper surface of the source polysilicon layer 103 is slightly lower than the upper surface of the substrate 101;

[0032] In some embodiments, in step 1, the deep trench is formed by photolithography and etching.

[0033] In some embodiments, the first conductivity type in step 1 is N type.

[0034] In some embodiments, in step 1, the source polysilicon layer 103 is wet etched to a desired height.

[0035] In some embodiments, the material of the first gate dielectric layer 102 in step 1 is silicon dioxide, which can be prepared by thermal oxidation, atomic layer deposition, chemical vapor deposition, and the like.

[0036] Step 2: doping the source polysilicon layer 103 by ion implantation of the first conductivity type to increase the doping concentration of the source polysilicon layer 103;

[0037] In some embodiments, the ion source of the ion implantation in step 2 is As, the implantation energy is 30-100 keV, and the implantation dose is 1E15-1E17, for example, the implantation energy is 70 keV, and the implantation dose is 4.4E15. In other embodiments, the tilt angle, dopant, dose and energy of the ion implantation can be adjusted according to process requirements.

[0038] Step 3: Etch the first gate dielectric layer 102 to form a shallow trench between the source polysilicon layer 103 and the substrate 101, and deposit a second gate dielectric layer 104 in the shallow trench. The second gate dielectric layer 104 can be formed by atomic layer deposition, chemical vapor deposition, etc. Since the doping concentration of the source polysilicon layer 103 is increased in step 2, the second gate dielectric layer 104 is formed faster on the surface of the source polysilicon layer 103 during the deposition process. The second gate dielectric layer 104 on the source polysilicon layer 103 is thicker than that at other locations, which is beneficial to increase the thickness of the second gate dielectric layer 104 between the gate polysilicon layer and the source polysilicon layer 103, thereby reducing the overlapping portion Cgs of the source polysilicon layer 103 and the gate polysilicon layer.

[0039] In some embodiments, the etching method in step three is wet etching.

[0040] In some embodiments, the material of the second gate dielectric layer 104 in step three is silicon dioxide.

[0041] Step 4: forming a gate polysilicon layer filling the shallow trench.

[0042] In some embodiments, in step 4, a source polysilicon layer filling the shallow trench is formed by deposition and polysilicon back etching.

[0043] In some embodiments, the method further includes: forming a body region on the substrate 101 on one side of the source polysilicon; forming a source region on the body region and a source metal leading out of the source region; and forming a drain metal on the back side of the substrate 101 .

[0044] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] In summary, the present invention can increase the thickness of the second gate dielectric layer between the gate polysilicon layer and the source polysilicon layer and reduce the output capacitance. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the source-drain capacitance of a shielded gate trench device, characterized in that: At least: Step 1, providing a substrate, forming a deep trench on the substrate, forming a first gate dielectric layer on the substrate and the deep trench, then forming a source polysilicon layer of the first conductivity type covering the substrate and filling the remaining deep trench, and etching the source polysilicon layer to a desired height; Step 2: doping the source polysilicon layer by ion implantation of the first conductivity type to increase the doping concentration of the source polysilicon layer; Step 3: etching the first gate dielectric layer to form a shallow trench between the source polysilicon layer and the substrate, and depositing a second gate dielectric layer in the shallow trench, wherein the second gate dielectric layer on the source polysilicon layer is thicker than that at other locations; Step 4: forming a gate polysilicon layer filling the shallow trench.

2. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: In step one, the deep trench is formed by photolithography and etching.

3. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: The first conductivity type in step 1 is N type.

4. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: In step 1, the source polysilicon layer is wet etched to a desired height.

5. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: The material of the first gate dielectric layer in step 1 is silicon dioxide.

6. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 3, characterized in that: The ion source of the ion implantation in step 2 is As, the implantation energy is 30-100 keV, and the implantation dose is 1E15-1E17.

7. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: The etching method in step three is wet etching.

8. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: The material of the second gate dielectric layer in step three is silicon dioxide.

9. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: In step 4, the source polysilicon layer filling the shallow trench is formed by deposition and polysilicon back etching.

10. The method for improving the source-drain capacitance of a shielded gate trench device according to claim 1, characterized in that: The method further includes: forming a body region on the substrate and located on one side of the source polysilicon; forming a source region on the body region and a source metal leading out of the source region; and forming a drain metal on the back side of the substrate.

Images