An integrated chip structure and a manufacturing method thereof

Abstract

The present invention provides an integrated chip structure and a manufacturing method thereof. The above structure includes a composite epitaxial structure, a high-voltage device region, a low-voltage device region, and a BJT region; the high-voltage device region, the low-voltage device region, and the BJT region are isolated from each other and disposed in the upper region of the composite epitaxial structure; the high-voltage device region is used to form high-voltage devices, the low-voltage device region is used to form low-voltage devices, and the BJT region is used to form bipolar junction transistors; the composite epitaxial structure includes a bottom layer, a SiC isolation layer, and a device preparation layer stacked along a second direction; the SiC isolation layer is bonded on the bottom layer, and a bonding interface layer is formed between the SiC isolation layer and the bottom layer; the device preparation layer is epitaxially disposed on the SiC isolation layer and is used to fabricate the high-voltage device region, the low-voltage device region, and the BJT region. The wafer size obtained by using this composite epitaxial structure can reach 12 inches, which is much larger than the size of the currently mainstream 4H-SiC wafers, thereby reducing the overall process cost. The bonded SiC isolation layer can effectively prevent the occurrence of current and voltage crosstalk.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an integrated chip structure and a manufacturing method thereof. Background Art

[0002] In recent years, the field of wide-bandgap semiconductor materials has developed rapidly, and materials such as SiC, GaN, gallium oxide (Ga2O3), diamond (C) and aluminum nitride (AlN) have emerged. Compared with traditional Si materials, these wide-bandgap semiconductor materials have shown significant advantages in key physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity, successfully breaking through the bottleneck that silicon-based materials are difficult to cope with high-power, high-voltage, high-frequency, and high-temperature application scenarios, and opening up a feasible path to surpass Moore's Law.

[0003] In practical applications, SiC power devices, due to their material properties, have shown broad application potential in new energy, aerospace, nuclear power and other fields facing high temperature, high pressure and high radiation environments. However, the driving circuits and protection circuits used with SiC power devices at this stage still use silicon-based materials. This mismatch greatly limits the full performance of SiC power devices, thereby restricting their application scope.

[0004] To overcome this problem, the field attempts to integrate the driving circuit and protection circuit of SiC power devices on SiC wafers, in order to effectively enhance system reliability, reduce parasitic effects, and optimize the overall system performance. However, as far as the existing silicon carbide integrated devices are concerned, although the phased results of monolithic integration have been achieved, they have fallen into a new dilemma: voltage or current crosstalk problems frequently occur between the device regions, which greatly reduces the chip performance.

[0005] Therefore, there is an urgent need to design a complex and effective isolation structure to resolve the above-mentioned technical difficulties and promote the in-depth application and steady development of wide bandgap semiconductor materials in the field of power devices. Summary of the invention

[0006] Based on the above description, the present invention provides an integrated chip structure and a method for manufacturing the same to solve the technical problem in the prior art that when performing monolithic integration on a SiC wafer, there is serious voltage and current crosstalk between device regions, which seriously affects the performance of the chip.

[0007] The technical solution of the present invention to solve the above technical problems is as follows:

[0008] In a first aspect, the present invention provides an integrated chip structure, comprising: a composite epitaxial structure, an interlayer dielectric layer, a high voltage device region, a low voltage device region and a BJT region;

[0009] The interlayer dielectric layer is disposed on the upper surface of the composite epitaxial structure;

[0010] The high-voltage device region, the low-voltage device region, and the BJT region are isolated from each other and disposed in the upper region of the composite epitaxial structure and the interlayer dielectric layer;

[0011] The high-voltage device region is used to form high-voltage devices, the low-voltage device region is used to form low-voltage devices, and the BJT region is used to form bipolar junction transistors;

[0012] Wherein, the composite epitaxial structure includes a bottom layer, a SiC isolation layer, and a device preparation layer stacked in sequence along the vertical direction; the SiC isolation layer is bonded on the bottom layer, and a bonding interface layer is formed between the SiC isolation layer and the bottom layer; the device preparation layer is epitaxially disposed on the SiC isolation layer and is used to fabricate the high-voltage device region, the low-voltage device region, and the BJT region.

[0013] On the basis of the above technical solution, the present invention can be further improved as follows.

[0014] Further, a first N-type well region and a P-body region are formed in the high-voltage device region;

[0015] And, a first P+ region and a first N+ region formed in the top region of the P-body region;

[0016] A gate oxide layer formed above the device preparation layer;

[0017] A first gate electrode formed on the gate oxide layer above the P-body region between the first N-type well region and the first N+ region, and the first gate electrode partially covers the first N-type well region and the first N+ region;

[0018] A first source electrode passing through the interlayer dielectric layer and connected to the first P+ region and the first N+ region;

[0019] A second N+ region formed in the top region of the first N-type well region;

[0020] A first drain electrode passing through the interlayer dielectric layer and connected to the second N+ region.

[0021] Further, the low-voltage device region includes a P-type MOS region and an N-type MOS region disposed at intervals in the device preparation layer.

[0022] Further, a second N-type well region is formed in the P-type MOS region;

[0023] And, a second P+ region, a third P+ region, and a third N+ region formed in the top region of the second N-type well region;

[0024] A second drain that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the second P+ region;

[0025] A second source that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the third P+ region and the third N+ region;

[0026] A second gate formed on the gate oxide dielectric layer above the P-body region between the second P+ region and the third P+ region, and the second gate partially covers the second P+ region and the third P+ region.

[0027] Furthermore, a first P-type well region is formed in the N-type MOS region;

[0028] And a fourth P+ region, a fourth N+ region, and a fifth N+ region formed in the top region of the first P-type well region;

[0029] A third source that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the fourth P+ region and the fourth N+ region;

[0030] A third drain that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the fifth N+ region;

[0031] A third gate formed on the gate oxide dielectric layer above the P-body region between the fourth N+ region and the fifth N+ region, and the third gate partially covers the fourth N+ region and the fifth N+ region.

[0032] Furthermore, when the device preparation layer is P-type epitaxy, a third N-type well region and a second P-type well region are formed in the BJT region; and a sixth N+ region and a fifth P+ region formed in the top region of the third N-type well region; a sixth P+ region formed in the top region of the second P-type well region; a base that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the sixth N+ region; an emitter that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the fifth N+ region; a collector that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the fourth N+ region;

[0033] When the device preparation layer is N-type epitaxy, a third P-type well region and a fourth N-type well region are formed in the BJT region; and a seventh P+ region, a seventh N+ region, and an eighth N+ region formed in the top region of the third P-type well region; a base that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the seventh P+ region; an emitter that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the seventh N+ region; a collector that is disposed through the interlayer dielectric layer and the gate oxide dielectric layer and is connected to the eighth N+ region.

[0034] Further, the bottom layer includes a Si substrate and a high heat dissipation layer epitaxially grown on the Si substrate; the high heat dissipation layer is a 3C-SiC epitaxial layer;

[0035] Or, the bottom layer is a 3C-SiC polycrystalline substrate.

[0036] Further, the device preparation layer is a 3C-SiC or 4H-SiC epitaxial layer.

[0037] In a second aspect, the present invention also provides a manufacturing method for manufacturing the integrated chip structure as described in the first aspect, including:

[0038] Epitaxially grow a 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC substrate;

[0039] Perform H+ implantation on the surface of a semi-insulating SiC wafer to form an H+ aggregation layer;

[0040] Clean the surfaces of the 3C-SiC substrate and the semi-insulating SiC wafer;

[0041] Flip the semi-insulating SiC wafer and bond it with the 3C-SiC substrate, and strengthen the bonding strength at 150 °C;

[0042] Peel off the semi-insulating SiC wafer along the H+ aggregation layer at 300 °C, anneal at 1100 °C to strengthen the bonding strength, and polish the wafer surface;

[0043] Epitaxially grow a 3C or 4H-SiC epitaxial layer to form a device preparation layer;

[0044] Fabricate integrated devices on the device preparation layer;

[0045] Wherein, the device preparation layer includes a high-voltage device area, a low-voltage device area, and a BJT area; a high-voltage device is formed in the high-voltage device area, a low-voltage device is formed in the low-voltage device area, and a bipolar junction transistor is formed in the BJT area.

[0046] Based on the above technical solutions, the present invention can also be improved as follows.

[0047] Further, the fabricating integrated devices on the device preparation layer specifically includes:

[0048] Form a plurality of N-type well regions, P-type well regions, P-body regions, N-type heavily doped regions, and P-type heavily doped regions in the device preparation layer by multiple ion implantations;

[0049] Grow a gate oxide dielectric layer by thermal oxidation;

[0050] Form a polysilicon gate through deposition and etching;

[0051] Form isolation trenches by etching and filling with a dielectric, or use PN junction isolation;

[0052] Grow an interlayer dielectric layer and etch metal vias;

[0053] Deposit and etch metal to form metal electrodes.

[0054] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects:

[0055] The integrated chip structure and its manufacturing method provided by the present invention have the following beneficial effects compared with the prior art:

[0056] The composite epitaxial structure therein is to first epitaxially grow a 3C-SiC epitaxial layer on a Si substrate, then bond a semi-insulating (HPSI) SiC peeling film on this structure, and then epitaxially grow a 3C-SiC or 4H-SiC epitaxial layer on the surface. Finally, the device structure is integrated into the 3C-SiC or 4H-SiC epitaxial layer on the surface - the high-voltage device area, the low-voltage device area, and the BJT area are mutually isolated and arranged in the upper area of the composite epitaxial structure. The high-voltage device area is used to form high-voltage devices, the low-voltage device area is used to form low-voltage devices, and the BJT area is used to form bipolar junction transistors.

[0057] The wafer size obtained by using the above composite epitaxial structure can reach 12 inches, which is much larger than the size of the current mainstream 4H-SiC wafers, thereby reducing the overall process cost and enabling the use of advanced processes in Si integrated circuits. In addition, after bonding the semi-insulating (HPSI) SiC peeling film, a SiC isolation layer is naturally formed, which can effectively prevent the occurrence of current and voltage crosstalk. Description of the Drawings

[0058] Figure 1 It is a schematic structural diagram of the integrated chip structure provided in Embodiment 1 of the present invention;

[0059] Figure 2 It is a schematic structural diagram of the composite epitaxial structure in the integrated chip structure provided in Embodiment 1 of the present invention;

[0060] Figure 3 It is a schematic structural diagram of the integrated chip structure provided in Embodiment 2 of the present invention;

[0061] Figure 4 It is a schematic structural diagram of the composite epitaxial structure in the integrated chip structure provided in Embodiment 3 of the present invention;

[0062] Figure 5 It is a schematic structural diagram of the integrated chip structure provided in Embodiment 4 of the present invention;

[0063] Figure 6 Schematic diagram of the integrated chip structure provided in Embodiment 5 of the present invention;

[0064] Figure 7 Schematic diagram of the manufacturing process of the integrated chip structure provided in Embodiment 6 of the present invention;

[0065] Figure 8 Schematic diagram of the process of fabricating integrated devices on the device preparation layer in the manufacturing process of the integrated chip structure provided in Embodiment 6 of the present invention;

[0066] In the drawings, the list of components represented by each reference numeral is as follows:

[0067] 1. Composite epitaxial structure; 11. Bottom layer; 111. Substrate; 112. High heat dissipation layer; 12. SiC isolation layer; 13. Device preparation layer;

[0068] 2. High-voltage device region; 21. First N-type well region; 22. P-body region; 23. First gate; 24. First P+ region; 25. First N+ region; 26. First source; 27. Second N+ region; 28. First drain;

[0069] 3. Low-voltage device region;

[0070] 31. P-type MOS region; 311. Second N-type well region; 312. Second P+ region; 313. Third P+ region; 314. Third N+ region; 315. Second source; 316. Second gate; 317. Second drain;

[0071] 32. N-type MOS region; 321. First P-type well region; 322. Fourth P+ region; 323. Fourth N+ region; 324. Fifth N+ region; 325. Third source; 326. Third drain; 327. Third gate;

[0072] 4. BJT region; 41. Third N-type well region; 42. Second P-type well region; 43. Sixth N+ region; 44. Fifth P+ region; 45. Sixth P+ region; 46. Base; 47. Emitter; 48. Collector; 49. Third P-type well region; 410. Fourth N-type well region; 411. Seventh P+ region; 412. Seventh N+ region; 413. Eighth N+ region;

[0073] 5. Isolation region;

[0074] 6. Shallow trench isolation;

[0075] 7. Interlayer dielectric layer;

[0076] 8. Gate oxide dielectric layer. Detailed implementation manners

[0077] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0078] In the prior art, the development status and existing defects of power devices are as follows:

[0079] 1. Currently, the drive circuits, protection circuits, etc. used in matching with silicon carbide power devices are still silicon-based, which limits the application scope of power devices.

[0080] 2. The cost of developing integrated chips on SiC is too high; currently, the mainstream SiC wafers are 6-inch 4H-SiC wafers. On the one hand, the price of the wafers themselves is relatively high, and on the other hand, the smaller wafer size brings higher process costs.

[0081] 3. Currently, the wafer sizes used in advanced Si processes are mostly 12 inches. Therefore, the 6-inch 4H-SiC wafers limit the application of more advanced processes.

[0082] 4. When performing monolithic integration on SiC wafers, there are serious voltage and current crosstalks between device regions, which will seriously affect the performance of the chips. Therefore, a relatively complex isolation structure needs to be designed.

[0083] Based on this, the present invention provides a new integrated chip structure and its manufacturing method.

[0084] The following will further describe in detail the implementation manners of the present invention with reference to the drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0085] It should be noted that: The terms "first", "second", etc. in the specification, claims, and drawings of this application are used to distinguish different objects, rather than to limit a specific order.

[0086] Embodiment 1

[0087] As Figure 1 shown, this embodiment provides an integrated chip structure, including: a composite epitaxial structure 1, an interlayer dielectric layer 7, a high-voltage device region 2, a low-voltage device region 3, and a BJT region 4.

[0088] The high-voltage device region 2, the low-voltage device region 3, and the BJT region 4 are mutually isolated and arranged in the upper region of the composite epitaxial structure 1 and the interlayer dielectric layer 7.

[0089] In this embodiment, the interlayer dielectric layer 7 is arranged on the upper surface of the composite epitaxial structure 1.

[0090] The high-voltage device region 2, the low-voltage device region 3, and the BJT region 4 are isolated from each other by an isolation trench to form an isolation region 5.

[0091] The high-voltage device region 2 is used to form high-voltage devices, the low-voltage device region 3 is used to form low-voltage devices, and the BJT region 4 is used to form bipolar junction transistors.

[0092] Among them, as Figure 2 shown, the composite epitaxial structure 1 includes a bottom layer 11, a SiC isolation layer 12, and a device preparation layer 13 that are sequentially stacked in the vertical direction; the SiC isolation layer 12 is bonded to the bottom layer 11, and a bonding interface layer is formed between the SiC isolation layer 12 and the bottom layer 11; the device preparation layer 13 is epitaxially grown on the SiC isolation layer 12 and is used to fabricate the high-voltage device region 2, the low-voltage device region 3, and the BJT region 4.

[0093] In this embodiment, as Figure 2 shown, the above-mentioned bottom layer 11 includes a Si substrate 111 and a high heat dissipation layer 112 epitaxially grown on the Si substrate; the high heat dissipation layer 112 is a 3C-SiC epitaxial layer.

[0094] The device preparation layer 13 is a 3C-SiC epitaxial layer or a 4H-SiC epitaxial layer.

[0095] Furthermore, in a specific example, as Figure 1 shown, the high-voltage device region 2 is formed with a first N-type well region 21 and a P-body region 22;

[0096] and, a first P+ region 24 and a first N+ region 25 formed in the top region of the P-body region 22;

[0097] a gate oxide layer 8 formed above the device preparation layer 13;

[0098] a first gate 23 formed on the gate oxide layer 8 above the P-body region 22 between the first N-type well region 21 and the first N+ region 25, and the first gate 23 partially covers the first N-type well region 21 and the first N+ region 25;

[0099] a first source 26 passing through the interlayer dielectric layer 7 and the gate oxide layer 8 and connected to the first P+ region 24 and the first N+ region 25;

[0100] a second N+ region 27 formed in the top region of the first N-type well region 21;

[0101] a first drain 28 passing through the interlayer dielectric layer 7 and the gate oxide layer 8 and connected to the second N+ region 27.

[0102] The low-voltage device region 3 includes a P-type MOS region 31 and an N-type MOS region 32 that are spaced apart in the device preparation layer 13.

[0103] Among them, a second N-type well region 311 is formed in the P-type MOS region 31;

[0104] And, a second P+ region 312, a third P+ region 313, and a third N+ region 314 formed in the top region of the second N-type well region 311;

[0105] A second drain 317 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the second P+ region 312;

[0106] A second source 315 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the third P+ region 313 and the third N+ region 314;

[0107] A second gate 316 formed on the gate oxide dielectric layer 8 above the P-body region 22 between the second P+ region 312 and the third P+ region 313, and the second gate 316 partially covers the second P+ region 312 and the third P+ region 313.

[0108] An N-type MOS region 32 is formed with a first P-type well region 321;

[0109] And, a fourth P+ region 322, a fourth N+ region 323, and a fifth N+ region 324 formed in the top region of the first P-type well region 321;

[0110] A third source 325 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fourth P+ region 322 and the fourth N+ region 323;

[0111] A third drain 326 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fifth N+ region 324;

[0112] A third gate 327 formed on the gate oxide dielectric layer 8 above the P-body region between the fourth N+ region 323 and the fifth N+ region 324, and the third gate 327 partially covers the fourth N+ region 323 and the fifth N+ region 324.

[0113] It should be noted that in this embodiment, the device preparation layer is P-type epitaxy. The BJT region 4 is formed with a third N-type well region 41 and a second P-type well region 42; and, a sixth N+ region 43 and a fifth P+ region 44 formed in the top region of the third N-type well region 41; a sixth P+ region 45 formed in the top region of the second P-type well region 42; a base 46 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the sixth N+ region 43; an emitter 47 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fifth N+ region 44; a collector 48 penetrating through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fourth N+ region 323.

[0114] In summary, for the integrated chip structure provided in this embodiment, a 3C-SiC epitaxial layer is first epitaxially grown on a Si substrate, and then a semi-insulating (HPSI) SiC peeling film is bonded to this structure. Next, a 3C-SiC epitaxial layer is epitaxially grown on the surface, and the device structure is integrated within the 3C-SiC epitaxial layer on the surface. The wafer size of the composite wafer fabricated by this solution can reach 12 inches, which is much larger than the size of the currently mainstream 4H-SiC wafers, thereby reducing the overall process cost and enabling the adoption of advanced processes in Si integrated circuits. Since 3C-SiC serves as a high heat dissipation layer, it can effectively improve the thermal characteristics of the device. In addition, a natural isolation layer is formed after bonding the semi-insulating (HPSI) SiC peeling film, which can effectively prevent the occurrence of current and voltage crosstalk.

[0115] Embodiment 2

[0116] Based on Embodiment 1, the difference from Embodiment 1 lies in:

[0117] In this embodiment, as Figure 3 shown, the device preparation layer on the surface can also be N-type. Correspondingly, the device structure will change to some extent (BJT region);

[0118] Specifically, when the device preparation layer is N-type epitaxy, a third P-type well region 49 and a fourth N-type well region 410 are formed in the BJT region 4; and, a seventh P+ region 411, a seventh N+ region 412, and an eighth N+ region 413 formed in the top region of the third P-type well region 49; a base passing through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the seventh P+ region 411; an emitter passing through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the seventh N+ region 412; a collector passing through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the eighth N+ region 413.

[0119] For the remaining same structures, refer to the description in Embodiment 1, which will not be elaborated here.

[0120] Embodiment 3

[0121] Based on Embodiment 1, the difference from Embodiment 1 lies in:

[0122] In this embodiment, as Figure 4 shown, the bottom layer 11 is a 3C-SiC polycrystalline substrate.

[0123] Specifically, a 3C-SiC polycrystalline substrate is used instead of epitaxially growing a 3C-SiC epitaxial layer on a Si substrate. The polycrystalline 3C-SiC substrate is inexpensive and has high mechanical strength.

[0124] For the remaining same structures, refer to the description in Embodiment 1, which will not be elaborated here.

[0125] Embodiment 4

[0126] Based on Embodiment 1, the difference from Embodiment 1 is as follows:

[0127] As Figure 5 shown, a shallow trench isolation (STI) 6 can be introduced between the NMOS region and the PMOS region in the low-voltage device region to avoid crosstalk between the NMOS and the PMOS.

[0128] For the remaining same structures, refer to the description of Embodiment 1 and will not be elaborated here.

[0129] Embodiment 5

[0130] Based on Embodiment 1, the difference from Embodiment 1 is as follows:

[0131] As Figure 6 shown, the isolation between different device regions can adopt PN junction isolation instead of trench isolation, and by grounding the epitaxial layer, it is ensured that the PN junction between the deep N-well region and the epitaxial layer will not be forward-biased and conduct.

[0132] For the remaining same structures, refer to the description of Embodiment 1 and will not be elaborated here.

[0133] Embodiment 6

[0134] This embodiment provides a manufacturing method of the integrated chip structure provided in Embodiment 1. As Figure 7 shown, the operations are as follows:

[0135] Step S1: Epitaxially grow a 3C-SiC epitaxial layer on the Si substrate to obtain a 3C-SiC substrate.

[0136] Next, bond a semi-insulating (HPSI) SiC wafer to the surface of the 3C-SiC epitaxial layer through the Smart-cut process. The bonding equipment and process can select the wafer bonding process equipment of the SAB (surface activation bonding) technology to avoid generating defects, oxide layers or amorphous layers at the bonding interface; through treatment means such as annealing, further repair and strengthen the bonding interface; the specific process includes the following steps S2 to S5:

[0137] Step S2: Perform H+ implantation on the surface of the semi-insulating SiC wafer to form an H+ aggregation layer.

[0138] Step S3: Clean the surfaces of the 3C-SiC substrate and the semi-insulating SiC wafer.

[0139] Step S4: Flip the semi-insulating SiC wafer and bond it to the 3C-SiC substrate, and strengthen the bonding strength at 150 °C;

[0140] Step S5: Peel the semi-insulating SiC wafer along the H+ aggregation layer at 300 °C, anneal at 1100 °C to enhance the bonding strength, and polish the wafer surface;

[0141] Step S6: Epitaxially grow a 3C epitaxial layer to form a device preparation layer;

[0142] Step S7: Fabricate integrated devices on the device preparation layer;

[0143] Among them, the device preparation layer includes a high-voltage device area, a low-voltage device area, and a BJT area; a high-voltage device is formed in the high-voltage device area, a low-voltage device is formed in the low-voltage device area, and a bipolar junction transistor is formed in the BJT area.

[0144] Specifically, in this embodiment, the P-type epitaxial layer is taken as an example for introduction, as Figure 8 shown, step S7 specifically includes:

[0145] Step S701: Form multiple N-type well regions (N-well), P-type well regions (P-well), P-body regions, N-type heavily doped regions (N+), and P-type heavily doped regions (P+) in the device preparation layer through multiple ion implantations;

[0146] Step S702: Thermally oxidize to grow a gate oxide dielectric layer;

[0147] Step S703: Deposit and etch to form a polysilicon gate;

[0148] Step S704: Form isolation trenches by etching and filling with a dielectric, or use PN junction isolation;

[0149] Step S705: Grow an interlayer dielectric layer and etch metal vias;

[0150] Step S706: Deposit and etch metal to form metal electrodes.

[0151] In summary, the integrated chip structures and corresponding manufacturing methods provided in the above Embodiments 1 to 6 have the following technical effects: The composite epitaxial structure therein is to first epitaxially grow a 3C-SiC epitaxial layer on a Si substrate, then bond a semi-insulating (HPSI) SiC peeling film on this structure, and then epitaxially grow a 3C-SiC or 4H-SiC epitaxial layer on the surface. Finally, the device structure is integrated into the 3C-SiC or 4H-SiC epitaxial layer on the surface - the high-voltage device area, the low-voltage device area, and the BJT area are isolated from each other and disposed in the upper region of the composite epitaxial structure. The high-voltage device area is used to form high-voltage devices, the low-voltage device area is used to form low-voltage devices, and the BJT area is used to form bipolar junction transistors.

[0152] The wafer size obtained using the above composite epitaxial structure can reach 12 inches, which is much larger than the size of the currently mainstream 4H-SiC wafers, thereby reducing the overall process cost and enabling the adoption of advanced processes in Si integrated circuits. In addition, after bonding and peeling the semi-insulating (HPSI) SiC thin film, a SiC isolation layer is naturally formed, which can effectively prevent the occurrence of current and voltage crosstalk.

[0153] In the description of this specification, the description with reference to terms such as "specific example" or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated chip structure, characterized in that, Comprising: A composite epitaxial structure, an interlayer dielectric layer, a high-voltage device region, a low-voltage device region, and a BJT region; The interlayer dielectric layer is disposed on the upper surface of the composite epitaxial structure; The high-voltage device region, the low-voltage device region, and the BJT region are isolated from each other and disposed in the upper region of the composite epitaxial structure and the interlayer dielectric layer; The high-voltage device region is used to form high-voltage devices, the low-voltage device region is used to form low-voltage devices, and the BJT region is used to form bipolar junction transistors; Wherein, the composite epitaxial structure includes a bottom layer, a SiC isolation layer, and a device preparation layer arranged in sequence and stacked in the vertical direction; the SiC isolation layer is bonded on the bottom layer, and a bonding interface layer is formed between the SiC isolation layer and the bottom layer; the device preparation layer is epitaxially grown on the SiC isolation layer and is used to fabricate the high-voltage device region, the low-voltage device region, and the BJT region; the device preparation layer is a 3C-SiC or 4H-SiC epitaxial layer.

2. The integrated chip structure according to claim 1, wherein The high-voltage device region is formed with a first N-type well region and a P-body region; And, a first P+ region and a first N+ region formed in the top region of the P-body region; A gate oxide layer formed above the device preparation layer; A first gate formed on the gate oxide layer above the P-body region between the first N-type well region and the first N+ region, and the first gate partially covers the first N-type well region and the first N+ region; A first source electrode passing through the interlayer dielectric layer and the gate oxide layer and connected to the first P+ region and the first N+ region; A second N+ region formed in the top region of the first N-type well region; A first drain electrode passing through the interlayer dielectric layer and the gate oxide layer and connected to the second N+ region.

3. The integrated chip structure according to claim 2, wherein The low-voltage device region includes a P-type MOS region and an N-type MOS region spaced apart from each other in the device preparation layer.

4. The integrated chip structure according to claim 3, characterized in that, The P-type MOS region is formed with a second N-type well region; And, a second P+ region, a third P+ region, and a third N+ region formed in the top region of the second N-type well region; A second drain electrode passing through the interlayer dielectric layer and the gate oxide layer and connected to the second P+ region; A second source electrode passing through the interlayer dielectric layer and the gate oxide layer and connected to the third P+ region and the third N+ region; A second gate formed on the gate oxide layer above the P-body region between the second P+ region and the third P+ region, and the second gate partially covers the second P+ region and the third P+ region.

5. The integrated chip structure according to claim 3, characterized in that, The N-type MOS region is formed with a first P-type well region; And, a fourth P+ region, a fourth N+ region, and a fifth N+ region formed in the top region of the first P-type well region; A third source electrode passing through the interlayer dielectric layer and the gate oxide layer and connected to the fourth P+ region and the fourth N+ region; A third drain electrode passing through the interlayer dielectric layer and the gate oxide layer and connected to the fifth N+ region; A third gate formed on the gate oxide dielectric layer above the P-body region formed between the fourth N+ region and the fifth N+ region, and the third gate partially covers the fourth N+ region and the fifth N+ region.

6. The integrated chip structure according to claim 5, wherein, When the device preparation layer is P-type epitaxial, a third N-type well region and a second P-type well region are formed in the BJT region; and, a sixth N+ region and a fifth P+ region formed in the top region of the third N-type well region; A sixth P+ region formed in the top region of the second P-type well region; a base passing through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the sixth N+ region; An emitter passing through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fifth N+ region; a collector passing through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fourth N+ region; When the device preparation layer is N-type epitaxial, a third P-type well region and a fourth N-type well region are formed in the BJT region; And, a seventh P+ region, a seventh N+ region and an eighth N+ region formed in the top region of the third P-type well region; a base passing through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the seventh P+ region; an emitter passing through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the seventh N+ region; a collector passing through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the eighth N+ region.

7. The integrated chip structure according to claim 1, wherein, The bottom layer includes a Si substrate and a high heat dissipation layer epitaxially grown on the Si substrate; the high heat dissipation layer is a 3C-SiC epitaxial layer; Or, the bottom layer is a 3C-SiC polycrystalline substrate.

8. A manufacturing method for manufacturing an integrated chip structure as described in any one of claims 1 to 7, characterized in that, Including: Epitaxially grow a 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC substrate; Perform H+ implantation on the surface of a semi-insulating SiC wafer to form an H+ aggregation layer; Clean the surfaces of the 3C-SiC substrate and the semi-insulating SiC wafer; Flip the semi-insulating SiC wafer and bond it with the 3C-SiC substrate, and strengthen the bonding strength at 150 °C; Peel off the semi-insulating SiC wafer along the H+ aggregation layer at 300 °C, anneal at 1100 °C, strengthen the bonding strength, and polish the wafer surface; Epitaxially grow a 3C or 4H-SiC epitaxial layer to form a device preparation layer; Fabricate an integrated device on the device preparation layer; Wherein, the device preparation layer includes a high-voltage device region, a low-voltage device region and a BJT region; a high-voltage device is formed in the high-voltage device region, a low-voltage device is formed in the low-voltage device region, and a bipolar junction transistor is formed in the BJT region.

9. The manufacturing method according to claim 8, characterized in that, The fabricating an integrated device on the device preparation layer specifically includes: Form a plurality of N-type well regions, P-type well regions, P-body regions, N-type heavily doped regions and P-type heavily doped regions in the device preparation layer by multiple ion implantations; Grow a gate oxide dielectric layer by thermal oxidation; Form a polysilicon gate by deposition and etching; Form isolation trenches by etching and filling a dielectric, or use PN junction isolation; Grow an interlayer dielectric layer and etch metal vias; Deposit metal and etch to form metal electrodes.

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