Pixel structure of linear array image sensor and sensor

Abstract

The invention relates to the technical field of CMOS (complementary metal oxide semiconductor) image sensors, in particular to a pixel structure of a linear array image sensor and the sensor, and the pixel structure comprises a partially-clamped photodiode with multi-stage clamping voltage and a high-resistance polycrystalline silicon transmission gate, through a processing technology, a part of the clamping photodiode forms a multi-stage gradient clamping voltage when being used up, so that a longitudinal potential difference and a uniform electric field are formed, and charges are helped to be rapidly transferred to the vicinity of a transmission gate from the upper side and the lower side in the longitudinal direction; different voltages are applied to the two ends of the polycrystalline silicon transmission gate, and a transverse gate voltage difference is formed on the polycrystalline silicon transmission gate, so that potential distribution which is gradually increased from the far end of the output end to the output end is formed when the buried channel is used up. According to the line scanning image sensor pixel structure, rapid transfer of photo-generated charges in a large-size photodiode is achieved, under the condition that the longitudinal size and the transverse size of pixels are large, electron transmission can still be effectively accelerated, the reading time is remarkably shortened, and the trailing phenomenon is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of CMOS image sensors, and in particular relates to a linear array image sensor pixel structure and a sensor. Background Art

[0002] According to the arrangement of the pixel matrix, image sensors can usually be divided into two types: area array image sensors and line array image sensors. Line array image sensors obtain the color, shape, size or distance information of the object by scanning the object line by line, and are usually used in automatic optical inspection machines, screening machines and other electronic imaging equipment. Generally, the lateral resolution of the line scan image sensor determines the detection accuracy, while the longitudinal size determines the effective photosensitive area. Generally, the larger the area of ​​a single pixel column, the higher the sensitivity of the image sensor, which is conducive to increasing the stability of detection and the accuracy of detecting weak signals. On the other hand, the longer the longitudinal size, the longer it takes for the charge in the photodiode to transfer from the far end to the output end, which affects the detection speed.

[0003] The technical document "Resistive gate type CCD linear image sensor with electronic shutter function" published on the website of Hamamatsu Photonics Co., Ltd. describes a method and structure for high-speed charge transfer of a large-size vertical photodiode under CCD (Charge Coupled Device) technology. Figure 1 As shown in the figure, the photosensitive device of this CCD consists of a resistor gate (REG) and a photodiode (PD). The resistor gate completely covers the photodiode, and two electrodes, REGH and REGL, are set at both ends. In addition, this structure includes a storage gate (STG), a transfer gate (TG), and a 2-phase CCD structure (P1H / P2H) for reading out pixel signals. When the photogenerated charge begins to transfer, REGH rises to a high voltage. At this time, the voltage difference between REGH and REGL forms a potential difference inside the diode to accelerate the transfer of charge in the horizontal direction. After the electrons are transferred to the storage gate, the transfer gate and the 2-phase CCD are operated in sequence to transfer the charge to the shift register for signal readout.

[0004] Although the above scheme can improve the detection speed, it uses CCD process and readout structure design. Compared with CIS process, CCD process has high production cost, backward process node, high power consumption, and is not conducive to large-scale integration of logic circuits and analog circuits in image sensor architecture. In addition, in the above scheme design, the transmission gate needs to completely cover the photodiode, the polysilicon gate area is too large, and the row logic circuit needs to provide very high driving capability, which will cause high power consumption problems. At the same time, excessive polysilicon density in local areas will cause yield problems such as uneven etching in production. Summary of the invention

[0005] In view of this, the present invention aims to provide a linear array image sensor pixel structure and sensor based on CMOS process, which enables the photogenerated electrons generated at different positions of the photodiode to be quickly transferred to the output end through gate voltage design, while solving the problem of excessively large polysilicon transmission gate area in the existing design.

[0006] To achieve the above object, the technical solution created by the present invention is implemented as follows: The invention provides a linear array image sensor pixel structure, comprising: a partially clamped photodiode, a polysilicon transmission gate disposed on the surface of the partially clamped photodiode, and a buried channel disposed under the polysilicon transmission gate; Among them, a portion of the clamped photodiode forms a multi-level gradient clamping voltage when depleted, which is used to transfer the charge longitudinally to the corresponding buried channel under the polysilicon transfer gate; The polysilicon transmission gate is laterally disposed at an M end away from the output end of the partially clamped photodiode and an N end close to the output end of the partially clamped photodiode, and the N end and the M end are used to apply voltage; When the voltage applied to the N terminal is greater than that to the M terminal, a gate voltage uniformly distributed laterally is formed on the polysilicon transmission gate; the gate voltage causes the buried channel to form an increasing potential distribution from the far end of the output terminal to the output terminal when depleted.

[0007] Preferably, the manufacturing process is CMOS.

[0008] Preferably, the clamping region of the partially clamped photodiode includes a p-type epitaxial layer, a p-type clamping layer and an n-type well layer.

[0009] Preferably, the polysilicon transmission gate is disposed in a longitudinal center region of the partially clamped photodiode.

[0010] Preferably, the partially clamped photodiode forms a multi-level clamping potential distribution in the clamping region that is low on both sides and high in the center in the longitudinal direction by adjusting the doping process.

[0011] Preferably, n-type doping with different concentrations and different area differences is injected into the clamping region of the partial clamping photodiode to form a multi-level clamping potential distribution with low potentials on both sides and high potentials in the center.

[0012] Preferably, n-type and / or p-type implantation is performed in a clamping region of a portion of the clamped photodiode according to a lateral continuous trapezoidal pattern, forming a multi-level clamping potential distribution with low potentials on both sides and high potentials in the center.

[0013] Preferably, a p-type silicon surface barrier layer and an n-type buried channel are formed under the polysilicon transfer gate by an ion implantation process, and the silicon surface barrier layer is used to reduce dark current.

[0014] Preferably, it includes a non-clamped state mode and a clamped state mode, wherein: In the non-clamped mode, when the electronic shutter is open, a low voltage is applied to the M terminal and a high voltage is applied to the N terminal. The buried channel forms a clamping voltage difference that increases from the far end of the output terminal to the output terminal when depleted, which promotes the charge to drift along the polysilicon transmission gate to the output terminal. In the clamping mode, when the electronic shutter is opened, low voltages are applied to M and N at the same time to suppress dark current; when the electronic shutter is closed, a low voltage is applied to the M terminal and a high voltage is applied to the N terminal. A clamping voltage difference that increases from the far end of the output terminal to the output terminal is formed through the buried channel when depleted, which promotes the charge to drift along the polysilicon transfer gate to the output terminal.

[0015] Another aspect of the invention provides a sensor that adopts a linear array image sensor pixel structure.

[0016] Compared with the prior art, the invention can achieve the following beneficial effects: The pixel structure of the line scan image sensor of the present invention is suitable for CMOS technology, avoiding the disadvantages of high production cost, backward process node, high power consumption and the like of the traditional CCD process. The present invention realizes the rapid transfer of photogenerated charge in a large-size photodiode through the combined design of a high-resistance polysilicon transfer gate (RTG) and a partially clamped photodiode (PPPD), avoiding the design of the traditional transfer gate completely covering the photodiode, significantly reducing the area of ​​the polysilicon transfer gate, and avoiding the disadvantages caused by the large-area polysilicon transfer gate. In the case of large longitudinal and lateral dimensions of the pixel, it can still effectively accelerate the transmission of electrons, significantly reduce the readout time, avoid the tailing phenomenon, and also reduce the residence time of the charge in the photodiode, thereby improving the detection accuracy and stability. This design not only improves the detection speed of the image sensor, but also reduces the power consumption by optimizing the charge transfer path, meeting the design goal of high speed and low power consumption.

[0017] The present invention designs a p-type silicon surface barrier layer and an n-type buried channel below the polysilicon transmission gate, thereby effectively isolating the direct contact between the charges and the silicon surface and reducing the generation of dark current. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 It is a schematic diagram of an existing CCD photosensitive device in the background technology; Figure 2 is a top view of a pixel structure of a linear array image sensor provided according to an embodiment of the present invention; Figure 3 is a schematic diagram of a clamping region of a partially clamped photodiode formed by a doping process according to an embodiment of the present invention; Figure 4 is a schematic diagram of a multi-level clamping potential formed by a doping process according to an embodiment of the present invention; Figure 5 is a schematic diagram of a partially clamped photodiode clamping region formed by trapezoidal implantation according to an embodiment of the present invention; Figure 6 is a schematic diagram of a multi-level clamping potential formed by trapezoidal injection according to an embodiment of the present invention; Figure 7 is a schematic diagram showing the influence of different gate voltages on the clamping potential during buried channel depletion according to an embodiment of the present invention; Figure 8 is a schematic diagram of the potential distribution from the M terminal to the N terminal according to an embodiment of the present invention; Fig. 9 is a structural design diagram for suppressing dark current provided according to an embodiment of the present invention; Fig.10 is a timing diagram of a non-clamped mode provided according to an embodiment of the present invention; Fig.11 A timing diagram of a clamping mode is provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the invention clearer, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and do not constitute a limitation to the invention. Similar components in different embodiments use associated similar component numbers. In the following embodiments, many detailed descriptions are to enable the invention to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other components, materials, and methods. In some cases, some operations related to the invention are not shown or described in the specification, in order to avoid the core part of the invention being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to form various implementation methods. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary sequence, unless otherwise specified that a certain sequence must be followed.

[0021] In the description of the invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the invention, unless otherwise specified, the meaning of "multiple" is two or more.

[0022] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0023] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0024] See also Figure 2 In one embodiment of the present invention, a linear array image sensor pixel structure based on CMOS technology is provided to solve the problems of excessively large transfer gate size and slow transfer speed of photogenerated electrons in the diode in the existing pixel structure. The specific pixel structure includes: a partially clamped photodiode (PPPD), a high resistance polysilicon transfer gate (RTG) and a buried channel, wherein the high resistance polysilicon transfer gate is arranged in the longitudinal center area of ​​the upper surface of the partially clamped photodiode. Usually, the partially clamped photodiode areas on both sides of the high resistance polysilicon transfer gate are equal in size.

[0025] The partially clamped photodiode has large lateral and longitudinal dimensions. As a photosensitive element, it is responsible for converting the incident light signal into photogenerated charge. In order to increase the charge transfer rate, a specific layout design and process flow are used to enable the partially clamped photodiode to form a multi-level longitudinal gradient clamping voltage when it is exhausted. The clamping region of the partially clamped photodiode includes a p-type epitaxial layer, a p-type clamping layer, and an n-type well layer. By injecting n-type and / or p-type doping with different concentrations and different area differences into the clamping region multiple times, a stepped clamping voltage is formed inside the partially clamped photodiode at different positions due to different doping concentrations or areas, thereby realizing a stepped potential distribution. Specifically, a multi-level clamping potential distribution is formed with low sides on both sides and high center on both sides in the longitudinal direction, that is, the potential gradually increases from the two sides close to the polysilicon transmission gate in the longitudinal direction. This potential distribution enables the charge to move quickly along the potential gradient in the photodiode toward the transmission gate, promotes the rapid transfer of the charge from the upper and lower sides in the longitudinal direction to the corresponding buried channel below the polysilicon transmission gate, and accelerates the charge transfer efficiency.

[0026] In order to realize a multi-level clamping potential distribution with low potentials on both sides and high potentials in the center in the clamping region of a partially clamped photodiode, the embodiments of the present invention show the following process design methods: First, see Figure 3, shows a design of forming a multi-level clamping potential by adjusting the doping process. Specifically, part of the clamped photodiode is partitioned along the longitudinal direction (i.e., the up and down direction in the figure), and different concentrations of n-type doping are designed to be injected into the clamped area, so that the total concentration of n-type doping is symmetrically distributed in the longitudinal center area and low in the two side areas in the part of the clamped photodiode. This design will form a symmetrical step-shaped clamping voltage due to different doping concentrations at different positions, thereby achieving Figure 4 The stepped potential distribution is shown, where RTGH and RTGL represent the high voltage and low voltage applied across the polysilicon transfer gate, respectively.

[0027] For the second one, see Figure 5 , shows a design of forming a multi-level clamping potential by a trapezoidal injection process. Specifically, a plurality of continuous isosceles trapezoidal patterns are designed in the partial clamping photodiode region on both sides of the polysilicon transmission gate along the horizontal direction (i.e., the left and right directions in the figure), and n-type or / and p-type injection is performed in the partial clamping photodiode clamping region according to the horizontal continuous trapezoidal pattern to form a Figure 6 The multi-level slope clamping potential distribution shown is low on both sides and high in the center.

[0028] The above processes can all realize the partially clamped photodiode with multi-level clamping voltage required by the embodiments of the present invention, and are all compatible with CMOS processes, which can avoid the complex process steps of traditional CCDs, not only reducing production costs but also improving the scalability and yield of the process.

[0029] Compared with the traditional large-area polysilicon transfer gate covering the diode, the high-resistance polysilicon transfer gate of the present invention reduces the gate area and the power of the driving circuit by optimizing the structural design. In order to improve the rapid lateral transfer of charges in the buried channel under the high-resistance polysilicon transfer gate, the embodiment of the present invention applies different voltages to the two lateral ends (M and N) of the polysilicon transfer gate. Among them, the M end is far away from the output end (PU, Pick-up Terminal) of the partial clamped photodiode, and the N end is close to the output end of the partial clamped photodiode. In order to promote the transfer of charge to the output end, a low voltage RTGL is applied to the M end, and a high voltage RTGH is applied to the N end, RTGH>RTGL. Due to the voltage difference between the M end and the N end, at this time, the voltage difference between RTGH and RTGL will be evenly distributed on the high-resistance polysilicon transfer gate, and a gate voltage evenly distributed laterally will be formed on the polysilicon transfer gate. Please refer to Figure 7 Under different gate voltages, the clamping voltage of the buried channel under the high resistance polysilicon transmission gate during depletion will also change with the gate voltage. Therefore, a Figure 8The potential distribution increases from the far end of the output terminal to the output terminal (i.e., the direction from M to N). Under the action of this potential, a uniform electric field is formed, and the charges gathered in the buried channel by the longitudinal multi-level gradient clamping voltage will be further quickly transferred to the output terminal by drift. In terms of readout, the pixel structure of the linear array image sensor provided by the embodiment of the present invention is compatible with a capacitive feedback cross-group amplifier circuit or a source follower.

[0030] As a preferred embodiment, please refer to Fig. 9 In order to suppress the dark current, the implantation process of the buried channel under the high-resistance polysilicon transfer gate can also be adjusted. Specifically, ion implantation is performed on the p-type layer and the n-type layer under the high-resistance polysilicon transfer gate to form a p-type silicon surface barrier layer and an n-type buried channel. The p-type silicon surface barrier layer can isolate the charge in the buried channel from the silicon surface of the high-resistance polysilicon transfer gate, thereby reducing the dark current.

[0031] Depending on the application requirements and operating conditions, the voltages applied to the M and N terminals can be adjusted, so that the signal acquisition and readout methods of the pixel structure can be used in two ways: The first unclamped mode, see Fig.10 , when the electronic shutter (ES) is opened, the M and N terminals of the polysilicon transfer gate are connected to fixed potentials RTGL and RTGH, respectively, where RTGH>RTGL. Due to the resistance characteristics of the high-resistance polysilicon transfer gate, a uniform potential distribution from RTGL to RTGH is formed on the polysilicon transfer gate. This potential difference generates a corresponding clamping voltage difference in the buried channel below the polysilicon transfer gate. The clamping voltage difference in the buried channel forms an electric field, which promotes the charge gathered in the area near the polysilicon transfer gate to drift rapidly toward the output end in the lateral direction. This design significantly speeds up the transfer speed of the charge and reduces the readout time. The non-clamped state mode is suitable for applications with short exposure times. In this mode, the charge can be quickly transferred to the output end, thereby achieving high-speed readout. However, a potential problem with this mode is that if the potential on the polysilicon transfer gate is higher than the clamping voltage of the buried channel below it, it may lead to an increase in dark current. Therefore, the non-clamped mode is more suitable for short exposure applications that do not require high dark current. The clamped mode can be used in applications that require long exposure and low dark current.

[0032] For the second clamping mode, see Fig.11When the electronic shutter is opened, the M and N terminals of the polysilicon transmission gate are connected to the fixed potential RTGL and set to the low potential RTGL. At this time, the polysilicon transmission gate is completely in an inversion state, and a large number of holes will gather in the area close to the silicon surface, thereby effectively suppressing the generation of dark current during the exposure time. At the moment when the electronic shutter is closed, when the electronic shutter is opened in the non-clamped state mode, the M and N terminals of the polysilicon transmission gate are connected to the fixed potentials RTGL and RTGH respectively. At this time, as in the non-clamped state mode, a clamping voltage difference that increases from the far end of the output end to the output end is formed by the buried channel when depleted. Under the action of the clamping voltage difference, the electrons quickly drift to the output end, thereby achieving the goal of high-efficiency and high-quality readout.

[0033] The sensor prepared by using the above-mentioned linear array image sensor pixel structure can significantly improve the target detection accuracy of the sensor, while reducing the readout time and avoiding the tailing phenomenon.

[0034] In short, the above description is only a preferred embodiment of this specification and is not intended to limit the protection scope of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the protection scope of this specification.

[0035] The systems, devices, modules or units described in one or more of the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0036] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0037] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0038] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A linear array image sensor pixel structure, characterized in that: include: A partially clamped photodiode, a polysilicon transmission gate disposed on a surface of the partially clamped photodiode, and a buried channel disposed below the polysilicon transmission gate; wherein the partially clamped photodiode forms a multi-level gradient clamping voltage when depleted, for transferring charges longitudinally to the corresponding buried channel below the polysilicon transfer gate; The polysilicon transmission gate is laterally connected to an M end away from the output end of the partially clamped photodiode and an N end close to the output end of the partially clamped photodiode, and the N end and the M end are used to apply voltage; When the voltage applied to the N terminal is greater than that to the M terminal, a gate voltage uniformly distributed laterally is formed on the polysilicon transmission gate; the gate voltage causes the buried channel to form a potential distribution increasing from the far end of the output terminal to the output terminal when depleted.

2. The pixel structure of the linear array image sensor according to claim 1, characterized in that: The manufacturing process is CMOS.

3. The pixel structure of the linear array image sensor according to claim 1, characterized in that: The clamping region of the partially clamped photodiode includes a p-type epitaxial layer, a p-type clamping layer and an n-type well layer.

4. The pixel structure of the linear array image sensor according to claim 3, characterized in that: The polysilicon transfer gate is disposed in a longitudinal center region of the partially clamped photodiode.

5. The pixel structure of the linear array image sensor according to claim 4, characterized in that: The partially clamped photodiode forms a multi-level clamping potential distribution with low potentials on both sides and high potentials in the center in the longitudinal direction in the clamping region by adjusting the doping process.

6. The pixel structure of the linear array image sensor according to claim 4, characterized in that: N-type doping with different concentrations and different area differences is injected into the clamping region of the partially clamped photodiode to form a multi-level clamping potential distribution with low potentials on both sides and high potentials in the center.

7. The pixel structure of the linear array image sensor according to claim 6, characterized in that: According to a lateral continuous trapezoidal pattern, n-type or / and p-type implantation is performed in the clamping region of the partial clamping photodiode to form a multi-level clamping potential distribution with low potentials on both sides and high potentials in the center.

8. The linear array image sensor pixel structure according to claim 1 or 7, characterized in that: A p-type silicon surface barrier layer and an n-type buried channel are formed under the polysilicon transfer gate by an ion implantation process, and the silicon surface barrier layer is used to reduce dark current.

9. The linear array image sensor pixel structure according to claim 1 or 7, characterized in that: Includes non-clamped mode and clamped mode, where: In the non-clamped mode, when the electronic shutter is open, a low voltage is applied to the M terminal, and a high voltage is applied to the N terminal, so that a clamping voltage difference increasing from the far end of the output terminal to the output terminal is formed by the buried channel when depleted, so as to promote the charge to drift along the polysilicon transmission gate to the output terminal; In the clamping mode, when the electronic shutter is opened, low voltages are applied to the M and N terminals simultaneously to suppress dark current; when the electronic shutter is closed, a low voltage is applied to the M terminal and a high voltage is applied to the N terminal, and a clamping voltage difference that increases from the far end of the output terminal to the output terminal is formed by the buried channel when depleted, thereby promoting charge drift along the polysilicon transfer gate to the output terminal.

10. A sensor, characterized in that: A linear array image sensor pixel structure as described in any one of claims 1 to 9 is adopted.

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