Pixel device based on semi-floating gate, manufacturing method thereof and image sensor

Abstract

The invention provides a semi-floating gate-based pixel device, a manufacturing method thereof and an image sensor. The semi-floating gate-based pixel device comprises a deep trap and a transistor, the active region of the transistor is adjacent to the deep trap, the drain is located on the surface of the deep trap close to the active region, and the source is located on the surface of the active region; semi-floating gates are formed on the surfaces of the deep well, the drain electrode and the active region, and the surfaces of the drain electrode and the active region are isolated from the semi-floating gates through a first oxide layer; and a second oxide layer and a control gate are sequentially formed on the surface of the semi-floating gate. A deep trap is used as a photodiode, so that a carrier generates photocurrent when the deep trap is exposed to a light source, holes are collected by a semi-floating gate to cause potential change, and illumination information can be obtained according to a current difference. According to the pixel device, all operations of a single pixel can be achieved through a single transistor, the pixel photosensitive area is effectively improved, the manufacturing process of the pixel device is completely compatible with the standard CMOS technology, and the problem of how to manufacture a 1T pixel device with strong light response on the basis of an existing CMOS manufacturing process is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a pixel device based on a semi-floating gate and a manufacturing method thereof, and an image sensor. Background Art

[0002] With the widespread application of CMOS image sensors (CIS) in fields such as new energy vehicles and smartphones, the market demand has grown significantly. This trend has driven the demand for image sensors with higher integration, stronger photosensitivity, and higher dynamic range. The pixels of traditional image sensors usually include a photodiode and multiple transistors (such as 3T1P and 4T1P structures), which causes the pixel array in the image sensor to occupy a large chip area, limiting the high integration development of CIS.

[0003] In order to reduce the size of pixels in image sensors, reducing the number of transistors in the pixel is an effective method. Among them, the single-transistor active pixel sensor (1T-APS) as an innovative solution has demonstrated its compact design advantages, which can significantly reduce the pixel size and improve the fill factor. Related technologies include 1T charge modulation technology based on metal oxide semiconductor field effect transistor (MOSFET), 1T tunneling field effect transistor technology, 1T phototransistor technology using germanium grating, and 1T device technology based on silicon on insulator (SOI).

[0004] However, due to its special structure or the materials used, the existing 1T device technology is not compatible with the existing standard CMOS manufacturing process. Moreover, the light absorption layer in the existing 1T device is relatively shallow, resulting in insufficient device sensitivity and limiting the ability to respond to strong light. In addition, the existing 1T devices usually have high power consumption. Summary of the invention

[0005] The purpose of the present invention is to provide a pixel device based on a semi-floating gate and a manufacturing method thereof, and an image sensor to solve the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

[0006] In order to solve the above technical problems, the present invention provides a pixel device based on a semi-floating gate, comprising a deep well formed between two adjacent shallow trench isolations and a transistor; the transistor comprises an active area, a source and a drain, the active area is adjacent to the deep well, the drain is located on the top surface of the deep well close to the active area, and the source is located on the top surface of the active area and separated from the drain; a semi-floating gate is formed on the top surface of the deep well, the top surface of the drain and the top surface of the active area, and the top surface of the drain and the top surface of the active area are isolated from the semi-floating gate by a first oxide layer; a second oxide layer and a control gate are sequentially formed on the top surface of the semi-floating gate.

[0007] Optionally, in the semi-floating gate based pixel device, the deep well is an N-type doped deep N-well; the active area is P-type lightly doped; the source, the drain and the control gate are N-type heavily doped; and the semi-floating gate is P-type doped.

[0008] Optionally, in the pixel device based on the semi-floating gate, the doping ions of the deep N-well are phosphorus; the doping ions of the source, the drain and the control gate are arsenic, and the doping concentration of the source and the drain is 4.5×10 2 cm -3 The doping ion of the semi-floating gate is boron, and the doping concentration is 1×10 18 cm -3 .

[0009] Optionally, in the semi-floating gate based pixel device, the pitch of the pixel device is 3.1 μm; the depth of the deep well is 3-5 μm; the thickness of the first oxide layer is 5-10 nm; and the thickness of the second oxide layer is 10-15 nm.

[0010] Optionally, in the semi-floating gate-based pixel device, sidewalls of the semi-floating gate, sidewalls of the second oxide layer, and sidewalls of the control gate are formed with sidewall spacers.

[0011] Optionally, in the semi-floating gate-based pixel device, a pseudo drain is formed on the top surface of the deep well away from the drain; the surface of the pseudo drain is covered with a pseudo isolation layer; and the semi-floating gate covers the pseudo isolation layer.

[0012] In order to solve the above technical problems, the present invention further provides a method for manufacturing a pixel device based on a semi-floating gate, which is used to manufacture a pixel device based on a semi-floating gate as described in any one of the above items, and the manufacturing method comprises: forming shallow trench isolations on the basic device, wherein a basic active region is formed between two adjacent shallow trench isolations; A deep well is formed on the left side of the base active region and an active region is formed on the right side; forming a drain electrode on the surface of the deep well and a source electrode on the surface of the active region; forming a first oxide layer on the surface of the drain electrode and the surface of the active region; forming a semi-floating gate on the surface of the deep well and the surface of the first oxide layer; A second oxide layer and a control gate are sequentially formed on the surface of the semi-floating gate.

[0013] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, the method for forming a deep well on the left side of the basic active area and forming an active area on the right side includes: Performing ion implantation and annealing in sequence on the left side of the basic active region to form a deep well, wherein the ion implanted element is an N-type element; Ion implantation is performed on the right side of the basic active region to form an active region, wherein the ion implanted element is a P-type element.

[0014] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, the method for forming a drain on the surface of a deep well and a source on the surface of an active area includes: Depositing a pad oxide layer and a silicon nitride layer on the surface of the active region near the deep well to form a simulated gate; The self-alignment technology is used to define the drain on the surface of the deep well and the source on the surface of the active area to obtain N-type heavily doped drain and source.

[0015] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, the method for forming a first oxide layer on the surface of the drain and the surface of the active area, and the method for forming a semi-floating gate on the surface of the deep well and the surface of the first oxide layer include: Define the window position on the deep well surface; etching a portion of the deep well at the window location; Depositing a first oxide layer, wherein the first oxide layer covers the surface of the deep well, the surface of the drain, and the surface of the active area; etching the first oxide layer at the window position; Depositing a boron-doped polysilicon layer, wherein the boron-doped polysilicon layer covers the surface of the deep well and the surface of the first oxide layer; Chemical mechanical polishing is used to smooth the boron-doped polysilicon layer to obtain a semi-floating gate.

[0016] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, after forming a control gate, the method further includes: Using photolithography and anisotropic etching processes, a gate pattern is formed on the surface of the control gate; forming a sidewall spacer on a sidewall of the semi-floating gate, a sidewall of the second oxide layer, and a sidewall of the control gate; Passivation treatment is performed to obtain a pixel device.

[0017] In order to solve the above technical problems, the present invention further provides an image sensor, comprising a pixel device based on a half-floating gate as described in any one of the above items.

[0018] The pixel device based on semi-floating gate and its manufacturing method and image sensor provided by the present invention include a deep well formed between two adjacent shallow trench isolations and a transistor; the transistor includes an active area, a source and a drain, the active area is adjacent to the deep well, the drain is located on the top surface of the deep well close to the active area, and the source is located on the top surface of the active area and separated from the drain; the top surface of the deep well, the top surface of the drain and the top surface of the active area are formed with a semi-floating gate, and the top surface of the drain and the top surface of the active area are isolated from the semi-floating gate by a first oxide layer; the top surface of the semi-floating gate is sequentially formed with a second oxide layer and a control gate. The deep well is used as a photodiode, so that when the deep well is exposed to a light source, the carriers generate photocurrent, and the holes are collected by the semi-floating gate to cause the potential to change, and the light information can be obtained according to the current difference. This pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the pixel's photosensitivity area. The manufacturing process of this pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic structural diagram of a pixel device based on a half-floating gate provided in this embodiment; Figure 2 A circuit schematic diagram of a pixel device based on a half-floating gate provided in this embodiment; Figure 3 A flow chart of a method for manufacturing a pixel device based on a half-floating gate provided in this embodiment; 4 (A) to 4 (L) are schematic diagrams of device structures in various steps of the manufacturing method provided in this embodiment; The descriptions of the reference numerals are as follows: 100-basic device; 101-shallow trench isolation; 110-deep well; 121 active area; 122-source; 123-drain; 130-first oxide layer; 140-semi-floating gate; 150-second oxide layer; 160-control gate; 170-sidewall; 181-pseudo drain; 182-pseudo isolation layer; 190-analog gate. DETAILED DESCRIPTION

[0020] The following is a further detailed description of the semi-floating gate-based pixel device and its manufacturing method and image sensor proposed in the present invention in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0021] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] This embodiment provides a pixel device based on a half-floating gate, such as Figure 1 As shown, it includes a deep well 110 formed between two adjacent shallow trench isolations 101 and a transistor; the transistor includes an active area 121, a source 122 and a drain 123, the active area 121 is adjacent to the deep well 110, the drain 123 is located on the top surface of the deep well 110 close to the active area 121, and the source 122 is located on the top surface of the active area 121 and is separated from the drain 123; a semi-floating gate 140 is formed on the top surface of the deep well 110, the top surface of the drain 123 and the top surface of the active area 121, and the top surface of the drain 123 and the top surface of the active area 121 are isolated from the semi-floating gate 140 by a first oxide layer 130; a second oxide layer 150 and a control gate 160 are formed in sequence on the top surface of the semi-floating gate 140.

[0023] The pixel device based on the semi-floating gate provided in this embodiment uses the deep well 110 as a photodiode, so that when the deep well 110 is exposed to a light source, the carriers generate a photocurrent, and the holes are collected by the semi-floating gate 140 to cause a change in the potential, and the light information can be obtained according to the current difference. The pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the photosensitive area of ​​the pixel, and the manufacturing process of the pixel device is fully compatible with the standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

[0024] Specifically, in this embodiment, the deep well 110 is an N-type doped deep N-well; the active area 121 is P-type lightly doped; the source 122, the drain 123 and the control gate 160 are N-type heavily doped; and the semi-floating gate 140 is P-type doped.

[0025] In a specific embodiment, the doping ions of the deep well 110 (deep N well) are phosphorus P; the doping ions of the source 122, the drain 123 and the control gate 160 are arsenic As, and the doping concentration of the source 122 and the drain 123 is 4.5×10 2 cm -3 The doping ion of the semi-floating gate 140 is boron B, and the doping concentration is 1×10 18 cm -3 .

[0026] Of course, in practical applications, corresponding doping ions and doping concentrations may be selected according to actual process requirements, and this application does not impose any restrictions on this.

[0027] Furthermore, in this embodiment, to simplify the process, the first oxide layer 130 and the second oxide layer 150 may be made of the same material, such as silicon oxide. The semi-floating gate 140 may be made of boron-doped polysilicon, and the control gate 160 may be made of polysilicon.

[0028] Furthermore, in this embodiment, in order to ensure that the pixel device has good strong light response performance, the pitch of the pixel device is controlled to be 3.1 μm; the depth of the deep well 110 is 3-5 μm. Correspondingly, the thickness of the first oxide layer 130 is 5-10 nm; the thickness of the second oxide layer 150 is 10-15 nm.

[0029] In practical applications, the material and thickness of each hierarchical structure can be selected according to actual process requirements.

[0030] Furthermore, in this embodiment, if Figure 1 As shown, a sidewall spacer 170 is formed on the sidewall of the semi-floating gate 140 , the sidewall of the second oxide layer 150 , and the sidewall of the control gate 160 .

[0031] In practical applications, the material of the sidewall spacer 170 may be nitride, such as silicon nitride.

[0032] In addition, in order to facilitate the process implementation, such as Figure 1 As shown, in this embodiment, a pseudo drain 181 is formed on the top surface of the deep well 110 away from the drain 123 ; the surface of the pseudo drain 181 is covered with a pseudo isolation layer 182 ; and the semi-floating gate 140 covers the pseudo isolation layer 182 .

[0033] In actual use, the pseudo drain 181 can be formed simultaneously with the drain 123 and have the same doping ions and doping concentration as the drain 123 ; the pseudo isolation layer 182 can be formed simultaneously with the first oxide layer 130 and have the same material and thickness as the first oxide layer 130 .

[0034] The pixel device based on the half-floating gate provided in this embodiment has a circuit schematic diagram in practical application as shown in FIG. Figure 2 As shown, the photodiode PD is implemented by a deep well 110, and the control gate CG, the semi-floating gate SFG, the source Source and the drain Drain constitute a semi-floating gate field effect transistor SFG-MOSFET; the control gate CG is connected to the row select line Rowselect line of the pixel array in the image sensor, the semi-floating gate SFG is connected to the positive electrode of the photodiode PD, the drain D is connected to the negative electrode of the photodiode PD, and the source S is grounded.

[0035] The working principle of the pixel device based on the semi-floating gate provided in this embodiment is roughly as follows: the deep well on the left is used as a photodiode, and the photogenerated holes generated by it are collected by the SFG to modulate the gate voltage of the MOSFET, thereby converting the optical signal into a current signal for reading. At the same time, the MOSFET can select the working area as needed, and has high adjustability. In addition, since the MOSFET has an extremely low off-state current, the dark current performance of the device is significantly enhanced.

[0036] The semi-floating gate-based pixel device provided in this embodiment can realize the functions of existing conventional 3T or 4T pixels using a single transistor structure, thus having obvious advantages in integration. In addition, compared with the existing typical 4T1P pixel structure, the fill factor of the semi-floating gate-based pixel device provided in this embodiment has increased by more than 30%, effectively improving the strong light response capability of the pixel device. In addition, the existing pixel structure relies on the series connection of multiple transistors, resulting in high power consumption. In contrast, the semi-floating gate-based pixel device provided in this embodiment only generates source leakage current when reading signals, thereby greatly reducing power consumption. Through actual measurements, at the same resolution, the pixel array composed of the pixel device provided in this embodiment has a power consumption per column that is about 10 times lower than that of the traditional pixel array.

[0037] This embodiment also provides a method for manufacturing a pixel device based on a semi-floating gate, which is used to manufacture the pixel device based on a semi-floating gate as described above. Figure 3 As shown, the manufacturing method comprises: S1, forming shallow trench isolation on the basic device, wherein a basic active area is formed between two adjacent shallow trench isolations; S2, forming a deep well on the left side of the base active area and an active area on the right side; S3, forming a drain on the surface of the deep well and a source on the surface of the active area; S4, forming a first oxide layer on the surface of the drain electrode and the surface of the active region; S5, forming a semi-floating gate on the surface of the deep well and the surface of the first oxide layer; S6, forming a second oxide layer and a control gate in sequence on the surface of the semi-floating gate.

[0038] The manufacturing method of the pixel device based on the semi-floating gate provided in this embodiment uses a deep well as a photodiode, so that when the deep well is exposed to a light source, the carriers generate a photocurrent, and the holes are collected by the semi-floating gate to cause a change in the potential, and the light information can be obtained according to the current difference. The pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the photosensitive area of ​​the pixel, and the manufacturing process of the pixel device is fully compatible with the standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

[0039] Specifically, in this embodiment, in step S1, a shallow trench isolation is formed on a basic device, wherein a basic active region is formed between two adjacent shallow trench isolations.

[0040] In practical applications, the shallow trench isolation 101 can be formed on the basic device 100 using the existing shallow trench isolation formation process. For example, a channel can be formed on the basic device 100 by photolithography and other processes, and then ion implantation is performed on the channel to form a P-type doping region, and finally an oxide layer is deposited to obtain the shallow trench isolation 101. The specific implementation method is well known to those skilled in the art, and this application will not be repeated. In addition, the basic device 100 in this embodiment can be a substrate, or a device structure with a certain functional area, and this application does not limit this.

[0041] The device structure obtained in this step is shown in Figure 4 (A).

[0042] Furthermore, in this embodiment, step S2, the method of forming a deep well on the left side of the base active area and forming an active area on the right side includes: S21, as shown in FIG4(B), ion implantation and annealing are sequentially performed on the left side of the basic active region to form a deep well, wherein the ion implanted element is an N-type element.

[0043] In a specific embodiment, phosphorus is ion-implanted into the left side of the basic active region to obtain a deep well 110 with a depth of 3-5 μm, wherein the concentration of the ion implantation can be reasonably determined according to the required depth of the deep well 110. Afterwards, annealing is performed for about 10 minutes until the device structure is stable.

[0044] S22, as shown in FIG4(C), ion implantation is performed on the right side of the base active region to form an active region, wherein the ion implanted element is a P-type element.

[0045] In a specific embodiment, boron is ion-implanted into the right side of the basic active region to form a lightly doped active region 121. Afterwards, boron can be further doped into the right side of the basic active region to adjust the threshold voltage of the transistor.

[0046] Furthermore, in this embodiment, step S3, the method of forming a drain on the surface of the deep well and a source on the surface of the active area includes: S31 , as shown in FIG. 4(D) , a pad oxide layer and a silicon nitride layer are deposited on the surface of the active region 121 close to the deep well 110 to form a dummy gate 190 .

[0047] S32 , as shown in FIG. 4 (E), a drain 123 is defined on the surface of the deep well 110 and a source 122 is defined on the surface of the active region 121 by using a self-alignment technique, so as to obtain an N-type heavily doped drain 123 and source 122 .

[0048] After the source 122 and the drain 123 are formed, the dummy gate 190 is removed. At this time, the device structure is as shown in FIG. 4(F).

[0049] Furthermore, in this embodiment, step S4, the method of forming a first oxide layer on the drain surface and the active area surface includes: S41, defining a window position on the surface of the deep well 110. For example, the central area of ​​the deep well 110 is defined as the window position.

[0050] S42, as shown in FIG4 (G), a portion of the deep well 110 at the window position is etched. At this time, since the drain 123 is previously formed on the entire surface of the deep well 110, after the deep well 110 at the window position is etched, N-type heavily doped regions are formed on the surfaces of the deep well 110 on both sides of the window position, wherein the N-type heavily doped region on the right side (close to the active area 121) is the drain 123 of the transistor, and the N-type heavily doped region on the left side (far away from the active area 121) is the pseudo drain 181, and the pseudo drain 181 has no function.

[0051] In practical applications, a portion of the deep well 110 at the window position may be etched by about 60 nm, so that the thickness of the drain 123 is 60 nm.

[0052] S43 , as shown in FIG. 4 (H) , a first oxide layer 130 is deposited. The first oxide layer 130 covers the surface of the deep well 110 , the surface of the drain 123 , and the surface of the active region 121 .

[0053] In practical applications, the first oxide layer 130 may be silicon oxide, and the deposition may be performed by chemical vapor deposition, with a deposition thickness of 5 to 10 nm, for example, 8 nm. At this time, the deposited first oxide layer 130 not only covers the surface of the deep well 110, the surface of the drain 123, and the surface of the active area 121, but also covers the surface of the pseudo drain 181, the source 122, and the shallow trench isolation 101.

[0054] S44, as shown in FIG4 (I), the first oxide layer 130 at the etching window position is removed, and the first oxide layer 130 on the top surface of the source 122 and the shallow trench isolation 101 is also removed. The etching can be performed by wet etching or photolithography. At this time, the first oxide layer 130 only covers the surface of the drain 123, the surface of the active area 121 and the surface of the pseudo drain 181, wherein the surface covering the drain 123 and the surface of the active area 121 is called the first oxide layer 130, and the surface covering the pseudo drain 181 is called the pseudo isolation layer 182.

[0055] In practical applications, the first oxide layer 130 may also cover a portion of the surface of the source 122 , so that a portion of the subsequent semi-floating gate structure can be formed on the region of the source 122 covered by the first oxide layer 130 .

[0056] Further, in this embodiment, step S5, the method of forming a semi-floating gate on the surface of the deep well and the surface of the first oxide layer includes: S51 , as shown in FIG. 4 (J) , a boron-doped polysilicon layer is deposited. The boron-doped polysilicon layer covers the surface of the deep well 110 and the surface of the first oxide layer 130 .

[0057] In practical applications, when depositing the boron-doped polysilicon layer, the boron-doped polysilicon is controlled to cover only the surface of the deep well 110 , the surface of the first oxide layer 130 and the surface of the dummy isolation layer 182 , ensuring that there is no boron-doped polysilicon on the surface of the source 122 and the surface of the shallow trench isolation 101 .

[0058] Specifically, a mask may be used to define the area to be deposited, and the mask may be used to cover the surface of the source 122 and the surface of the shallow trench isolation 101, and then the mask and the boron-doped polysilicon thereon may be removed after the boron-doped polysilicon is deposited. Alternatively, a boron-doped polysilicon layer may be deposited to cover the entire device surface, and then the boron-doped polysilicon on the surface of the source 122 and the surface of the shallow trench isolation 101 may be removed by etching.

[0059] S52 , smoothing the boron-doped polysilicon layer by chemical mechanical polishing (CMP) and determining the height of the boron-doped polysilicon layer to obtain a semi-floating gate 140 .

[0060] Furthermore, in this embodiment, in step S6 , as shown in FIG. 4(K) , a second oxide layer 150 and a control gate 160 are sequentially formed on the surface of the semi-floating gate 140 .

[0061] Specifically, the second oxide layer 150 is deposited by chemical vapor deposition to cover the device surface, and then polysilicon is deposited on the surface of the second oxide layer 150 to form the control gate 160, wherein the deposition thickness of the second oxide layer 150 may be 10-15 nm, for example, 12 nm. Then, the second oxide layer 150 and the control gate 160 on the top surface of the semi-floating gate 140 are retained, and the second oxide layer 150 and the control gate 160 in other areas are etched away.

[0062] So far, the main structure of the pixel device has been completed. Afterwards, in order to ensure the stability of the device structure and the functional effectiveness, in this embodiment, the manufacturing method further includes: S7, using photolithography and anisotropic etching processes, a gate pattern is formed on the surface of the control gate 160. The gate pattern is used to lead out wires later and connect to the row selection line of the pixel array.

[0063] S8, as shown in FIG4 (L), a sidewall spacer 170 is formed on the sidewalls of the semi-floating gate 140, the sidewalls of the second oxide layer 150, and the sidewalls of the control gate 160. The sidewall spacer 170 can improve the stability of the structure between the semi-floating gate 140, the second oxide layer 150, and the control gate 160, and isolate them from other device structures.

[0064] In practical applications, the material of the sidewall 170 may be nitride, such as silicon nitride. The formation method of the sidewall is well known to those skilled in the art, and will not be described in detail in this application.

[0065] S9, passivation treatment to obtain a pixel device.

[0066] Through the passivation treatment, a protective film is formed on the surface of the device, thereby improving the reliability and stability of the pixel device. The material used for the passivation treatment can be silicon oxide or silicon nitride. Specifically, a silicon oxide layer or a silicon nitride layer can be formed on the surface of the device by chemical vapor deposition or physical vapor deposition. Among them, silicon oxide has good insulation and the ability to adsorb impurities; silicon nitride has high density, low water permeability and good adhesion, and can effectively protect the device. The specific process of the passivation treatment is well known to those skilled in the art, and this application will not go into details.

[0067] The manufacturing method of the pixel device based on the semi-floating gate provided in this embodiment can be implemented based on the 0.13μm technology CMOS standard process, so it is fully compatible with the existing CMOS process and reduces the manufacturing cost of the single transistor pixel device.

[0068] It should be noted that FIG. 4 (A) to FIG. 4 (L) only illustrate the relationship between the various hierarchical structures in a graphical manner, but in actual applications, affected by factors such as the process, the edges of the actual structures of each level may have inclinations, curvatures, etc., which can be understood by those skilled in the art.

[0069] Furthermore, this embodiment further provides an image sensor, comprising the half-floating gate based pixel device as described above.

[0070] In actual applications, a plurality of pixel devices are arranged in an array and connected via row selection lines to obtain a pixel array.

[0071] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0072] The pixel device based on semi-floating gate and its manufacturing method and image sensor provided in this embodiment include a deep well and a transistor formed between two adjacent shallow trench isolations; the transistor includes an active area, a source and a drain, the active area is adjacent to the deep well, the drain is located on the top surface of the deep well close to the active area, and the source is located on the top surface of the active area and separated from the drain; the top surface of the deep well, the top surface of the drain and the top surface of the active area are formed with a semi-floating gate, and the top surface of the drain and the top surface of the active area are isolated from the semi-floating gate by a first oxide layer; the top surface of the semi-floating gate is sequentially formed with a second oxide layer and a control gate. The deep well is used as a photodiode, so that when the deep well is exposed to a light source, the carriers generate photocurrent, and the holes are collected by the semi-floating gate to cause the potential to change, and the light information can be obtained according to the current difference. This pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the pixel's photosensitivity area. The manufacturing process of this pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

[0073] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A pixel device based on a semi-floating gate, characterized in that: The invention comprises a deep well formed between two adjacent shallow trench isolations and a transistor; the transistor comprises an active region, a source and a drain, the active region is adjacent to the deep well, the drain is located on the top surface of the deep well close to the active region, and the source is located on the top surface of the active region and is separated from the drain; A semi-floating gate is formed on the top surface of the deep well, the top surface of the drain and the top surface of the active area, and the top surface of the drain and the top surface of the active area are isolated from the semi-floating gate by a first oxide layer; A second oxide layer and a control gate are sequentially formed on the top surface of the semi-floating gate.

2. The pixel device based on a semi-floating gate according to claim 1, characterized in that: The deep well is an N-type doped deep N-well; the active area is P-type lightly doped; the source, the drain and the control gate are N-type heavily doped; and the semi-floating gate is P-type doped.

3. The pixel device based on a semi-floating gate according to claim 2, characterized in that: The doping ions of the deep N-well are phosphorus; the doping ions of the source, the drain and the control gate are arsenic, and the doping concentration of the source and the drain is 4.5×10 2 cm -3 The doping ion of the semi-floating gate is boron, and the doping concentration is 1×10 18 cm -3 .

4. The pixel device based on a semi-floating gate according to claim 1, characterized in that: The pitch of the pixel device is 3.1 μm; the depth of the deep well is 3-5 μm; the thickness of the first oxide layer is 5-10 nm; and the thickness of the second oxide layer is 10-15 nm.

5. The pixel device based on a semi-floating gate according to claim 1, characterized in that: Sidewall spacers are formed on the sidewalls of the semi-floating gate, the sidewalls of the second oxide layer and the sidewalls of the control gate.

6. The pixel device based on a semi-floating gate according to claim 1, characterized in that: A pseudo drain is formed on the top surface of the deep well away from the drain; the surface of the pseudo drain is covered with a pseudo isolation layer; and the semi-floating gate covers the pseudo isolation layer.

7. A method for manufacturing a pixel device based on a semi-floating gate, used to manufacture the pixel device based on a semi-floating gate as claimed in any one of claims 1 to 6, characterized in that: The manufacturing method comprises: forming shallow trench isolations on the basic device, wherein a basic active region is formed between two adjacent shallow trench isolations; A deep well is formed on the left side of the base active region and an active region is formed on the right side; forming a drain electrode on the surface of the deep well and a source electrode on the surface of the active region; forming a first oxide layer on the surface of the drain electrode and the surface of the active region; forming a semi-floating gate on the surface of the deep well and the surface of the first oxide layer; A second oxide layer and a control gate are sequentially formed on the surface of the semi-floating gate.

8. The method for manufacturing a pixel device based on a semi-floating gate according to claim 7, characterized in that: The method of forming a deep well on the left side of the base active region and forming an active region on the right side comprises: Performing ion implantation and annealing in sequence on the left side of the basic active region to form a deep well, wherein the ion implanted element is an N-type element; Ion implantation is performed on the right side of the basic active region to form an active region, wherein the ion implanted element is a P-type element.

9. The method for manufacturing a pixel device based on a semi-floating gate according to claim 7, characterized in that: The method of forming a drain on the surface of the deep well and a source on the surface of the active area comprises: Depositing a pad oxide layer and a silicon nitride layer on the surface of the active region near the deep well to form a simulated gate; The self-alignment technology is used to define the drain on the surface of the deep well and the source on the surface of the active area to obtain N-type heavily doped drain and source.

10. The method for manufacturing a pixel device based on a semi-floating gate according to claim 7, characterized in that: The method of forming a first oxide layer on the surface of the drain and the surface of the active area, and forming a semi-floating gate on the surface of the deep well and the surface of the first oxide layer comprises: Define the window position on the deep well surface; etching a portion of the deep well at the window location; Depositing a first oxide layer, wherein the first oxide layer covers the surface of the deep well, the surface of the drain, and the surface of the active area; etching the first oxide layer at the window position; Depositing a boron-doped polysilicon layer, wherein the boron-doped polysilicon layer covers the surface of the deep well and the surface of the first oxide layer; Chemical mechanical polishing is used to smooth the boron-doped polysilicon layer to obtain a semi-floating gate.

11. The method for manufacturing a pixel device based on a semi-floating gate according to claim 7, characterized in that: After forming the control gate, the manufacturing method further comprises: Using photolithography and anisotropic etching processes, a gate pattern is formed on the surface of the control gate; forming a sidewall spacer on a sidewall of the semi-floating gate, a sidewall of the second oxide layer, and a sidewall of the control gate; Passivation treatment is performed to obtain a pixel device.

12. An image sensor, characterized in that: It comprises a half-floating gate based pixel device as described in any one of claims 1 to 6.

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