Photovoltaic module, solar cell and preparation method thereof

Abstract

The invention discloses a solar cell, a preparation method of the solar cell and a photovoltaic module, relates to the technical field of solar cells, and aims to solve the problem that the contact performance of an electrode and a silicon substrate in the solar cell is poor. The solar cell comprises a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface which are opposite; a first passivation layer and a first electrode are sequentially stacked on the first surface, and the first electrode penetrates through the first passivation layer and is electrically connected with the first surface; the area, covering the first surface, of the first electrode is a contact area, a first metal element is arranged in the contact area, and the contact area comprises a first contact area and a second contact area; the first metal element content of the first contact region is greater than the first metal element content of the second contact region.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a photovoltaic module, a solar cell and a method for preparing the same. Background Art

[0002] Currently, a screen printing process is generally used to coat a conductive paste on the surface of the passivation layer, and then a sintering process is performed to allow the conductive paste to penetrate the passivation layer and form an ohmic contact with the emitter to form an electrode.

[0003] The ability of electrodes to collect photogenerated carriers is crucial to the photoelectric conversion efficiency of solar cells. In the prior art, selective emitters are often formed by heavily doping the surface of the silicon substrate in the electrode area to reduce the contact resistance of the interface between the electrode and the silicon substrate. However, the high temperature process of forming the selective emitter will have a negative impact on the silicon substrate, thereby reducing the efficiency of the cell. Summary of the invention

[0004] In response to the problems existing in the prior art, the present application provides a solar cell and a preparation method, aiming to simplify the cell structure and process flow while meeting the current transmission requirements, improving the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the extraction efficiency of the photogenerated current.

[0005] Specifically, this application involves the following aspects:

[0006] A first aspect provides a solar cell, the solar cell comprising a silicon substrate, the silicon substrate having a first surface and a second surface opposite to each other;

[0007] A first passivation layer and a first electrode are sequentially stacked on the first surface, and the first electrode penetrates the first passivation layer and is electrically connected to the first surface;

[0008] The area where the first electrode covers the first surface is a contact area, the contact area has a first metal element, and the contact area includes a first contact area and a second contact area;

[0009] A content of the first metal element in the first contact region is greater than a content of the first metal element in the second contact region.

[0010] Furthermore, in the first contact region, the mass ratio of the first metal element at any position to all elements at that position is w 1-1 ,

[0011] In the second contact region, the mass ratio of the first metal element at any position to all elements at that position is w 2-1 ,in

[0012] w 1-1 -w 2-120-60wt%.

[0013] Furthermore, the contact area has a second metal element, the content of the second metal element in the first contact area is greater than the content of the second metal element in the second contact area, and in the first contact area, the mass proportion of the second metal element at any position of all elements at that position is w 1-2 ,

[0014] In the second contact region, the mass proportion of the second metal element at any position to all elements at that position is w 2-2 ,in

[0015] |w 1-2 -w 2-2 |≤10wt%.

[0016] Furthermore, the first contact region has conductive particles therein, and the conductive particles contain a first metal element.

[0017] Furthermore, the particle size of the conductive particles ranges from 20 to 100 nm.

[0018] Furthermore, in the silicon substrate, a first diffusion region is formed in a direction extending from the first surface of the first contact region to the inside of the silicon substrate, and the first diffusion region contains a first metal element;

[0019] In the first diffusion region, a content of the first metal element at an end away from the first surface is less than a content at an end close to the first surface; and / or

[0020] In the silicon substrate, a second diffusion region is formed in a direction extending from the first surface of the second contact region to the inside of the silicon substrate, and the second diffusion region contains a first metal element.

[0021] In the second diffusion region, a content of the first metal element at an end away from the first surface is smaller than a content of the first metal element at an end close to the first surface.

[0022] Furthermore, the thickness of the first diffusion region and the second diffusion region are both 150-400 nm.

[0023] Furthermore, the first passivation layer is in direct contact with the first surface.

[0024] Furthermore, a tunneling oxide layer, a doped polysilicon layer, a second passivation layer and a second electrode are sequentially stacked on the second surface, and the second electrode penetrates the second passivation layer and is electrically connected to the doped polysilicon layer;

[0025] The doping type of the doped polysilicon layer is opposite to that of the silicon substrate.

[0026] In a second aspect, an embodiment of the present application further provides a method for preparing a solar cell, the method comprising: a method for preparing a solar cell, wherein the method comprises the following steps:

[0027] Providing a silicon substrate having a first surface and a second surface opposite to each other;

[0028] forming a first passivation layer on a first surface of the silicon substrate;

[0029] forming a first electrode precursor on a surface of the first passivation layer facing away from the silicon substrate, wherein the first electrode precursor penetrates the first passivation layer and is electrically connected to the silicon substrate;

[0030] The first electrode precursor is processed by an induced sintering process to obtain a first electrode;

[0031] The area where the first electrode covers the silicon substrate is a contact area, the contact area has a first metal element, and the contact area includes a first contact area and a second contact area;

[0032] A content of the first metal element in the first contact region is greater than a content of the first metal element in the second contact region.

[0033] Furthermore, in the induced sintering process, a laser is used to scan a surface on one side where the first electrode precursor is located or a surface on a side away from the first electrode precursor, and a reverse bias is applied at the same time, thereby forming the first electrode;

[0034] The energy of the laser is 200W / cm 2 -5000 W / cm 2 , the reverse bias is 5-20V.

[0035] In a third aspect, an embodiment of the present application provides a photovoltaic module, which includes the aforementioned solar cell or the solar cell prepared by the aforementioned method.

[0036] Due to the differentiated distribution of the content of the first metal element in the first contact area and the second contact area of ​​the solar cell of the present application, the first contact area can provide more channels for the carriers that are quickly transferred to the first surface, so that they are transferred to the first electrode, so as to ensure a higher fill factor, thereby ensuring a higher cell efficiency. The second contact area can reduce the parasitic absorption generated by the first metal element, and the differentiated setting can reduce the damage to the passivation performance of the first passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to better understand the present application and do not constitute an improper limitation on the present application.

[0038] Figure 1This is a schematic diagram of the structure of the solar cell provided in this application.

[0039] Figure 2 A schematic diagram of a contact area provided in the present application in a specific embodiment.

[0040] Figure 3 This is a scanning electron microscope energy spectrum (EDS) surface scan of the contact area provided in this application.

[0041] Figure 4 This is the SEM measured image of the contact area provided in this application.

[0042] Description of Reference Numerals

[0043] 1-solar cell, 10-silicon substrate, 11-first passivation layer, 12-first electrode, 13-second electrode, 14-second passivation layer, 15-doped polysilicon layer, 16-tunneling oxide layer, 17-contact region, 171-first contact region, 172-second contact region, 18-conductive particles. DETAILED DESCRIPTION

[0044] The following is a description of the exemplary embodiments of the present application, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0045] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present application are described at the angles shown in the accompanying drawings and should not be understood as limiting the embodiments of the present application. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is connected to another element "upper" or "lower", it can not only be directly connected to another element "upper" or "lower", but also indirectly connected to another element "upper" or "lower" through an intermediate element.

[0046] In the prior art, selective emitters are often formed by heavily doping the electrode region to reduce the contact resistance of the interface between the electrode and the silicon substrate. However, the high temperature process of forming the selective emitter will have a negative impact on the silicon substrate, thereby reducing the efficiency of the battery.

[0047] In order to simplify the cell structure of a solar cell and balance the issues of simplifying the process and optimizing the cell performance, the present application provides a solar cell to solve the above technical problems.

[0048] like Figure 1It is a schematic diagram of a solar cell 1 , which includes a silicon substrate 10 , a first passivation layer 11 , a first electrode 12 , a second electrode 13 , a second passivation layer 14 , a doped polysilicon layer 15 , and a tunneling oxide layer 16 .

[0049] The silicon substrate 10 has a first surface and a second surface. The silicon substrate 10 may include P-type monocrystalline silicon doped with a P-type doping element (e.g., boron or gallium) or N-type monocrystalline silicon doped with a P-type doping element (e.g., phosphorus). The type of the silicon substrate 10 is not specifically limited in this embodiment.

[0050] The tunneling oxide layer 16 is stacked on the second surface, the doped polysilicon layer 15 is stacked on the side of the tunneling oxide layer 16 away from the first surface, the second passivation layer 14 is stacked on the side of the doped polysilicon layer 15 away from the first surface, and the second electrode 13 is stacked on the side of the second passivation layer 14 away from the tunneling oxide layer 16 and is electrically connected to the doped polysilicon layer 15. The doping type of the doped polysilicon layer 15 is opposite to that of the silicon substrate 10.

[0051] The first passivation layer 11 is stacked on the first surface, and the main material of the first passivation layer 11 is one or more of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and aluminum oxynitride. The thickness of the first passivation layer 11 is 50nm to 150nm.

[0052] The first electrode 12 is located on a side of the first passivation layer 11 away from the silicon substrate 10, penetrates the first passivation layer 11 and is electrically connected to the silicon substrate 10, and the electrode main body gate line width is 10μm to 80μm. The material of the first electrode 12 is silver or an alloy of silver and metals such as gold, aluminum, copper, and nickel.

[0053] like Figure 2 The solar cell is shown as a partial structural diagram, including a silicon substrate 10, a first passivation layer 11 and a first electrode 12. The area of ​​the first surface covered by the first electrode 12 is a contact area 17. Figure 3 The scanning electron microscope energy spectrum (EDS) surface scan of the contact area 17 is shown in FIG. Figure 2 and Figure 3 The contact area 17 includes a plurality of first contact areas 171 and a second contact area 172. A person skilled in the art can understand that the higher the brightness of an element in the EDS surface scan image, the higher its content. That is, the content of the first metal element in the first contact area 171 is greater than the content of the first metal element in the second contact area 172.

[0054] In one embodiment, due to the differential distribution of the content of the first metal element in the first contact region 171 and the second contact region 172, the first contact region 171 with a larger content of the first metal element is provided in the contact region 17, which can provide more channels for the carriers that are quickly transferred to the first surface, so that they are transferred to the first electrode 12, so as to ensure a higher fill factor, thereby ensuring a higher battery efficiency. The second contact region 172 with a low content of the first metal element can reduce the parasitic absorption generated by the first metal element, and the differential distribution can reduce the damage to the passivation performance of the first passivation layer 11.

[0055] In one embodiment, in the first contact region 171, the mass percentage of the first metal element at any position to all elements at that position is w. 1-1 In the second contact region 172, the mass percentage of the first metal element at any position to all elements at that position is w 2-1 , w 1-1 -w 2-1 is 20-60wt%, in one embodiment, w 1-1 -w 2-1 is 20-50wt%, in one embodiment, w 1-1 -w 2-1 is 25-50wt%. Specifically, w 1-1 -w 2-1 It can be any value between 20wt%, 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt%, 55wt% and 60wt%.

[0056] In this paper, the first metal element content of the first contact region 171, the first metal element content of the second contact region 172, and 1-1 and w 2-1 All of them can be obtained through EDS scanning. For example, in the area where the first electrode is located, on a plane perpendicular to the direction from the first electrode to the silicon substrate, the electron beam is scanned point by point along a line passing through the first contact area 171 and the second contact area 172, and a distribution curve of the change in the content of the first metal element on this line can be obtained.

[0057] The difference in mass fraction of the first metal element between the first contact area 171 and the second contact area 172 cannot be too large, otherwise voids will be formed on the surface of the battery and the silicon substrate 10. The presence of the voids will reduce the contact area between the electrode and the first surface of the silicon substrate 10, weakening the ability of the first electrode 12 to collect current. At the same time, the presence of the voids will increase the surface defects of the first electrode 12 and increase the carrier interface recombination rate.

[0058] In the present application, the first contact region 171 and the second contact region 172 may be divided according to the content of the first metal element.

[0059] In one embodiment, in the first electrode 12, the cross section of the electrode grid line is trapezoidal or quasi-trapezoidal, and the cross section is a cross section perpendicular to the extension direction of the electrode grid line. The surface where the upper base of the trapezoid is located corresponds to the first contact area 171 in the orthographic projection area of ​​the first surface, and the areas on both sides of the first contact area 171 correspond to the second contact area 172.

[0060] In one embodiment, when the first electrode 12 is prepared from silver paste, the first metal element is silver. When the first electrode 12 is prepared from a paste mixed with silver and gold, aluminum, copper, nickel or other metals, the first metal element is the element with the highest metal content in the first electrode 12.

[0061] In one embodiment, the contact region 17 has a second metal element, the second metal element content of the first contact region 171 is greater than the second metal element content of the second contact region 172, and in the first contact region 171, the mass percentage of the second metal element at any position in all elements at that position is w 1-2 In the second contact region 172, the mass percentage of the second metal element at any position to all elements at that position is w 2-2 ,|w 1-2 -w 2-2 |≤10wt%. In one embodiment, |w 1-2 -w 2-2 |≤8wt%, in one embodiment, |w 1-2 -w 2-2 |≤5wt%. Specifically, |w 1-2 -w 2-2 |It can be 10wt%, 9wt%, 8wt%, 7wt%, 6wt%, 5wt%, 4wt%, 3wt%, 2wt% and the like.

[0062] In one embodiment, w 1-2 -w 2-2 ≤10wt%.

[0063] In one embodiment, w 2-2 -w 1-2 ≤10wt%.

[0064] Herein, the second metal element content of the first contact region 171, the second metal element content of the second contact region 172, and the 1-2 and w 2-2 The test method can refer to the above w 1-1 and w 2-1 Testing method.

[0065] In this embodiment, the second metal element may be aluminum. The content of the second metal element in the contact area 17 is less than that of the first metal element, so the second metal element is approximately evenly distributed in the contact area 17, which is conducive to reducing the gaps in the distribution of the second metal element and is more conducive to improving the contact performance between the electrode and the surface of the silicon substrate 10.

[0066] In one embodiment, when the first electrode 12 is prepared from silver paste, the first metal element is silver, and the second metal element is Al or nickel, etc. When the first electrode 12 is prepared from a paste mixed with silver and gold, aluminum, copper, nickel, etc., the first metal element is the element with the highest content of the metal element in the first electrode 12, and the second metal element is the element with the second highest content.

[0067] like Figure 4 The SEM image of the contact area 17 is shown in FIG. Figure 2 and Figure 4 , there are a plurality of conductive particles 18 in the first contact region 171. Figure 4 As shown, the first surface has a pyramid-shaped texture structure, which is only shown as an example and does not serve as a special limitation. That is, the first surface can be a polished surface or can have a pyramid-shaped texture structure, for example.

[0068] The metal element in the conductive particles 18 is the same as the first metal element in the first electrode 12. The conductive particles 18 are microcrystals formed by the first metal element in the first electrode 12 and silicon. When the first metal in the first electrode 12 is Ag, the conductive particles 18 are Ag-Si microcrystals.

[0069] The first metal element in the first contact region 171 is composed of the metal element in the conductive particles 18 and other compounds containing the first metal element.

[0070] After the first electrode is sintered, the first metal element (Ag) in the first electrode will diffuse toward the silicon substrate under the first electrode, and other compounds containing the first metal element will be formed during the diffusion process (the specific composition of the other compounds containing the first metal element is not further limited, and the first metal element in any form of other compounds containing the first metal element can be obtained through the aforementioned EDS test). At the same time, during the high-temperature sintering process, the first passivation layer under the first electrode is partially etched by the corrosive components in the first electrode, and part of the silicon on the first surface of the silicon substrate melts. During the cooling process, the molten silicon recrystallizes and forms conductive particles, namely, Ag-Si microcrystals, with the first metal element in the first electrode. Therefore, the first metal element in the first contact area is formed during the process of the first electrode contacting the silicon substrate through sintering, including the first metal element formed by diffusion and the first metal element in the conductive particles.

[0071] In one embodiment, the first contact region 171 and the second contact region 172 both have other compounds containing the first metal element.

[0072] As can be seen from the foregoing, the first contact area 171 and the second contact area 172 in the present application are divided according to the content of the first metal element. In some embodiments, the first contact area 171 has conductive particles, and the second contact area 172 has no conductive particles. Alternatively, the number of conductive particles in the first contact area 171 is greater than the number of conductive particles in the second contact area 172.

[0073] Since the first electrode 12 is burned through the first passivation layer 11 during the preparation process and is electrically connected to the first surface of the silicon substrate 10, in one embodiment, the first electrode 12 does not completely burn the first passivation layer 11 thereunder, and only a partial area is burned through, so a partial area of ​​the first electrode 12 is in contact with the first surface of the silicon substrate 10, and a partial area of ​​the first electrode 12 is stacked with the first passivation layer 11, so that the conductive particles 18 are located at the contact interface between the first passivation layer 11 and the first electrode 12 in the first contact area 171, or at the junction of the first passivation layer 11 and the first surface of the silicon substrate 10 in the first contact area 171, or at the junction of the first electrode 12 and the first surface of the silicon substrate 10 in the first contact area 171. In another embodiment, the first electrode 12 completely burns the first passivation layer 11 thereunder, so that the first electrode 12 is in contact with the first surface of the silicon substrate 10, and the conductive particles 18 are located at the junction of the first electrode 12 and the first surface of the silicon substrate 10 in the first contact area 171.

[0074] In this embodiment, the conductive particles 18 can serve as a transmission channel for carriers, thereby enhancing the transmission of carriers in the silicon substrate 10 to the first electrode 12 .

[0075] The particle size distribution range of the conductive particles 18 is 20-100 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc. The conductive particles 18 of different particle sizes can provide multiple transmission channels for carriers, thereby improving the transmission efficiency of carriers.

[0076] Herein, the particle size distribution of the conductive particles 18 may be obtained by a SEM scanning electron microscope.

[0077] The conductive particles 18 appearing in the first contact region 171 are not connected to each other, and the spacing between the conductive particles 18 is less than or equal to 15 nm. For example, the spacing between the adjacent conductive particles 18 may be 3 nm, 6 nm, 9 nm, 12 nm, 15 nm, etc.

[0078] In one embodiment, the distance between adjacent conductive particles 18 is less than or equal to 15 nm, so that the conditions of quantum tunneling effect can be met between adjacent conductive particles 18, so that an electron transmission path is formed between adjacent conductive particles 18 to achieve electron transmission, further ensuring the transmission efficiency of carriers and improving the filling factor.

[0079] like Figure 3 As shown, in the silicon substrate 10, a diffusion region is formed in a direction extending from the first surface of the first contact region 171 and the second contact region 172 to the inside of the silicon substrate 10, and the diffusion region contains the first metal element. That is, the first diffusion region is formed in a direction extending from the first surface of the first contact region 171 to the inside of the silicon substrate 10, and the second diffusion region is formed in a direction extending from the first surface of the second contact region 172 to the inside of the silicon substrate 10, and the first diffusion region and the second diffusion region both contain the first metal element.

[0080] In the first diffusion region, the content of the first metal element at the end away from the first surface is less than that at the end close to the first surface. In the second diffusion region, the content of the first metal element at the end away from the first surface is less than that at the end close to the first surface.

[0081] In one embodiment, in the first diffusion region, the concentration of the first metal element gradually decreases from the first surface to the inside of the silicon substrate 10. In the second diffusion region, the concentration of the first metal element gradually decreases from the first surface to the inside of the silicon substrate 10.

[0082] In one embodiment, the content of the first metal element in the first contact region 171 is greater than that in the first diffusion region. The content of the first metal element in the second contact region 172 is greater than that in the second diffusion region.

[0083] By setting a diffusion region where the first metal element is distributed, a better ohmic contact can be further formed to improve the battery efficiency. However, the content of the first metal element in the corresponding diffusion region should be less than its content in the corresponding contact region, in order to reduce the recombination caused by the diffusion of the metal in the silicon substrate 10.

[0084] In this article, the test method of the content and concentration of the first metal element in the first diffusion region and the second diffusion region can refer to the above-mentioned w 1-1 and w 2-1 Testing method.

[0085] Furthermore, the thickness of the first diffusion region is 150-400 nm. The thickness of the second diffusion region is 150-400 nm.

[0086] Exemplarily, the thickness of the first diffusion region and the second diffusion region can be 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, 310nm, 320nm, 330nm, 340nm, 350nm, 360nm, 370nm, 380nm, 390nm, 400nm, etc.

[0087] In one embodiment, the first passivation layer 11 is in direct contact with the first surface of the silicon substrate 10 .

[0088] Compared with conventional solar cells, the first surface of the silicon substrate 10 of the solar cell of this embodiment is directly in contact with the first electrode 12, eliminating the doped polysilicon layer 15 on the light-facing side of the silicon substrate 10, which not only reduces the Auger recombination effect of the cell, but also simplifies the process flow and reduces costs. At the same time, the conductive particles 18 in the contact area 17 facilitate the movement of carriers to the first electrode 12, speeding up the transmission rate of carriers, thereby shortening the time required for carriers to pass through the first passivation layer 11. The problem of reduced contact performance due to the elimination of the front surface field is solved.

[0089] In one embodiment, the solar cell is a topcon cell, which includes a first electrode 12, a first passivation layer 11, a silicon substrate 10, a tunneling oxide layer 16, a doped polysilicon layer 15, a second passivation layer 14 and a second electrode 13 stacked in sequence from its light-facing side to its backlight side. The first electrode 12 penetrates the first passivation layer 11 and is electrically connected to the silicon substrate 10, and the second electrode 13 penetrates the second passivation layer 14 and is electrically connected to the doped polysilicon layer 15.

[0090] The first passivation layer 11 includes a stacked structure of one or more of aluminum oxide and silicon nitride materials. The material of the tunneling oxide layer 16 includes silicon oxide, aluminum oxide, molybdenum oxide, etc., including but not limited to these.

[0091] The doped polysilicon layer 15 may be one of an n-type doped polysilicon layer, an n-type doped amorphous silicon layer, an n-type doped microcrystalline silicon layer, an n-type doped silicon carbide layer, and the like.

[0092] The second surface of the silicon substrate 10 can be a smooth surface or a rough surface.

[0093] In one embodiment, the solar cell is a back contact cell, which includes a silicon substrate, a front passivation layer and an anti-reflection layer are sequentially stacked on the light-facing surface of the silicon substrate, and a first region and a second region are alternately arranged on the backlight surface of the silicon substrate. In the first region, a doped region is formed by extending a certain thickness from the backlight surface of the silicon substrate to the inside of the silicon substrate, and a first passivation layer and a first electrode are sequentially stacked on the surface of the doped region away from the silicon substrate. The first electrode penetrates the first passivation layer and is electrically connected to the doped region. In the second region, a tunneling oxide layer, a doped polysilicon layer, a second passivation layer 14 and a second electrode 13 are sequentially stacked on the backlight surface of the silicon substrate. The first region and the second region have a gap structure for isolating the first region from the second region. The doping type of the doped polysilicon layer is opposite to that of the silicon substrate, and the doping type of the doped region is the same as that of the silicon substrate.

[0094] The present application also provides a method for preparing the aforementioned solar cell, comprising the following steps:

[0095] Step 1: providing a silicon substrate 10, wherein the silicon substrate 10 has a first surface and a second surface opposite to each other;

[0096] Step 2: forming a first passivation layer 11 on the first surface of the silicon substrate 10;

[0097] Step 3: forming a first electrode precursor on a surface of the first passivation layer 11 facing away from the silicon substrate 10, wherein the first electrode precursor penetrates the first passivation layer 11 and is electrically connected to the silicon substrate 10;

[0098] Step 4: The first electrode precursor is treated by an induced sintering process to obtain the first electrode 12 .

[0099] Step 1 includes the following detailed steps:

[0100] Step 1.1: Texturing is performed on the first surface and the second surface of the silicon substrate 10 to form a first texture structure. The silicon substrate 10 is a p-type silicon substrate.

[0101] Step 1.2: forming an oxide layer on the first texture structure on the first surface of the silicon substrate 10. The oxide layer may be SiO x The thickness of the layer can be 50-150 nm.

[0102] Step 1.3: Polishing the second surface of the silicon substrate 10 to remove the first texture structure on the second surface.

[0103] Step 1.4: forming a tunneling oxide layer 16 and a doped polysilicon layer 15 in sequence on the second surface of the silicon substrate 10 .

[0104] The preparation steps of the tunnel oxide layer 16 and the doped polysilicon layer 15 are conventional preparation steps. For example, the tunnel oxide layer 16 is prepared by LPCVD, and the doped polysilicon layer 15 is prepared by LPCVD.

[0105] Step 1.5: removing the oxide layer on the first surface of the silicon substrate 10 to expose the silicon substrate 10;

[0106] In step 2, while forming the first passivation layer 11 on the first surface of the silicon substrate 10, the second passivation layer 14 is formed on the surface of the doped polysilicon layer 15 facing away from the silicon substrate 10. The preparation step of the second passivation layer 14 is a conventional preparation step, for example, it can be prepared by ALD+PECVD method.

[0107] In step three, the first electrode precursor and the second electrode 13 are obtained by screen printing electrode slurry and sintering annealing.

[0108] In step 4, in the induced sintering process, a laser is used to scan the side surface where the first electrode precursor is located or the side surface away from the first electrode precursor, and a reverse bias is applied at the same time, thereby obtaining the first electrode 12. The first electrode 12 includes a plurality of electrode grid lines, and the induced sintering process is a LECO process. The laser in the LECO process is used to continuously scan the side surface where the first electrode precursor is located for multiple times, or continuously scan the side surface away from the first electrode precursor for multiple times, or first scan the side surface where the first electrode precursor is located and then scan the side surface away from the first electrode precursor, or first scan the side surface away from the first electrode precursor and then scan the side surface where the first electrode precursor is located, which is specifically determined according to actual operating conditions.

[0109] As an achievable method, laser irradiation is used to irradiate at least one side of a solar cell, including:

[0110] The laser is scanned along the direction in which the thin grid lines of the first electrode precursor extend.

[0111] The laser scans along the extending direction of the fine grid lines perpendicular to the first electrode precursor, which is beneficial to ensure that the laser traverses and scans each fine grid line, thereby ensuring the quality of laser induced sintering.

[0112] The laser in the LECO process is green light or infrared light, the reverse bias voltage is 5V-20V, preferably between 15V-17V, the scanning mode is front scanning or back scanning, and the scanning speed is 0.1m / s to 80m / s.

[0113] The reverse bias voltage ranges from 5V to 20V, and the laser energy is 200w / cm 2 -5000w / cm 2The reverse bias voltage and laser energy are conducive to reliable laser induced sintering without causing damage to other parts of the body.

[0114] Specifically, the reverse bias voltage may be, but is not limited to, 5V, 7V, 9V, 10V, 12V, 14V, 15V, 17V, 18V or 20V, etc.; the energy of the laser may be, but is not limited to, 200w / cm 2 、300w / cm 2 , 400w / cm 2 , 500w / cm 2 、600w / cm 2 , 700w / cm 2 、800w / cm 2 , 900w / cm 2 , 1000w / cm 2 、1500w / cm 2 , 2000w / cm 2 , 2500w / cm 2 、3000w / cm 2 、3500w / cm 2 , 4000w / cm 2 , 4500w / cm 2 , 5000w / cm 2 Etc., without making any specific limitation on this.

[0115] The energy of the laser is defined as the energy density of the laser irradiated on the grid line, which is obtained by dividing the laser power by the area of ​​the light spot irradiated on the grid line.

[0116] LECO treatment improves the contact performance between the P-type silicon wafer substrate and the metal gate line.

[0117] Compared with the traditional method, the preparation method of the present application eliminates P++ and uses LECO technology to achieve direct contact between the metal electrode (first electrode 12) and the P-type silicon substrate, which can directly save the boron diffusion, laser doping, high-temperature push-junction, wet removal of BSG plating and patterning processes required by P++ or even P+ structures, greatly saving production costs. In addition, since the boron diffusion process will reduce the life of the silicon substrate and there is a risk of producing "concentric circles", the method of the present application does not perform a boron diffusion process, but only an oxidation process, which cooperates with the impurity absorption effect of the phosphorus diffusion process in the preparation process of the subsequent n-type polysilicon doping layer, which has a significant effect on improving the life of the silicon substrate; at the same time, the requirements for the oxygen content in the silicon substrate will be further reduced, effectively reducing the cost of the silicon substrate.

[0118] The solar cell prepared by the preparation method of the present application includes the aforementioned solar cell.

[0119] The present application provides a photovoltaic assembly, comprising the aforementioned solar cell.

[0120] Example

[0121] The experimental methods used in the following examples are all conventional methods unless otherwise specified.

[0122] Unless otherwise specified, the materials and reagents used in the following examples can be obtained from commercial sources.

[0123] Example 1

[0124] The solar cell of this embodiment comprises the following steps:

[0125] Step 1: Clean the P-type silicon wafer with standard RCA and use a slot-type texturing device to perform double-sided texturing to form a pyramid-shaped texture structure. The P-type silicon wafer is 182mm×182mm.

[0126] Step 2: Oxidize the P-type silicon wafer on one side after texturing in a tubular oxidation furnace to form a thicker silicon oxide layer on the front side (facing the light), with a thickness of 100nm.

[0127] Step 3: Clean the silicon oxide layer plated on the back side with HF in a chain cleaning device, and then polish the back side of the silicon substrate with NaOH and alkaline polishing additives in a tank cleaning device.

[0128] Step 4: Use LPCVD equipment to grow a tunneling oxide layer (SiOx) with a thickness of 1.2 nm on the back side (polished surface) of the silicon substrate by thermal oxidation.

[0129] Step 5: Grow an intrinsic polysilicon layer with a thickness of 160 nm on the surface of the tunnel oxide layer facing away from the silicon substrate, and then perform phosphorus diffusion on the intrinsic polysilicon layer in a tubular diffusion furnace using POCl3 as a phosphorus source to prepare an n-type polysilicon layer with a doping concentration of 1E18 cm -3 -1E21 cm -3 .

[0130] Step 6: Use HF to clean the PSG plated on the front side in a chain cleaning device, then use an alkaline solution containing NaOH to wash away the n-type polysilicon layer plated on the front side in a tank cleaning device, and then use HF to simultaneously wash away the silicon oxide layer on the front side and the PSG on the back side.

[0131] Step 7: Use ALD equipment to deposit a 7nm thick aluminum oxide layer on the front side of the silicon substrate, and then use PECVD to perform double-sided SiNx coating to form a 75nm thick silicon nitride layer on the surface of the aluminum oxide layer facing away from the silicon substrate and on the surface of the n-type polysilicon doped layer facing away from the tunneling oxide layer.

[0132] Step eight: forming a first electrode precursor and a second electrode by screen printing silver paste and sintering annealing treatment, wherein the first electrode precursor penetrates the silicon nitride layer and the aluminum oxide layer to connect with the silicon substrate, and the second electrode penetrates the silicon nitride layer to connect with the n-type polysilicon doped layer.

[0133] Step nine: using the LECO process to process the first electrode precursor, thereby forming the first electrode.

[0134] The laser used in the LECO process is green light, the laser power is 375W, and the laser spot size is 5×5mm 2 , the reverse bias voltage is 15V, the reverse current is 8A, and the scanning mode is that the laser spot scans along the extension direction of the electrode grid line. The area where the first electrode covers the pyramid texture structure is the contact area, and the contact area includes the first contact area and the second contact area. The first contact area has conductive particles (Ag-Si microcrystals) with a grain diameter range of 20-100nm. The first metal element in the first contact area is silver, and the first metal element in the second contact area is silver. Figure 3 It can be seen that the content of the first metal element in the first contact region is greater than the content of the first metal element in the second contact region.

[0135] The boron expansion process on the front of the solar cell is eliminated to reduce the damage caused by the high temperature process of the boron expansion, and the LECO process is used to improve the contact performance between the first electrode 12 and the P-type silicon wafer substrate, thereby improving the electrical performance of the battery. Compared with the comparative example in which the boron expansion step is not eliminated and the LECO process is used or the boron expansion is not eliminated and the selective emitter is formed by heavy doping in the electrode area, the series resistance of the solar cell of the present application is reduced, the fill factor FF is improved, and the open circuit voltage is improved.

[0136] The electrical properties of the solar cell of this embodiment are shown in Table 1.

[0137] The difference between Example 2 to Example 5 and Example 1 is that the laser power is different, and the other parameters are the same. The parameters of the solar cell of this example are shown in Table 1.

[0138] The difference between Example 6 to Example 9 and Example 1 is that the reverse bias voltage is different, and the other parameters are the same. The parameters of the solar cell of this embodiment are shown in Table 1.

[0139] Comparative Example 1

[0140] The solar cell preparation method of this comparative example comprises the following steps:

[0141] Step 1: Clean the P-type silicon wafer with standard RCA and perform double-sided texturing using a tank texturing equipment.

[0142] Step 2: Use BCl3 as the boron source to perform single-sided diffusion and oxidation push-junction on the P-type silicon wafer after texturing in a tubular diffusion furnace to form a P+ layer and a thicker BSG layer on the front side (light incident side) of the silicon substrate. The BSG thickness is 100nm; the square resistance of the P+ layer is 225Ω / sq, and its depth is 100nm.

[0143] Step 3: Use HF to clean the back of the silicon substrate in a chain cleaning device and then polish the back of the silicon substrate with NaOH and alkaline polishing additives in a tank cleaning device;

[0144] Step 4: Use LPCVD equipment to grow a tunneling oxide layer (silicon oxide) with a thickness of 1-2 nm on the back side (polished surface) of the silicon substrate by thermal oxidation.

[0145] Step 5: growing an intrinsic polysilicon layer on the surface of the tunnel oxide layer facing away from the silicon substrate, and then performing phosphorus diffusion on the intrinsic polysilicon layer in a tubular diffusion furnace using POCl3 as a phosphorus source to prepare an n-type doped polysilicon layer with a thickness of 230 nm;

[0146] Step 6: Use HF to clean the PSG on the front side in a chain cleaning device, then use an alkaline solution containing NaOH to wash away the Poly on the front side in a tank cleaning device, and then use HF to wash away the BSG on the front side and the PSG on the back side at the same time;

[0147] Step 7: Use ALD equipment to deposit a 7.2nm thick aluminum oxide layer on the surface of the P+ layer facing away from the silicon substrate, and then use PECVD to perform double-sided silicon nitride coating to form a 70nm thick silicon nitride layer on the surface of the aluminum oxide layer facing away from the silicon substrate and on the surface of the n-type polysilicon doped layer facing away from the tunneling oxide layer.

[0148] Step eight: forming a first electrode and a second electrode by screen printing silver paste and sintering annealing treatment, wherein the first electrode penetrates the silicon nitride layer and the aluminum oxide layer and is connected to the P+ layer, and the second electrode penetrates the silicon nitride layer and is connected to the n-type polysilicon doped layer.

[0149] The electrical properties of the solar cell of this comparative example are shown in Table 1.

[0150] Comparative Example 2

[0151] The solar cell of this comparative example comprises the following steps:

[0152] Step 1: Clean the N-type silicon wafer with standard RCA and perform double-sided texturing using a tank texturing equipment.

[0153] Step 2: The N-type silicon wafer after texturing is diffused on one side in a tubular diffusion furnace using BCl3 as a boron source to form a P+ layer; the sheet resistance of the P+ layer is 201Ω / sq, and its depth is 100nm.

[0154] Step 3: Form a localized P++ structure on the front side (light incident side) through infrared laser doping. The square resistance of the P++ structure is 100Ω / sq and the junction depth is 250nm.

[0155] Step 4: The tubular oxidation furnace performs oxidation push-joint at high temperature. During this process, BSG with a thickness of about 120nm will be generated on the front side, and at the same time, BSG will be plated on the back side. The back side of the BSG will be cleaned with HF in the chain cleaning equipment, and the back side of the silicon substrate will be polished with alkaline solution containing NaOH in the tank cleaning equipment.

[0156] Step 5: Use LPCVD equipment to grow a tunnel oxide layer (silicon oxide) on the back side (polished surface) of the silicon substrate by thermal oxidation, then grow an intrinsic polysilicon layer on the tunnel oxide layer, and then use POCl3 as a phosphorus source in a tubular diffusion furnace to perform phosphorus diffusion on the intrinsic polysilicon layer to prepare an n-type polysilicon layer with a thickness of 223nm.

[0157] Step 6: Use HF to clean the PSG plated on the front side in a chain cleaning device, then use an alkaline solution containing NaOH to wash away the Poly plated on the front side in a tank cleaning device, and then use HF to simultaneously wash away the BSG on the front side and the PSG on the back side.

[0158] Step 7: Use ALD equipment to deposit an AlOx layer with a thickness of 7.6nm on the surface of the P+ layer and the P++ layer facing away from the silicon substrate, and then use PECVD to perform double-sided silicon nitride coating to form a 72nm thick silicon nitride layer on the surface of the aluminum oxide layer facing away from the silicon substrate and the surface of the n-type polysilicon doped layer facing away from the tunneling oxide layer.

[0159] Step eight: Form a first electrode 1 and a second electrode by screen printing silver paste and sintering annealing treatment. The first electrode 1 penetrates the SiNx layer and the aluminum oxide layer and connects to the P++ layer (the orthographic projection of the P++ layer on the silicon substrate coincides with the orthographic projection of the first electrode 1 on the silicon substrate), and the second electrode penetrates the silicon nitride layer and connects to the n-type polysilicon doped layer.

[0160] The electrical properties of the solar cell of this comparative example are shown in Table 1.

[0161] Table 1 shows the parameters of each embodiment and comparative example.

[0162] Laser power / W Reverse bias voltage / V Lifetime(us) <![CDATA[Jsc / (mA·cm -2 )]]> Eff / % Example 1 375 15 1531 40.53 25.44 Example 2 400 15 1517 40.50 25.41 Example 3 425 15 1512 39.93 25.03 Example 4 475 15 1418 40.58 25.37 Example 5 500 15 1396 39.88 24.89 Example 6 375 17 1429 40.21 25.11 Example 7 375 19 1375 39.71 24.77 Example 8 375 21 1298 40.24 25.03 Example 9 375 23 1249 39.74 24.58 Comparative Example 1 -- -- 830 40.10 24.40 Comparative Example 2 -- -- 1046 39.66 24.38

[0163] Summary: Compared with the comparative examples in which the boron diffusion step is not eliminated or the boron diffusion is not eliminated and the selective emitter is formed by heavy doping in the electrode area, the solar cell of the present application has a longer minority carrier lifetime and an increased short-circuit current density (Jsc). It can be seen that the boron diffusion process on the front of the solar cell is eliminated, the damage caused by the high-temperature boron diffusion process is reduced, and the passivation performance of the entire cell surface is improved. The LECO process is then used to improve the contact performance between the first electrode 12 and the silicon wafer substrate. It can be seen from the improved conversion efficiency (Eff) of the solar cell of the present application compared to the comparative example that the solar cell of the present application has better cell performance.

[0164] Although the embodiments of the present application are described above in conjunction with the accompanying drawings, the present application is not limited to the above specific embodiments and application fields, and the above specific embodiments are merely illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present application, all of which belong to the protection of the present application.

Claims

1. A solar cell, wherein: comprising a silicon substrate having a first surface and a second surface opposite to each other; A first passivation layer and a first electrode are sequentially stacked on the first surface, and the first electrode penetrates the first passivation layer and is electrically connected to the first surface; The area where the first electrode covers the first surface is a contact area, the contact area has a first metal element, and the contact area includes a first contact area and a second contact area; A content of the first metal element in the first contact region is greater than a content of the first metal element in the second contact region.

2. The solar cell according to claim 1, wherein: In the first contact area, the mass ratio of the first metal element at any position to all elements at that position is w 1-1 , In the second contact region, the mass ratio of the first metal element at any position to all elements at that position is w 2-1 ,in w 1-1 -w 2-1 20-60wt%.

3. The solar cell according to claim 1, wherein: The contact area has a second metal element, the content of the second metal element in the first contact area is greater than the content of the second metal element in the second contact area, and in the first contact area, the mass proportion of the second metal element at any position to all elements at that position is w 1-2 , In the second contact region, the mass proportion of the second metal element at any position to all elements at that position is w 2-2 ,in |in 1-2 -In 2-2 |≤10tue%。 4. The solar cell according to claim 1, wherein: The first contact region has conductive particles therein, and the conductive particles have a first metal element therein.

5. The solar cell according to claim 4, wherein: The particle size distribution range of the conductive particles is 20-100 nm.

6. The solar cell according to claim 1, wherein: In the silicon substrate, a first diffusion region is formed in a direction extending from the first surface of the first contact region to the inside of the silicon substrate, and the first diffusion region contains a first metal element; In the first diffusion region, a content of the first metal element at an end away from the first surface is less than a content at an end close to the first surface; and / or In the silicon substrate, a second diffusion region is formed in a direction extending from the first surface of the second contact region to the inside of the silicon substrate, and the second diffusion region contains a first metal element. In the second diffusion region, a content of the first metal element at an end away from the first surface is smaller than a content of the first metal element at an end close to the first surface.

7. The solar cell according to claim 6, wherein: The thickness of the first diffusion region and the second diffusion region are both 150-400 nm.

8. The solar cell according to claim 1, wherein: The first passivation layer is in direct contact with the first surface.

9. The solar cell according to any one of claims 1 to 8, wherein: A tunneling oxide layer, a doped polysilicon layer, a second passivation layer and a second electrode are sequentially stacked on the second surface, and the second electrode penetrates the second passivation layer and is electrically connected to the doped polysilicon layer; The doping type of the doped polysilicon layer is opposite to that of the silicon substrate.

10. A method for preparing a solar cell, wherein: The steps include: Providing a silicon substrate having a first surface and a second surface opposite to each other; forming a first passivation layer on a first surface of the silicon substrate; forming a first electrode precursor on a surface of the first passivation layer facing away from the silicon substrate, wherein the first electrode precursor penetrates the first passivation layer and is electrically connected to the silicon substrate; The first electrode precursor is processed by an induced sintering process to obtain a first electrode; The area where the first electrode covers the silicon substrate is a contact area, the contact area has a first metal element, and the contact area includes a first contact area and a second contact area; A content of the first metal element in the first contact region is greater than a content of the first metal element in the second contact region.

11. The preparation method according to claim 10, wherein: In the induced sintering process, a laser is used to scan a surface on one side where the first electrode precursor is located or a surface on a side away from the first electrode precursor, and a reverse bias is applied at the same time, thereby forming a first electrode; The energy of the laser is 200W / cm 2 -5000 W / cm 2 , the reverse bias is 5-20V.

12. A photovoltaic module, wherein: The invention comprises the solar cell according to any one of claims 1 to 9 or the solar cell prepared by the preparation method according to claim 10 or 11.

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