Silicon optical chip structure and manufacturing method

Abstract

The invention discloses a silicon optical chip structure and a manufacturing method. The silicon optical chip structure comprises a first dielectric layer and a second dielectric layer which are sequentially arranged on the surface of a substrate, a first device layer is arranged on the surface of the first dielectric layer, and a first passive device is arranged on the first device layer; a second device layer is arranged on the surface of the second dielectric layer, and a second passive device and an active device are arranged on the second device layer; the first device layer and the second device layer are isolated through a second dielectric layer; the first dielectric layer prevents light conducted to the first device layer and the second device layer from leaking into the substrate. According to the invention, the stability and reliability of the chip structure can be improved, light can be effectively prevented from leaking into the substrate, thermal crosstalk can be prevented, and integration of a silicon optical process and improvement of the performance of the silicon optical chip are facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a silicon photonic chip structure and a manufacturing method. Background Art

[0002] In the era of big data, people have higher and higher requirements for the computing power and speed of electronic computer processing systems. Electronic chips developed based on Moore's Law have encountered great challenges in computing speed and power consumption. Photonic chips use photons as information carriers and have the advantages of high-speed parallelism and low power consumption. Therefore, they are considered to be a very promising solution for future applications in high-speed, large-volume, and artificial intelligence computing and processing.

[0003] Silicon photonics is an integrated circuit manufacturing technology based on silicon substrate materials that integrates various optical waveguides, optical modulators and photodetectors onto the same chip. It can make full use of existing semiconductor logic circuit manufacturing technology to achieve high-performance optoelectronic device integration.

[0004] In silicon photonic chips, end couplers are generally used as input / output devices of silicon photonic chips. However, since the optical mode spot size of ordinary optical fibers is much larger than that of the optical mode spot size in silicon photonic chips, such as end couplers, this will cause large insertion losses. Therefore, how to reduce the insertion loss of end couplers is an important research topic in silicon photonic chip manufacturing.

[0005] On the one hand, since the light spot size in the silicon nitride waveguide is larger than that in the silicon waveguide, the spot mismatch loss can be reduced by using a silicon nitride end coupler. However, silicon nitride materials are difficult to integrate with other silicon optical devices. On the other hand, in order to reduce the leakage loss of light into the substrate, it is usually necessary to use a substrate hollowing (Undercut) structure, but this will also bring mechanical stability and reliability problems. These will have an impact on the integrated application of silicon nitride materials in silicon optical chips. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a silicon photonic chip structure and a manufacturing method.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] The present invention provides a silicon photonic chip structure, comprising:

[0009] substrate;

[0010] A first dielectric layer and a second dielectric layer are sequentially disposed on the surface of the substrate;

[0011] A first device layer is provided on the surface of the first dielectric layer, and the first device layer is provided with a first passive device;

[0012] A second device layer is provided on the surface of the second dielectric layer, and the second device layer is provided with second passive devices and active devices; the first device layer and the second device layer are isolated from each other by the second dielectric layer;

[0013] The first dielectric layer prevents light guided to the first device layer and the second device layer from leaking into the substrate.

[0014] Furthermore, it also includes: a fourth dielectric layer and an end face coupling deep groove, the fourth dielectric layer is arranged on the surface of the second dielectric layer and covers the second passive device and the active device, the top of the end face coupling deep groove is located on the surface of the fourth dielectric layer, and the bottom extends into the substrate through the fourth dielectric layer, the second dielectric layer and the first dielectric layer, the end face coupling deep groove is located on the outer side of the first device layer and the second device layer, the edge of the first device layer is provided with a first end face coupler as the first passive device, the edge of the second device layer is provided with a second end face coupler as the second passive device, and is arranged close to the end face coupling deep groove.

[0015] Furthermore, the end face coupling deep trench includes a first deep trench and a second deep trench connected to each other, the top of the first deep trench is located on the surface of the fourth dielectric layer, the bottom of the first deep trench is located on the surface of the substrate, the top of the second deep trench is located on the surface of the substrate and is connected to the bottom of the first deep trench, the bottom of the second deep trench is located in the substrate, and the second end face coupler and the first end face coupler are arranged close to the first deep trench.

[0016] Further, the first device layer material includes annealed dielectric, and / or, the second device layer material includes semiconductor, and / or, the first dielectric layer material includes silicon dioxide, and / or, the first dielectric layer has a thickness of 30,000 to 100,000 angstroms.

[0017] Further, the second device layer is formed by a top silicon layer of an SOI substrate, the top silicon layer is bonded to the surface of the second dielectric layer through a third dielectric layer formed on the surface to form the second device layer, the second passive device and the active device are formed through the top silicon layer, the fourth dielectric layer is located on a side surface of the third dielectric layer away from the bonding surface, and covers the second passive device and the active device; and / or, the fourth dielectric layer is further provided with connected conductive vias and a metal interconnection layer, and the active device is led out through the conductive vias and the metal interconnection layer.

[0018] The present invention also provides a method for manufacturing a silicon photonic chip structure, comprising the following steps:

[0019] providing a substrate;

[0020] forming a first dielectric layer on the surface of the substrate;

[0021] forming a first device layer on the surface of the first dielectric layer, and forming a first passive device on the first device layer;

[0022] forming a second dielectric layer on the surface of the first dielectric layer to cover the first passive device;

[0023] forming a second device layer on the surface of the second dielectric layer, and forming a second passive device and an active device on the second device layer;

[0024] When forming the first dielectric layer, the first dielectric layer has a first thickness that prevents light transmitted to the first device layer and the second device layer from leaking into the substrate, and when forming the second dielectric layer, the second dielectric layer has a second thickness that isolates the second device layer from the first device layer.

[0025] Further, when forming the first passive device, it includes forming a first end face coupler at the edge of the first device layer, and when forming the second passive device, it includes forming a second end face coupler at the edge of the second device layer; and further includes:

[0026] forming a fourth dielectric layer on the surface of the second dielectric layer to cover the second passive device and the active device;

[0027] An end face coupling deep groove is formed on the surface of the fourth dielectric layer, the bottom of which passes through the fourth dielectric layer, the second dielectric layer and the first dielectric layer and extends into the substrate, and the end face coupling deep groove is located on the outer side of the first device layer and the second device layer and is close to one side of the second end face coupler and the first end face coupler.

[0028] Furthermore, before forming the end surface coupling deep groove, the method specifically includes:

[0029] forming a first interlayer dielectric layer on the surface of the second dielectric layer to cover the second passive device and the active device;

[0030] forming a conductive via connected to the active device and a metal interconnect layer connected to the conductive via in the first interlayer dielectric layer;

[0031] forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer, and forming a lead pad connected to the metal interconnection layer at the bottom on the surface of the second interlayer dielectric layer;

[0032] forming a third interlayer dielectric layer on the surface of the second interlayer dielectric layer, forming a window on the surface of the third interlayer dielectric layer to expose the top of the pad; the first interlayer dielectric layer to the third interlayer dielectric layer constitute the fourth dielectric layer;

[0033] When forming the end surface coupling deep groove, it specifically includes:

[0034] First, a first deep trench is formed on the surface of the third interlayer dielectric layer, the bottom of which passes through the third interlayer dielectric layer to the first interlayer dielectric layer, the second dielectric layer and the first dielectric layer and stops at the surface of the substrate, and then a second deep trench is formed on the bottom of the first deep trench and extends to the substrate, thereby forming the end face coupling deep trench composed of the first deep trench and the second deep trench, and the first deep trench is located on the outer side of the first device layer and the second device layer, and is close to one side of the second end face coupler and the first end face coupler.

[0035] Further, when forming the first dielectric layer, the first thickness of the first dielectric layer is 30,000 to 100,000 angstroms, and / or, when forming the second dielectric layer, the second thickness of the second dielectric layer is greater than the thickness of the first device layer, and / or, before forming the first passive device, the method further includes:

[0036] The first device layer is annealed to drive out hydrogen in the material of the first device layer and reduce the absorption of C-band light by the material of the first device layer.

[0037] Further, when forming the second device layer, it specifically includes:

[0038] Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer arranged in sequence;

[0039] forming a third dielectric layer on the surface of the top silicon layer;

[0040] Aligning the SOI substrate with the substrate, and bonding the surface of the third dielectric layer with the surface of the second dielectric layer through the surface of the third dielectric layer;

[0041] The bottom silicon layer and the buried oxide layer are removed, and the third dielectric layer and the top silicon layer as the second device layer are sequentially formed on the surface of the second dielectric layer.

[0042] It can be seen from the above technical scheme that the present invention can effectively prevent the light transmitted to the first device layer and the second device layer from leaking into the substrate by forming the first dielectric layer on the substrate, using the thick thickness (first thickness) of the first dielectric layer, thereby improving the characteristics of silicon photonic chip devices (such as the first end face coupler and the second end face coupler), thereby eliminating the need to form a traditional substrate hollowing structure, completely avoiding the process risks of structural collapse, peeling, etc., and improving mechanical stability, reliability and yield. In addition, by using annealed dielectric as the material for forming the first passive device, a high-performance optical passive device that is superior to ordinary semiconductor materials can be formed, and the influence of high-temperature processes on the formation of active devices can be avoided; by using the top silicon layer of the SOI substrate to form the second device layer after bonding, a high degree of integration of high-performance optoelectronic devices including active devices and passive devices can be achieved on a single chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a schematic diagram of a silicon photonic chip structure according to a preferred embodiment of the present invention.

[0044] Figure 2 The present invention is a flowchart of a method for manufacturing a silicon photonic chip structure according to a preferred embodiment of the present invention.

[0045] Figure 3-Figure 10 A preferred embodiment of the present invention is based on Figure 2 Schematic diagram of the process steps for forming a silicon photonic chip structure using the method. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0047] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0048] refer to Figure 1A silicon photonic chip structure of the present invention comprises a first dielectric layer 202 and a second dielectric layer 204 sequentially disposed on the upper surface of a substrate 201 , a first device layer 203 disposed on the upper surface of the first dielectric layer 202 , and a second device layer 205 disposed on the upper surface of the second dielectric layer 204 .

[0049] The first device layer 203 and the second device layer 205 are sequentially arranged above the upper surface of the substrate 201, and the first device layer 203 and the second device layer 205 are isolated from each other by the second dielectric layer 204, and are arranged together with the substrate 201. The first device layer 203 is provided with first passive devices (such as a first end face coupler 2031 and other first passive devices 2032); the second device layer 205 is provided with second passive devices (such as a second end face coupler 2051 and other second passive devices 2054) and active devices (such as a modulator 2052, a thermal phase shifter 2053, and a photodetector 2055).

[0050] Furthermore, the first dielectric layer 202 plays a role in preventing the light transmitted to the first device layer 203 and the second device layer 205 from leaking into the substrate 201. This role is ensured by the thickness of the first dielectric layer 202 (first thickness H).

[0051] refer to Figure 1 In some embodiments, a fourth dielectric layer 206 is further provided on the surface of the second dielectric layer 204, and the fourth dielectric layer 206 covers the second passive device and the active device. An end face coupling deep groove 209 is further provided on the surface of the fourth dielectric layer 206; the top of the end face coupling deep groove 209 is located on the surface of the fourth dielectric layer 206, and the bottom of the end face coupling deep groove 209 passes through the fourth dielectric layer 206, the second dielectric layer 204 and the first dielectric layer 202 and extends into the substrate 201.

[0052] Furthermore, the end face coupling deep groove 209 is located at the outer side of the first device layer 203 and the second device layer 205 (for example Figure 1 The first device layer 203 and the second device layer 205 are shown as being located on the left side of the periphery. A first end face coupler 2031 as a first passive device is provided at the edge of the first device layer 203; and a second end face coupler 2051 as a second passive device is provided at the edge of the second device layer 205. The second end face coupler 2051 and the first end face coupler 2031 are arranged close to the end face coupling deep groove 209, that is, the second end face coupler 2051 and the first end face coupler 2031 are arranged closer to the end face coupling deep groove 209 than other devices in the same layer, and the side surfaces of the second end face coupler 2051 and the first end face coupler 2031 are isolated from the side walls of the end face coupling deep groove 209 by the fourth dielectric layer 206, the second dielectric layer 204 and the first dielectric layer 202.

[0053] The first device layer 203 is located on the first dielectric layer 202 and in the second dielectric layer 204 ; the second device layer 205 is located on the second dielectric layer 204 and in the fourth dielectric layer 206 .

[0054] In some embodiments, the fourth dielectric layer 206 is further provided with connected conductive vias 207 and metal interconnection layers 208. The active devices (modulator 2052, thermal phase shifter 2053, photodetector 2055) provided in the second device layer 205 are led out through the conductive vias 207 and metal interconnection layers 208.

[0055] In some embodiments, the substrate 201 may be a semiconductor substrate 201 , for example, the substrate 201 may be a silicon substrate 201 .

[0056] The material of the first device layer 203 includes an annealed dielectric, such as annealed silicon nitride, silicon oxynitride, aluminum nitride or silicon carbide.

[0057] The material of the second device layer 205 includes semiconductor, for example, silicon semiconductor.

[0058] The materials of the first dielectric layer 202 and the second dielectric layer 204 include silicon dioxide.

[0059] The thickness of the first dielectric layer 202 (first thickness H) is 30,000 to 100,000 angstroms.

[0060] refer to Figure 1 In some embodiments, the first passive device includes a first end face coupler 2031 and other first passive devices 2032 (eg, waveguides, etc.). By having a thicker first dielectric layer 202, light transmitted to the first device layer 203 can be prevented from leaking to the substrate 201.

[0061] In some embodiments, the second passive device includes a second end face coupler 2051 and other second passive devices 2054 (such as waveguides, etc.). The active device includes a modulator 2052, a thermal phase shifter 2053, and a photodetector 2055. Through the combined effect of the first dielectric layer 202 and the second dielectric layer 204 having a relatively thick thickness, the light conducted to the second device layer 205 can be prevented from leaking to the substrate 201, and the thermal crosstalk caused by the thermal phase shifter 2053 to the substrate 201 can be reduced. Thereby, the device characteristics of the silicon photonic chip are improved.

[0062] In some embodiments, the conductive via 207 may be, for example, a conductive tungsten via.

[0063] The metal interconnection layer 208 can be made of, for example, copper metal interconnection lines in one or more layers.

[0064] In some embodiments, the end face coupling deep trench 209 includes a first deep trench 2091 and a second deep trench 2092 connected to each other. The top of the first deep trench 2091 is located on the surface of the fourth dielectric layer 206, and the bottom of the first deep trench 2091 is located on the surface of the silicon substrate 201; the top of the second deep trench 2092 is located on the surface of the silicon substrate 201 and is connected to the bottom of the first deep trench 2091, and the bottom of the second deep trench 2092 is located in the silicon substrate 201. The second end face coupler 2051 and the first end face coupler 2031 are arranged close to the first deep trench 2091.

[0065] In some embodiments, the second device layer 205 is formed using another SOI substrate. The SOI substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer arranged in sequence. A third dielectric layer is formed on the surface of the top silicon layer; by aligning the SOI substrate with the silicon substrate 201, and bonding the surface of the third dielectric layer to the upper surface of the second dielectric layer 204 on the silicon substrate 201, and removing the bottom silicon layer and the buried oxide layer after bonding, a third dielectric layer (not shown) and a top silicon layer are sequentially formed on the upper surface of the second dielectric layer 204, and the top silicon layer is used as the second device layer 205. The second passive device and the active device are formed by patterning the top silicon layer. The fourth dielectric layer 206 is located on the upper surface of the third dielectric layer away from the bonding surface, and covers the second passive device and the active device formed on the top silicon layer.

[0066] The second device layer 205 may also be formed using another silicon substrate.

[0067] In some embodiments, the fourth dielectric layer 206 includes a first interlayer dielectric layer 2061, a second interlayer dielectric layer (not shown), and a third interlayer dielectric layer (not shown) sequentially disposed on the upper surface of the third dielectric layer. The first interlayer dielectric layer 2061 covers the second passive device and the active device, and the conductive via 207 and the metal interconnection layer 208 are located in the first interlayer dielectric layer 2061. The second interlayer dielectric layer is located on the upper surface of the first interlayer dielectric layer 2061, and a lead pad for bottom connection to the metal interconnection layer 208 is formed on the upper surface of the second interlayer dielectric layer. The pad can be, for example, an aluminum pad. The third interlayer dielectric layer is located on the upper surface of the second interlayer dielectric layer as a passivation layer, and a window is formed on the upper surface of the third interlayer dielectric layer, and the top of the pad is exposed from the window. The third interlayer dielectric layer (passivation layer) can be a multi-layer dielectric stack, for example, the third interlayer dielectric layer can be a stack of silicon dioxide and silicon nitride.

[0068] Furthermore, the end face coupling deep groove 209 also passes through the third interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer 2061, the third dielectric layer, the second dielectric layer 204 and the first dielectric layer 202 from the upper surface of the third interlayer dielectric layer downward, and extends to the bottom in the substrate 201. Among them, the first deep trench 2091 is formed from the upper surface of the third interlayer dielectric layer downward in the third interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer 2061, the third dielectric layer, the second dielectric layer 204 and the first dielectric layer 202, and the bottom of the first deep trench 2091 is located on the upper surface of the substrate 201; the second deep trench 2092 is formed from the upper surface of the substrate 201 downward in the substrate 201. The opening top of the second deep trench 2092 is connected to the bottom of the first deep trench 2091 , and the first deep trench 2091 is located on the left side of the periphery of the first device layer 203 and the second device layer 205 , and is arranged close to the left side of the first end face coupler 2031 and the second end face coupler 2051 .

[0069] The materials of the first interlayer dielectric layer 2061 and the second interlayer dielectric layer can be silicon dioxide, for example. It should be noted that the various materials listed above are only used to illustrate the embodiments of the present invention, and are not used to limit the types of materials used in the structure of the present invention.

[0070] The following is a further detailed description of a method for manufacturing a silicon photonic chip structure of the present invention through specific implementation methods and in combination with the accompanying drawings.

[0071] refer to Figure 2 Combined with reference Figure 3-Figure 10 The present invention provides a method for manufacturing a silicon photonic chip structure, which can be used to manufacture the above-mentioned Figure 1 A silicon photonic chip structure of the present invention may include the following steps:

[0072] Step S1: providing a substrate 201 .

[0073] like Figure 3 As shown, a silicon wafer substrate 201 can be used to manufacture the above-mentioned Figure 1 A silicon photonic chip structure of the present invention.

[0074] Step S2: forming a first dielectric layer 202 on the surface of the substrate 201 .

[0075] like Figure 3 As shown, a PECVD process is used to form a silicon substrate 201 having a first thickness H (reference Figure 1), so that the first dielectric layer 202 has the ability to prevent the light transmitted to the first device layer 203 and the second device layer 205 from leaking into the substrate. The first thickness H of the first dielectric layer 202 is 30000 to 100000 angstroms. In this embodiment, silicon dioxide with a first thickness H of 50000 angstroms is deposited to form the first dielectric layer 202, which serves as a dielectric isolation layer structure between the first device layer 203 and the substrate 201.

[0076] Step S3 : forming a first device layer 203 on the surface of the first dielectric layer 202 , and forming a first passive device on the first device layer 203 .

[0077] like Figure 4 As shown, a first device layer 203 is formed on the upper surface of the first dielectric layer 202 by using an LPCVD process. The first device layer 203 has a thickness of 500 to 10,000 angstroms and is used to form a first passive device such as a high-performance waveguide. In this embodiment, a high-performance waveguide material silicon nitride is deposited with a thickness of 4,000 angstroms to form the first device layer 203.

[0078] Then, the first device layer 203 formed of the high-performance waveguide material is subjected to high-temperature annealing at a temperature of 700-1300° C. to drive out hydrogen in the material of the first device layer 203 and reduce the absorption of C-band light by the material of the first device layer 203. In this embodiment, the silicon substrate 201 having the first device layer 203 of the high-performance waveguide material silicon nitride is placed in a nitrogen atmosphere and annealed at 1200° C. for about 1 hour, so that the NH bonds and Si-H bonds in the high-performance waveguide material silicon nitride are broken, and H is driven out of the silicon nitride film, thereby achieving the effect of reducing the absorption of C-band light.

[0079] like Figure 5 As shown, then, a patterning process is used to form a first passive device on the first device layer 203. In this embodiment, a high-performance silicon nitride waveguide material is patterned by photolithography and etching processes to form a silicon nitride first end face coupler 2031 and other silicon nitride first passive devices 2032 (such as silicon nitride waveguides) as the first passive device. By forming a silicon dioxide first dielectric layer 202 with a thickness of 50,000 angstroms, the silicon nitride first end face coupler 2031 is located above the first dielectric layer 202 and is 50,000 angstroms away from the silicon substrate, thereby preventing light from leaking to the silicon substrate 201, thereby improving the device characteristics of the first end face coupler 2031.

[0080] Step S4: forming a second dielectric layer 204 on the surface of the first dielectric layer 202 to cover the first passive device.

[0081] like Figure 6As shown, a CVD process, such as an LPCVD process, a PECVD process, or an HDPCVD process, is used to form a second dielectric layer 204 on the upper surface of the first dielectric layer 202 to cover the first passive device. In this embodiment, the HDPCVD process is used to deposit a second thickness L (reference Figure 1 ) is 6000 angstroms of silicon dioxide as the second dielectric layer 204, so that the second thickness L of the second dielectric layer 204 is greater than the thickness of 4000 angstroms of the first device layer 203, and the silicon nitride first passive device is covered so that the subsequently formed second device layer 205 is isolated from the first device layer 203, and the second dielectric layer 204 and the first dielectric layer 202 together serve as a dielectric isolation layer structure between the second device layer 205 and the substrate 201, and a chemical mechanical polishing process is used to flatten the upper surface of the second dielectric layer 204.

[0082] Step S5: forming a second device layer 205 on the surface of the second dielectric layer 204 , and forming second passive devices and active devices on the second device layer 205 .

[0083] like Figure 7 As shown, a silicon second device layer 205 is formed on the upper surface of the second dielectric layer 204 and covers the first passive device. The thickness of the silicon second device layer 205 is 1000 to 30000 angstroms. The silicon second device layer 205 located on the second dielectric layer 204 can be formed by transferring the top silicon layer of the SOI substrate (or other silicon substrate) to the upper surface of the planarized second dielectric layer 204.

[0084] In this embodiment, an SOI substrate is used, and the SOI substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer arranged in sequence. The thickness of the top silicon layer is, for example, 2200 angstroms. And by using the LPCVD process, for example, 1000 angstroms of silicon dioxide is deposited on the surface of the top silicon layer of the SOI substrate as a third dielectric layer (not shown). Next, the SOI substrate is aligned with the silicon substrate 201, and a silicon dioxide-silicon dioxide fusion bonding process is used to bond the SOI substrate face to face with the silicon substrate 201 formed with a second silicon dioxide dielectric layer 204 through the surface of the third dielectric layer. Afterwards, the bottom silicon layer and the buried oxide layer of the SOI substrate are removed to form a third dielectric layer and a silicon second device layer 205 (top silicon layer) sequentially located on the second dielectric layer 204.

[0085] like Figure 8As shown, a second passive device and an active device are formed on the second device layer 205 by a patterning process. In this embodiment, photolithography, etching and other processes are used to complete silicon patterning of different depths on the second device layer 205. Then, various silicon-based devices and germanium-based devices of the silicon photonic chip are formed by implantation, germanium epitaxy and patterning processes for different devices. Among them, the silicon-based device includes a second end face coupler 2051 as a second passive device, other second passive devices 2054 (such as waveguides), and a modulator 2052 and a thermal phase shifter 2053 as active devices. The germanium-based device includes a germanium photodetector 2055 as an active device. The formed second end face coupler 2051 is located above the third dielectric layer to the first dielectric layer 202, and is greater than 50,000 angstroms from the silicon substrate 201, which can prevent light from leaking to the silicon substrate 201. The thermal phase shifter 2053 is located above the third dielectric layer 202 at different positions, which can prevent light from leaking to the silicon substrate 201 and reduce thermal crosstalk, thereby improving device characteristics.

[0086] Step S6: forming a fourth dielectric layer 206 on the surface of the second dielectric layer 204 to cover the second passive device and the active device, and forming an end face coupling deep groove 209 on the surface of the fourth dielectric layer 206 with the bottom extending into the substrate.

[0087] like Fig. 9 As shown, a first interlayer dielectric layer 2061 is formed on the upper surface of the second dielectric layer 204 (third dielectric layer) to cover the second passive device and the active device. In this embodiment, a conventional CMOS process is used to first deposit the first interlayer dielectric layer 2061 of the first part. Then, a tungsten conductive via 207 is formed in the first interlayer dielectric layer 2061 of the first part by using processes such as photolithography, etching, tungsten deposition and CMP, and the tungsten conductive via 207 is connected to the modulator 2052, the thermal phase shifter 2053 and the germanium photodetector 2055 below. Then, the first interlayer dielectric layer 2061 of the second part is continuously deposited on the first interlayer dielectric layer 2061 of the first part, and a copper metal interconnection layer 208 connected to the tungsten conductive via 207 is formed in the first interlayer dielectric layer 2061 of the second part by using a Damascene process. The copper metal interconnection layer 208 can be a single copper metal interconnection line layer or a multi-layer copper metal interconnection line layer formed by multiple Damascene processes.

[0088] Then, further, it also includes: forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer 2061, and using a patterning process to form a lead-out pad connected to the bottom metal interconnection layer 208 on the upper surface of the second interlayer dielectric layer. And forming a third interlayer dielectric layer as a dielectric passivation layer on the upper surface of the second interlayer dielectric layer, and using a patterning process to form a window on the upper surface of the third interlayer dielectric layer to expose the top of the pad (not shown above). In this embodiment, firstly, a second interlayer dielectric layer of silicon dioxide is deposited on the surface of the first interlayer dielectric layer 2061; then, a pad through hole is formed on the upper surface of the second interlayer dielectric layer by photolithography and etching processes; then, aluminum is deposited and patterned to form an aluminum pad for lead-out; then, silicon dioxide and silicon nitride are deposited on the upper surface of the second interlayer dielectric layer as a dielectric passivation layer (third interlayer dielectric layer), and a window is formed on the upper surface of the dielectric passivation layer by photolithography and etching processes to expose the top of the aluminum pad. The first interlayer dielectric layer 2061 to the third interlayer dielectric layer together constitute the fourth dielectric layer 206 .

[0089] like Fig.10 As shown, an end face coupling deep groove 209 is formed on the upper surface of the fourth dielectric layer 206 (third interlayer dielectric layer) with the bottom passing through the fourth dielectric layer 206 (third interlayer dielectric layer to first interlayer dielectric layer 2061), the third dielectric layer to the first dielectric layer 202 and extending to the substrate 201, and the end face coupling deep groove 209 is located on the outer side of the first device layer 203 and the second device layer 205, and is close to one side of the second end face coupler 2051 and the first end face coupler 2031.

[0090] In some embodiments, a step-by-step patterning process is used to first form a first deep trench 2091 below the upper surface of the third interlayer dielectric layer, with the bottom located on the surface of the substrate 201, and then a second deep trench 2092 is formed on the bottom of the first deep trench 2091, with the bottom extending into the substrate 201, thereby forming an end face coupling deep trench 209 composed of the first deep trench 2091 and the second deep trench 2092. In this embodiment, a dielectric etching process is first used to etch the dielectric layers above the silicon substrate 201 (the third interlayer dielectric layer to the first interlayer dielectric layer 2061, the third dielectric layer to the first dielectric layer 202), forming the first deep trench 2091 with the bottom located on the upper surface of the silicon substrate 201. Then, a deep silicon etching process, such as a Bosch process, is used to continue etching the silicon substrate 201, and a second deep trench 2092 with a depth of, for example, about 100 μm is formed in the silicon substrate 201, thereby forming a complete end face coupling deep trench 209. The first deep trench 2091 can be located on the left side of the periphery of the first device layer 203 and the second device layer 205, and close to the left side of the first end face coupler 2031 and the second end face coupler 2051. After etching, cleaning can be performed to complete the silicon photonic process.

[0091] In summary, the present invention forms the first dielectric layer 202 on the substrate 201, and can utilize the thick thickness (first thickness H) of the first dielectric layer 202 to effectively prevent the light conducted to the first device layer 203 and the second device layer 205 from leaking into the substrate 201, thereby improving the characteristics of silicon photonic chip devices (such as the first end face coupler 2031, the second end face coupler 2051, and the thermal phase shifter 2053), thereby eliminating the need to form a traditional substrate hollowing structure, completely avoiding the process risks of structural collapse, peeling, etc., and improving mechanical stability, reliability, and yield. In addition, by using annealed dielectrics (such as high-performance waveguide materials such as silicon nitride annealed at high temperature) as the material for forming the first passive device, a high-performance optical passive device that is superior to ordinary semiconductor materials can be formed, and the influence of high-temperature processes on the formation of active devices can be avoided. The second device layer 205 can also be formed by utilizing the top silicon layer of the SOI substrate after bonding, and a high degree of integration of high-performance optoelectronic devices including active devices and passive devices can be achieved on a single chip.

[0092] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A silicon photonic chip structure, characterized in that: include: substrate; A first dielectric layer and a second dielectric layer are sequentially disposed on the surface of the substrate; A first device layer is provided on the surface of the first dielectric layer, and the first device layer is provided with a first passive device; A second device layer is provided on the surface of the second dielectric layer, and the second device layer is provided with second passive devices and active devices; the first device layer and the second device layer are isolated from each other by the second dielectric layer; The first dielectric layer prevents light guided to the first device layer and the second device layer from leaking into the substrate.

2. The silicon photonic chip structure according to claim 1, characterized in that: Also includes: A fourth dielectric layer and an end-face coupling deep groove, wherein the fourth dielectric layer is disposed on the surface of the second dielectric layer and covers the second passive device and the active device, the top of the end-face coupling deep groove is disposed on the surface of the fourth dielectric layer, and the bottom thereof extends through the fourth dielectric layer, the second dielectric layer and the first dielectric layer to the substrate, the end-face coupling deep groove is disposed on the outer periphery of the first device layer and the second device layer, a first end-face coupler serving as the first passive device is disposed at the edge of the first device layer, and a second end-face coupler serving as the second passive device is disposed at the edge of the second device layer and is disposed close to the end-face coupling deep groove.

3. The silicon photonic chip structure according to claim 2, characterized in that: The end face coupling deep trench includes a first deep trench and a second deep trench connected to each other, the top of the first deep trench is located on the surface of the fourth dielectric layer, the bottom of the first deep trench is located on the surface of the substrate, the top of the second deep trench is located on the surface of the substrate and is connected to the bottom of the first deep trench, the bottom of the second deep trench is located in the substrate, and the second end face coupler and the first end face coupler are arranged close to the first deep trench.

4. The silicon photonic chip structure according to claim 1, characterized in that: The first device layer material includes annealed dielectric, and / or, the second device layer material includes semiconductor, and / or, the first dielectric layer material includes silicon dioxide, and / or, the first dielectric layer has a thickness of 30,000 to 100,000 angstroms.

5. The silicon photonic chip structure according to claim 1, characterized in that: The second device layer is formed by a top silicon layer of an SOI substrate, the top silicon layer is bonded to the surface of the second dielectric layer through a third dielectric layer formed on the surface to form the second device layer, the second passive device and the active device are formed through the top silicon layer, the fourth dielectric layer is located on a side surface of the third dielectric layer away from the bonding surface, and covers the second passive device and the active device; and / or, the fourth dielectric layer is further provided with connected conductive vias and a metal interconnection layer, and the active device is led out through the conductive vias and the metal interconnection layer.

6. A method for manufacturing a silicon photonic chip structure, characterized in that: The following steps are involved: providing a substrate; forming a first dielectric layer on the surface of the substrate; forming a first device layer on the surface of the first dielectric layer, and forming a first passive device on the first device layer; forming a second dielectric layer on the surface of the first dielectric layer to cover the first passive device; forming a second device layer on the surface of the second dielectric layer, and forming a second passive device and an active device on the second device layer; When forming the first dielectric layer, the first dielectric layer has a first thickness that prevents light transmitted to the first device layer and the second device layer from leaking into the substrate, and when forming the second dielectric layer, the second dielectric layer has a second thickness that isolates the second device layer from the first device layer.

7. The method for manufacturing a silicon photonic chip structure according to claim 6, characterized in that: When forming the first passive device, the method includes forming a first end face coupler at the edge of the first device layer, and when forming the second passive device, the method includes forming a second end face coupler at the edge of the second device layer; and further includes: forming a fourth dielectric layer on the surface of the second dielectric layer to cover the second passive device and the active device; An end face coupling deep groove is formed on the surface of the fourth dielectric layer, the bottom of which passes through the fourth dielectric layer, the second dielectric layer and the first dielectric layer and extends into the substrate, and the end face coupling deep groove is located on the outer side of the first device layer and the second device layer and is close to one side of the second end face coupler and the first end face coupler.

8. The method for manufacturing a silicon photonic chip structure according to claim 7, characterized in that: Before forming the end surface coupling deep groove, the method specifically includes: forming a first interlayer dielectric layer on the surface of the second dielectric layer to cover the second passive device and the active device; forming a conductive via connected to the active device and a metal interconnect layer connected to the conductive via in the first interlayer dielectric layer; forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer, and forming a lead pad connected to the metal interconnection layer at the bottom on the surface of the second interlayer dielectric layer; forming a third interlayer dielectric layer on the surface of the second interlayer dielectric layer, forming a window on the surface of the third interlayer dielectric layer to expose the top of the pad; the first interlayer dielectric layer to the third interlayer dielectric layer constitute the fourth dielectric layer; When forming the end surface coupling deep groove, it specifically includes: First, a first deep trench is formed on the surface of the third interlayer dielectric layer, the bottom of which passes through the third interlayer dielectric layer to the first interlayer dielectric layer, the second dielectric layer and the first dielectric layer and stops at the surface of the substrate, and then a second deep trench is formed on the bottom of the first deep trench and extends to the substrate, thereby forming the end face coupling deep trench composed of the first deep trench and the second deep trench, and the first deep trench is located on the outer side of the first device layer and the second device layer, and is close to one side of the second end face coupler and the first end face coupler.

9. The method for manufacturing a silicon photonic chip structure according to claim 6, characterized in that: When forming the first dielectric layer, the first thickness of the first dielectric layer is 30,000 to 100,000 angstroms, and / or, when forming the second dielectric layer, the second thickness of the second dielectric layer is greater than the thickness of the first device layer, and / or, before forming the first passive device, the method further includes: The first device layer is annealed to drive out hydrogen in the material of the first device layer and reduce the absorption of C-band light by the material of the first device layer.

10. The method for manufacturing a silicon photonic chip structure according to claim 6, characterized in that: When forming the second device layer, it specifically includes: Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer arranged in sequence; forming a third dielectric layer on the surface of the top silicon layer; Aligning the SOI substrate with the substrate, and bonding the surface of the third dielectric layer with the surface of the second dielectric layer through the surface of the third dielectric layer; The bottom silicon layer and the buried oxide layer are removed, and the third dielectric layer and the top silicon layer as the second device layer are sequentially formed on the surface of the second dielectric layer.

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