Display substrate, its preparation method and display device

Abstract

A display substrate is provided, comprising: a substrate substrate; a driving circuit layer; a first electrode layer comprising a first electrode, the first electrode being electrically connected with the driving circuit layer; a partition layer comprising a pixel opening; and a light-emitting functional layer; the partition layer comprises at least one interval opening between two adjacent pixel openings, a side of the partition layer facing the interval opening has a first undercut structure; the light-emitting functional layer comprises a charge generation layer, at least a part of the charge generation layer is disconnected at the first undercut structure; and the display substrate further comprises at least one support column, the support column is located on a side of the driving circuit layer away from the substrate substrate, at least a part of the support column has a projection on the substrate substrate, the projection is located in a projection of the interval opening on the substrate substrate, and the support column is spaced apart from the first undercut structure, at least a part of the charge generation layer is located on a side of the support column away from the substrate substrate, and at least another part of the charge generation layer is located between the support column and the adjacent first undercut structure.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for preparing the substrate, and a display device. Background Technology

[0002] With the development of display technology, Organic Light Emitting Diode (OLED) displays have gained a significant share of the high-end display market in recent years due to their excellent picture quality and wide range of applications. Consequently, users' demands for the display performance of OLED displays are also increasing. Tandem OLED is a high-efficiency OLED device structure formed by connecting multiple OLED devices in series through a charge generation layer (CGL). However, the newly added CGL in Tandem OLED suffers from lateral leakage, leading to abnormal brightening issues in low grayscale images during lamp-lit tests. In Tandem OLED displays, how to avoid crosstalk between pixels caused by lateral leakage in the charge generation layer is one of the key issues that display product developers are focusing on.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, wherein the display substrate comprises:

[0005] Substrate;

[0006] The driving circuit layer is located on the substrate.

[0007] A first electrode layer is located on the side of the driving circuit layer away from the substrate. The first electrode layer includes a first electrode, which is electrically connected to the driving circuit layer.

[0008] A barrier layer, located on the side of the first electrode layer away from the substrate, the barrier layer including a pixel opening that exposes at least a portion of the first electrode; and

[0009] A light-emitting functional layer is located on the side of the barrier layer away from the substrate, and a portion of the light-emitting functional layer is located within the pixel opening and in contact with the first electrode.

[0010] The partition layer includes at least one spacer opening, the spacer opening is located between two adjacent pixel openings, and the partition layer has a first undercut structure on the side facing the spacer opening;

[0011] The light-emitting functional layer includes a first light-emitting functional sublayer, a charge-generating layer located on the side of the first light-emitting functional sublayer away from the substrate, and a second light-emitting functional sublayer located on the side of the charge-generating layer away from the substrate, wherein at least a portion of the charge-generating layer is broken at the first undercut structure; and

[0012] The display substrate further includes at least one support pillar, which is located on the side of the driving circuit layer away from the substrate. At least a portion of the support pillar has its orthographic projection on the substrate within the orthographic projection of the spaced opening on the substrate. The support pillar is spaced apart from the first undercut structure. At least a portion of the charge generation layer is located on the side of the support pillar away from the substrate, and at least another portion of the charge generation layer is located between the support pillar and the adjacent first undercut structure.

[0013] According to some exemplary embodiments, the partition layer includes a first sublayer and a second sublayer located on the first sublayer near the substrate, wherein one end of the first sublayer facing the spacer opening protrudes relative to the other end of the second sublayer facing the spacer opening.

[0014] According to some exemplary embodiments, the partition layer includes a third sublayer located on the side of the second sublayer closer to the substrate, wherein one end of the third sublayer facing the spacer opening protrudes relative to the end of the second sublayer facing the spacer opening.

[0015] According to some exemplary embodiments, the display substrate further includes a planarization layer located between the driving circuit layer and the first electrode layer, the planarization layer including vias through which the first electrode is electrically connected to the driving circuit layer; and

[0016] The planarization layer has a groove that is at least partially recessed into the planarization layer in a direction close to the substrate. The orthographic projection of the groove on the substrate at least partially overlaps with the orthographic projection of the spacer opening on the substrate. The groove includes a first sidewall facing the spacer opening. One end of the third sublayer facing the spacer opening protrudes towards the spacer opening relative to the first sidewall.

[0017] According to some exemplary embodiments, the shape of the orthographic projection of the support post on the substrate includes an elongated strip shape.

[0018] According to some exemplary embodiments, at least a portion of the elongated strip extends along the edge of the orthographic projection of at least one adjacent pixel opening onto the substrate.

[0019] According to some exemplary embodiments, in a direction perpendicular to the extension direction of the support column, the distance between the orthographic projection of the support column on the substrate and the orthographic projection of the adjacent first undercut structure on the substrate is 2μm-3μm.

[0020] According to some exemplary embodiments, the side of the partition layer facing the pixel opening has a second undercut structure, and at least a portion of the charge generating layer is broken at the second undercut structure.

[0021] According to some exemplary embodiments, the first electrode includes a first electrode body portion and a first electrode connection portion connected as an integral structure, the pixel opening exposes at least a portion of the first electrode body portion, and the orthographic projection of the spaced opening on the substrate is spaced apart from the orthographic projection of the first electrode connection portion on the substrate.

[0022] According to some exemplary embodiments, at least two adjacent spaced openings are connected; and / or,

[0023] At least two adjacent gap openings are spaced apart, and the orthographic projections of the two adjacent openings on the substrate are respectively located on both sides of the orthographic projection of at least one first electrode connection portion on the substrate.

[0024] According to some exemplary embodiments, the first sublayer, the second sublayer, and the third sublayer all comprise inorganic insulating materials, and the materials of the first sublayer and the second sublayer are different, as are the materials of the second sublayer and the third sublayer.

[0025] In another aspect, a display device is provided, the display device comprising a display substrate according to any one of the above claims.

[0026] In another aspect, a method for preparing a display substrate is provided, the method comprising:

[0027] A driving circuit layer is formed on the substrate.

[0028] A first electrode layer is formed on the side of the driving circuit layer away from the substrate. The first electrode layer includes a first electrode, which is electrically connected to the driving circuit layer.

[0029] A partition layer is formed on the side of the first electrode layer away from the substrate. The partition layer includes a pixel opening that exposes at least a portion of the first electrode. The partition layer includes at least one spacer opening located between two adjacent pixel openings. The partition layer has a first undercut structure on the side facing the spacer opening.

[0030] A support pillar is formed on the side of the driving circuit layer away from the substrate, at least a portion of the support pillar having its orthographic projection on the substrate within the orthographic projection of the spaced opening on the substrate, and the support pillar being spaced apart from the first undercut structure; and

[0031] A light-emitting functional layer is formed on the side of the partition layer away from the substrate. A portion of the light-emitting functional layer is located within the pixel opening and in contact with the first electrode. The light-emitting functional layer includes a first light-emitting functional sub-layer, a charge-generating layer located on the side of the first light-emitting functional sub-layer away from the substrate, and a second light-emitting functional sub-layer located on the side of the charge-generating layer away from the substrate. The charge-generating layer is broken at the first undercut structure. At least a portion of the charge-generating layer is located on the side of the support pillar away from the substrate, and at least another portion of the charge-generating layer is located between the support pillar and the adjacent first undercut structure. Attached Figure Description

[0032] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0033] Figure 1 A schematic cross-sectional view of a display substrate in the related art is shown.

[0034] Figure 2 A schematic cross-sectional view of a display substrate according to some embodiments of the present disclosure is shown.

[0035] Figure 3 A schematic cross-sectional view of a display substrate according to some embodiments of the present disclosure is shown.

[0036] Figures 4-7 A schematic plan view of a display substrate according to some embodiments of the present disclosure is shown. Wherein, Figure 4 A plan view of the first electrode layer is shown. Figure 5 The diagram illustrates the combination of the first electrode layer and the partition layer. Figure 6 This diagram illustrates a combination of the first electrode layer, the partition layer, and the support column layer. Figure 7 This illustrates another plan view of the combination of the first electrode layer, the partition layer, and the support column layer.

[0037] Figure 8 A flowchart illustrating a method for fabricating a display substrate according to some embodiments of the present disclosure is shown schematically.

[0038] Figures 9A-9H The diagram schematically illustrates the fabrication process of a display substrate fabrication method according to some embodiments of the present disclosure.

[0039] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0040] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0041] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0042] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements present. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0043] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0044] Figure 1 A schematic cross-sectional view of a display substrate in the related art is shown.

[0045] Reference Figure 1The display substrate includes a first electrode 311', a pixel defining layer PDL' located on the first electrode 311', a support pillar PS' located on the side of the pixel defining layer PDL' away from the first electrode 311', and a light-emitting functional layer 320' located on the side of the support pillar PS' away from the first electrode 311'. The light-emitting functional layer 320' includes a first light-emitting functional sub-layer 321', a second light-emitting functional sub-layer 322', and a charge-generating layer CGL' located between the first light-emitting functional sub-layer 321' and the second light-emitting functional sub-layer 322'. The charge-generating layer CGL' is formed by evaporation using an open mask. The charge-generating layers CGL' of each sub-pixel are connected to form a full-surface film. Due to the relatively high conductivity of the charge-generating layer CGL', the lateral leakage current in the charge-generating layer CGL' can cause crosstalk problems between adjacent sub-pixels, thereby affecting the display effect.

[0046] Figure 2 A schematic cross-sectional view of a display substrate according to some embodiments of the present disclosure is shown.

[0047] Reference Figure 2 The display substrate includes a substrate 100, a driving circuit layer 200 located on the substrate 100, and a light-emitting device layer 300 located on the side of the driving circuit layer 200 away from the substrate 100. The driving circuit layer 200 includes a plurality of pixel driving circuits arranged at intervals, and the light-emitting device layer 300 includes a plurality of light-emitting devices 300A arranged at intervals, and the plurality of light-emitting devices 300A are electrically connected to the plurality of pixel driving circuits respectively.

[0048] The light-emitting device layer 300 includes a first electrode layer 310, a light-emitting functional layer 320 located on the side of the first electrode layer 310 away from the substrate 100, and a second electrode layer 330 located on the side of the light-emitting functional layer 320 away from the substrate 100. The first electrode layer 310 includes a plurality of first electrodes 311 spaced apart and located in the display area. A partition layer 400 is also provided between the first electrode layer 310 and the light-emitting functional layer 320. The partition layer 400 includes a plurality of pixel openings KK located in the display area, and the plurality of pixel openings KK expose the plurality of first electrodes 311 respectively. The light-emitting functional layer 320 contacts the plurality of first electrodes 311 through the plurality of pixel openings KK respectively. Each light-emitting device 300A includes a first electrode 311 and a portion of the light-emitting functional layer 320 and the second electrode layer 330 located above the first electrode 311.

[0049] The light-emitting functional layer 320 includes a first light-emitting functional sublayer 321, a charge-generating layer CGL located on the side of the first light-emitting functional sublayer 321 away from the substrate 100, and a second light-emitting functional sublayer 322 located on the side of the charge-generating layer CGL away from the substrate 100. For example, the first light-emitting functional sublayer 321 may include a first hole transport layer located on the first electrode layer 310, a first light-emitting layer located on the side of the first hole transport layer away from the substrate 100, and a first electron transport layer located on the side of the first light-emitting layer away from the substrate 100; the second light-emitting functional sublayer 322 may include a second hole transport layer located on the side of the charge-generating layer CGL away from the substrate 100, a second light-emitting layer located on the side of the second hole transport layer away from the substrate 100, and a second electron transport layer located on the side of the second light-emitting layer away from the substrate 100.

[0050] The isolation layer 400 includes at least one spacing opening 401 located between two adjacent pixel openings KK. The side of the isolation layer 400 facing the spacing opening 401 has a first undercut structure UC1, and at least a portion of the charge generation layer CGL is disconnected at the first undercut structure UC1. By providing the first undercut structure UC1 between the pixel openings KK, a portion of the charge generation layer CGL can be effectively isolated, thereby effectively avoiding crosstalk between adjacent light-emitting devices 300A caused by lateral leakage current in the charge generation layer CGL. In addition, since this isolation layer can also serve as a pixel demarcation layer of the display substrate, no additional film layer is required, meaning that providing this isolation layer 400 does not increase the manufacturing cost of the display substrate.

[0051] It should be noted that, in this paper, the undercut structure should be understood as a structure in which the edge of the surface away from the substrate 100 is more convex than the edge of the surface closer to the substrate 100.

[0052] Reference Figure 2 The display substrate also includes a support pillar layer 500, which includes at least one support pillar PS. The support pillar PS is located on the side of the driving circuit layer 200 away from the substrate 100. At least a portion of the support pillar PS has its orthographic projection on the substrate 100 within the orthographic projection of the spacer opening 401 on the substrate 100. The support pillar PS is spaced apart from the first undercut structure UC1. At least a portion of the charge generation layer CGL is located on the side of the support pillar PS away from the substrate 100, and at least another portion of the charge generation layer CGL is located between the support pillar PS and the adjacent first undercut structure UC1.

[0053] The support pillar PS is a structure that supports the mask during the vapor deposition of the light-emitting functional layer 320. The surface of the support pillar PS away from the substrate 100 is further away from the substrate 100 than the surface of the partition layer 400 away from the substrate 100. At the same time, at least a portion of the support pillar PS is disposed within the spacer opening 401. The surface of the support pillar PS near the substrate 100 can contact the film layer (e.g., the planarization layer PLN) located on the side of the partition layer 400 near the substrate 100, so that the support pillar PS has a higher height. The support pillar PS with a higher height located between adjacent pixel openings KK can extend the path of the lateral leakage current in the charge generation layer CGL between adjacent light-emitting devices, thereby helping to further avoid the problem of crosstalk between adjacent light-emitting devices caused by the lateral leakage current in the charge generation layer CGL.

[0054] Furthermore, the support pillar PS is obtained by patterning using only a regular mask, compared to using a halftone mask to form both the pixel boundary layer and the support pillar PS (i.e., Figure 1 The technology shown in the diagram can effectively reduce mask costs.

[0055] It should be noted that the first light-emitting layer in the first light-emitting functional sublayer 321 and the second light-emitting layer in the second light-emitting functional sublayer 322 are both films formed by vapor deposition using a fine mask, and are essentially not deposited at the first undercut structure UC1. In the light-emitting functional layer 320, other films besides the light-emitting layers (including the first and second light-emitting layers) and the charge generation layer CGL can be separated by the first undercut structure UC1 or continuous at the first undercut structure UC1. Figure 2 The diagram schematically illustrates the structure in which the first light-emitting functional sublayer 321 is separated by the first undercut structure UC1 and the second light-emitting functional sublayer 322 is continuous at the first undercut structure UC1.

[0056] In addition, it is necessary to adjust the size of the first undercut structure UC1 and the vapor deposition process parameters of the second electrode layer 330 so that the second electrode layer 330 is continuous at the first undercut structure UC1.

[0057] According to some exemplary embodiments, refer to Figure 2 The partition layer 400 includes a first sublayer 410 and a second sublayer 420 located near the substrate 100. The end of the first sublayer 410 facing the spacer opening 401 protrudes more than the end of the second sublayer 420 facing the spacer opening 401 to form a first undercut structure UC1.

[0058] According to some exemplary embodiments, refer to Figure 2Both the first sub-layer 410 and the second sub-layer 420 comprise inorganic insulating materials, and the materials of the first sub-layer 410 and the second sub-layer 420 are different. Therefore, when etching the barrier layer 400, by selecting appropriate etching gas etching process parameters, the etching amount of the second sub-layer 420 can be greater than that of the first sub-layer 410, resulting in the edge of the second sub-layer 420 being more recessed than that of the first sub-layer 410. Furthermore, the barrier layer 400, composed of inorganic materials, is thinner, which can improve the mura problem caused by the difficulty in leveling the organic encapsulation layer. This allows for a reduction in the thickness of the encapsulation layer located on the light-emitting device layer 300, facilitating the thinning of the display substrate and improving its bending performance.

[0059] According to some exemplary embodiments, the inorganic insulating material may include silicon oxide, silicon nitride, and silicon oxynitride. For example, the material of the first sublayer 410 includes one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second sublayer 420 includes another of silicon oxide, silicon nitride, and silicon oxynitride. Alternatively, both the materials of the first sublayer 410 and the second sublayer 420 may include silicon oxynitride, but the ratio of nitrogen to oxygen content may be different.

[0060] According to some exemplary embodiments, refer to Figure 2 The partition layer 400 has a second undercut structure UC2 on the side facing the pixel opening KK, and at least a portion of the charge generation layer CGL is disconnected at the second undercut structure UC2. One end of the first sub-layer 410 facing the pixel opening KK protrudes beyond the end of the second sub-layer 420 facing the pixel opening KK to form the second undercut structure UC2. The second undercut structure UC2 and the first undercut structure UC1 can be formed in the same patterning process. By providing the second undercut structure UC2 on the side of the partition layer 400 facing the pixel opening KK, it is beneficial to further avoid crosstalk between adjacent light-emitting devices caused by lateral leakage current in the charge generation layer CGL.

[0061] According to some exemplary embodiments, refer to Figure 2 The partition layer 400 includes a third sublayer 430 located on the side of the second sublayer 420 close to the substrate 100. The end of the third sublayer 430 facing the spacing opening 401 protrudes more than the end of the second sublayer 420 facing the spacing opening 401. The end of the third sublayer 430 facing the pixel opening KK protrudes more than the end of the second sublayer 420 facing the pixel opening KK.

[0062] In order to make the edge of the second sublayer 420 more recessed than the edge of the first sublayer 410, the etching power is relatively high when etching the second sublayer 420. In order to avoid damage to the surface of the first electrode 311 in the lower layer when etching the second sublayer 420, a third sublayer 430 is added between the second sublayer 420 and the first electrode 311 to protect the first electrode 311 when etching the second sublayer 420. In addition, by setting the etching power of the third sublayer 430 to be lower, damage to the surface of the first electrode 311 can be effectively avoided.

[0063] According to some exemplary embodiments, refer to Figure 2 The third sublayer 430 comprises an inorganic insulating material, and the materials of the third sublayer 430 and the second sublayer 420 are different. For example, the material of the third sublayer 430 may be the same as the material of the first sublayer 410.

[0064] Figure 3 A schematic cross-sectional view of a display substrate according to some embodiments of the present disclosure is shown.

[0065] According to some exemplary embodiments, refer to Figure 3 The display substrate also includes a planarization layer PLN located between the driving circuit layer 200 and the first electrode layer 310. The planarization layer PLN includes a via V0, through which the first electrode 311 is electrically connected to the driving circuit layer 200. The planarization layer PLN has a groove G, which is at least partially recessed into the planarization layer PLN in a direction close to the substrate 100. The orthographic projection of the groove G on the substrate 100 at least partially overlaps with the orthographic projection of the spacer opening 401 on the substrate 100. The support post PS is in direct contact with the bottom of the groove G near the surface of the substrate 100.

[0066] The groove G includes a first sidewall G1 facing the spacer opening 401, and the end of the third sublayer 430 facing the spacer opening 401 protrudes towards the spacer opening 401 relative to the first sidewall G1. That is, the third sublayer 430 and the planarization layer PLN form a third undercut structure UC3 at the spacer opening 401. The third undercut structure UC3 is located on the side of the first undercut structure UC1 closer to the substrate 100, and the stacked first undercut structure UC1 and third undercut structure UC3 can achieve a better separation effect.

[0067] It should be noted that the planarization layer PLN is made of organic resin, which is different from the material of the third sublayer 430. The groove G can be etched by changing the etching gas after the third sublayer 430 is etched, and the planarization layer PLN can be etched again. By setting the etching process parameters, the resulting groove G can be made smaller than that of the third sublayer 430.

[0068] Figures 4-7 A schematic plan view of a display substrate according to some embodiments of the present disclosure is shown. Wherein, Figure 4 A plan view of the first electrode layer is shown. Figure 5 The diagram illustrates the combination of the first electrode layer and the partition layer. Figure 6 This diagram illustrates a combination of the first electrode layer, the partition layer, and the support column layer. Figure 7 This illustrates another plan view of the combination of the first electrode layer, the partition layer, and the support column layer.

[0069] According to some exemplary embodiments, in conjunction with reference to Figure 2 , Figure 5 and Figure 6 The shape of the orthographic projection of the spacing opening 401 on the substrate includes an elongated shape, at least a portion of which extends along the edge of the orthographic projection of the adjacent plurality of pixel openings KK on the substrate. At least four adjacent spacing openings 401 can be interconnected to form a cross shape. The orthographic projection of the support post PS on the substrate includes a circle and is located at the intersection of the cross shape.

[0070] According to some exemplary embodiments, in conjunction with reference to Figure 2 , Figure 5 and Figure 7 The support pillar PS has an elongated shape as its orthographic projection onto the substrate, and the support pillar PS extends along the edge of at least one adjacent pixel opening KK. Setting the support pillar PS to an elongated shape helps to further extend the path of lateral leakage current in the charge generation layer CGL between adjacent light-emitting devices, thereby helping to further avoid crosstalk problems between adjacent light-emitting devices caused by lateral leakage current in the charge generation layer CGL.

[0071] It should be noted that, Figure 7 The illustration shows an arrangement of elongated support pillars PS, but the display substrate of this embodiment is not limited to this. The elongated support pillars PS can be arranged reasonably in combination with the support effect of the support pillars PS on the mask. For example, the elongated support pillars PS can be set only between the pixel openings KK with small spacing.

[0072] exist Figure 7 In the schematic plan view, the orthographic projection of a portion of the support pillar PS onto the substrate overlaps with the orthographic projection of the partition layer 400 onto the substrate, while the orthographic projection of the other portion of the support pillar PS onto the substrate does not overlap with the orthographic projection of the partition layer 400 onto the substrate. (Refer to reference...) Figure 2That is, one part of the support column PS is directly set on the planarization layer PLN, and the other part of the support column PS is directly set on the partition layer 400. Of course, depending on the actual needs, the support column PS can also be set only on the planarization layer PLN, that is, the support column PS can be set only in the interval opening 401 of the partition layer 400.

[0073] According to some exemplary embodiments, in conjunction with reference to Figure 2 and Figure 7 In the direction perpendicular to the extension direction of the support column PS, the distance D between the orthographic projection of the support column PS on the substrate and the orthographic projection of the adjacent first undercut structure UC1 on the substrate is 2μm-3μm.

[0074] According to some exemplary embodiments, in conjunction with reference to Figure 4 and Figure 5 The first electrode 311 includes a first electrode body portion 311A ​​and a first electrode connection portion 311B connected as an integral structure. The pixel opening KK exposes at least a portion of the first electrode body portion 311A. The orthographic projection of the spacing opening 401 on the substrate is spaced apart from the orthographic projection of the first electrode connection portion 311B on the substrate. That is, the spacing opening 401 needs to be positioned to avoid the first electrode connection portion 311B, so that the partition layer 400 covers the portion of the first electrode layer 310 outside the pixel opening KK area, preventing the first electrode 311 from contacting other structures in the upper layer and causing display defects.

[0075] It should be noted that the shape of the first electrode body 311A ​​is relatively regular, such as a rectangle, rounded rectangle, hexagon, circle, ellipse, etc. The first electrode connecting part 311B is a structure connected to the outside of the first electrode body 311A ​​and used for electrical connection with the lower driving circuit layer. The size of the first electrode connecting part 311B along the first direction X and / or the second direction Y is smaller than that of the first electrode body 311A. The boundary line between the first electrode connecting part 311B and the first electrode body 311A ​​should be considered as the position where the shape and size change abruptly.

[0076] According to some exemplary embodiments, in conjunction with reference to Figure 4 and Figure 5 At least two adjacent gap openings 401 are connected.

[0077] According to some exemplary embodiments, in conjunction with reference to Figure 4 and Figure 5 At least two adjacent spaced openings 401 are spaced apart, and the two adjacent orthographic projections on the substrate are respectively located on both sides of the orthographic projection of at least one first electrode connection portion 311B on the substrate.

[0078] According to some exemplary embodiments, in conjunction with reference to Figure 4 and Figure 5 The plurality of first electrodes 311 include a plurality of first sub-electrodes 311R, a plurality of second sub-electrodes 311G, and a plurality of third sub-electrodes 311B. The first sub-electrodes 311R can serve as the anode of the first light-emitting device, which emits red light; the second sub-electrodes 311G can serve as the anode of the second light-emitting device, which emits green light; and the third sub-electrodes 311B can serve as the anode of the third light-emitting device, which emits blue light.

[0079] Multiple second sub-electrodes 311G are arranged along the second direction Y to form a first electrode column L1. Multiple first sub-electrodes 311R and multiple third sub-electrodes 311B are alternately arranged along the second direction Y to form a second electrode column L2. Multiple first electrode columns L1 and multiple second electrode columns L2 are alternately arranged along the first direction X. In adjacent first electrode columns L1 and second electrode columns L2, a second sub-electrode 311G is located between adjacent first sub-electrodes 311R and third sub-electrodes 311B.

[0080] In the first sub-electrode 311R and the third sub-electrode 311B adjacent along the second direction Y, and the two second sub-electrodes 311G arranged along the second direction Y that are adjacent to the first sub-electrode 311R and the third sub-electrode 311B, the four spaced openings 401 between the four first electrodes 311 can be interconnected to form a cross shape.

[0081] Figure 8 A flowchart illustrating a method for fabricating a display substrate according to some embodiments of the present disclosure is shown schematically.

[0082] At least some embodiments of this disclosure also provide a method for preparing a display substrate, with reference to... Figure 8 The preparation method includes the following steps S10-S50.

[0083] In step S10, a driving circuit layer is formed on the substrate.

[0084] In step S20, a first electrode layer is formed on the side of the driving circuit layer away from the substrate. The first electrode layer includes a first electrode, which is electrically connected to the driving circuit layer.

[0085] In step S30, a partition layer is formed on the side of the first electrode layer away from the substrate. The partition layer includes a pixel opening that exposes at least a portion of the first electrode. The partition layer also includes at least one spacer opening located between two adjacent pixel openings. The side of the partition layer facing the spacer opening has a first undercut structure.

[0086] In step S40, a support pillar is formed on the side of the driving circuit layer away from the substrate. At least a portion of the support pillar has its orthographic projection on the substrate located within the orthographic projection of the spaced opening on the substrate, and the support pillar is spaced apart from the first undercut structure.

[0087] In step S50, a light-emitting functional layer is formed on the side of the partition layer away from the substrate. A portion of the light-emitting functional layer is located within the pixel opening and in contact with the first electrode. The light-emitting functional layer includes a first light-emitting functional sub-layer, a charge-generating layer located on the side of the first light-emitting functional sub-layer away from the substrate, and a second light-emitting functional sub-layer located on the side of the charge-generating layer away from the substrate. The charge-generating layer is broken at the first undercut structure. At least a portion of the charge-generating layer is located on the side of the support pillar away from the substrate, and at least another portion of the charge-generating layer is located between the support pillar and the adjacent first undercut structure.

[0088] Figures 9A-9H The diagram schematically illustrates the fabrication process of a display substrate fabrication method according to some embodiments of the present disclosure.

[0089] Reference Figure 9A A driving circuit layer 200 is formed on a substrate 100. A planarization layer PLN is formed on the side of the driving circuit layer 200 away from the substrate 100, and the planarization layer PLN includes a via V0. A first electrode layer 310 is formed on the side of the planarization layer PLN away from the substrate 100. The first electrode layer 310 includes a first electrode 311, and the first electrode 311 is electrically connected to the driving circuit layer 200 through the via V0 in the planarization layer PLN. A pixel defining film 400' is formed on the side of the first electrode layer 310 away from the substrate 100. The pixel defining film 400' includes a third sub-film 430', a second sub-film 420' located on the side of the third sub-film 430' away from the substrate 100, and a first sub-film 410' located on the side of the second sub-film 420' away from the substrate 100. A photoresist layer PR is formed on the side of the pixel defining film 400' away from the substrate 100.

[0090] Combined with reference Figure 9A and Figure 9B Under the cover of the photoresist layer PR, the first sub-film 410' is dry etched to obtain the first sub-layer 410.

[0091] Combined with reference Figure 9B and Figure 9C Under the obstruction of the photoresist layer PR, the second sub-film 420' is dry etched. The gas used to etch the second sub-film 420' is different from the gas used to etch the first sub-film, resulting in the second sub-layer 420. The edge of the second sub-layer 420 is recessed compared to the edge of the first sub-layer 410.

[0092] Reference Figure 9D Under the obstruction of the photoresist layer PR, the third sub-film 430' is dry etched. The gas used to etch the third sub-film 430' is different from the gas used to etch the second sub-film, and the etching power of the third sub-film 430' is less than that of the second sub-film, thus obtaining the third sub-layer 430. The edge of the third sub-layer 430 protrudes compared to the edge of the second sub-layer 420.

[0093] The resulting stacked first sublayer 410, second sublayer 420, and third sublayer 430 constitute a partition layer 400. The partition layer 400 includes pixel openings KK and spacing openings 401. Pixel openings KK expose at least a portion of the first electrode 311, and spacing openings 401 are located between adjacent pixel openings KK. The end of the first sublayer 410 facing the spacing opening 401 protrudes more than the end of the second sublayer 420 facing the spacing opening 401 to form a first undercut structure UC1. The end of the first sublayer 410 facing the pixel opening KK protrudes more than the end of the second sublayer 420 facing the pixel opening KK to form a second undercut structure UC2.

[0094] Combined with reference Figure 9D and Figure 9E Under the cover of the photoresist layer PR, the portion of the planarization layer PLN exposed by the spacer opening 401 is dry etched to form a groove G within the planarization layer PLN, and then the photoresist layer PR is removed. The groove G is at least partially recessed into the planarization layer PLN in a direction close to the substrate 100. The orthographic projection of the groove G on the substrate 100 at least partially overlaps with the orthographic projection of the spacer opening 401 on the substrate 100. The groove G includes a first sidewall G1 facing the spacer opening 401, and the end of the third sublayer 430 facing the spacer opening 401 protrudes towards the spacer opening 401 relative to the first sidewall G1. That is, the third sublayer 430 and the planarization layer PLN form a third undercut structure UC3 at the location facing the spacer opening 401.

[0095] Reference Figure 9F A support pillar PS is formed on the side of the planarization layer PLN away from the substrate 100. At least a portion of the support pillar PS has its orthographic projection on the substrate 100 located within the orthographic projection of the spacer opening 401 on the substrate 100, and is spaced apart from the adjacent partition layer 400.

[0096] Reference Figure 9GA light-emitting functional layer 320 is formed on the side of the partition layer 400 and the support pillar PS away from the substrate 100. The light-emitting functional layer 320 includes a first light-emitting functional sublayer 321, a charge-generating layer CGL located on the side of the first light-emitting functional sublayer 321 away from the substrate 100, and a second light-emitting functional sublayer 322 located on the side of the charge-generating layer CGL away from the substrate 100. A portion of the charge-generating layer CGL is broken at a first undercut structure UC1, and / or a second undercut structure UC2, and / or a third undercut structure UC3. At least a portion of the charge-generating layer CGL is located between the support pillar PS and the adjacent partition layer 400, and at least another portion of the charge-generating layer CGL is located on the side of the support pillar PS away from the substrate 100.

[0097] Reference Figure 9H A second electrode layer 330 is formed on the side of the light-emitting functional layer 320 away from the substrate 100, thus obtaining a display substrate.

[0098] At least some embodiments of this disclosure also provide a display device comprising the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0099] It should be understood that the display device according to some exemplary embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be referred to in the above description of the display substrate and will not be repeated here.

[0100] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0101] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; a driving circuit layer on the substrate substrate; a first electrode layer on a side of the driving circuit layer away from the substrate substrate, the first electrode layer comprising a first electrode, the first electrode being electrically connected with the driving circuit layer; a partition layer on a side of the first electrode layer away from the substrate substrate, the partition layer comprising a pixel opening, the pixel opening exposing at least a part of the first electrode; and a light-emitting functional layer on a side of the partition layer away from the substrate substrate, a part of the light-emitting functional layer being located in the pixel opening and being in contact with the first electrode, wherein the partition layer comprises at least one spacing opening between two adjacent pixel openings, a side of the partition layer facing the spacing opening having a first undercut structure; the light-emitting functional layer comprises a first light-emitting functional sub-layer, a charge generation layer on a side of the first light-emitting functional sub-layer away from the substrate substrate, and a second light-emitting functional sub-layer on a side of the charge generation layer away from the substrate substrate, at least a part of the charge generation layer being broken at the first undercut structure; and the display substrate further comprises at least one support column on a side of the driving circuit layer away from the substrate substrate, at least a part of a projection of the support column on the substrate substrate being located in a projection of the spacing opening on the substrate substrate, and the support column is spaced apart from the first undercut structure, at least a part of the charge generation layer being located on a side of the support column away from the substrate substrate, and at least another part of the charge generation layer being located between the support column and the adjacent first undercut structure. 2.The display substrate of claim 1, wherein, The partition layer comprises a first sub-layer and a second sub-layer on a side of the first sub-layer close to the substrate substrate, an end of the first sub-layer facing the spacing opening being protruded compared to an end of the second sub-layer facing the spacing opening. 3.The display substrate of claim 2, wherein, The partition layer comprises a third sub-layer on a side of the second sub-layer close to the substrate substrate, an end of the third sub-layer facing the spacing opening being protruded compared to an end of the second sub-layer facing the spacing opening. 4.The display substrate of claim 3, wherein, The display substrate further comprises a planarization layer between the driving circuit layer and the first electrode layer, the planarization layer comprising a via, the first electrode being electrically connected with the driving circuit layer through the via; and The planarization layer has a groove recessed at least partially into the planarization layer in a direction close to the substrate substrate, a projection of the groove on the substrate substrate at least partially overlapping with a projection of the spacing opening on the substrate substrate, the groove comprising a first sidewall facing the spacing opening, an end of the third sub-layer facing the spacing opening being protruded compared to the first sidewall towards the side of the spacing opening. 5.The display substrate according to any one of claims 1-4, wherein, The shape of the projection of the support column on the substrate substrate comprises a long strip shape. 6.The display substrate of claim 5, wherein, At least a part of the long strip shape is arranged along an edge of a projection of at least one adjacent pixel opening on the substrate substrate. 7.The display substrate of claim 5, wherein, A projection of the support column on the substrate substrate in a direction perpendicular to an extending direction of the support column is spaced apart from a projection of the adjacent first undercut structure on the substrate substrate by 2-3 μm. 8.The display substrate according to any one of claims 1-4, 6-7, wherein, The partition layer has a second undercut structure on a side facing the pixel opening, and at least a portion of the charge generation layer is disconnected at the second undercut structure. 9.The display substrate of any one of claims 1-4, 6-7, wherein, The first electrode includes a first electrode main portion and a first electrode connecting portion connected as an integral structure, the pixel opening exposes at least a portion of the first electrode main portion, and a projection of the spacer opening on the substrate substrate is spaced apart from a projection of the first electrode connecting portion on the substrate substrate. 10.The display substrate of claim 9, wherein, At least two adjacent spacer openings are connected; and / or, At least two adjacent spacer openings are spaced apart, and projections of two adjacent spacer openings on the substrate substrate are respectively located on two sides of a projection of at least one first electrode connecting portion on the substrate substrate. 11.The display substrate according to claim 3 or 4, wherein The first sub-layer, the second sub-layer, and the third sub-layer each include an inorganic insulating material, and a material of the first sub-layer and a material of the second sub-layer are different, and a material of the second sub-layer and a material of the third sub-layer are different.

12. A display device, wherein, The display device includes the display substrate according to any one of claims 1-11.

13. A method for manufacturing a display substrate, wherein The preparation method includes: forming a driving circuit layer on a substrate substrate; forming a first electrode layer on a side of the driving circuit layer away from the substrate substrate, the first electrode layer including a first electrode, the first electrode being electrically connected with the driving circuit layer; forming a partition layer on a side of the first electrode layer away from the substrate substrate, the partition layer including a pixel opening, the pixel opening exposing at least a portion of the first electrode, the partition layer including at least one spacer opening between two adjacent pixel openings, and a side of the partition layer facing the spacer opening having a first undercut structure; forming a support column on a side of the driving circuit layer away from the substrate substrate, at least a portion of a projection of the support column on the substrate substrate being located within a projection of the spacer opening on the substrate substrate, and the support column being spaced apart from the first undercut structure; and forming a light-emitting functional layer on a side of the partition layer away from the substrate substrate, a portion of the light-emitting functional layer being located within the pixel opening and being in contact with the first electrode, the light-emitting functional layer including a first light-emitting functional sub-layer, a charge generation layer on a side of the first light-emitting functional sub-layer away from the substrate substrate, and a second light-emitting functional sub-layer on a side of the charge generation layer away from the substrate substrate, the charge generation layer being disconnected at the first undercut structure, at least a portion of the charge generation layer being located on a side of the support column away from the substrate substrate, and at least another portion of the charge generation layer being located between the support column and the adjacent first undercut structure.

Images