Resistive memory structure and manufacturing method thereof
By adjusting the oxygen concentration, the oxygen atom ratio in the lower electrode changes gradiently, the problem of many steps in the traditional resistive memory lower electrode production process is solved, and a single deposition process and efficient conductive wire formation are achieved.
Patent Information
- Application Number
- CN202311610826.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-14
- Filing Date
- 2023-11-28
- Publication Date
- 2025-05-16
AI Technical Summary
There are many steps to make electrodes under traditional resistive memory, resulting in a long process time.
By adjusting the oxygen concentration, the oxygen atom ratio in the lower electrode changes in gradients, thereby reducing process steps. The specific method is to combine the input oxygen and titanium to form titanium oxide during the deposition process, and the flow of oxygen changes with the increase of deposition time until the ratio of oxygen atoms to titanium atoms in the titanium oxide is equal to 2.
The single deposition process of the lower electrode is realized, which reduces the process steps, improves the process efficiency, and assists in the formation of the variable resistance layer conductive wire.
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Figure CN120018771A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a resistive memory structure and a manufacturing method thereof, and particularly to a structure in which the oxygen atom ratio in the lower electrode varies in a gradient manner (gradient variation) and a manufacturing method thereof. Background Art
[0002] Resistive Random Access Memory (RRAM) is a type of non-volatile memory that offers the following advantages: small memory cell size, ultra-high speed operation, low power operation, high durability, and CMOS compatibility.
[0003] The main operating principle of the resistive memory is to use the fact that the resistance value of a metal oxide changes with the applied bias voltage to generate different resistance values for storing data, and how to distinguish the internally stored values is determined by the level of the internal resistance value.
[0004] However, conventionally, when fabricating the lower electrode of a resistive memory, multiple deposition process steps are required, which results in a longer process time. Summary of the Invention
[0005] In view of this, the present invention adjusts the input oxygen concentration to make the oxygen atom ratio in the lower electrode vary in a gradient manner, thereby reducing the process steps.
[0006] According to a preferred embodiment of the present invention, a resistive memory structure includes a resistive memory, which includes a lower electrode, a variable resistance layer, and an upper electrode stacked from bottom to top. The lower electrode is composed of titanium oxide (TiO x ), where 0 < x ≤ 2, and x shows an increased gradient variation in the direction towards the upper electrode.
[0007] According to another preferred embodiment of the present invention, a manufacturing method of a resistive memory structure includes forming a resistive memory, which includes a lower electrode, a variable resistance layer, and an upper electrode stacked from bottom to top. The lower electrode is composed of titanium oxide (TiO x ), where 0 < x ≤ 2, and x shows an increased gradient variation in the direction towards the upper electrode.
[0008] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and in conjunction with the accompanying drawings, a detailed description is as follows. However, the following specific preferred embodiments and the accompanying drawings are only for reference and illustration, and are not used to limit the present invention. Brief Description of the Drawings
[0009] Figures 1 to 5A method for manufacturing a resistive memory structure is shown in accordance with a preferred embodiment of the present invention.
[0010] Figures 6 to 8 FIG. 4 is a graph showing the change of oxygen atomic ratio according to a preferred embodiment of the present invention.
[0011] Fig. 9 A resistive memory is shown according to an exemplary embodiment of the present invention.
[0012] Fig.10 FIG. 4 is a graph showing the change of oxygen atomic ratio according to an example of the present invention.
[0013]
Explanation of symbols
[0014] 10: First dielectric layer
[0015] 12: Conductive thread
[0016] 14: Etch stop layer
[0017] 16: Second dielectric layer
[0018] 18:Contact hole
[0019] 20: Titanium plug
[0020] 20a: Titanium metal layer
[0021] 22: Lower electrode
[0022] 22a: Lower electrode material layer
[0023] 22b: Lower surface
[0024] 22t: Upper surface
[0025] 24: Variable resistance layer
[0026] 24a: variable resistance material layer
[0027] 26: Upper electrode
[0028] 26a: Upper electrode material layer
[0029] 28: Mask layer
[0030] 28a: Mask layer
[0031] 100: Resistive Memory
[0032] 122: Lower electrode
[0033] 122b: Lower surface
[0034] 122i: Material layer
[0035] 122j: Material layer
[0036] 122k: Material layer
[0037] 122t: Upper surface
[0038] 124: variable resistance layer
[0039] 126: Upper electrode
[0040] 200: Resistive Memory
[0041] 300: Resistive memory structure DETAILED DESCRIPTION
[0042] Figures 1 to 5 A method for manufacturing a resistive memory structure is shown in accordance with a preferred embodiment of the present invention.
[0043] like Figure 1 As shown, a first dielectric layer 10 is first provided, in which at least one conductive line 12 is arranged. Figure 1 Taking two conductive lines 12 as an example, an etch stop layer 14 is formed to cover the first dielectric layer 10, and then a second dielectric layer 16 is formed to cover the etch stop layer 14, and then a patterned mask (not shown) is formed to cover the second dielectric layer 16, and then the second dielectric layer 16 and the etch stop layer 14 are etched using the patterned mask as a mask to form a contact hole 18 penetrating the second dielectric layer 16 and the etch stop layer 14. At this time, the conductive line 12 is exposed by the contact hole 18.
[0044] like Figure 2 As shown, a titanium metal layer 20a is formed to fill the contact hole 18 and cover the upper surface of the second dielectric layer 16. The titanium metal layer 20a can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition, and then the titanium metal layer 20a is planarized. The planarization method can be performed by chemical mechanical polishing.
[0045] like Figure 3 As shown, a lower electrode material layer 22a is formed to cover the titanium metal layer 20a. The lower electrode material layer 22a is made of titanium oxide (TiO x) It consists of [description of components], where x is the ratio of oxygen atoms to titanium atoms in titanium oxide. According to a preferred embodiment of the present invention, 0 < x ≤ 2, and x changes with an increased gradient variation in the direction away from the titanium metal layer 20a. The increased gradient variation is continuous and the variation unit of the increased gradient variation is a non-integer. The lower electrode material layer 22a is formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. During the deposition process, titanium is used as a target and bombarded by an inert gas, and oxygen is introduced to combine with titanium to form titanium oxide. The flow rate of oxygen increases with the deposition operation time, that is, the flow rate of the input oxygen changes with an increased gradient variation as the operation time increases until the ratio of oxygen atoms to titanium atoms in titanium oxide equals 2, that is, when x equals 2, the deposition stops. In this way, the lower electrode material layer 22a can be formed. Additionally, during the deposition process, oxygen is continuously introduced and the bombardment of the inert gas does not stop. Therefore, the lower electrode material layer 22a is completed with only one deposition process.
[0046] As Figure 4 shown, a variable resistance material layer 24a, an upper electrode material layer 26a, and a mask layer 28a are sequentially formed to cover the lower electrode material layer 22a. The variable resistance material layer 24a is preferably tantalum oxide or hafnium oxide, and the upper electrode material layer 26a is preferably titanium nitride or tantalum nitride. The mask layer 28a is preferably silicon oxide or silicon oxynitride.
[0047] As Figure 5 shown, the mask layer 28a is patterned to form the mask layer 28. Then, using the patterned mask layer 28 as a mask, the upper electrode material layer 26a, the variable resistance material layer 24a, the lower electrode material layer 22a, and the titanium metal layer 20a are etched to form a resistive memory 100 and a titanium plug 20 located below it. After etching, the upper electrode material layer 26a becomes the upper electrode 26, the variable resistance material layer 24a becomes the variable resistance layer 24, the lower electrode material layer 22a becomes the lower electrode 22, and the titanium metal layer 20a becomes the titanium plug 20. The lower electrode 22, the variable resistance layer 24, and the upper electrode 26 together constitute the resistive memory 100 of the present invention.至此本发明电阻式存储器100业已完成。如上文所述因为下电极材料层22a只用一个沉积制程工艺就完成,因此下电极22为一体成型。
[0048] As Figure 5 shown, a resistive memory structure 300 includes a resistive memory 100. The resistive memory 100 includes a lower electrode 22, a variable resistance layer 24, and an upper electrode 26 stacked from bottom to top. The lower electrode 22 is made of titanium oxide (TiO xIt consists of 0 < x ≤ 2, and x changes in an ascending gradient in the direction of the upper electrode 26. In other words, in the lower electrode 22, the value of x at each position along the direction of the upper electrode 26 is different. x is the ratio of oxygen atoms to titanium atoms in titanium oxide. The lower electrode 22 has a lower surface 22b and an upper surface 22t. The lower surface 22b contacts the titanium plug 20, and the upper surface 22t contacts the variable resistance layer 24. According to a preferred embodiment of the present invention, the lower electrode 22 is formed by stacking more than 100 layers of titanium oxide, and the value of x in each layer of titanium oxide is different.
[0049] Figures 6 to 8 What is shown is the change value of x between the lower surface 22b and the upper surface 22t of the lower electrode 22. As Figure 6 shown, 0 < x ≤ 2, and the gradient change of x from the lower surface 22b to the upper surface 22t is linear, ascending, and continuous, that is, there is no abrupt change in x. As Figure 7 shown, 0 < x ≤ 2, and the gradient change of x from the lower surface 22b to the upper surface 22t is curvilinear, ascending, and continuous. The curve is concave up, and similarly, there is no abrupt change in x. As Figure 8 shown, 0 < x ≤ 2, and the gradient change of x from the lower surface 22b to the upper surface 22t is curvilinear, ascending, and continuous. The curve is concave down, and there is no abrupt change in x.
[0050] In addition, the composition of the lower electrode 22 is nonhomogeneous in the direction of the upper electrode 26, and the change unit of the ascending gradient change is non-integer, that is, the change unit of x is non-integer. For example, the gradient change of x in the direction of the upper electrode 26 can be 0.1, 0.2, 0.3, until x equals 2. In this example, the change unit is 0.1.
[0051] Please refer to again Figure 5A second dielectric layer 16 is disposed below the resistive memory 100, a titanium plug 20 is buried in the second dielectric layer 16, and the titanium plug 20 is T-shaped, the vertical portion of the T-shaped portion fills the contact hole 18, and the horizontal portion of the T-shaped portion is located outside the contact hole 18, on the second dielectric layer 16, and directly contacts the second dielectric layer 16. The horizontal portion of the titanium plug 20 directly contacts the lower electrode 22. An etching stop layer 14 and a first dielectric layer 10 are located below the second dielectric layer 16. A conductive line 12 is embedded in the first dielectric layer 10. The conductive layer 12 contacts the titanium plug 20. Furthermore, a switching element (not shown) may be disposed below the first dielectric layer 10, such as a transistor. The transistor may be electrically connected to the lower electrode 22 of the resistive memory 100 through the conductive line 12. The upper electrode 26 of the resistive memory 100 may be externally connected to another conductive line (not shown). When a bias voltage is applied to the lower electrode 22 and the upper electrode 26, a conductive filament may be formed in the variable resistance layer 24, and part of the conductive filament may extend into the lower electrode 22. In this way, the step of forming a conductive channel may be completed.
[0052] According to a preferred embodiment of the present invention, the variable resistance layer 24 comprises tantalum oxide or hafnium oxide, the upper electrode 26 comprises titanium nitride or tantalum nitride, the etching stop layer 14 is preferably nitrogen-doped silicon carbide (NDC), and the first dielectric layer 10 and the second dielectric layer 16 are preferably silicon oxide or silicon oxynitride.
[0053] like Fig. 9 As shown, in a conventional resistive memory 200, the lower electrode 122 is composed of three material layers 122i, 122j, and 122k. The lower electrode has an upper surface 122t and a lower surface 122b. The upper surface 122t contacts the variable resistance layer 124, and the lower surface 122b can contact a conductive plug (not shown). An upper electrode 126 is disposed on the variable resistance layer 124. There are interfaces, such as interface a and interface b, between the three material layers 122i, 122j, and 122k. The deposition process of each of the three material layers 122i, 122j, and 122k is closed and then restarted after the input gas is turned off. In terms of structure, each of the three material layers 122i, 122j, and 122k is homogenous in the direction toward the upper electrode. For example, from the lower surface 122b of the lower electrode 122 toward the interface a, the composition of the material layer 122i itself is fixed, that is, homogenous. From the interface a toward the interface b, the composition of the material layer 122j itself is fixed and homogenous. The same is true for the material layer 122k. The number of material layers in the lower electrode 122 of the conventional resistive memory 200 is relatively small, usually consisting of less than 3 material layers. Fig.10As shown, the material of the lower electrode is metal oxide (MO n ), n>0, M is a metal atom, and the change of n from the lower surface 122b to the upper surface 122t is a step-like increase, that is, the n value of the lower electrode 122 at certain positions is fixed.
[0054] It can be seen that compared with the conventional resistive memory 200 , the resistive memory 100 of the present invention has fewer steps for manufacturing the lower electrode 22 , and because the oxygen atomic ratio of the lower electrode 22 changes in a gradient, it is easier to form the conductive filaments of the variable resistance layer 24 .
[0055] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A resistive memory structure, comprising: A resistive memory, the resistive memory comprising: The lower electrode, the variable resistance layer and the upper electrode are stacked from bottom to top, wherein the lower electrode is composed of titanium oxide, and x changes in an ascending gradient in the direction toward the upper electrode. 2 . The resistive memory structure as claimed in claim 1 , wherein a unit of the rising gradient change is a non-integer. 3 . The resistive memory structure as claimed in claim 1 , wherein the rising gradient changes continuously. 4 . The resistive memory structure as claimed in claim 1 , wherein the rising gradient changes in a linear or curved manner. 5 . The resistive memory structure of claim 1 , wherein the composition of the lower electrode is non-homogeneous in a direction toward the upper electrode.
6. The resistive memory structure of claim 1, further comprising: A dielectric layer is disposed below the resistive memory; and The titanium plug is buried in the dielectric layer, wherein the titanium plug contacts the bottom electrode.
7. The resistive memory structure as claimed in claim 6, wherein the bottom electrode is bulk-formed. 8 . The resistive memory structure as claimed in claim 6 , wherein the titanium plug directly contacts the dielectric layer. 9 . The resistive memory structure as claimed in claim 6 , wherein the titanium plug is T-shaped. 10 . The resistive memory structure of claim 1 , wherein the variable resistance layer comprises tantalum oxide or hafnium oxide.
11. The resistive memory structure of claim 1, wherein 0 <x≤2。 12. A method for manufacturing a resistive memory structure, comprising: A resistive memory is formed, the resistive memory comprising: The lower electrode, the variable resistance layer and the upper electrode are stacked from bottom to top, wherein the lower electrode is composed of titanium oxide, and x changes in an ascending gradient in the direction toward the upper electrode. 13 . The method for manufacturing a resistive memory structure as claimed in claim 12 , wherein a unit of the rising gradient change is a non-integer. 14 . The method for manufacturing a resistive memory structure as claimed in claim 12 , wherein the rising gradient changes continuously. 15 . The method for manufacturing a resistive memory structure as claimed in claim 12 , wherein the rising gradient changes in a linear or curved manner. 16 . The method for manufacturing a resistive memory structure as claimed in claim 12 , wherein the composition of the lower electrode is inhomogeneous in a direction toward the upper electrode.
17. The method for manufacturing a resistive memory structure according to claim 12, further comprising: A dielectric layer is disposed below the resistive memory; and The titanium plug is buried in the dielectric layer, wherein the titanium plug contacts the bottom electrode.
18. The method for manufacturing a resistive memory structure as claimed in claim 17, wherein the bottom electrode is bulk-formed. 19 . The method for manufacturing a resistive memory structure as claimed in claim 17 , wherein the titanium plug directly contacts the dielectric layer. 20 . The method for manufacturing a resistive memory structure as claimed in claim 17 , wherein the titanium plug is T-shaped. 21 . The method for manufacturing a resistive memory structure as claimed in claim 12 , wherein the variable resistance layer comprises tantalum oxide or hafnium oxide.
22. The method for manufacturing a resistive memory structure according to claim 12, wherein <x≤2。