Semiconductor device

Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes: a first element layer including a bit line driving circuit; a second element layer including a first switching circuit, a first memory cell, and a first wiring disposed between the first switching circuit and the first memory cell; and a third element layer including a second switching circuit, a second memory cell, and a second wiring disposed between the second switching circuit and the second memory cell. The first switching circuit has a function of bringing the first wiring and the third wiring into a non-conductive state during a data writing operation or a data reading operation of the second memory cell. The second switching circuit has a function of bringing the second wiring and the third wiring into a non-conductive state during a data writing operation state or a data reading operation state of the first memory cell.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and the like.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a manufacturing method. One embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, methods for driving these devices or methods for manufacturing these devices can be cited. Background Art

[0003] In recent years, research and development on the structure of three-dimensionally stacked multiple grains (e.g., silicon grains) having circuits with different functions, such as SRAM (Static Random Access Memory) cells or DRAM (Dynamic Random Access Memory) cells, has been very active (e.g., Non-Patent Documents 1 and 2).

[0004] In addition, in recent years, by using a transistor using an oxide semiconductor for a channel formation region (hereinafter, an OS transistor), a semiconductor device capable of holding a charge according to data has been technically developed. A layer including an OS transistor can be provided in a manner stacked on a crystal grain including a transistor using silicon for a channel formation region (hereinafter, a Si transistor). Patent document 1 discloses a structure in which a layer including a plurality of OS transistors is provided in a manner stacked three-dimensionally on a crystal grain including a Si transistor.

[0005] [Prior technical literature]

[0006] [Patent Document]

[0007] [Patent Document 1] International Patent Application Publication No. 2020 / 152522

[0008] [Non-patent literature]

[0009] [Non-patent document 1] W. Gomes et al., ISSCC Dig. Tech. Papers, pp. 42-43, 2022.

[0010] [Non-patent document 2] M. Park et al., ISSCC Dig. Tech. Papers, pp. 444-445, 2022. Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] The structure in which an element layer including multiple OS transistors is provided on an element layer including Si transistors is effective for achieving high integration of circuits, such as improving storage density. However, in a structure in which high integration is achieved by increasing the number of stacked element layers including OS transistors, the wiring used to electrically connect the circuit in the upper element layer with the circuit in the lower element layer becomes longer. For example, the wiring between the bit line driver circuit provided in the element layer including Si transistors and the memory cell provided in the upper element layer including OS transistors may become longer. As a result, the parasitic capacitance and parasitic resistance of the wiring used for writing or reading data between the bit line driver circuit and the memory cell increase, which may cause a decrease in operating speed or damage to data reliability.

[0013] One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure that is superior in terms of low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure with improved operating speed. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure with high data reliability.

[0014] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purposes do not prevent the existence of other purposes. In addition, other purposes are purposes that are not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or drawings, etc. Note that one embodiment of the present invention achieves at least one of the above-mentioned purposes and / or other purposes.

[0015] Solutions to technical problems

[0016] One embodiment of the present invention is a semiconductor device, comprising: a first element layer including a bit line driving circuit; a second element layer including a first switch circuit, a first storage unit, and a first wiring arranged between the first switch circuit and the first storage unit; and a third element layer including a second switch circuit, a second storage unit, and a second wiring arranged between the second switch circuit and the second storage unit. The second element layer is stacked on the first element layer, the third element layer is stacked on the second element layer, the second element layer and the third element layer are provided with a third wiring electrically connected to the bit line driving circuit, the bit line driving circuit is electrically connected to the first switch circuit and the second switch circuit through the third wiring, the first switch circuit has a function of making the first wiring and the third wiring non-conductive during the data writing operation or reading operation of the second storage unit, and the second switch circuit has a function of making the second wiring and the third wiring non-conductive during the data writing operation or reading operation of the first storage unit.

[0017] In the above-described one embodiment of the present invention, preferably, a transistor in which a semiconductor layer including a channel formation region is made of an oxide semiconductor is provided in the second element layer and the third element layer.

[0018] In the above-mentioned one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0019] In the above-described one embodiment of the present invention, preferably, a transistor including a semiconductor layer including a channel formation region made of silicon is provided in the first element layer.

[0020] In the above-described one embodiment of the present invention, preferably, the first switch circuit has a function of precharging a potential of the first wiring, and the second switch circuit has a function of precharging a potential of the second wiring.

[0021] In one embodiment of the present invention described above, preferably, the first element layer includes an operation circuit having the function of performing operation processing based on data read out to the bit line driving circuit, and the operation circuit is arranged in an area overlapping with an area where the first storage unit in the second element layer and the second storage unit in the third element layer are arranged.

[0022] In the above-mentioned one aspect of the present invention, preferably, the first wiring and the second wiring include portions provided in the same direction as a direction perpendicular to a surface of the substrate on which the first element layer is provided.

[0023] One embodiment of the present invention is a semiconductor device, comprising: a first element layer including a word line driving circuit and a bit line driving circuit; a second element layer including a first switching circuit, a first layer selection circuit, a first memory cell, a first wiring arranged between the first switching circuit and the first memory cell, and a second wiring arranged between the first layer selection circuit and the first memory cell; and a third element layer including a second switching circuit, a second layer selection circuit, a second memory cell, a third wiring arranged between the second switching circuit and the second memory cell, and a fourth wiring arranged between the second layer selection circuit and the second memory cell. Among them, the second element layer is stacked on the first element layer, and the third element layer is stacked on the second element layer. The second element layer and the third element layer are provided with a fifth wiring electrically connected to the bit line driving circuit and a sixth wiring electrically connected to the word line driving circuit. The bit line driving circuit is electrically connected to the first switch circuit and the second switch circuit through the fifth wiring, and the word line driving circuit is electrically connected to the first layer selection circuit and the second layer selection circuit through the sixth wiring. The first switch circuit has the function of making the first wiring and the fifth wiring in a non-conductive state during the data writing operation or reading operation of the second storage unit, and the second switch circuit has the function of making the third wiring and the fifth wiring in a non-conductive state during the data writing operation or reading operation of the first storage unit, and the first layer selection circuit and the second layer selection circuit have the function of outputting the signal output by the word line driving circuit to the second wiring or the fourth wiring.

[0024] In the above-described one embodiment of the present invention, preferably, a transistor in which a semiconductor layer including a channel formation region is made of an oxide semiconductor is provided in the second element layer and the third element layer.

[0025] In the above-mentioned one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0026] In the above-described one embodiment of the present invention, preferably, a transistor including a semiconductor layer including a channel formation region made of silicon is provided in the first element layer.

[0027] In the above-described one embodiment of the present invention, preferably, the first switch circuit has a function of precharging a potential of the first wiring, and the second switch circuit has a function of precharging a potential of the third wiring.

[0028] In one embodiment of the present invention described above, preferably, the first element layer includes an operation circuit having the function of performing operation processing based on data read out to the bit line driving circuit, and the operation circuit is arranged in an area overlapping with an area where the first storage unit in the second element layer and the second storage unit in the third element layer are arranged.

[0029] In the above-mentioned one aspect of the present invention, preferably, the first wiring and the third wiring include portions provided in the same direction as a direction perpendicular to a surface of the substrate on which the first element layer is provided.

[0030] Note that other aspects of the present invention are described in the description and drawings of the embodiment modes described below.

[0031] Effects of the Invention

[0032] One embodiment of the present invention can provide a novel semiconductor device, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that is superior in terms of low power consumption, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that has an improved operating speed, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that has high data reliability, etc.

[0033] Note that the description of these effects does not prevent the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1A and Figure 1B A diagram illustrating a structural example of a semiconductor device.

[0035] Figure 2A and Figure 2B A diagram illustrating a structural example of a semiconductor device.

[0036] Figure 3A and Figure 3B A diagram illustrating a structural example of a semiconductor device.

[0037] Figure 4 A diagram illustrating a structural example of a semiconductor device.

[0038] Figure 5A is a circuit diagram illustrating a structural example of a semiconductor device. Figure 5B and Figure 5C It is a timing chart for explaining an operation example of a semiconductor device.

[0039] Fig. 6A and Figure 6B A diagram illustrating a structural example of a semiconductor device.

[0040] Figure 7 A diagram illustrating a structural example of a semiconductor device.

[0041] Fig. 8A and Figure 8B A diagram illustrating a structural example of a semiconductor device.

[0042] Fig. 9A and Fig. 9B A diagram illustrating a structural example of a semiconductor device.

[0043] Fig.10 It is a timing chart for explaining an operation example of a semiconductor device.

[0044] Fig.11 A diagram illustrating a structural example of a semiconductor device.

[0045] Fig.12 A diagram illustrating a structural example of a semiconductor device.

[0046] Fig.13 A diagram illustrating a structural example of a semiconductor device.

[0047] Fig.14 It is a timing chart for explaining an operation example of a semiconductor device.

[0048] Fig.15A and Fig. 15B A diagram illustrating a structural example of a semiconductor device.

[0049] Fig.16 A diagram illustrating a structural example of a semiconductor device.

[0050] Fig.17 A diagram illustrating a structural example of a semiconductor device.

[0051] Fig.18A and Fig.18B A diagram illustrating a structural example of a semiconductor device.

[0052] Fig.19 A diagram illustrating a structural example of a semiconductor device.

[0053] FIG. 20A to FIG. 20C A diagram illustrating a structural example of a semiconductor device.

[0054] Fig.21 A diagram illustrating a structural example of a semiconductor device.

[0055] FIG. 22A to FIG. 22D A diagram illustrating a structural example of a semiconductor device.

[0056] Fig.23 A diagram illustrating a structural example of a semiconductor device.

[0057] Fig.24A A diagram illustrating a structural example of a semiconductor device. Fig. 24B A diagram illustrating an equivalent circuit of a semiconductor device.

[0058] Fig.25A and Fig.25B This is a diagram for explaining an example of an electronic component.

[0059] Fig.26A and Fig.26B is a diagram showing an example of an electronic device, FIG. 26C to FIG. 26E This is a diagram showing an example of a large computer.

[0060] Fig. 27 is a diagram showing an example of space equipment.

[0061] Fig.28 is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0062] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0063] In the drawings, dimensions, layer thicknesses, or regions are sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or values ​​shown in the drawings.

[0064] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also called the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0065] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor may refer to a transistor containing a metal oxide or an oxide semiconductor.

[0066] (Implementation Method 1)

[0067] In this embodiment, a configuration example, an operation example, and the like of a semiconductor device which is one embodiment of the present invention are described.

[0068] A semiconductor device according to one embodiment of the present invention has a function of a SoC (System on Chip) in which a memory cell array provided across a plurality of element layers, a driving circuit for driving the memory cell array, and the like are closely integrated.

[0069] Figure 1A and Figure 1B A schematic diagram and a block diagram illustrating a structural example of a semiconductor device according to one embodiment of the present invention.

[0070] In addition, Figure 1A , Figure 1B In the schematic diagrams and block diagrams shown in FIG. 1 and FIG. 2 , in order to explain the arrangement of the components constituting the semiconductor device, the X direction, the Y direction, and the Z direction are set. The X direction, the Y direction, and the Z direction are perpendicular or substantially perpendicular to each other.

[0071] In addition, Figure 1A , Figure 1B In the figure, in order to facilitate understanding of the configuration of each component constituting the semiconductor device 10, each component is shown separately. Each component provided in the same layer is preferably formed in the same process, but is not limited to this. For example, components formed in different processes can also be integrated using bonding technology.

[0072] Figure 1A , Figure 1B The semiconductor device 10 shown in FIG. 1 has a structure in which another element layer (element layer 40) is stacked on an element layer 50. For example, Figure 1B As shown, four element layers 40 are stacked on the element layer 50 (element layers 40 [ 1 ] to 40 [ 4 ] are shown as an example).

[0073] Note that the first element layer 40 is represented as element layer 40[1], the second element layer 40 is represented as element layer 40[2], and the third element layer 40 is represented as element layer 40[3]. In addition, the k-th element layer 40 (k is an integer greater than or equal to 2) is represented as element layer 40[k]. Note that in this embodiment, when describing matters related to the plurality of element layers 40 as a whole, or when showing matters common to each layer of the plurality of element layers 40, sometimes only "element layer 40" is mentioned. The same applies to the components to which the symbols describing the plurality of components are attached.

[0074] The device layers 40 [ 1 ] to 40 [ 4 ] include OS transistors. The device layers 40 [ 1 ] to 40 [ 4 ] including OS transistors can be stacked on a substrate such as the device layer 50 .

[0075] In the element layer 40, metal oxides used for OS transistors include, for example, indium oxide, gallium oxide, and zinc oxide. In addition, the metal oxide preferably contains two or more selected from indium, element M, and zinc. Element M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0076] In particular, as the metal oxide, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin and zinc (also referred to as ITZO) is preferably used. Alternatively, an oxide containing indium, gallium, tin and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also referred to as IAGZO) is preferably used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn) and tin (Sn) (also referred to as IGZTO) is preferably used.

[0077] In addition, the metal oxide used for the OS transistor may include two or more metal oxide layers with different compositions. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer may be appropriately used.

[0078] Alternatively, for example, a stacked-layer structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be used.

[0079] In addition, the metal oxide used for the OS transistor preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS. By using crystalline oxide semiconductors, a semiconductor device with high reliability can be provided.

[0080] Each of the element layers 40 is provided with a memory cell section 41 (memory cell sections 41 [1] to 41 [4]). Each memory cell section 41 includes a plurality of memory cells 42. The plurality of memory cell sections 41 provided in each element layer 40 constitute a memory cell array 43.

[0081] The memory cell array 43 including the memory cell 42 preferably has a NOSRAM circuit structure, for example. That is, the memory cell 42 is a memory cell having a NOSRAM circuit structure. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)". NOSRAM refers to a memory in which the memory cell is a two-transistor type (2T) or three-transistor type (3T) gain unit and the transistor is an OS transistor.

[0082] The current flowing between the source and drain of the OS transistor that can be set in the element layer 40 in the off state, that is, the off-state current is extremely small. NOSRAM can be used as a non-volatile memory by maintaining the charge corresponding to the data in the storage unit by utilizing the characteristic of extremely small off-state current. In particular, NOSRAM can be read out in a manner that does not destroy the retained data (non-destructive readout), so it is suitable for arithmetic processing that only repeatedly performs multiple data read operations. NOSRAM can increase the data capacity by stacking, so it can be used as a large-scale cache memory, main memory (main memory), and auxiliary memory (storage memory) to achieve high performance of semiconductor devices.

[0083] The element layer 40 includes wirings WBL (wirings WBL[1] to WBL[4]) for writing data to the memory cell 42 and wirings RBL (wirings RBL[1] to RBL[4]) for reading data. Figure 1B In FIG. 4 , wiring WBL[1] and wiring RBL[1] represent wiring WBL and wiring RBL provided in element layer 40[1]. Similarly, wiring WBL[2] to WBL[4] and wiring RBL[2] to RBL[4] represent wiring provided in element layers 40[2] to 40[4].

[0084] The wiring WBL is connected to the memory cell 42. The wiring WBL has a function of a bit line for writing data to the memory cell 42. The wiring RBL is connected to the memory cell 42. The wiring RBL has a function of a bit line for reading data from the memory cell 42.

[0085] The element layer 40 includes switch circuits SW (switch circuits SW[1] to SW[4]). Figure 1B, the switch circuit SW[1] represents the switch circuit SW provided in the element layer 40[1]. Similarly, the switch circuits SW[2] to SW[4] represent the switch circuits provided in the element layers 40[2] to 40[4]. The switch circuit SW has the function of switching the electrical connection between any one of the plurality of wirings WBL (wirings WBL[1] to WBL[4]) and the wiring GWBL and the electrical connection between any one of the plurality of wirings RBL (wirings RBL[1] to RBL[4]) and the wiring GRBL.

[0086] The wiring GWBL and the wiring GRBL are provided so as to extend from the element layer 50 to the plurality of element layers 40 in the direction (Z direction) in which the element layer 40 is stacked on the element layer 50. The Z direction is a direction perpendicular to the surface of the substrate on which the element layer 50 is provided. The wiring GWBL has a function of transmitting a potential corresponding to data output from the write bit line driver circuit 53 to the switch circuit SW of each layer. The wiring GRBL has a function of transmitting a potential corresponding to data read from the memory cell 42 in the element layer 40 to the wiring RBL to the read bit line driver circuit 54 via the switch circuit SW.

[0087] The switch circuit SW includes a plurality of switches for switching the electrical connection between the wiring WBL and the wiring GWBL and the electrical connection between the wiring RBL and the wiring GRBL. The plurality of switches may be formed by transistors. The transistors in the switch circuit SW are preferably OS transistors that can be provided in the element layer 40. By adopting this structure, when the OS transistors in the switch circuit SW are in the off state, the potentials of the wirings WBL and RBL can be maintained.

[0088] The element layer 50 includes elements provided on a silicon substrate or the like. The element layer 50 is provided with a Si transistor. As the Si transistor, it is particularly preferred to use silicon with high crystallinity such as single crystal silicon or polycrystalline silicon because high field effect mobility can be achieved and higher speed operation can be performed. The element layer 50 is sometimes also referred to as a substrate or a silicon substrate.

[0089] Figure 1B The component layer 50 shown includes Figure 1A The write word line driving circuit 51, the read word line driving circuit 52, the write bit line driving circuit 53 and the read bit line driving circuit 54 are shown. Figure 1B The component layer 50 shown includes Figure 1A The arithmetic circuit 55, the arithmetic control circuit 56 and the control circuit 57 are shown. Each circuit can be formed using Si transistors in the element layer 50, so that high-speed operation can be achieved.

[0090] The write word line drive circuit 51 outputs a signal for controlling data writing to the memory cell 42 provided in the element layer 40 to a wiring used as a write word line. The read word line drive circuit 52 outputs a signal for controlling data reading from the memory cell 42 provided in the element layer 40 to a wiring used as a read word line. The write word line drive circuit 51 and the read word line drive circuit 52 are sometimes collectively referred to as a word line drive circuit.

[0091] The write bit line driver circuit 53 outputs a potential (signal) corresponding to data written into the memory cell 42 provided in the element layer 40 to the wiring GWBL. The read bit line driver circuit 54 outputs data based on a potential corresponding to data read from the memory cell 42 provided in the element layer 40 to the wiring GRBL via the switch circuit SW. The write bit line driver circuit 53 and the read bit line driver circuit 54 are sometimes collectively referred to as a bit line driver circuit.

[0092] The arithmetic circuit 55 has a function of performing arithmetic processing based on data obtained from the read bit line driving circuit 54. The arithmetic control circuit 56 is a circuit for controlling the operation in the arithmetic circuit 55. The arithmetic circuit 55 includes, for example, a plurality of PEs (processing elements). For example, the PE can perform parallel processing of row and column operations in graphics processing, parallel processing of product and sum operations in neural networks, parallel processing of floating-point operations in scientific and technological calculations, etc. by performing parallel processing of product and sum operations. In this case, the storage unit 42 preferably stores weight data for the arithmetic processing. The semiconductor device 10 has a so-called SoC function that closely combines the arithmetic circuit 55 that performs parallel processing and the storage unit 42 that holds the weight data, thereby shortening the wiring between the devices for connecting the data transfer, thereby suppressing the increase in heat generation and power consumption.

[0093] The control circuit 57 has a function of a memory controller for controlling the bit line driving circuit and the word line driving circuit. The control circuit 57 may also have a function of controlling the operation control circuit 56, etc. In addition, in the semiconductor device 10, the operation circuit 55, the operation control circuit 56, and the control circuit 57 may also have other structures.

[0094] To explain the operation example of the semiconductor device 10, Figure 2A Shown in Figure 1B The case where the element layer 40 in FIG. 1 is two layers. Figure 2B Show Figure 2A A specific example of the circuit included in the switch circuits SW[1] and SW[2] in the structure.

[0095] Figure 2B The switch circuit SW[1] shown includes a switch circuit SW[1] that utilizes a signal A switch that controls the on or off state. Figure 2B The switch circuit SW[2] shown includes a switch circuit SW[2] that utilizes a signal A switch that controls the on or off state. The switch included in the switch circuit SW[1] switches the conductive (on) state or the non-conductive (off) state between the wiring GWBL and the wiring WBL[1] and between the wiring GRBL and the wiring RBL[1]. The switch included in the switch circuit SW[2] switches the conductive (on) state or the non-conductive (off) state between the wiring GWBL and the wiring WBL[2] and between the wiring GRBL and the wiring RBL[2]. When the element layer 40 has three or more layers, a switch circuit SW including a switch is also provided to switch the conductive (on) state or the non-conductive (off) state between the wiring GWBL and the wiring WBL and between the wiring GRBL and the wiring RBL.

[0096] Signal is a selection signal for selecting a layer in response to writing or reading data from the storage unit 42 in the element layer 40[1] or the element layer 40[2]. For example, when writing or reading data to the element layer 40[1]: the signal is effective, that is, the signal that turns on the switch; The signal provided to other switch circuits SW is invalid, that is, a signal that turns off the switch. In addition, when writing or reading data to the element layer 40[2]: the signal is effective, that is, the signal that turns on the switch; The signal provided to other switch circuits SW is invalid, that is, a signal to close the switch.

[0097] Figure 3A Schematically shows the opening (ON) or closing (OFF) of the switches in the switch circuits SW[1] and SW[2] when the memory cell 42 in the selection element layer 40[1] is written or read. Figure 3A As shown, by using the signal Turn on the switch in the switch circuit SW[1] and use the signal By closing the switch in the switch circuit SW[2], the memory cell 42 in the element layer 40[1] can be selected for data writing or reading. Figure 3A In FIG. 1 , the input / output of data between the memory cell 42 and the bit line driver circuit (write bit line driver circuit 53, read bit line driver circuit 54) is shown by dotted arrows between the wiring GWBL and the wiring WBL[1] and between the wiring GRBL and the wiring RBL[1].

[0098] Figure 3BSchematically shows the opening (ON) or closing (OFF) of the switches in the switch circuits SW[1] and SW[2] when the memory cell 42 in the selection element layer 40[2] is written or read. Figure 3B As shown, by using the signal Turn on the switch in the switch circuit SW[2] and use the signal By closing the switch in the switch circuit SW[1], the memory cell 42 in the element layer 40[2] can be selected for data writing or reading. Figure 3B In the figure, the input / output of data between the memory cell 42 and the bit line driver circuit (write bit line driver circuit 53, read bit line driver circuit 54) is shown by dotted arrows between the wiring GWBL and the wiring WBL[2] and between the wiring GRBL and the wiring RBL[2].

[0099] In addition, although Figure 3A and Figure 3B Although the structure in which the switch of the switch circuit SW is provided between the wiring GWBL and the wiring WBL and between the wiring GRBL and the wiring RBL is shown, other structures may be adopted. Figure 4 As shown in FIG. 1 , a structure in which a switch between the wiring GWBL and the wiring WBL is omitted may be employed.

[0100] In a semiconductor device of one embodiment of the present invention, in a structure for writing or reading data to a memory cell arranged across multiple element layers, a structure is adopted in which a switch circuit is provided between wiring connected to a bit line driving circuit and wiring connected to a memory cell in each element layer. By adopting this structure, wiring connected to a memory cell in an element layer where data is not written or read to the memory cell and wiring connected to a memory cell in an element layer where data is written or read to the memory cell can be electrically insulated. Therefore, by adopting a stacked memory cell including an OS transistor, not only low power consumption, high density, and large storage capacity can be achieved, but also the wiring load of wiring used as a signal line can be reduced, thereby achieving high speed of data reading and writing and improving data reliability.

[0101] Figure 5A 4 is a circuit diagram of a NOSRAM that can be used for the storage unit 42. In addition, Figure 5B and Figure 5C Yes Description Figure 5A The timing diagram of the operation of NOSRAM is shown.

[0102] Figure 5A Shown can be used Figure 1B An example of a circuit structure of a memory cell of a NOSRAM including a memory cell in the embodiment of the present invention. Figure 5AThe memory cell 42 shown includes transistors M1 to M3 and a capacitor C. The transistors M1 to M3 can be OS transistors. Figure 5A 2 shows wiring WWL, wiring RWL, wiring WBL, wiring RBL, and wiring SL connected to the elements in the memory cell 42. The wiring SL can be used as a wiring for transmitting a potential supplied to the back gate of each transistor in addition to being used as a capacitor line.

[0103] Reference Figure 5B An operation example of the storage unit 42 will be described. Figure 5B 1 is a timing diagram showing an example of the operation of the memory cell 42. In the write operation (Write), the read operation (Read) and the standby state (Standby), VDD is input to each wiring as an "H" potential, and VSS is input to each wiring as an "L" potential. Note that although the figure shows that the potentials of VDD and VSS in each wiring are the same, VDD and VSS in each wiring may be different.

[0104] In the write operation, the wiring WWL selected by the write word line driving circuit 51 is set to "H", and the wiring RWL selected by the read word line driving circuit 52 is set to "L". The potential corresponding to the data is input to the wiring WBL selected by the write bit line driving circuit 53 and the switch circuit SW. The wiring RBL selected by the read bit line driving circuit 54 and the switch circuit SW is set to "L". The gate potential of the transistor M2 of the selected memory cell 42 is VDD when data "1" is written, and is VSS when data "0" is written.

[0105] exist Figure 5B In the read operation, the wiring RBL selected by the read bit line driving circuit 54 and the switch circuit SW is pre-discharged (sometimes simply recorded as discharged) to VSS. Next, the wiring RWL selected by the read word line driving circuit 52 is set to "H". When the selected memory cell 42 holds the data "1", VDD is input to the gate of the transistor M2, and by making the wiring SL VDD, a large current flows between the source and drain of the transistor M2. Therefore, the wiring RBL is quickly charged and the potential of the wiring RBL rises. When the selected memory cell 42 holds the data "0", VSS is input to the gate of the transistor M2, and almost no drain current flows through the transistor M2. Therefore, the wiring RBL maintains the discharge voltage (VSS).

[0106] Furthermore, in the read operation, wiring RBL selected by read bit line driver circuit 54 may be precharged to VDD. Figure 5C This situation is shown.

[0107] exist Figure 5CIn the read operation, the wiring RBL selected by the read bit line driver circuit 54 is precharged to VDD. Next, the wiring RWL selected by the read word line driver circuit 52 is set to "H". When the selected memory cell 42 holds data "1", VDD is input to the gate of the transistor M2, and by making the wiring SL VSS, a large current flows between the source and drain of the transistor M2. Therefore, the wiring RBL is discharged quickly, and the potential of the wiring RBL drops. When the selected memory cell 42 holds data "0", VSS is input to the gate of the transistor M2, so almost no drain current flows through the transistor M2. Therefore, the wiring RBL maintains the precharge voltage (VDD).

[0108] In the standby state, during the period other than the write operation and the read operation, the wiring WWL and the wiring RBL are "L". The transistors M1 and M3 of the memory cell 42 are in the off state. Since the transistors M1 to M3 are OS transistors with extremely small off-state currents, the memory cell 42 can retain data for a long time by turning off the transistors M1 and M3. In principle, the memory cell 42 has no limit on the number of write operations (rewrites), can rewrite data with low energy, and does not consume power when retaining data. Therefore, the semiconductor device 10 can have a non-volatile, low-power memory cell.

[0109] The circuit structure of the storage unit 42 is not limited to Figure 5A For example, it is also possible to Fig. 6A As shown in the memory cell 42A in FIG. 1 , the transistors M1 to M3 have a back gate structure. Figure 6B The memory cell 42B in FIG. 1 is shown in FIG. 1 , in which the transistor M3 is omitted. Alternatively, a structure in which the capacitor element C is omitted by utilizing parasitic capacitance or gate capacitance may be adopted.

[0110] Figure 7 It indicates the use of Figure 2A and Figure 2B FIG. 4 is a diagram showing the structure of wirings WWL and RWL connected to memory cells 42 of each element layer in the case of two element layers 40 shown. Figure 7 It is shown that three memory cells 42 are provided in each of the memory cell sections 41 [ 1 ] and 41 [ 2 ] in each element layer 40 . Figure 7 Wiring WWL[1]-[6] used as write word lines and wiring RWL[1]-[6] used as read word lines for controlling each memory cell 42 of the memory cell units 41[1] and 41[2] are shown.

[0111] Figure 7 Show Figure 5A The circuit diagram of the NOSRAM memory cell in FIG. The memory cell 42 in the memory cell section 41[1] is connected to the common wirings WBL[1] and RBL[1]. In addition, Figure 7 The three memory cells 42 in the memory cell section 41[1] are connected to different wirings WWL[1]-[3] and RWL[1]-[3]. Figure 7 In the example, the memory cell 42 in the memory cell section 41[2] is connected to the common wirings WBL[2] and RBL[2]. Figure 7 The three memory cells 42 in the memory cell section 41 [ 2 ] shown are connected to different wirings WWL [ 4 ] - [ 6 ] and RWL [ 4 ] - [ 6 ] .

[0112] Figure 7 The switches in the switch circuits SW[1] and SW[2] are shown as transistors. The transistors in the switch circuit SW[1] are represented by transistors RS_1 and WS_1. The on / off state is controlled, thereby controlling the conduction state or non-conduction state between the wiring GWBL and the wiring WBL[1], and between the wiring GRBL and the wiring RBL[1]. In addition, the transistors in the switch circuit SW[2] are represented by transistors RS_2 and WS_2. Using the signal By controlling the on or off state, the conductive state or non-conductive state between the wiring GWBL and the wiring WBL[2], and between the wiring GRBL and the wiring RBL[2] is controlled.

[0113] Each transistor in the switch circuits SW[1] and SW[2] can be an OS transistor, similar to the transistor in the memory cell 42. When the OS transistor is an n-channel type, it has the following switching function: it is turned on when the potential supplied to the gate is at an H level, and it is turned off when it is at an L level. In addition, as described above, the off-state current of the OS transistor is small, so by turning off the transistor, the potential of the wirings WBL and RBL can be maintained.

[0114] Fig. 8A Yes Figure 1A The structure described above is supplemented with schematic diagrams of layer selection circuits LSW[1] to LSW[4]. By providing the layer selection circuit LSW, the semiconductor device 10 can provide signals from the write word line driver circuit 51 and the read word line driver circuit 52 to the wirings WWL[1]-[6] and the wirings RWL[1]-[6] based on the signal for selecting an arbitrary element layer 40.

[0115] Figure 8B is a diagram showing the use of layer selection circuits LSW[1] and LSW[2] for Figure 7The structure is composed of wiring WWL[1]-[6], wiring RWL[1]-[6], wiring GWWL, and wiring GRWL connected to layer selection circuits LSW[1] and LSW[2]. Wiring GWWL has the function of transmitting the signal of the write word line driving circuit 51 to the layer selection circuit LSW of each element layer 40. Wiring GRWL has the function of transmitting the signal of the read word line driving circuit 52 to the layer selection circuit LSW of each element layer 40.

[0116] The layer selection circuit LSW receives inputs of a signal from the write word line driver circuit 51 supplied via the wiring GWWL, a signal from the read word line driver circuit 52 supplied via the wiring GRWL, and a signal for selecting any one of the element layers 40 (signal The write word line driver circuit 51 and the read word line driver circuit 52 are connected to the upper element layer 40 by a plurality of wirings, and the plurality of wirings are connected to the upper element layer 40. The write word line driver circuit 51 and the read word line driver circuit 52 are connected to the upper element layer 40 by a plurality of wirings, and the plurality of wirings are connected to the upper element layer 40. Therefore, as the number of element layers 40 increases, the write word line driver circuit 51 and the read word line driver circuit 52 are connected to the upper element layer 40 by a plurality of wirings.

[0117] Fig. 9A is a circuit diagram illustrating an example of a circuit configuration that can be used for the layer selection circuit LSW. Fig. 9A The layer selection circuit LSW shown is supplied with constant potential (VDD, VSS), signal Signal ( The inverted signal from the write word line driver circuit 51, the signal GWWL_S from the read word line driver circuit 52 can generate the signal WWL1 (the signal provided to the wiring WWL[1]) and the signal RWL1 (the signal provided to the wiring RWL[1]).

[0118] Fig. 9A The layer selection circuit LSW shown in the figure includes transistors M11 to M16. As with the memory cell 42, the transistors M11 to M16 can be OS transistors provided in the stacked element layer 40. Fig. 8A The layer selection circuits LSW[1] to LSW[4] can be as follows Fig. 8A The arrangement shown is overlapping in the Z direction.

[0119] Fig. 9B 1 is a circuit diagram for explaining an example of a circuit configuration of layer selection circuits LSW[1] and LSW[2] corresponding to two layers. Fig. 9BAs shown, it is possible to generate constant potential (VDD, VSS), signal Signal Signal Signal ( an inverted signal from the write word line driver circuit 51, a signal WWL1 (a signal provided to wirings WWL[1] to WWL[3]), a signal RWL1 (a signal provided to wirings RWL[1] to RWL[3]), a signal WWL2 (a signal provided to wirings WWL[4] to WWL[6]), and a signal RWL2 (a signal provided to wirings RWL[4] to RWL[6]).

[0120] Layer selection circuits LSW[1] and LSW[2] include transistors M11 to M16 and transistors M21 to M26. As with the memory cell 42, the transistors M11 to M16 and M21 to M26 can be OS transistors disposed in the stacked element layers 40[1] to 40[2]. The layer selection circuits LSW[1] and LSW[2] can be disposed so as to overlap in the Z direction.

[0121] The number of stacked layers corresponding to the signals provided to the wirings WWL[1]-[6] and the wirings RWL[1]-[6] for driving the memory cells 42 provided in different element layers 40 increases. By adopting a structure in which the layer selection circuit LSW is provided, even if the number of element layers 40 increases, the signals provided to the wirings WWL and the wirings RWL can be output by simply increasing the number of signals for providing the signals for layer selection. Therefore, the semiconductor device 10 can suppress the increase in the area of ​​the word line driving circuit caused by the increase in the number of element layers 40 provided with the memory cells 42. That is, the semiconductor device 10 can increase the number of element layers 40 provided with the memory cells 42 without increasing the area cost.

[0122] Next, refer to Fig.10 The timing chart shown explains an operation example of the semiconductor device.

[0123] based on Figure 5B The writing and reading operations of the storage unit 42 are Fig.10 That is, the wiring SL is set to VDD, and the wiring RBL (corresponding to the wiring GRBL) is discharged to VSS in the read operation.

[0124] Period P1 is a period for accessing address A1 (ADDR) of storage unit 42 in element layer 40 [1]. Period P2 is a period for accessing address A2 (ADDR) of storage unit 42 in element layer 40 [2]. Periods P1 and P2 include a write operation (Write), a read operation (Read), and a standby state (Standby). During access to element layer 40 [1], the signal In the selected state (H level), the signal It is the selected state (H level).

[0125] exist Fig.10 , the node connected to the gate of the transistor M2 at the address A1 of the memory cell 42 in the element layer 40[1] is referred to as the node SN1. The node connected to the gate of the transistor M2 at the address A2 of the memory cell 42 in the element layer 40[2] is referred to as the node SN2. The nodes SN1 and SN2 are described on the premise that L level (VSS) data is written in the initial state.

[0126] In addition, Fig.10 In the example, as the signals of the wiring GWBL, the wiring GWWL, the wiring GRBL, and the wiring GRWL, the signal may be combined. and signal This signal is used as a signal to be supplied to the wiring connected to the memory cell 42 accessed in each period.

[0127] For example, in period P1, the potential of the wiring GWWL at the H level is set by the signal A signal selectively supplied to the wiring WWL[1] connected to the memory cell 42 in the element layer 40[1]. In addition, during the period P2, the potential of the wiring GWWL at the H level is set by the signal A signal selectively supplied to the wiring WWL[2] connected to the memory cell 42 in the element layer 40[2].

[0128] In addition, during the period P1, the potential of the wiring GWBL at the H level is set by the signal A signal selectively supplied to the wiring WBL[1] connected to the memory cell 42 in the element layer 40[1]. In addition, during the period P2, the potential of the wiring GWBL at the L level is set by the signal A signal selectively supplied to the wiring WBL[2] connected to the memory cell 42 in the element layer 40[2].

[0129] In the period P1, the potential of the wiring GWBL changes according to the potential of the data written to the selected memory cell 42 by the signal A signal is selectively supplied to the wiring WBL[1] connected to the memory cell 42 in the element layer 40[1]. In addition, in the period P2, the potential of the wiring GWBL changes according to the potential of the data written to the selected memory cell 42 by the signal A signal selectively supplied to the wiring WBL[2] connected to the memory cell 42 in the element layer 40[2].

[0130] In the period P1, the potential of the wiring GRBL changes according to the potential held in the selected memory cell 42 according to the signal The potential of the wiring GRBL that changes according to the potential held in the selected memory cell 42 changes according to the potential change of the RBL[1] that is selectively connected to the memory cell 42 in the element layer 40[1]. In addition, in the period P2, the potential of the wiring GRBL that changes according to the potential held in the selected memory cell 42 changes according to the potential change of the wiring GRBL through the signal The potential of RBL[2] selectively connected to the memory cell 42 in the element layer 40[2] changes.

[0131] During the period P1 of accessing the address A1 of the memory cell 42 in the element layer 40[1], the signal In the selected state (H level), data "1" is written to the designated memory cell 42 as a write operation (Write). The wiring GWBL and the wiring GWWL become H level (VDD), and the signal The wiring WBL[1] and the wiring WWL[1] in the selected element layer 40 become H level, thereby increasing the potential of the node SN1. The potential of the node SN1 slightly changes due to the influence of feedthrough or charge injection caused by the switching of the on or off state of the transistor M1 caused by the decrease in the wiring GWWL (from VDD to VSS). During and after the standby state (Standby), the potential increase of the node SN1 is maintained. In the read operation (Read), data "1" is read from the specified storage cell 42. By discharging the wiring GRBL, the signal The wiring RBL[1] in the selected element layer 40 is discharged. By setting the wiring GRWL to the H level, the signal The wiring RWL[1] in the selected element layer 40 changes to the H level. As a result, the wiring RBL[1] is charged and connected to the selected element layer 40 by the signal The wiring GRBL connected to the wiring RBL[1] in the selected element layer 40 is also charged. Thereafter, during the standby state (Standby), the potential of the node SN1 is maintained.

[0132] During the period P2 of accessing the address A2 of the memory cell 42 in the element layer 40[2], the signal In the selected state (H level), data "0" is written to the designated memory cell 42 as a write operation (Write). The wiring GWBL changes to L level, and the signal The wiring WBL[2] in the selected element layer 40 becomes L level. The wiring GWWL becomes H level (VDD), and the signal The wiring WWL[2] in the selected element layer 40 changes to the H level. The potential of the node SN2 changes slightly due to the influence of feedthrough or charge injection caused by the rise (from VSS to VDD) and fall of the wiring GWWL, but the potential does not change before and after the write operation (Write). The potential of the node SN2 is maintained during and after the standby state (Standby). In the read operation (Read), data "0" is read from the specified storage cell 42. By discharging the wiring GRBL, the signal The wiring RBL[2] in the selected element layer 40 is discharged. By setting the wiring GRWL to the H level, the signal The wiring RWL[2] in the selected element layer 40 changes to the H level. As a result, the wiring RBL[2] remains at the L level, and the signal The wiring GRBL connected to the wiring RBL[2] in the selected element layer 40 also maintains the L level. Thereafter, during the standby state (Standby), the potential of the node SN2 is maintained.

[0133] then, Fig.11 Modification examples of the switch circuit SW will be described. Fig.11 The structure shown is Figure 7 The switch circuit SW[1] shown in the figure is added with a transistor PS_1 connected to the wiring RBL[1], and the switch circuit SW[2] is added with a transistor PS_2 connected to the wiring RBL[2]. The transistor PS_1 has a function of providing a potential VDD to the wiring RBL[1] in response to the control of the precharge signal PRE. The transistor PS_2 has a function of providing a potential VDD to the wiring RBL[2] in response to the control of the precharge signal PRE. By adopting this structure, a structure in which the switch in the switch circuit SW is precharged when it is closed can be realized, thereby reducing the parasitic capacitance of the precharged wiring, thereby shortening the precharge period. In addition, when the precharge voltage is VSS, discharge can also be performed.

[0134] Fig.12 Shown with Fig.11 A different modification of the switch circuit SW in which an AND gate is added. The AND gate AND_1 is supplied with a signal for selecting the element layer 40[1]. Similarly, AND gate AND_2 is supplied with a signal for selecting element layer 40[2]. and a precharge signal PRE. Thus, a structure can be realized in which the switch in the switch circuit SW of the selected element layer 40 is turned on and the switch in the switch circuit SW of the unselected element layer 40 is turned off to perform precharging. Thus, the wiring RBL to be precharged can be separated from the wiring RBL not to be precharged, thereby reducing the parasitic capacitance of the wiring to be precharged. As a result, the precharge period can be shortened.

[0135] When as Fig.12 The AND gates AND_1 and AND_2 shown use Fig.13 When the OS transistor is constructed as shown, it can be provided in the element layer 40 . Fig.13 The AND gate shown is composed of transistors M41 to M45 which are n-channel type OS transistors. Fig.13 The AND gate shown obtains an output signal Y corresponding to the input signals A and B. When the input signals A and B are both at the H level, the output signal can also be at the H level, so the transistors M41 to M45 can be used as AND gates.

[0136] Next, refer to Fig.14 The timing diagram shown is for use Fig.12 An operation example of the semiconductor device having the structure shown will be described.

[0137] based on Figure 5C The writing and reading operations of the storage unit 42 are Fig.14 That is, the wiring SL is set to VSS, and the wiring RBL (corresponding wiring GRBL) is precharged to VDD during the read operation.

[0138] Period P1 is a period for accessing address A1 (ADDR) of storage unit 42 in element layer 40 [1]. Period P2 is a period for accessing address A2 (ADDR) of storage unit 42 in element layer 40 [2]. Periods P1 and P2 include a write operation (Write), a read operation (Read), and a standby state (Standby). During access to element layer 40 [1], the signal In the selected state (H level), the signal It is the selected state (H level).

[0139] exist Fig.14 , the node connected to the gate of the transistor M2 at the address A1 of the memory cell 42 in the element layer 40[1] is referred to as the node SN1. The node connected to the gate of the transistor M2 at the address A2 of the memory cell 42 in the element layer 40[2] is referred to as the node SN2. The nodes SN1 and SN2 are described on the premise that L level (VSS) data is written in the initial state.

[0140] In addition, Fig.14 In the example, as the signals of the wiring GWBL, the wiring GWWL, the wiring GRBL, the wiring GRWL and the precharge signal PRE, the signal can be combined. and signal This signal is used as a signal to be supplied to the wiring connected to the memory cell 42 accessed in each period.

[0141] For example, in period P1, the potential of the wiring GWWL at the H level is set by the signal The potential of the wiring WWL[1] connected to the memory cell 42 in the element layer 40[1] is selectively supplied. In addition, during the period P2, the potential of the wiring GWWL at the H level is set by the signal A potential selectively supplied to the wiring WWL[2] connected to the memory cell 42 in the element layer 40[2].

[0142] In addition, during the period P1, the potential of the wiring GWBL at the H level is set by the signal The potential of the wiring WBL[1] connected to the memory cell 42 in the element layer 40[1] is selectively supplied. In addition, during the period P2, the potential of the wiring GWBL at the L level is set by the signal A potential selectively supplied to the wiring WBL[2] connected to the memory cell 42 in the element layer 40[2].

[0143] In the period P1, the potential of the wiring GWBL changes according to the potential of the data written to the selected memory cell 42 by the signal The potential of the wiring WBL[1] connected to the memory cell 42 in the element layer 40[1] is selectively provided. In addition, in the period P2, the potential of the wiring GWBL, which changes according to the potential of the data written to the selected memory cell 42, is changed by the signal A potential selectively supplied to the wiring WBL[2] connected to the memory cell 42 in the element layer 40[2].

[0144] In the period P1, the potential of the wiring GRBL changes according to the potential held in the selected memory cell 42 according to the signal The potential of the wiring GRBL that changes according to the potential held in the selected memory cell 42 changes according to the potential change of the RBL[1] that is selectively connected to the memory cell 42 in the element layer 40[1]. In addition, in the period P2, the potential of the wiring GRBL that changes according to the potential held in the selected memory cell 42 changes according to the potential change of the wiring GRBL through the signal The potential of RBL[2] selectively connected to the memory cell 42 in the element layer 40[2] changes.

[0145] For example, during period P1, the VDD provided by the precharge signal PRE is controlled by the signal The VDD signal is selectively supplied to the wiring RBL[1] connected to the memory cell 42 in the device layer 40[1]. In addition, during the period P2, the VDD signal supplied in accordance with the control of the precharge signal PRE is transmitted through the signal The voltage is selectively supplied to the wiring RBL[2] connected to the memory cell 42 in the element layer 40[2].

[0146] During the period P1 of accessing the address A1 of the memory cell 42 in the element layer 40[1], the signal In the selected state (H level), data "1" is written to the designated memory cell 42 as a write operation (Write). The wiring GWBL and the wiring GWWL become H level (VDD), and the signal The wiring WBL[1] and the wiring WWL[1] in the selected element layer 40 become H level, thereby increasing the potential of the node SN1. The potential of the node SN1 changes slightly due to the influence of feedthrough or charge injection caused by the decrease of the wiring GWWL (from VDD to VSS). During and after the standby state, the potential increase of the node SN1 is maintained. In the read operation (Read), data "1" is read from the designated storage cell 42. By making the precharge signal PRE H level, the signal The wiring RBL[1] in the selected element layer 40 is precharged. By setting the wiring GRWL to the H level, the signal The wiring RWL[1] in the selected element layer 40 changes to the H level. As a result, the wiring RBL[1] is discharged and the wiring RWL[1] is connected to the selected element layer 40. The wiring GRBL connected to the wiring RBL[1] in the selected element layer 40 is also discharged. Thereafter, the potential of the node SN1 is maintained during the standby state.

[0147] During the period P2 of accessing the address A2 of the memory cell 42 in the element layer 40[2], the signal In the selected state (H level), data "0" is written to the designated memory cell 42 as a write operation (Write). The wiring GWBL changes to L level, and the signal The wiring WBL[2] in the selected element layer 40 becomes L level. The wiring GWWL becomes H level (VDD), and the signal The wiring WWL[2] in the selected element layer 40 changes to the H level. The potential of the node SN2 changes slightly due to the influence of feedthrough or charge injection caused by the rise (from VSS to VDD) and fall of the wiring GWWL, but the potential does not change before and after the write operation (Write). The potential of the node SN2 is maintained during and after the standby state (Standby). In the read operation (Read), data "0" is read from the specified storage cell 42. By making the precharge signal PRE to be H level, the signal The wiring RBL[2] in the selected element layer 40 is precharged. By setting the wiring GRWL to the H level, the signal The wiring RWL[2] in the selected element layer 40 changes to the H level. As a result, the wiring RBL[2] maintains the H level, and The wiring GRBL connected to the wiring RBL[2] in the selected element layer 40 also maintains the H level. Thereafter, during the standby state, the potential of the wiring GRWL is discharged by the off-state current of the Si transistor, etc., and the potential of the node SN2 is maintained.

[0148] In a semiconductor device of one embodiment of the present invention, in a structure for writing or reading data to a memory cell arranged across multiple element layers, a structure is adopted in which a switch circuit is provided between wiring connected to a bit line driving circuit and wiring connected to a memory cell in each element layer. By adopting this structure, wiring connected to a memory cell in an element layer where data is not written or read to the memory cell and wiring connected to a memory cell in an element layer where data is written or read to the memory cell can be electrically insulated. Therefore, by adopting a stacked memory cell including an OS transistor, not only low power consumption, high density, and large storage capacity can be achieved, but also the wiring load of wiring used as a signal line can be reduced, thereby achieving high speed of data reading and writing and improving data reliability.

[0149] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0150] (Implementation Method 2)

[0151] In this embodiment, a configuration example different from the configuration example of the semiconductor device according to one embodiment of the present invention described in Embodiment 1 is described.

[0152] In this embodiment, description of the same structure as that of Embodiment 1 is omitted. In this embodiment, a structure in which wiring is provided across element layer 40 and element layer 50 is described using schematic diagrams and block diagrams, and this modification can also be appropriately applied to Embodiment 1.

[0153] Fig.15A and Fig. 15B 1 is a schematic diagram and a block diagram for explaining a structural example of a semiconductor device according to one embodiment of the present invention. Figure 1A and Figure 1B same, Fig.15A and Fig. 15B The semiconductor device 10V shown includes another element layer 40 stacked on the element layer 50. For example, Fig. 15B As shown, four element layers 40 are stacked on the element layer 50 (element layers 40 [1] to 40 [4] are shown as an example). Fig.15A As shown, in the semiconductor device 10V, data is written or read from the storage cells 42 in each element layer 40 by wiring from the bit line driving circuit (write bit line driving circuit 53, read bit line driving circuit 54) to the upper element layer 40 and wiring configured from the upper element layer 40 to the lower element layer 40.

[0154] exist Fig.15A and Fig. 15B In the structure shown, the element layer 40 includes wirings WBL (wirings WBL[1] to WBL[3]) for writing data to the memory cell 42 and wirings RBL (wirings RBL[1] to RBL[3]) for reading data. Fig. 15B , as the wiring WBL and the wiring RBL connected to the memory cells 42 in the element layers 40[1] to 40[4], the wiring WBL[1] to WBL[3] and the wiring RBL[1] to RBL[3] are shown. The wiring WBL[1] to WBL[3] and the wiring RBL[1] to RBL[3] are connected to the upper element layer 40( Fig. 15B The wiring arranged in a direction perpendicular to the direction in which the element layer 40[4]) is stacked on the element layer 50 (a direction perpendicular to the Z direction) and the wiring arranged in the direction in which the element layer 40 is stacked on the element layer 50 (the Z direction) electrically connect each storage unit 42 to the wiring GWBL or the wiring GRBL.

[0155] The wiring GWBL and the wiring GRBL are provided so as to extend from the element layer 50 to the plurality of element layers 40 in the direction (Z direction) in which the element layer 40 is stacked on the element layer 50. The wiring GWBL has a function of transmitting a potential corresponding to data outputted from the write bit line driving circuit 53 to the upper element layer 40 ( Fig. 15B The wiring GRBL has the function of transmitting a potential corresponding to data read from the memory cell 42 in the element layer 40 to the wiring RBL of the element layer 40[4] to the read bit line driver circuit 54.

[0156] To explain a specific example of the semiconductor device 10V, Fig.16 Show Fig. 15B The case where the element layer 40 in FIG. 1 is two layers. Fig.17 It indicates the use of Fig.16 FIG. 4 is a diagram showing the structure of wirings WWL and RWL connected to memory cells 42 of each element layer in the case of two element layers 40 shown. Fig.17 It is shown that three memory cells 42 are provided in each of the memory cell sections 41 [ 1 ] and 41 [ 2 ] in each element layer 40 . Fig.17 Wiring WWL[1]-[6] used as write word lines and wiring RWL[1]-[6] used as read word lines for controlling each memory cell 42 of the memory cell units 41[1] and 41[2] are shown.

[0157] Fig.17 The embodiment 1 is shown in Figure 5A Circuit diagram of NOSRAM memory cell in FIG. The memory cell 42 in the memory cell sections 41[1] and 41[2] arranged in an overlapping manner along the Z direction is connected to the common wirings WBL[1] and RBL[1] (wirings WBL[2] and RBL[2] or wirings WBL[3] and RBL[3]). In addition, Fig.17 The three memory cells 42 in the memory cell section 41[1] are connected to different wirings WWL[1]-[3] and RWL[1]-[3]. Fig.17 The three memory cells 42 in the memory cell section 41 [ 2 ] shown are connected to different wirings WWL [ 4 ] - [ 6 ] and RWL [ 4 ] - [ 6 ] .

[0158] The wiring WBL and the wiring RBL have a portion arranged in a direction (Z direction) parallel to the arrangement direction of the wiring GWBL and the wiring GRBL. The wiring WBL and the wiring RBL can be arranged in a direction perpendicular to the plane where each element layer 40 is located by being arranged in the Z direction across multiple element layers 40. The wiring WBL and the wiring RBL can be arranged perpendicularly to other wirings (for example, wirings WWL and RWL) in the element layer 40. Therefore, by adopting a stacked arrangement of a memory cell including OS transistors, not only can low power consumption, high density, and large storage capacity be achieved, but also the wiring load of the wiring used as a signal line can be reduced, thereby achieving high speed of data reading and writing and improving data reliability.

[0159] In addition, when the influence of wiring resistance is greater than the influence of wiring capacitance as a wiring load, it is preferable to configure the wiring for transmitting signals in a ring shape (loop shape). Fig.18A The embodiment 1 is shown in a direction parallel to the Z direction. Figure 2AThe structure of the additional wiring WBL[1] and the wiring WBL[2] configured in different element layers 40 is connected and configured in a ring (loop shape) as an example. Similarly, the wiring RBL[1] and the wiring RBL[2] configured in different element layers 40 are also configured in a ring (loop shape) as an example. In addition, Fig.18A In the present invention, wiring for connecting wiring WBL[1] and wiring WBL[2] (wiring RBL[1] and wiring RBL[2]) is added. Therefore, although the switching circuit is omitted, when other wiring WBL (for example, wiring WBL[3] and wiring WBL[4]) or wiring RBL (for example, wiring RBL[3] and wiring RBL[4]) are included, it is preferable to set a switching circuit for each wiring WBL (wiring RBL) configured in a ring shape.

[0160] As other structural examples, for example, Fig.18B The embodiment described in this embodiment is shown in a direction parallel to the Z direction. Fig.16 The structure is an example of a structure in which the wiring WBL or the wiring RBL arranged in a different element layer 40 and the wiring of the memory cell 42 are additionally connected and arranged in a ring shape (loop shape).

[0161] like Fig.18A and Fig.18B As shown, by configuring the wiring for transmitting signals in a ring shape (loop shape), the wiring resistance can be reduced. As a result, the wiring load (such as wiring capacitance and wiring resistance) of the wiring used as the signal line can be reduced, thereby achieving high-speed data reading and writing and improving data reliability.

[0162] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0163] (Implementation method 3)

[0164] In this embodiment, a transistor structure applicable to the semiconductor device described in the above embodiment is described. As an example, a structure in which transistors having different electrical characteristics are stacked is described. By adopting this structure, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration of the semiconductor device can be increased.

[0165] Fig.19 A partial cross-sectional structure of a semiconductor device is shown. Fig.19 The semiconductor device shown includes a transistor 550 , a transistor 500 , and a capacitor 600 . Fig. 20A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 20B is a cross-sectional view of the transistor 500 in the channel width direction, Fig. 20C2 is a cross-sectional view in the channel width direction of the transistor 550. For example, the transistor 550 corresponds to the Si transistor described in the above embodiment, and the transistor 500 corresponds to the OS transistor.

[0166] exist Fig.19 In the embodiment, the transistor 500 is disposed above the transistor 550 , and the capacitor 600 is disposed above the transistor 550 and the transistor 500 .

[0167] The transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b functioning as a source region or a drain region.

[0168] like Fig. 20C As shown, in the transistor 550, the conductor 316 covers the top surface and the side surface in the channel width direction of the semiconductor region 313 via the insulator 315. In this way, by making the transistor 550 have a Fin-type structure, the effective channel width increases, thereby improving the on-state characteristics of the transistor 550. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 550 can be improved.

[0169] Furthermore, transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0170] The channel formation region of the semiconductor region 313 or the region near it, the low resistance region 314a and the low resistance region 314b used as the source region or the drain region preferably include semiconductors such as silicon-based semiconductors, and more preferably include single crystal silicon. In addition, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that controls the effective mass by subjecting the lattice to stress to change the interplanar spacing can be used. In addition, the transistor 550 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0171] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0172] As the conductor 316 serving as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0173] In addition, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferred in terms of heat resistance.

[0174] Alternatively, the transistor 550 may be formed using a SOI (Silicon on Insulator) substrate or the like.

[0175] In addition, as SOI substrates, there can be used: SIMOX (Separation by Implanted Oxygen) substrates formed by forming an oxide layer in a region at a certain depth from the surface and eliminating defects generated in the surface layer after oxygen ion implantation in a mirror-polished thin slice, and SOI substrates formed by the smart peeling method or ELTRAN method (registered trademark: Epitaxial Layer Transfer) in which a semiconductor substrate is split by growing tiny gaps formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.

[0176] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 550 .

[0177] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0178] Note that in this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. Note that in this specification, aluminum oxynitride refers to a material containing more oxygen than nitrogen, and aluminum nitride oxide refers to a material containing more nitrogen than oxygen.

[0179] The insulator 322 may also be used as a planarization film for planarizing a step caused by the transistor 550 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0180] As the insulator 324 , a film having a barrier property that can prevent hydrogen, impurities, and the like from diffusing from the substrate 311 , the transistor 550 , or the like into a region where the transistor 500 is provided is preferably used.

[0181] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 550. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0182] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 1×10 16 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0183] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0184] In addition, conductors 328 and 330 connected to transistor 550 are embedded in insulators 320, 322, 324, and 326. In addition, conductors 328 and 330 have the function of plugs or wiring. Note that the same symbol is sometimes used to represent a plurality of conductors having the function of plugs or wiring. In addition, in this specification, wiring and a plug connected to the wiring may also be one component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0185] As the material of each plug and wiring (conductor 328, conductor 330, etc.), a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0186] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.19In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed between the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function of a plug or wiring connected to the transistor 550. The conductor 356 can be made of the same material as the conductor 328 and the conductor 330.

[0187] In addition, similar to the insulator 324, the insulator 350 preferably uses an insulator having a barrier property to hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 350 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0188] Note that as a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is preferably used. Furthermore, by stacking tantalum nitride and tungsten having high conductivity, it is possible to maintain the conductivity as a wiring and suppress the diffusion of hydrogen from the transistor 550. At this time, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

[0189] Alternatively, a wiring layer may be provided on the insulator 354 and the conductor 356. Fig.19 In the embodiment, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function of a plug or wiring. In addition, the conductor 366 can use the same material as the conductor 328 and the conductor 330.

[0190] In addition, similar to the insulator 324, the insulator 360 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 360 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0191] Alternatively, a wiring layer may be provided on the insulator 364 and the conductor 366. Fig.19 In the embodiment, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function of a plug or wiring. In addition, the conductor 376 can use the same material as the conductor 328 and the conductor 330.

[0192] In addition, similar to the insulator 324, the insulator 370 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 370 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0193] Alternatively, a wiring layer may be provided on the insulator 374 and the conductor 376. Fig.19 In the embodiment, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 has a function of a plug or wiring. In addition, the conductor 386 can use the same material as the conductor 328 and the conductor 330.

[0194] In addition, similar to the insulator 324, the insulator 380 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 380 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, so that the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0195] In the above description, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

[0196] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As any of the insulators 510, 512, 514, and 516, a substance having a barrier property against oxygen, hydrogen, and the like is preferably used.

[0197] For example, a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided is preferably used as the insulator 510 and the insulator 514. Therefore, the insulator 510 and the insulator 514 can be made of the same material as the insulator 324.

[0198] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 550 and transistor 500.

[0199] For example, as a film having a barrier property against hydrogen, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0200] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from penetrating. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0201] For example, the insulator 512 and the insulator 516 can use the same material as the insulator 320. In addition, by using a material with a low dielectric constant for the insulator, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 and the insulator 516 can use a silicon oxide film, a silicon oxynitride film, or the like.

[0202] In addition, a conductor 518 or a conductor (for example, the conductor 503) constituting the transistor 500 is embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be made of the same material as the conductor 328 and the conductor 330.

[0203] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. With this structure, the transistor 550 can be separated from the transistor 500 by a layer having a barrier property to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 550 into the transistor 500.

[0204] The transistor 500 is provided above the insulator 516 .

[0205] like Fig. 20A and Fig. 20BAs shown, transistor 500 includes a conductor 503 configured in a manner of embedding insulators 514 and 516, an insulator 520 configured on the insulator 516 and the conductor 503, an insulator 522 configured on the insulator 520, an insulator 524 configured on the insulator 522, a metal oxide 530a configured on the insulator 524, a metal oxide 530b configured on the metal oxide 530a, a conductor 542a and a conductor 542b configured separately from each other on the metal oxide 530b, an insulator 580 configured on the conductors 542a and 542b and forming an opening in a manner overlapping between the conductors 542a and 542b, an insulator 545 configured on the bottom and side surfaces of the opening, and a conductor 560 configured on the formation surface of the insulator 545.

[0206] In addition, if Fig. 20A and Fig. 20B As shown in FIG. 5 , an insulator 544 is preferably disposed between the metal oxide 530a, the metal oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Fig. 20A and Fig. 20B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 545 and a conductor 560b disposed in a manner embedded inside the conductor 560a. Fig. 20A and Fig. 20B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 545 .

[0207] Note that in this specification and the like, the metal oxide 530 a and the metal oxide 530 b may be collectively referred to as the metal oxide 530 .

[0208] In the transistor 500, two layers of the metal oxide 530a and the metal oxide 530b are stacked in the channel forming region and its vicinity, but the present invention is not limited thereto. For example, the metal oxide 530b may have a single layer structure or a stacked structure of three or more layers.

[0209] In addition, in the transistor 500, the conductor 560 has a two-layer structure, but the present invention is not limited to this. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that Fig.19 and Fig. 20A The structure of the transistor 500 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0210] Here, the conductor 560 is used as the gate electrode of the transistor, and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode. As described above, the conductor 560 is set in a manner embedded in the opening of the insulator 580 and in the area sandwiched between the conductor 542a and the conductor 542b. The configuration of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner according to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be configured in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 500 can be reduced. Thus, miniaturization and high integration of semiconductor devices can be achieved.

[0211] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not include a region overlapping with the conductor 542a or the conductor 542b. Thus, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be increased, so that the transistor 500 can have high frequency characteristics.

[0212] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by independently changing the potential supplied to conductor 503 without linking it with the potential supplied to conductor 560. In particular, by supplying a negative potential to conductor 503, the threshold voltage of transistor 500 can be made to exceed 0V to reduce the off-state current. Therefore, compared with when no negative potential is applied to conductor 503, when a negative potential is applied to conductor 503, the drain current when the potential applied to conductor 560 is 0V can be reduced.

[0213] The conductor 503 is arranged to overlap the metal oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the metal oxide 530 can be covered.

[0214] In this specification, etc., the structure of a transistor in which the electric field of the first gate electrode electrically surrounds the channel forming region is called a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. has a structure different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can also be regarded as a kind of Fin-type structure. In this specification, etc., the Fin-type structure refers to a structure in which the gate electrode is configured in a manner of surrounding at least two or more surfaces of the channel (specifically, two surfaces, three surfaces or four surfaces, etc.). By adopting the Fin-type structure and the S-channel structure, a transistor with improved resistance to short channel effects can be realized. In other words, a transistor that is not prone to short channel effects can be realized.

[0215] By adopting a transistor having the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. In addition, the S-channel structure can also be said to be substantially equal to the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure because it electrically surrounds the channel formation region. By making the transistor have an S-channel structure, a GAA structure or a LGAA structure, the channel formation region formed at or near the interface between the metal oxide 530 and the gate insulator can be set in the entire bulk of the metal oxide 530. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor will be improved.

[0216] In addition, the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is formed inside. In addition, in the transistor 500, the conductor 503a and the conductor 503b are stacked, but the present invention is not limited to this. For example, the conductor 503 may have a single-layer structure or a stacked structure of three or more layers.

[0217] Here, as the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (not allowing the above oxygen to pass through easily). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0218] For example, by providing the conductor 503a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0219] In addition, when the conductor 503 also has a wiring function, it is preferable to use a conductive material with high conductivity whose main component is tungsten, copper or aluminum as the conductor 503b. In addition, although the conductor 503 composed of a stack of conductors 503a and 503b is shown in this embodiment, the conductor 503 may also have a single-layer structure.

[0220] The insulator 520 , the insulator 522 , and the insulator 524 serve as a second gate insulating film.

[0221] Here, the insulator 524 in contact with the metal oxide 530 preferably contains oxygen exceeding the stoichiometric composition. This oxygen is easily released from the film by heating. In this specification, etc., the oxygen released by heating is sometimes referred to as "excess oxygen". That is, it is preferred that a region containing excess oxygen (also referred to as "excess oxygen region") is formed in the insulator 524. By providing the insulator containing excess oxygen in contact with the metal oxide 530, the oxygen vacancies (V O : oxygen vacancy), thereby improving the reliability of the transistor 500. In addition, when hydrogen enters the oxygen vacancy of the metal oxide 530, the defect (hereinafter, sometimes referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, because hydrogen in oxide semiconductors is easy to move due to heat, electric field, etc., when oxide semiconductors contain a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, it is preferred to minimize the V O H and become high purity intrinsic or substantially high purity intrinsic. In this way, in order to obtain such V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxidation treatment). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and can provide stable electrical characteristics.

[0222] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0223] In addition, any one or more of heating treatment, microwave treatment, or RF treatment may be performed in such a manner that the insulator having the excess oxygen region and the metal oxide 530 are in contact with each other. By performing this treatment, water or hydrogen in the metal oxide 530 can be removed. For example, a reaction occurs in the metal oxide 530 in which VoH bonding is severed, in other words, a “V O H→Vo+H" reaction can be dehydrogenated. A part of the hydrogen generated at this time is sometimes bonded to oxygen and removed from the metal oxide 530 or the insulator near the metal oxide 530 as H2O. In addition, a part of the hydrogen is sometimes doped by the conductors 542a and 542b.

[0224] In addition, as the above-mentioned microwave treatment, for example, it is preferable to use a device including a power supply for generating high-density plasma or a device including a power supply for applying RF to one side of the substrate. For example, by using a gas containing oxygen and a high-density plasma, a high-density oxygen radical can be generated, and by applying RF to one side of the substrate, the oxygen radical generated by the high-density plasma can be efficiently introduced into the metal oxide 530 or an insulator near the metal oxide 530. In addition, in the above-mentioned microwave treatment, the pressure is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the device for performing microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0225] In addition, in the manufacturing process of the transistor 500, it is preferred to perform heat treatment in a state where the surface of the metal oxide 530 is exposed. The heat treatment can be performed, for example, at a temperature of 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thus, oxygen can be supplied to the metal oxide 530 to reduce oxygen vacancies (V O ). In addition, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen or an inert gas, and then the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more to fill the oxygen that has been separated. Alternatively, the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more, and then the heat treatment may be performed continuously in an atmosphere of nitrogen or an inert gas.

[0226] In addition, by performing an oxidation treatment on the metal oxide 530, the supplied oxygen can fill the oxygen vacancies in the metal oxide 530. In other words, the reaction of "Vo+O→null" can be promoted. Furthermore, by reacting the hydrogen remaining in the metal oxide 530 with the supplied oxygen, the hydrogen can be removed as H2O (dehydration). Thus, the hydrogen remaining in the metal oxide 530 can be suppressed from re-bonding with the oxygen vacancies to form V. O H.

[0227] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0228] When the insulator 522 has a function of suppressing diffusion of oxygen, impurities, and the like, it is preferable because oxygen included in the metal oxide 530 does not diffuse toward the insulator 520. In addition, the conductor 503 can be suppressed from reacting with oxygen included in the insulator 524 or the metal oxide 530.

[0229] As the insulator 522, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as off-state current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0230] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing the diffusion of impurities and oxygen (not allowing the above oxygen to pass easily). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 522 is formed using such a material, the insulator 522 is used as a layer that suppresses the release of oxygen from the metal oxide 530 or the entry of impurities such as hydrogen into the metal oxide 530 from the surrounding part of the transistor 500.

[0231] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. In addition, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0232] The insulator 520 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0233] In addition, Fig. 20A and Fig. 20B In the transistor 500, the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer stacked structure, but the second gate insulating film may also have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers. In this case, the stacked structure is not limited to being made of the same material, and a stacked structure made of different materials may be used.

[0234] In the transistor 500 , a metal oxide that functions as an oxide semiconductor is used as the metal oxide 530 including a channel formation region.

[0235] The metal oxide used as the oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. The metal oxide used as the oxide semiconductor will be described in detail in another embodiment.

[0236] The metal oxide used as the channel formation region in the metal oxide 530 preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0237] In the metal oxide 530 , when the metal oxide 530 a is provided below the metal oxide 530 b , diffusion of impurities from a structure formed below the metal oxide 530 a to the metal oxide 530 b can be suppressed.

[0238] In addition, the metal oxide 530 preferably has a structure of multiple oxide layers in which the atomic number ratios of each metal atom are different from each other. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used in the metal oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used in the metal oxide 530b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used in the metal oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used in the metal oxide 530b. In addition, the atomic number ratio of In in the metal oxide used in the metal oxide 530b is preferably greater than the atomic number ratio of In in the metal oxide used in the metal oxide 530a.

[0239] It is preferred that the energy of the conduction band bottom of the metal oxide 530a be higher than the energy of the conduction band bottom of the metal oxide 530b. In other words, the electron affinity of the metal oxide 530a is preferably smaller than the electron affinity of the metal oxide 530b.

[0240] Here, in the junction of the metal oxide 530a and the metal oxide 530b, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of the metal oxide 530a and the metal oxide 530b continuously changes or continuously joins. For this reason, it is preferred to reduce the defect state density of the mixed layer formed at the interface between the metal oxide 530a and the metal oxide 530b.

[0241] Specifically, by making the metal oxide 530a and the metal oxide 530b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the metal oxide 530b is an In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. as the metal oxide 530a.

[0242] At this time, the main path of the carrier is the metal oxide 530b. By making the metal oxide 530a have the above structure, the defect state density at the interface between the metal oxide 530a and the metal oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of the transistor 500 can be increased.

[0243] In addition, although the present embodiment shows an example in which the metal oxide 530 adopts a double-layer structure of a metal oxide 530a and a metal oxide 530b on the metal oxide 530a, it is not limited to this. For example, the metal oxide 530 may also adopt a three-layer structure in which metal oxide 530a, metal oxide 530b and metal oxide 530c (not shown) are formed in sequence. When the metal oxide 530c has the same composition as the metal oxide 530a, it is possible to suppress the diffusion of impurities from the structure formed above the metal oxide 530c to the metal oxide 530b. In addition, by adopting a structure in which the metal oxide 530a and the metal oxide 530c sandwich the metal oxide 530b (i.e., the so-called embedded channel structure), the channel formation region can be kept away from the insulating film interface. In addition, by adopting an embedded channel structure, the interface scattering of carriers can be reduced and a transistor with high field effect mobility can be realized.

[0244] Conductors 542a and 542b serving as a source electrode and a drain electrode are provided on the metal oxide 530b. As the conductors 542a and 542b, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the above metal elements as components, or alloys combining the above metal elements are preferably used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Metal nitride films such as tantalum nitride have barrier properties against hydrogen or oxygen, so they are more preferred.

[0245] In addition, although Fig. 20A Although the single-layer structure of the conductor 542a and the conductor 542b is shown, a stacked structure of two or more layers may be adopted. For example, it is preferable to stack a tantalum nitride film and a tungsten film. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure of stacking an aluminum film on a tungsten film, a two-layer structure of stacking a copper film on a copper-magnesium-aluminum alloy film, a two-layer structure of stacking a copper film on a titanium film, and a two-layer structure of stacking a copper film on a tungsten film may also be adopted.

[0246] In addition, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0247] In addition, if Fig. 20A As shown in FIG. 1 , a region 543a and a region 543b are sometimes formed as low resistance regions at the interface between the metal oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. In this case, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0248] The oxygen concentration of the region 543a (region 543b) may be reduced by providing the above-mentioned conductor 542a (conductor 542b) in contact with the metal oxide 530. In addition, a metal compound layer containing a component of the metal contained in the conductor 542a (conductor 542b) and the metal oxide 530 may be formed in the region 543a (region 543b). In this case, the carrier concentration of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.

[0249] The insulator 544 is provided so as to cover the conductors 542 a and 542 b to suppress oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided so as to cover the side surface of the metal oxide 530 and to be in contact with the insulator 524.

[0250] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium. Alternatively, the insulator 544 can be made of silicon nitride oxide or silicon nitride.

[0251] In particular, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing oxides of one or both of aluminum and hafnium, are preferably used. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, insulator 544 does not necessarily need to be provided when conductor 542a and conductor 542b are composed of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed. It can be appropriately designed according to the required transistor characteristics.

[0252] By including the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 into the metal oxide 530b. In addition, it is possible to suppress the oxidation of the conductors 542a and 542b by excess oxygen contained in the insulator 580.

[0253] The insulator 545 is used as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similarly to the insulator 524 described above.

[0254] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0255] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied to the channel formation region of the metal oxide 530b from the insulator 545. In addition, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 545. The thickness of the insulator 545 is preferably not less than 1 nm and not more than 20 nm.

[0256] In addition, in order to efficiently supply the excess oxygen contained in the insulator 545 to the metal oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, the excess oxygen amount supplied to the metal oxide 530 can be suppressed from decreasing. In addition, the oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0257] In addition, like the second gate insulating film, the insulator 545 may also have a stacked structure. When miniaturization and high integration of transistors are performed, sometimes the thinning of the gate insulating film leads to problems such as off-state current. Therefore, by using the insulator used as the gate insulating film to have a stacked structure of a high-k material and a material with thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a stacked structure with thermal stability and a high relative dielectric constant can be achieved.

[0258] exist Fig. 20A and Fig. 20B In the embodiment, the conductor 560 serving as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0259] As the conductor 560a, it is preferred to use a conductive material having the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, it is preferred to use a conductive material having the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by the oxidation of the conductor 560b due to the oxygen contained in the insulator 545. As a conductive material having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide, etc. are preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be applied to the metal oxide 530 can be used. In this case, by forming the conductor 560b by sputtering, the resistance value of the conductor 560a can be reduced to make it a conductor. It can be called an OC (Oxide Conductor) electrode.

[0260] As the conductor 560b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductor 560b is also used as wiring, it is preferable to use a conductor with high conductivity. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials may be used.

[0261] The insulator 580 is preferably disposed on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, silicon oxide and silicon oxide with pores are preferred because they are easy to form an excess oxygen region in the subsequent process.

[0262] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 that releases oxygen by heating, the oxygen in the insulator 580 can be efficiently supplied to the metal oxide 530. In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 580.

[0263] The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is provided so as to be embedded in the opening of the insulator 580 and in the region between the conductor 542a and the conductor 542b.

[0264] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. For this reason, when the thickness of the conductor 560 is increased, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, since the conductor 560 is provided in a manner embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 does not collapse during the process.

[0265] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be formed in the insulator 545 and the insulator 580. Thus, oxygen can be supplied to the metal oxide 530 from the excess oxygen region.

[0266] For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0267] In particular, aluminum oxide has high barrier properties and can inhibit the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can be used as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0268] Furthermore, an insulator 581 serving as an interlayer film is preferably provided over the insulator 574. As with the insulator 524 and the like, the concentration of impurities such as water and hydrogen in the insulator 581 is preferably reduced.

[0269] In addition, the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided so as to face each other via the conductor 560. The conductors 540a and 540b have the same structure as the conductors 546 and 548 described later.

[0270] An insulator 582 is provided on the insulator 581. The insulator 582 is preferably made of a material having a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be made of the same material as the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0271] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from passing through. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0272] In addition, an insulator 586 is provided on the insulator 582. As the insulator 586, the same material as the insulator 320 can be used. In addition, by using a material with a low dielectric constant as these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film or a silicon oxynitride film can be used.

[0273] In addition, the conductor 546 and the conductor 548 are embedded in the insulator 520 , the insulator 522 , the insulator 524 , the insulator 544 , the insulator 580 , the insulator 574 , the insulator 581 , the insulator 582 , and the insulator 586 .

[0274] The conductor 546 and the conductor 548 are used as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be made of the same material as the conductor 328 and the conductor 330.

[0275] In addition, after forming the transistor 500, an opening may be formed around the transistor 500, and an insulator having a high barrier to hydrogen or water may be formed to cover the opening. By wrapping the transistor 500 with the above-mentioned high barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be wrapped with an insulator having a high barrier to hydrogen or water. In addition, in the case of forming an opening around the transistor 500, for example, when an opening is formed to reach the insulator 522 or the insulator 514 and the above-mentioned high barrier insulator is formed in contact with the insulator 522 or the insulator 514, it can also serve as a part of the manufacturing process of the transistor 500, so it is preferred. In addition, as an insulator having a high barrier to hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 can be used.

[0276] The transistors that can be used in the present invention are not limited to Fig. 20A and Fig. 20B The transistor 500 shown. For example, it is also possible to use Fig.21 A transistor 500 having a structure as shown. Fig.21 The transistor 500 is shown with Fig. 20A and Fig. 20BThe transistor shown is different in that an insulator 555 is used and the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) have a stacked-layer structure.

[0277] The conductor 542a has a laminated structure of a conductor 542a1 and a conductor 542a2 on the conductor 542a1, and the conductor 542b has a laminated structure of a conductor 542b1 and a conductor 542b2 on the conductor 542b1. The conductors 542a1 and 542b1 in contact with the metal oxide 530b are preferably conductors that are not easily oxidized, such as metal nitrides. Thus, the conductors 542a and 542b can be prevented from being excessively oxidized by oxygen contained in the metal oxide 530b. In addition, the conductors 542a2 and 542b2 are preferably conductors such as metal layers having higher conductivity than the conductors 542a1 and 542b1. Thus, the conductors 542a and 542b can be used as wiring or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductors 542a and 542b serving as wiring or electrodes are provided in contact with the top surface of the metal oxide 530 serving as an active layer.

[0278] As the conductors 542a1 and 542b1, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferred.

[0279] The electrical conductivity of the conductor 542a2 and the conductor 542b2 is preferably higher than that of the conductor 542a1 and the conductor 542b1. For example, the thickness of the conductor 542a2 and the conductor 542b2 is preferably greater than that of the conductor 542a1 and the conductor 542b1. As the conductor 542a2 and the conductor 542b2, the conductor that can be used for the conductor 560b described above can be used. By adopting the above structure, the resistance of the conductor 542a2 and the conductor 542b2 can be reduced.

[0280] For example, tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.

[0281] like Fig.21As shown in FIG. 1 , when viewed from a cross section in the channel length direction of the transistor 500, the distance between the conductor 542a1 and the conductor 542b1 is smaller than the distance between the conductor 542a2 and the conductor 542b2. By adopting this structure, the distance between the source and the drain can be further shortened, and the channel length can be shortened accordingly. Therefore, the frequency characteristics of the transistor 500 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0282] The insulator 555 is preferably an insulator that is not easily oxidized, such as a nitride. The insulator 555 is formed in a manner that contacts the side surface of the conductor 542a2 and the side surface of the conductor 542b2, and has the function of protecting the conductor 542a2 and the conductor 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, it is preferably an inorganic insulator that is not easily oxidized. In addition, since the insulator 555 contacts the conductor 542a2 and the conductor 542b2, it is preferably an inorganic insulator that is not easily oxidized by the conductors 542a2 and 542b2. Therefore, the insulator 555 is preferably an insulating material that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 555.

[0283] Openings are formed in the insulator 580 and the insulator 544, and the insulator 555 is formed so as to be in contact with the side walls of the openings. The conductor 542a1 and the conductor 542b1 are separated using a mask, thereby forming Fig.21 The transistor 500 shown in FIG. 1 is a transistor 500. Here, the opening overlaps the region between the conductor 542a2 and the conductor 542b2. In addition, a portion of the conductor 542a1 and the conductor 542b1 protrude into the opening. Therefore, the insulator 555 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 in the opening. In addition, the insulator 545 is in contact with the top surface of the metal oxide 530 in the region between the conductor 542a1 and the conductor 542b1.

[0284] Preferably, after the conductor 542a1 is separated from the conductor 542b1, a heat treatment is performed in an oxygen-containing atmosphere before the insulator 545 is deposited. Thus, oxygen is supplied to the metal oxide 530a and the metal oxide 530b, thereby reducing oxygen vacancies. Furthermore, by forming the insulator 555 in contact with the side of the conductor 542a2 and the side of the conductor 542b2, the conductor 542a2 and the conductor 542b2 can be prevented from being excessively oxidized. Thus, the electrical characteristics and reliability of the transistor can be improved. In addition, the uneven electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed.

[0285] like Fig.21As shown, in the transistor 500 , the insulator 524 may be formed in an island shape. Here, the side end of the insulator 524 may be substantially aligned with the metal oxide 530 .

[0286] like Fig.21 As shown in FIG. 5 , in the transistor 500, the insulator 522 may be in contact with the insulator 516 and the conductor 503. In other words, it is also possible not to set Fig. 20A and Fig. 20B Insulator 520 is shown.

[0287] Next, a capacitor 600 is provided above the transistor 500 . The capacitor 600 includes a conductor 610 , a conductor 620 , and an insulator 630 .

[0288] Furthermore, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 is used as a plug or wiring connected to the transistor 500. The conductor 610 is used as an electrode of the capacitor 600. Alternatively, the conductor 612 and the conductor 610 may be formed at the same time.

[0289] As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements as a component (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used.

[0290] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto and they may have a stacked structure of two or more layers. For example, a conductor having high tightness to the conductor having a barrier property and the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

[0291] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Conductive materials such as metal materials, alloy materials, and metal oxide materials can be used as the conductor 620. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0292] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be made of the same material as the insulator 320. In addition, the insulator 640 can be used as a planarization film that covers the uneven shape thereunder.

[0293] By adopting this structure, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved.

[0294] As a substrate for a semiconductor device that can be used in one embodiment of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (for example, a stainless steel substrate, a substrate containing a stainless steel foil, a tungsten substrate, a substrate containing a tungsten foil, etc.), a semiconductor substrate (for example, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate or a compound semiconductor substrate), an SOI (SOI: Silicon on Insulator) substrate, etc. can be used. In addition, a heat-resistant plastic substrate that can withstand the processing temperature of this embodiment can also be used. As an example of a glass substrate, barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass or soda-lime glass can be cited. In addition, crystallized glass, etc. can also be used.

[0295] In addition, as a substrate, a flexible substrate, a laminated film, paper or a base film containing a fibrous material can be used. As a flexible substrate, a laminated film, a base film, etc., the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Or, as an example, synthetic resins such as acrylic resins can be cited. Or, as an example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Or, as an example, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, paper, etc. can be cited. In particular, by using semiconductor substrates, single crystal substrates or SOI substrates to manufacture transistors, it is possible to manufacture transistors with small deviations in characteristics, size or shape, high current capacity and small size. When the above-mentioned transistors are used to form a circuit, low power consumption of the circuit or high integration of the circuit can be achieved.

[0296] In addition, a flexible substrate may be used as a substrate, and transistors, resistors and / or capacitors may be directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistors, resistors and / or capacitors. The peeling layer may be used in a case where a part or all of a semiconductor device is manufactured on the peeling layer, and then the semiconductor device is separated from the substrate and transferred to another substrate. In this case, the transistors, resistors and / or capacitors may be transferred to a substrate with low heat resistance or a flexible substrate. In addition, as the above-mentioned peeling layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen may be used.

[0297] That is, after forming a semiconductor device on one substrate, the semiconductor device can be transferred to another substrate. As the substrate to which the semiconductor device is transferred, not only the above-mentioned substrate on which a transistor can be formed can be used, but also paper substrates, glass paper substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium, rayon, regenerated polyester)), leather substrates, rubber substrates, etc. can be used. By using such a substrate, it is possible to manufacture a flexible semiconductor device, manufacture a semiconductor device that is not easily damaged, improve heat resistance, and reduce weight or thickness.

[0298] By providing a semiconductor device on a flexible substrate, it is possible to provide a semiconductor device that is less likely to be damaged while suppressing an increase in weight.

[0299] Fig.19 The structure of transistor 550 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure, driving method, etc. For example, when the semiconductor device is a unipolar circuit (a circuit composed of transistors of the same polarity such as n-channel transistors) having only OS transistors, transistor 550 can have the same structure as transistor 500.

[0300] In addition, the transistors applicable to the present invention are not limited to Fig. 20A , Fig. 20B and Fig.21 The transistor 500 shown. For example, it is also possible to use FIG. 22A to FIG. 22D Transistor 500A of the structure shown. FIG. 22A to FIG. 22D The transistor 500A shown is a vertical channel transistor. Fig. 20A , Fig. 20B and Fig.21 The transistors shown are different.

[0301] FIG. 22A to FIG. 22D 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor. Fig.22A is a top view of transistor 500A. Fig. 22B yes Fig.22A The cross-sectional view of the portion indicated by the dot-dash line A1-A2, Fig. 22C yes Fig.22A A cross-sectional view of the portion indicated by the dot-dash line A3-A4. Fig.22D yes Fig. 22B A top view of the portion indicated by the dot-dash line B1-B2 in FIG. Fig.22A and Fig.22D In the top view, some components are omitted for clarity.

[0302] The transistor 500A includes a conductor 241 and an insulator 270 on an insulator 210 , a metal oxide 230 on the conductor 241 , an insulator 250 on the metal oxide 230 , a conductor 260 on the insulator 250 , and a conductor 242 on the insulator 270 .

[0303] The conductor 241 includes a region serving as one of the source electrode and the drain electrode of the transistor 500A, the conductor 242 includes a region serving as the other of the source electrode and the drain electrode of the transistor 500A, and the conductor 260 includes a region serving as the gate electrode of the transistor 500A. The metal oxide 230 includes a region serving as a channel formation region.

[0304] The metal oxide 230 can use the materials described above as the metal oxide 530 a and the metal oxide 530 b .

[0305] The metal oxide 230 includes a channel formation region in the transistor 500A and a source region and a drain region provided so as to sandwich the channel formation region. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with one of the conductor 241 and the conductor 242, and the drain region overlaps with the other of the conductor 241 and the conductor 242.

[0306] An opening 290 that reaches the conductor 241 is provided in the conductor 242 and the insulator 270. In addition, the opening 290 has a region overlapping with the conductor 241 when viewed from above. In addition, at least a portion of each of the metal oxide 230, the insulator 250, and the conductor 260 is arranged in the opening 290. In addition, it can be said that the opening 290 includes an opening in the conductor 242 and an opening in the insulator 270. In addition, it can also be said that the conductor 242 has an opening that overlaps with the conductor 241 when viewed from above.

[0307] The metal oxide 230 is provided in such a manner as to be in contact with the side surfaces and bottom surfaces of the opening 290 provided in the conductor 242 and the insulator 270. In other words, the metal oxide 230 includes regions that are in contact with the side surfaces of the opening 290 in the conductor 242 and the insulator 270 and the top surfaces of the conductors 241 and 242, respectively. In addition, the metal oxide 230 has a concave portion. The concave portion has a region that overlaps with the opening 290 in the conductor 242 in a plan view.

[0308] At least a portion of the insulator 250 is disposed in the concave portion of the metal oxide 230. In addition, the insulator 250 has a region in contact with the top surface of the metal oxide 230. In addition, the insulator 250 has a concave portion. The concave portion is located inside the concave portion in the metal oxide 230.

[0309] The conductor 260 is provided in a manner embedded in the recess of the insulator 250. In addition, the conductor 260 includes a region in contact with the top surface of the insulator 250. In addition, the conductor 260 has a region overlapping with the metal oxide 230 via the insulator 250 in the region between the conductor 241 and the conductor 242 when viewed in cross section. In addition, the conductor 260 having a needle-like bottom shape may also be referred to as a needle-shaped gate.

[0310] In the above structure, the channel length of the transistor 500A is the distance from the top surface of the conductor 241 to the bottom surface of the conductor 242 when viewed in cross section. That is, the channel length of the transistor 500A can be adjusted by the thickness of the insulator 270 in the region overlapping the conductor 241. For example, by forming the insulator 270 thinner, the transistor 500A having a short channel length can be manufactured.

[0311] In addition, in the above structure, the channel width of the transistor 500A is the length of the region where the insulator 270 contacts the metal oxide 230 when viewed from above, and is also the length of the outline (periphery) of the metal oxide 230 when viewed from above. That is, the channel width of the transistor 500A can be adjusted according to the diameter of the opening provided in the insulator 270. For example, by increasing the diameter of the opening, a transistor 500A having a large channel width can be manufactured. In addition, the opening can also be referred to as an opening in which a part of the components of the transistor 500A (here, the metal oxide 230, the insulator 250, and the conductor 260) is provided.

[0312] The transistor 500A has a structure in which a channel formation region surrounds a gate electrode. Therefore, the transistor 500A can also be said to be a transistor with a CAA (Channel-All-Around) structure.

[0313] In addition, although Fig.22D The top surface of the opening in the conductor 242 is shown as a circular structure, but the present invention is not limited to this. For example, the top surface of the opening in the conductor 242 may also be an ellipse, a polygon, or a rounded polygon. Here, the polygon refers to a triangle, a quadrilateral, a pentagon, a hexagon, etc.

[0314] The insulator 250 may have a single-layer structure or a stacked-layer structure.

[0315] As the insulator 250, for example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.

[0316] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 be reduced.

[0317] Note that an insulator having a barrier property to oxygen may be provided between the insulator 250 and the metal oxide 230. The insulator is provided in contact with the bottom surface of the insulator 250 and the recessed portion of the metal oxide 230. By making the insulator have a barrier property to oxygen, it is possible to suppress excessive supply of oxygen to the channel formation region when the oxygen in the insulator 250 is supplied to the channel formation region. In addition, it is possible to suppress the release of oxygen from the metal oxide 230 during heat treatment or the like, thereby suppressing the formation of oxygen vacancies in the metal oxide 230. Therefore, the electrical characteristics of the transistor 500A can be improved, thereby improving the reliability.

[0318] As the above-mentioned insulator, it is preferable to use an insulator including an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. can be used. As the above-mentioned insulator, aluminum oxide is preferably used. In this case, the above-mentioned insulator contains at least oxygen and aluminum. Note that the above-mentioned insulator, for example, is less likely to allow oxygen to pass through than the insulator 250. In addition, as the above-mentioned insulator, for example, a material that is less likely to allow oxygen to pass through than the insulator 250 can be used. As the above-mentioned insulator, for example, magnesium oxide, gallium oxide, gallium zinc oxide, or indium gallium zinc oxide can also be used.

[0319] Fig. 22B The conductor 260 is shown as an example of a single-layer structure. Note that the conductor 260 may also have a stacked structure. For example, the conductor 260 preferably includes a first conductor and a second conductor on the first conductor. Specifically, the first conductor of the conductor 260 is preferably arranged so as to surround the bottom surface and side surfaces of the second conductor of the conductor 260.

[0320] As the first conductor of the conductor 260, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, or copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). Alternatively, it is preferable to use a conductive material that is not easily oxidized.

[0321] When the first conductor of the conductor 260 has a function of suppressing the diffusion of oxygen, for example, it is possible to suppress the oxygen contained in the insulator 250 from oxidizing the second conductor of the conductor 260 and causing a decrease in conductivity. As a conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0322] An insulator 283 is provided on the insulator 250. An insulator having a barrier property to hydrogen is preferably used for the insulator 283. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor 500A through the insulator 250 to the metal oxide 230. Since the silicon nitride film and the silicon oxynitride film each have the characteristics of less release of impurities (e.g., water and hydrogen) from themselves and less penetration of oxygen and hydrogen, they can be applied to the insulator 283.

[0323] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0324] (Implementation 4)

[0325] In this embodiment, an example of a cross-sectional structure of an element layer (storage layer) including an OS transistor disposed on an element layer (driving circuit layer) including stacked Si transistors is described, and this structure can be used in various circuits in a semiconductor device. In this embodiment, an example of a schematic cross-sectional view of a circuit structure that can be used for a NOSRAM is described.

[0326] Fig.23 An example of a cross-sectional structure when a circuit structure using NOSRAM is shown. Fig.23 An example is shown in which element layers 700 [ 1 ] to 700 [ 3 ] are stacked on an element layer 701 . The element layer 701 corresponds to the element layer 50 described in the first embodiment, and the element layer 700 corresponds to the element layer 40 .

[0327] also, Fig.23 An example of the transistor 550 included in the element layer 701 is shown. As the transistor 550, the transistor 550 described in the above embodiment mode can be applied.

[0328] also, Fig.23 The transistor 550 shown is just an example, and an appropriate transistor may be used according to the circuit structure or driving method without being limited to the structure.

[0329] A wiring layer including an interlayer film, wiring, and plugs may be provided between the component layer 701 and the component layer 700, or between the k-th component layer 700 and the k+1-th component layer 700. In addition, in the present embodiment, the k-th component layer 700 is sometimes referred to as the component layer 700[k], and the k+1-th component layer 700 is sometimes referred to as the component layer 700[k+1]. Here, k is an integer greater than 1 and less than N. In addition, in the present embodiment, when referred to as "k+α (α is an integer greater than 1)" or "k-α", the solutions of "k+α" and "k-α" are each integer greater than 1 and less than N.

[0330] In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, a wiring and a plug electrically connected to the wiring may also be one component. That is, a part of a conductor may be used as a wiring, and a part of a conductor may be used as a plug.

[0331] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 550. In addition, a conductor 328 or the like is embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 or the like is embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0332] In addition, the insulator used as the interlayer film can be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 320, planarization can also be achieved by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0333] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.23 In the embodiment, an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are sequentially stacked on the insulator 326 and the conductor 330. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 is used as a contact plug or a wiring.

[0334] The insulator 514 included in the element layer 700[1] is provided on the insulator 354. In addition, the conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 is used as a contact plug or wiring. For example, the wiring WBL (or the wiring RBL) and the transistor 550 are electrically connected through the conductor 358, the conductor 356, and the conductor 330.

[0335] Fig.24A An example of a cross-sectional structure of the element layer 700[k] is shown. Fig. 24B yes Fig.24A Equivalent circuit diagram of .

[0336] Fig.23 and Fig.24A The illustrated memory cell MC includes a transistor M1, a transistor M2, and a transistor M3 on an insulator 514. In addition, a conductor 215 is provided on the insulator 514. The conductor 215 can be formed simultaneously with the conductor 503 using the same material and the same process.

[0337] also, Fig.23 and Fig.24A The transistor M2 and the transistor M3 shown in the figure share an island-shaped metal oxide 530. In other words, a portion of the island-shaped metal oxide 530 is used as a channel formation region of the transistor M2, and another portion is used as a channel formation region of the transistor M3. In addition, the source of the transistor M2 and the drain of the transistor M3 or the drain of the transistor M2 and the source of the transistor M3 are shared. Therefore, compared with the case where the transistor M2 and the transistor M3 are provided separately, the occupied area of ​​the transistor is small.

[0338] In addition, Fig.23 and Fig.24A In the illustrated memory cell MC, an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287. Furthermore, an insulator 514 of the element layer 700[k+1] is provided on the insulator 287 and the conductor 161.

[0339] exist Fig.23 and Fig.24A In the embodiment, the conductor 215 of the element layer 700[k+1] is used as one terminal of the capacitor C, the insulator 514 of the element layer 700[k+1] is used as a dielectric of the capacitor C, and the conductor 161 is used as the other terminal of the capacitor C. In addition, the other of the source and the drain of the transistor M1 is electrically connected to the conductor 161 through a contact plug, and the gate of the transistor M2 is electrically connected to the conductor 161 through another contact plug.

[0340] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0341] (Implementation method 5)

[0342] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In addition, in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0343] [OS Transistor]

[0344] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×1010 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0345] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0346] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0347] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, when V O When the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor may have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0348] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0349] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0350] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0351] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0352] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0353] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type junction-less transistor structure, in which the channel forming region is n - Type region, source region and drain region are n +Type area.

[0354] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the top view of the transistor.

[0355] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0356] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0357] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0358] (Implementation 6)

[0359] In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0360] [Electronic components]

[0361] Fig.25A A perspective view of a substrate (circuit board 704 ) on which electronic components 709 are mounted is shown. Fig.25A The electronic component 709 shown includes a semiconductor device 710 within a mold 711. Fig.25A709 is partially omitted to show the inside. The electronic component 709 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 709 is mounted on the printed circuit board 702, for example. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, the circuit board 704 is completed.

[0362] In addition, the semiconductor device 710 includes a driving circuit layer 715 and an element layer 716. The element layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the element layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the element layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0363] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0364] In addition, it is preferred that multiple memory cell arrays in the element layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. The bandwidth refers to the amount of data transmitted per unit time, and the access delay refers to the time between accessing and starting the exchange of data. When Si transistors are used in the element layer 716, it is more difficult to realize a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0365] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0366] then, Fig.25B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0367] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0368] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0369] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit disposed on the interposer 731 to the electrode disposed on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0370] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0371] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0372] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0373] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0374] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.25B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0375] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0376] [Electronic equipment]

[0377] then, Fig.26A A perspective view of electronic device 6500 is shown. Fig.26AThe electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, and the like.

[0378] Fig.26B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, etc. In addition, by using a semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0379] [Mainframe computer]

[0380] then, Fig.26C A perspective view of a mainframe computer 5600 is shown. Fig.26C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0381] Computer 5620 may have, for example, Fig.26D The structure of the stereogram is shown. Fig.26D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0382] Fig.26E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.26ESemiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0383] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0384] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0385] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0386] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0387] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 709 can be used.

[0388] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0389] [Space Equipment]

[0390] The semiconductor device of one embodiment of the present invention can be applied to space equipment such as equipment for processing and storing information.

[0391] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation and is therefore suitable for environments where radiation may be incident. For example, the OS transistor is suitable for use in outer space.

[0392] exist Fig. 27 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 27 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0393] In addition, although Fig. 27 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0394] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0395] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0396] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0397] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use a semiconductor device of one embodiment of the present invention for the control device 6807. Compared with Si transistors, the electrical characteristics of OS transistors change less due to radiation exposure. In other words, OS transistors have high reliability even in an environment where radiation may be incident and are suitable for such an environment.

[0398] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0399] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention is suitable for use in space equipment such as a spacecraft, a space capsule, and a space probe.

[0400] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0401] [Data Center]

[0402] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0403] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0404] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0405] Fig.28 A storage system that may be used in a data center is shown. Fig.28 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0406] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0407] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the storage and output of data.

[0408] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0409] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0410] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0411] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0412] <Notes on the Descriptions in This Manual, etc.>

[0413] Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0414] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0415] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0416] The contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using articles described in the specification.

[0417] In addition, more figures may be formed by combining a drawing (or part thereof) shown in a certain embodiment with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment, and / or drawings (or parts thereof) shown in one or more other embodiments.

[0418] In this specification, etc., constituent elements are classified according to function and are represented as mutually independent blocks in a block diagram. However, it is difficult to classify constituent elements according to function in an actual circuit, etc., and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the division of blocks in a block diagram is not limited to the constituent elements described in the specification, but can be appropriately different according to the situation.

[0419] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. The drawings are for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include uneven signals, voltages or currents caused by noise or timing deviations.

[0420] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc., depending on the situation.

[0421] In addition, in this specification, "electrode" or "wiring" does not limit the function of a component. For example, an "electrode" is sometimes used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" or "wiring" are formed as one.

[0422] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference from the reference potential. For example, when the reference potential is the ground voltage (ground voltage), voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0423] In this specification, the words "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0424] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0425] In this specification, etc., for example, the channel length refers to the distance between the source and the drain in the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap or in the area where the channel is formed in a top view of the transistor.

[0426] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate electrode overlap, or the portion where the source and drain electrodes face each other in the region where the channel is formed.

[0427] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit structure or device structure, etc. In addition, a terminal, wiring, etc. may also be referred to as a node.

[0428] In this specification, etc., "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection that can transmit an electric signal between A and B when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between A and B. Note that the case where A and B are electrically connected includes the case where A and B are directly connected. Here, direct connection between A and B means a connection that can transmit an electric signal between A and B through wiring (or electrodes) etc. without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit.

[0429] [Explanation of symbols]

[0430] 10: semiconductor device, 40: element layer, 41: memory cell unit, 42: memory cell, 43: memory cell array, 50: element layer, 51: write word line driver circuit, 52: read word line driver circuit, 53: write bit line driver circuit, 54: read bit line driver circuit, 55: calculation circuit, 56: calculation control circuit, 57: control circuit

Claims

1. A semiconductor device comprising: A first element layer including a bit line driver circuit; A second element layer including a first switch circuit, a first storage unit, and a first wiring arranged between the first switch circuit and the first storage unit; as well as a third element layer including a second switch circuit, a second storage unit, and a second wiring provided between the second switch circuit and the second storage unit, wherein the second component layer is stacked on the first component layer, The third element layer is stacked on the second element layer, The second element layer and the third element layer are provided with a third wiring electrically connected to the bit line driving circuit. The bit line driving circuit is electrically connected to the first switch circuit and the second switch circuit via the third wiring. The first switch circuit has a function of making the first wiring and the third wiring non-conductive during data writing or reading operation of the second memory cell. Furthermore, the second switch circuit has a function of making the second wiring and the third wiring non-conductive during a data writing operation or a data reading operation of the first memory cell. 2 . The semiconductor device according to claim 1 , wherein a transistor whose semiconductor layer including a channel formation region is an oxide semiconductor is provided in the second element layer and the third element layer. 3 . The semiconductor device according to claim 2 , wherein the oxide semiconductor includes In, Ga, and Zn. 4 . The semiconductor device according to claim 1 , wherein a transistor whose semiconductor layer including a channel formation region is made of silicon is provided in the first element layer.

5. The semiconductor device according to claim 1, wherein the first switch circuit has a function of precharging the potential of the first wiring, Furthermore, the second switch circuit has a function of precharging the potential of the second wiring.

6. The semiconductor device according to claim 1, The first element layer includes a calculation circuit that performs calculation processing based on the data read out to the bit line driving circuit. And the arithmetic circuit is provided in a region overlapping with a region where the first memory cell in the second element layer and the second memory cell in the third element layer are provided. 7 . The semiconductor device according to claim 1 , wherein the third wiring includes a portion provided in the same direction as a direction perpendicular to a surface of a substrate on which the first element layer is provided.

8. A semiconductor device comprising: A first component layer including a word line driving circuit and a bit line driving circuit; A second element layer including a first switch circuit, a first layer selection circuit, a first storage unit, a first wiring arranged between the first switch circuit and the first storage unit, and a second wiring arranged between the first layer selection circuit and the first storage unit; as well as a third element layer including a second switch circuit, a second layer selection circuit, a second storage unit, a third wiring arranged between the second switch circuit and the second storage unit, and a fourth wiring arranged between the second layer selection circuit and the second storage unit, wherein the second component layer is stacked on the first component layer, The third element layer is stacked on the second element layer, The second element layer and the third element layer are provided with a fifth wiring electrically connected to the bit line driving circuit and a sixth wiring electrically connected to the word line driving circuit. The bit line driving circuit is electrically connected to the first switch circuit and the second switch circuit via the fifth wiring. The word line driving circuit is electrically connected to the first layer selection circuit and the second layer selection circuit through the sixth wiring. The first switch circuit has a function of making the first wiring and the fifth wiring non-conductive during data writing or reading operation of the second memory cell. The second switch circuit has a function of making the third wiring and the fifth wiring non-conductive during data writing or reading operation of the first memory cell. Furthermore, the first layer selection circuit and the second layer selection circuit have a function of outputting the signal output from the word line driving circuit to the second wiring or the fourth wiring. 9 . The semiconductor device according to claim 8 , wherein transistors including a semiconductor layer including a channel formation region made of an oxide semiconductor are provided in the second element layer and the third element layer. 10 . The semiconductor device according to claim 9 , wherein the oxide semiconductor includes In, Ga, and Zn.

11. The semiconductor device according to claim 8, wherein a transistor whose semiconductor layer including a channel formation region is made of silicon is provided in the first element layer.

12. The semiconductor device according to claim 8, wherein the first switch circuit has a function of precharging the potential of the first wiring, Furthermore, the second switch circuit has a function of precharging the potential of the second wiring.

13. The semiconductor device according to claim 8, The first element layer includes a calculation circuit that performs calculation processing based on the data read out to the bit line driving circuit. And the arithmetic circuit is provided in a region overlapping with a region where the first memory cell in the second element layer and the second memory cell in the third element layer are provided. 14 . The semiconductor device according to claim 8 , wherein the fifth wiring and the sixth wiring each include a portion provided in the same direction as a direction perpendicular to a surface of a substrate on which the first element layer is provided.

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