Memory device with vertical transistor in peripheral circuit

Abstract

The invention relates to a memory device and a memory system. An exemplary memory device includes an array of memory cells and a peripheral circuit. Each memory cell in the array of memory cells includes a corresponding first vertical transistor and a corresponding memory structure coupled to the corresponding first vertical transistor in a first direction. The peripheral circuit is adjacent to the array of memory cells in a second direction perpendicular to the first direction. The peripheral circuit includes a second vertical transistor coupled to the first vertical transistor of the corresponding memory cell.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices and memory systems. Background Art

[0002] The semiconductor industry is driven by the need to produce smaller and faster chips. Manufacturers of memory devices and systems are also pushing for improved scaling technology. Dynamic random access memory (DRAM) is a common type of memory device widely used in computer systems. The mainstream DRAM architecture has used 8F for many years. 2 Unit Design and 6F 2 Unit design, and is now in the process of moving to 4F 2 In the process of cell design transformation. The scaling of DRAM devices faces many challenges. For example, the manufacturing process has developed from 18 nanometer (nm) process and 15nm process to 10nm process. However, the increased density of memory cells in the chip and the row hammer effect may cause interference errors. Therefore, advanced technologies are needed to alleviate these problems and improve the scaling of DRAM devices. Summary of the invention

[0003] The present disclosure relates to a memory device and a memory system. An exemplary memory device includes an array of memory cells and a peripheral circuit. Each memory cell in the array of memory cells includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The peripheral circuit is adjacent to the array of memory cells in a second direction perpendicular to the first direction. The peripheral circuit includes a second vertical transistor, which is coupled to a memory cell in the array of memory cells through the first vertical transistor of the memory cell in the array of memory cells.

[0004] Although generally described as computer-implemented software embodied on a tangible medium that processes and transforms corresponding data, some or all of the various aspects may be computer-implemented methods, or further included in corresponding systems or other devices for performing such described functionality. These and other aspects of the disclosure and details of implementation are set forth in the drawings and the following description. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A schematic diagram showing a cross-section of a memory device according to some aspects of the present disclosure.

[0006] Figure 2A-2B A schematic diagram of a memory device with vertical transistors according to some aspects of the present disclosure is shown.

[0007] Figure 3 A side view of a cross section of a memory device with vertical transistors is shown in accordance with some aspects of the present disclosure.

[0008] Figure 4 A memory device having multiple memory cell arrays according to some aspects of the present disclosure is shown.

[0009] Figure 5A A plan view of a memory device having two memory cell arrays according to some aspects of the present disclosure is shown.

[0010] Figure 5B A plan view of a memory device having at least one word line driver device according to some aspects of the present disclosure is shown.

[0011] Figure 6 A flow chart of a method for forming an array wafer of memory devices according to some aspects of the present disclosure is shown.

[0012] Figure 7A-7C An example of a semiconductor layer having trenches according to some aspects of the present disclosure is shown.

[0013] Figure 8A-8D An example of forming a gate structure in a semiconductor layer according to some aspects of the present disclosure is shown.

[0014] Fig. 9 An example of forming a source and a drain for a semiconductor body in a semiconductor layer according to some aspects of the present disclosure is shown.

[0015] Figures 10A-10F Examples of forming memory structures and interconnects in semiconductor layers according to some aspects of the present disclosure are shown.

[0016] Fig.11 A block diagram of a system having a memory device according to some aspects of the present disclosure is shown.

[0017] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0018] Transistors can be used in memory cells and peripheral circuits of memory devices. For example, a one-transistor / one-capacitor (1T / 1C) memory cell of a DRAM device has a capacitor and a transistor. Bits of data are stored in the capacitor, and the transistor acts as a switch that controls the discharge of the capacitor. Transistors are also commonly used in sense amplifiers, which are part of the peripheral circuits of a DRAM device. The sense amplifier can be coupled to the memory cell through a bit line and can be configured to amplify a small voltage or current during a read operation of the memory cell.

[0019] In order to reduce the size of the memory device and increase the density of the memory cell, chip manufacturers use vertical transistors to replace the planar transistors in the memory cells of the memory device. The planar transistor in the memory cell may have a horizontal structure with a buried word line in the substrate and a bit line above the substrate. Because the source and drain of the planar transistor are laterally arranged at different positions, the planar transistor may occupy a larger area in the memory cell. In contrast, the vertical transistor generally has a semiconductor body extending vertically. The source and drain of the vertical transistor may be arranged at both ends of the semiconductor body. Therefore, the use of vertical transistors to replace the planar transistors in the memory cell can reduce the occupied area of ​​each memory cell and simplify the layout of the interconnection structure of the memory cell, the word line and the bit line.

[0020] The present disclosure provides a technology for using vertical transistors in both memory cells and one or more peripheral circuits for a memory device. For example, the memory device includes an array of memory cells and a peripheral circuit adjacent to the array of memory cells in a horizontal direction. Each memory cell in the array of memory cells includes a vertical transistor and a capacitor coupled to the vertical transistor in a vertical direction. The peripheral circuit includes at least one vertical transistor, which is coupled to a memory cell in the array of memory cells through the vertical transistor of the memory cell.

[0021] The techniques described in the present disclosure may be implemented to achieve one or more of the following advantages. First, the size of the peripheral circuit of the memory device may be reduced. Second, the memory cell and the portion of the peripheral circuit using the vertical transistor may be produced during the same manufacturing process, which reduces manufacturing complexity and improves yield. Third, the metal wiring and routing of the interconnection lines in the memory device are simplified, which may reduce the coupling capacitance of the memory device (e.g., the coupling capacitance between the bit line and the storage element). Fourth, since the vertical transistor of the sense amplifier has a metal gate, the mismatch of the sense amplifier may be reduced, which improves the sensing margin of the sense amplifier.

[0022] In the present disclosure, some embodiments are described in the context of DRAM devices. However, it should be appreciated that such embodiments are not so limited and are equally applicable to memory devices implemented using any other suitable technology, such as phase change memory (PCM), static random access memory (SRAM), ferroelectric DRAM (FRAM), resistive memory, magnetic memory, spin transfer torque (STT) memory, or combinations thereof.

[0023] Figure 1A schematic diagram of a cross section of a memory device 100 according to some aspects of the present disclosure is shown. The memory device 100 represents an example of a bonded chip. The memory device 100 includes a semiconductor structure 102 and a semiconductor structure 104 bonded together. The semiconductor structure 104 includes a memory cell array 108. The memory cell array 108 may also be referred to as an array of memory cells. The array 108 of memory cells in the semiconductor structure 104 (memory cell array) may use vertical transistors as switches and selection devices. In some embodiments, the memory cell array 108 includes an array of DRAM cells.

[0024] The memory device 100 includes peripheral circuits 110 of the memory cell array 108. The peripheral circuits 110 (which may also be referred to as control and sensing circuits) may include any suitable digital, analog, and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits 110 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current reference or a voltage reference, any portion (e.g., a subcircuit) of the functional circuits mentioned above, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0025] The peripheral circuit 110 includes a vertical circuit 112 and a planar circuit 114. The vertical circuit 112 is located in the semiconductor structure 104 and includes one or more vertical transistors. The planar circuit 114 is located in the semiconductor structure 102 and includes one or more planar transistors. Each of the vertical circuit 112 and the planar circuit 114 may also be referred to as a peripheral circuit or a portion (or subcircuit) of the peripheral circuit 110. According to some embodiments, both the vertical circuit 112 and the planar circuit 114 may use complementary metal oxide semiconductor (CMOS) technology, which may be implemented using a logic process (e.g., 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes). In some embodiments, the semiconductor structure 102 is referred to as a CMOS wafer, and the semiconductor structure 104 is referred to as an array wafer.

[0026] It should be noted that the x, y and z axes are included in Figure 1, to further illustrate the spatial relationship of the various components in the memory device 100. The substrate of the memory device includes two lateral surfaces extending laterally in the xy plane: a top surface located on the front side of the wafer on which the components of the memory device can be formed, and a bottom surface located on the back side of the wafer opposite to the front side. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate is located in the lowest plane of the memory device in the z-direction, a component (e.g., a layer or device) is determined relative to the substrate of the memory device in the z-direction (a vertical direction perpendicular to the xy plane, for example, the thickness direction of the substrate) to be "on", "above" or "below" another component (e.g., a layer or device) of the memory device. The same concept used to describe spatial relationships is applied throughout the present disclosure.

[0027] like Figure 1 As shown, the memory device 100 also includes (in the vertical direction, for example, Figure 1 The bonding interface 106 between the semiconductor structure 102 and the semiconductor structure 104 is located in the z-direction in the memory device 100. The components of the memory device 100 (e.g., the semiconductor structure 102 and the semiconductor structure 104) can be formed separately on different substrates and then connected to form a bonded chip. The semiconductor structures 102 and 104 can be manufactured separately so that the thermal budget of manufacturing one of the semiconductor structures 102 and 104 does not limit the process of manufacturing the other of the semiconductor structures 102 and 104. In some embodiments, the semiconductor structure 102 and the semiconductor structure 104 can be manufactured in parallel. In addition, in contrast to the long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board such as a printed circuit board (PCB), a large number of interconnections (e.g., bonding contacts) can be formed through the bonding interface 106 to form a direct, short-distance (e.g., micrometer-level) electrical connection between the semiconductor structure 102 and the semiconductor structure 104, thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transmission between the semiconductor structure 104 and the semiconductor structure 102 (e.g., data transmission between the memory cell array 108 and the planar circuit 114 and data transmission between the vertical circuit 112 and the planar circuit 114) may be performed through interconnections (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the semiconductor structures 102 and 104, such as stacking both semiconductor structures 102 and 104 in a vertical direction, chip size may be reduced and memory cell density may be increased.

[0028] In some embodiments, semiconductor structures 102 and 104 are joined by hybrid bonding, which is also referred to as “metal / dielectric hybrid bonding.” Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can achieve both metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding.

[0029] It should be appreciated that the relative positions of the stacked semiconductor structures 102 and 104 are not limited. In some embodiments, the semiconductor structure 102 is located above the semiconductor structure 104. In some embodiments, the semiconductor structure 102 is adjacent to the semiconductor structure 104 in a lateral direction (eg, in an xy plane).

[0030] In some embodiments, the semiconductor structure 104 includes a plurality of memory cell arrays 108. In some embodiments, the memory device 100 includes a plurality of peripheral circuits 110, and at least one of the plurality of peripheral circuits 110 includes a vertical circuit 112 located within the semiconductor structure 104. In some embodiments, all transistors in the peripheral circuit 110 are vertical transistors and located within the vertical circuit 112, and the planar circuit 114 may not include any transistors at all.

[0031] Figure 2A-2B Schematic diagram of a memory device 200 with vertical transistors according to some aspects of the present disclosure is shown. The memory device 200 includes a memory cell array 108 and a peripheral circuit 110 coupled together. The peripheral circuit 110 includes a vertical circuit 112 and a planar circuit 114. The memory device 200 may be Figure 1 1. For example, the memory cell array 108 and the vertical circuit 112 of the memory device 200 are included in the semiconductor structure 104, and the planar circuit 114 of the memory device 200 is included in the semiconductor structure 102. The memory cell array 108 can be any suitable memory cell array, wherein each memory cell 208 includes a vertical transistor 202 and a storage element 212 coupled together. In some embodiments, the memory cell 208 is a DRAM cell, and the storage element 212 is a capacitor for storing charge as binary information stored by the DRAM cell.

[0032] like Figure 2AAs shown, the memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 200 may include: word lines 204, which couple the peripheral circuit 110 with the memory cell array 108 for controlling the switching of the vertical transistors 202 in the memory cells 208 located in a row; and bit lines 206, which couple the peripheral circuit 110 with the memory cell array 108 for sending data to the memory cells 208 located in a column and / or receiving data from the memory cells 208 located in a column. That is, each word line 204 is coupled to the memory cells 208 of the corresponding row, and each bit line is coupled to the memory cells 208 of the corresponding column. In some embodiments, each word line 204 is a vertical line and is coupled to the memory cells 208 of the corresponding column, and each bit line 206 is a horizontal line and is coupled to the memory cells 208 of the corresponding row.

[0033] In some embodiments, vertical circuit 112 is a sense amplifier (SA) and planar circuit 114 is an I / O circuit. Vertical circuit 112 or SA112 may be a differential SA. Figure 2B As shown, SA 112 includes a sensing circuit 222 and a voltage equalization circuit 232. The sensing circuit 222 and the voltage equalization circuit 232 are coupled to the bit line 206 and the bit line 240. The sensing circuit 222 is also referred to as a latch circuit. The bit line 206 is located within the memory cell array 108 and is configured to connect a column of memory cells 208 in the memory cell array 108 to the SA 112. The bit line 240 may be located within another memory cell array and serves as a reference for a read operation performed on the column of memory cells 208 coupled to the bit line 206. When the storage element 212 of the memory cell 208 is discharging, the SA 112 is configured to amplify the small voltage difference between the bit line 206 and the bit line 240 and output the amplified voltage to the I / O driver 114. The SA 112 may also be configured to recharge the storage element 212 after reading the data stored in the memory cell 208 to refresh the memory cell 208.

[0034] In some embodiments, the sensing circuit 222 includes two N-type metal oxide semiconductor (NMOS) transistors 210 and 226 and two P-type metal oxide semiconductor (PMOS) transistors 224 and 228. The NMOS transistors 210 and 226 are coupled to the SA control line 242 (SAN). The PMOS transistors 224 and 228 are coupled to the SA control line 244 (SAP). In some embodiments, the sensing circuit 222 is constructed using CMOS technology. The voltage equalization circuit 232 includes transistors 234, 236, and 238 coupled to the equalization line 254. In this example, the transistors 210, 224, 226, 228, 234, 236, and 238 are vertical transistors.

[0035] Figure 2B An exemplary structure of a vertical transistor 210 is shown. Figure 2B As shown, in some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor 210 includes a substrate ( Figure 2B The semiconductor body 214 may extend vertically (in the z-direction) above the substrate (not shown). That is, the semiconductor body 214 may extend above the top surface of the substrate, thereby exposing not only the top surface of the semiconductor body 214 but also one or more side surfaces thereof. Figure 2B As shown, for example, the semiconductor body 214 can have a rectangular parallelepiped shape to expose its four sides. It should be appreciated that the semiconductor body 214 can have any appropriate 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in a plan view (e.g., in an xy plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other appropriate shape. Consistent with the scope of the present disclosure, for a semiconductor body having a circular or elliptical cross-section in a plan view, the semiconductor body can still be considered to have multiple sides so that the gate structure contacts more than one side of the semiconductor body. As described below with respect to the manufacturing process, the semiconductor body 214 can be formed from a substrate (e.g., by etching or epitaxy) and, therefore, has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0036] like Figure 2B As shown, the vertical transistor 210 may further include a gate structure 216 in contact with one or more sides of the semiconductor body 214, i.e., in one or more planes of the side surface(s) of the active region. In other words, the active region of the vertical transistor 210 (i.e., the semiconductor body 214) may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 218 located on one or more sides of the semiconductor body 214, e.g., as Figure 2B As shown, the gate structure 216 contacts the four side surfaces of the semiconductor body 214. The gate structure 216 may also include a gate electrode 220 located above the gate dielectric 218 and in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide, i.e., a gate oxide. The gate electrode 220 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 220 includes multiple conductive layers, such as a W layer above the TiN layer.

[0037] The vertical transistor 210 may further include a pair of source and drain (S / D doped regions, also referred to as source electrode and drain electrode) formed at both ends of the semiconductor body 214 in the vertical direction (z direction), respectively. The source and drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)), or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain may be separated in the vertical direction (z direction) by a gate structure 216. In other words, the gate structure 216 is vertically formed between the source and the drain.

[0038] In some embodiments, Figure 2B As shown, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 214 (e.g., Figure 2B In other words, unlike a planar transistor that includes only a single planar gate (and causes a single planar channel), due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214, Figure 2B The vertical transistor 210 shown in FIG. 2 may include multiple vertical gates located on multiple sides of the semiconductor body 214. Thus, compared with a planar transistor, Figure 2B The vertical transistor 210 shown in the figure can have a larger gate control area, thereby achieving better channel control with a smaller subthreshold swing. During the off state, the leakage current (Ioff) of the vertical transistor 210 can also be significantly reduced due to the complete depletion of the channel. As described in detail below, the multi-gate vertical transistor can include a dual-gate vertical transistor (e.g., a dual-side gate vertical transistor), a tri-gate vertical transistor (e.g., a tri-side gate vertical transistor), and a full-surround gate (GAA) vertical transistor.

[0039] Although the vertical transistor 210 is Figure 2B 214. Although illustrated as a multi-gate transistor in the drawings, the vertical transistors disclosed herein may also include single-gate transistors as described in detail below. That is, for example, for the purpose of increasing the density of transistors and memory cells, the gate structure 216 may contact a single side of the semiconductor body 214. It should also be appreciated that although the gate dielectric 218 is illustrated as being separated (i.e., a separate structure) from other gate dielectrics of adjacent vertical transistors (not shown), the gate dielectric 218 may be part of a continuous dielectric layer having multiple gate dielectrics of the vertical transistors.

[0040] In planar transistors and some lateral multi-gate transistors (e.g., fin field effect transistors (FinFETs)), an active region, e.g., a semiconductor body (e.g., a fin), extends laterally (in an xy plane), and a source and a drain are disposed at different locations in the same lateral plane (xy plane). In contrast, according to some embodiments, in a vertical transistor 210, a semiconductor body 214 extends vertically (in the z direction), and a source and a drain are disposed in different lateral planes. In some embodiments, the source and the drain are respectively formed at both ends of the semiconductor body 214 in the vertical direction (z direction) so as to overlap in a plan view. Thus, the area occupied by the vertical transistor 210 (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. In addition, because the vertical transistor 210, the memory cell 208, and the bit line 206 are located in the same semiconductor structure (e.g., Figure 1 The semiconductor structure 104 in the vertical transistor 210 is formed within the vertical transistor 210, so the metal wiring coupled to the vertical transistor 210 can be simplified.

[0041] The transistor 202 of each memory cell 208 is also a vertical transistor and can have a structure similar to the transistor structure 210. In some embodiments, the gate of the transistor 202 is coupled to the word line 204, one of the source and the drain of the transistor 202 is coupled to the bit line 206, the other of the source and the drain of the transistor 202 is coupled to one electrode of the storage element 212, and the other electrode of the storage element 212 is coupled to the ground. In other words, the transistor 202 of the memory cell 208 is coupled to the transistor 210 through the bit line 206.

[0042] Planar circuit 114 includes transistors 246 and 248 coupled to column select line (CSL) 256 and transistors 250 and 252 coupled to write enable (WE) line 258. Transistors 246, 248, 250, and 252 are planar transistors. Planar circuit 114 also includes input ports 260 and 264 and output ports 262 and 266. In some embodiments, planar circuit 114 may include Figure 2B The sensing circuit 222 in or any other portion of the SA circuit that is not located within the vertical circuit 112.

[0043] although Figure 2A-2B An exemplary memory device with vertical transistors is shown, but this example is not intended to be interpreted in a limiting sense. Other embodiments, modifications, and permutations of the described embodiments that are apparent to those skilled in the art are also applicable without departing from the spirit and scope of the present disclosure. For example, a sensing circuit or voltage equalization circuit with any appropriate number of transistors may be used in the peripheral circuit 110.

[0044] In some embodiments, Figure 2B A portion of the SA circuitry in the vertical circuit 112 is located within the vertical circuit 112, and the remainder of the SA circuitry is located within the planar circuit 114. For example, the sensing circuit 222 is implemented using vertical transistors and is located within the vertical circuit 112, and the voltage equalization circuit 232 is implemented using planar transistors and is located within the planar circuit 114. In some embodiments, any portion of the peripheral circuit 110 (e.g., transistor 246 of the I / O circuit) can be implemented using vertical transistors and is located within the vertical circuit 112. In some embodiments, the entire peripheral circuit 110 can be implemented using vertical transistors and integrated into the semiconductor structure 104. In some embodiments, the peripheral circuit 110 includes a word line driver (in Figure 2A-2B 1. The vertical circuit 112 includes a first portion of a word line driver, and the first portion of the word line driver includes vertical transistors. The planar circuit 114 includes a second portion of a word line driver, and the second portion of the word line driver includes planar transistors.

[0045] In some implementations, vertical circuit 112 is part of sensing circuit 222. For example, vertical circuit 112 can include transistors 210 and 224. Transistors 226 and 228 of sensing circuit 222 are located outside vertical circuit 112.

[0046] To determine which portion of the peripheral circuit 110 can be implemented using vertical transistors and integrated into the semiconductor structure 104, one or more of the following factors may be considered. A first factor is whether the vertical transistors can meet the performance requirements of the peripheral circuit 110. For example, the performance requirements may include channel length, drive current, and Vds (maximum voltage between the drain and the source). A second factor is the size constraints placed on the semiconductor structure 104. A third factor is the density requirements for the memory cells in the semiconductor structure 104. For example, if the size of the semiconductor structure 104 is fixed, adding a portion or all of the peripheral circuit to the semiconductor structure 104 may take up space that may have been used for memory cells, which may affect the memory cell density.

[0047] Figure 3 3 shows a side view of a cross section of a memory device 300 including vertical transistors according to some aspects of the present disclosure. It should be appreciated that Figure 3 It is for illustrative purposes only and may not necessarily reflect actual device structures (eg, interconnections) in practice. Figure 1 As an example of the memory device 100 in FIG. 1 , the memory device 300 is a bonded chip including a semiconductor structure 102 and a semiconductor structure 104 stacked on the semiconductor structure 102. According to some embodiments, the semiconductor structures 102 and 104 are connected at a bonding interface 106 located therebetween. The memory device 300 includes a memory cell array 108 and a peripheral circuit 110 of the memory cell array 108. The memory cell array 108 is located within the semiconductor structure 104. The peripheral circuit 110 includes a vertical circuit 112 located within the semiconductor structure 104 and a planar circuit 114 located within the semiconductor structure 102.

[0048] The memory cell array 108 includes an array of memory cells and a plurality of bit lines. Figure 3 The cross-section of the memory device 300 in FIG. 3 can be made along the bit line direction (y direction). One bit line (bit line 304) of the plurality of bit lines extends laterally in the y direction and is coupled to a column of memory cells 302 in the array of memory cells. Each memory cell 302 includes a vertical transistor 308 (e.g., Figure 2A The vertical transistor 202 in FIG. 1 and the capacitor 306 (eg, Figure 2A304 and capacitor 212 in the vertical transistor 308). The vertical transistor 308 includes a semiconductor body extending vertically (in the z direction) and a source and a drain disposed at both ends (upper and lower ends) of the semiconductor body. The vertical transistor 308 may have one end (one of the source or drain of the vertical transistor 308) coupled to the bit line 304 and another end (the other of the source or drain of the vertical transistor 308) coupled to the capacitor 306. In some embodiments, the vertical transistor 308 has a dual gate 310.

[0049] like Figure 3 As shown, in some embodiments, each capacitor 306 includes an electrode 336 located above and in contact with the source or drain of the vertical transistor 308. The capacitor 306 also includes: a capacitor dielectric 338 located above and in contact with the electrode 336, and another electrode 340 located above and in contact with the capacitor dielectric 338. That is, the capacitor dielectric 338 is sandwiched between the electrodes 336 and 340. In some embodiments, each electrode 336 is coupled to a corresponding vertical transistor 308 in the same memory cell 302, and all electrodes 340 are parts of a common conductive structure coupled to ground. The structure and construction of the capacitor 306 are not limited to Figure 3 , and may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate plate capacitor. In some embodiments, the memory cell 302 may have any suitable structure and construction, such as 1T, 1T1C, or 1TnC. That is, the number of capacitors connected to the vertical transistors of the memory cell 302 may be 0, 1, or n (n is an integer). In some embodiments, the capacitor dielectric 338 is made of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to: Al 2 O 3 , HfO 2 、 2 O 5 、ZrO 2 、TiO 2 or any combination thereof. It should be appreciated that in some examples, capacitor 306 can be a ferroelectric capacitor used in a FRAM cell, and capacitor dielectric 338 can be replaced by a ferroelectric layer having a ferroelectric material, such as zirconate titanate (PZT) or strontium bismuth tantalate (SBT). In some embodiments, electrodes 336 and 340 are made of a conductive material, including but not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0050] The vertical circuit 112 includes vertical transistors 312, 314, 316, and 318 of the peripheral circuit 110. In some embodiments, the vertical transistors 312, 314, 316, and 318 also have dual gates (e.g., gate 332 of vertical transistor 318). The vertical circuit 112 can be coupled to bit lines from different memory cell arrays. Figure 3 As shown, vertical circuit 112 is coupled to bit line 304 through vertical transistor 312 and to bit line 320 through vertical transistor 318. Bit line 320 is from another memory cell array ( Figure 3 104 ), which may also be located within semiconductor structure 104. Each of vertical transistors 312, 314, 316, and 318 may include a semiconductor body extending vertically (in the z-direction) and a source and a drain disposed at both ends (upper and lower ends) of the semiconductor body. Each of vertical transistors 312, 314, 316, and 318 may be coupled to a bit line (e.g., bit line 304 or bit line 320) via one of its source or drain, and coupled to some other interconnect line (e.g., line 322 or line 324) via the other of its source or drain. Vertical transistors 312, 314, 316, and 318 may be implemented using CMOS technology. For example, line 322 is a SAN line of a SA circuit (e.g., Figure 2B SAN 242 in FIG. 1 ), and vertical transistors 312 and 314 are NMOS transistors (eg, Figure 2B 210 and 226 in the SA circuit). Line 324 may be a SAP line of the SA circuit (e.g., Figure 2B SAP 244 in ), and vertical transistors 316 and 318 are PMOS transistors (e.g., Figure 2B transistors 224 and 228 in FIG.

[0051] In some embodiments, the vertical transistors (e.g., vertical transistors 308, 312, 314, 316, and 318) in the semiconductor structure 104 may have different sizes based on their specific performance requirements. For example, the semiconductor bodies and gate structures of the vertical transistors may have different sizes (different lengths, widths, or heights). In another example, the gate dielectric layers of the vertical transistors may have different thicknesses.

[0052] The vertical transistors in the vertical circuit 112 are not limited to Figure 3, and may include any appropriate number of vertical transistors. In some embodiments, the vertical circuit 112 may include less than four vertical transistors (e.g., one) or more than four vertical transistors. The vertical transistors in the vertical circuit 112 may belong to a latch circuit, a sense amplifier, a page buffer, a decoder (e.g., a row decoder and a column decoder), a driver (e.g., a word line driver and a bit line driver), an I / O circuit, a charge pump, a voltage source or a voltage generator, or a current reference or a voltage reference in the peripheral circuit 110. In addition, the vertical transistors in the vertical circuit 112 may belong to any combination of the above circuits. As described above with respect to Figure 2A-2B As described, several factors (e.g., performance requirements of sub-circuits of the peripheral circuit 110, size constraints on the semiconductor structure 104, and density requirements on memory cells in the semiconductor structure 104) may be considered to determine which portion of the peripheral circuit 110 may be implemented using vertical transistors and integrated into the vertical circuit 112.

[0053] like Figure 3 As shown, semiconductor structure 102 may include substrate 334, which may be made of silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. Planar circuit 114 includes planar transistors 326, 328, and 330 of peripheral circuit 110, which are located on substrate 334.

[0054] Figure 4 4 shows a memory device 400 having a plurality of memory cell arrays according to some aspects of the present disclosure. The memory device 400 is a bonded chip including a semiconductor structure 102 and a semiconductor structure 104. The semiconductor structure 104 is stacked on the semiconductor structure 102. According to some embodiments, the semiconductor structures 102 and 104 are bonded at a bonding interface ( Figure 4 Memory device 400 includes memory cell arrays 402, 404, 406, and 408 and peripheral circuits 110 of these memory cell arrays. Memory cell arrays 402, 404, 406, and 408 are located within semiconductor structure 104. Peripheral circuit 110 includes vertical circuit 112 located within semiconductor structure 104 and planar circuit 114 located within semiconductor structure 102. Vertical circuit 112 includes one or more vertical transistors, and planar circuit 114 includes one or more planar transistors. Vertical circuit 112 includes circuit 410 and circuit 412. Each of circuits 410 and 412 is also referred to as a peripheral circuit.

[0055] like Figure 4As shown, circuit 410 is coupled to both memory cell arrays 402 and 404. Memory cell array 402, circuit 410, and memory cell array 404 are positioned along the y-direction. Circuit 410 is disposed between memory cell arrays 402 and 404. Circuit 412 is coupled to both memory cell arrays 406 and 408. Memory cell array 406, circuit 412, and memory cell array 408 are also positioned along the y-direction. Circuit 412 is disposed between memory cell arrays 406 and 408. Memory cell arrays 402, 404, 406, and 408 and the vertical transistors of vertical circuit 112 have their semiconductor bodies extend vertically in the z-direction.

[0056] In some implementations, circuit 410 is coupled to a bit line of memory cell array 402 through a set of vertical transistors of circuit 410. Circuit 410 is also coupled to a bit line of memory cell array 404 through another set of vertical transistors of circuit 410.

[0057] In some implementations, circuit 410 is coupled to a word line of memory cell array 402 through a set of vertical transistors of circuit 410. Circuit 410 is also coupled to a word line of memory cell array 404 through another set of vertical transistors of circuit 410.

[0058] Figure 5A A plan view of a memory device 500 having two memory cell arrays according to some aspects of the present disclosure is shown. The memory device 500 is a bonded chip including a semiconductor structure 104 and another semiconductor structure. The semiconductor structure 104 is stacked on top of the other semiconductor structure. According to some embodiments, the semiconductor structure 104 and the other semiconductor structure are connected at a bonding interface located therebetween. Figure 5A Another semiconductor and bonding interface are not shown. Semiconductor structure 104 includes memory cell array 502, circuit 504, and memory cell array 506 positioned along the y direction. Memory cell array 502, circuit 504, and memory cell array 506 each include vertical transistors. In some embodiments, circuit 504 is Figure 1 An example of a vertical circuit 112 in FIG.

[0059] The memory cell array 502 includes a plurality of bit lines 508 extending in the y direction and a plurality of word lines 510 extending in the x direction. The memory cell array 502 also includes memory cells formed at the intersections of the bit lines 508 and the word lines 510. Each memory cell in the memory cell array 502 includes a corresponding vertical transistor 512. The memory cell array 506 includes a plurality of bit lines 514 extending in the y direction and a plurality of word lines 516 extending in the x direction. The memory cell array 506 also includes memory cells formed at the intersections of the bit lines 514 and the word lines 516. Each memory cell in the memory cell array 506 includes a corresponding vertical transistor 518. The circuit 504 also includes an array of vertical transistors. The memory cell array 502, the circuit 504, and each vertical transistor in the memory cell array 506 have a semiconductor body extending vertically (in a direction perpendicular to the xy plane). As shown in FIG. Figure 5A As shown, these vertical transistors are single-gate transistors having a gate electrode that contacts one side of the semiconductor body of the vertical transistor and serves as part of a corresponding word line.

[0060] Each row of vertical transistors in circuit 504 is coupled to a corresponding bit line 508 in memory cell array 502 and a corresponding bit line 514 in memory cell array 506. In some implementations, each row of vertical transistors in circuit 504 is a sense amplifier (e.g., Figure 2B For example, vertical transistors 520, 522, 524, and 526 are respectively Figure 2B Examples of vertical transistors 210, 226, 224 and 228 in FIG. Figure 5A As shown, vertical transistor 520 is coupled to bit line 508, and vertical transistor 526 is coupled to bit line 514. In some implementations, vertical transistors 520, 522, 524, and 526 are constructed using CMOS technology.

[0061] It should be recognized that Figure 5A This is for illustrative purposes only, and the actual device structure (eg, interconnections) in practice is not limited to Figure 5A The interconnections between the vertical transistors in circuit 504 may depend on the actual requirements and configuration of circuit 504. In some embodiments, each column of vertical transistors in circuit 504 has their gate electrodes coupled to the same connection line. For example, Figure 5A As shown, the gate electrodes of vertical transistors 520, 528, and 530 are part of a connection line 532. In some embodiments, if the gate electrodes of two adjacent vertical transistors are not coupled together, the connection line 532 may be separated by a gap between the two adjacent vertical transistors.

[0062] Figure 5B A plan view of a memory device 550 having at least one word line driver device according to some aspects of the present disclosure is shown. The memory device 550 is a bonded chip including a semiconductor structure 104 and another semiconductor structure. The semiconductor structure 104 is stacked on top of the other semiconductor structure. According to some embodiments, the semiconductor structure 104 and the other semiconductor structure are connected at a bonding interface located therebetween. Figure 5B Another semiconductor and bonding interface are not shown. Semiconductor structure 104 includes a memory cell array 542 and a word line driver device 560 located in the xy plane. Memory cell array 542 includes a plurality of bit lines 544 extending in the y direction and a plurality of word lines 546, 548, 550, 552, 554 and 556 extending in the x direction. Memory cell array 542 also includes memory cells formed at the intersections of bit lines 544 and word lines 546-556. Each memory cell in memory cell array 542 includes a corresponding vertical transistor 558.

[0063] Both the memory cell array 542 and the word line driver device 560 include vertical transistors. Figure 5B As shown, the word line driver device 560 is adjacent to the memory cell array 542 along the y direction. At least one terminal of the word line driver device 560 is electrically connected to a word line (e.g., word line 546) of the memory cell array 542. The terminal of the word line driver device 560 can be a source or a drain of a vertical transistor of the word line driver device 560. In some embodiments, the terminal of the word line driver device 560 can be directly connected to the word line of the memory cell array 542. In some embodiments, the terminal of the word line driver device 560 can be indirectly connected to the word line of the memory cell array 542 through another device (e.g., a conductive line such as a metal, a jumper, or a switch device).

[0064] In some embodiments, the memory cell array 542 is coupled to more than one word line driver device. The word line driver devices coupled to adjacent word lines can be located at opposite sides of the memory cell array 542. For example, Figure 5B As shown, word line driver device 560 is coupled to word line 546 and is located at the top of memory cell array 542. Word line driver device 562 is coupled to word line 548 (which is adjacent to word line 546) and is located at the bottom of memory cell array 542 opposite word line driver device 560. In some embodiments, each word line of memory cell array 542, including word lines 550, 552, 554, and 556, is coupled to a word line driver device that is similarly positioned as word line driver devices 560 and 562.

[0065] Components of a memory device (e.g., Figure 1 A CMOS wafer or semiconductor structure 102 in Figure 1 The array wafer or semiconductor structure 104 in the embodiment of the present invention can be formed separately on different substrates and then connected to form a bonded chip. The array wafer and the CMOS wafer can be manufactured separately so that the thermal budget of manufacturing one of them does not limit the process of manufacturing the other. In some embodiments, the array wafer and the CMOS wafer can be manufactured in parallel.

[0066] Figure 6 A flow chart of a method 600 for forming an array wafer of a memory device according to some aspects of the present disclosure is shown. At operation 602, a first semiconductor body (also referred to as an array wafer or semiconductor structure) of a first vertical transistor is formed in a first region of a semiconductor layer, and a second semiconductor body of a second vertical transistor is formed in a second region adjacent to the first region of the semiconductor layer. In some embodiments, the first region is referred to as an array region or a core array region, and the second region is referred to as a circuit region. The first semiconductor body and the second semiconductor body are formed on a first side of the semiconductor layer. In some embodiments, the second region is adjacent to the first region in a lateral direction (e.g., a y direction). In some embodiments, the first semiconductor body and the second semiconductor body extend vertically in a direction perpendicular to the lateral direction (e.g., a z direction). The semiconductor layer may be a silicon on insulator (SOI) substrate. In some embodiments, to form the first semiconductor body and the second semiconductor body, the semiconductor layer is etched in two lateral directions so that two opposite sides of each semiconductor body are exposed.

[0067] In some implementations, operation 602 further includes: forming a third semiconductor body of the third vertical transistor.The third semiconductor body of the third vertical transistor may be located in the second region.

[0068] In some embodiments, operation 602 further includes: doping the first region of the semiconductor layer with a P-type dopant to form a first semiconductor body of the first vertical transistor. Operation 602 may also include: doping a portion of the second region of the semiconductor layer with a P-type dopant to form a second semiconductor body of the second vertical transistor. Operation 602 may also include: doping another portion of the second region of the semiconductor layer with an N-type dopant to form a third semiconductor body of the third vertical transistor.

[0069] In some embodiments, operation 602 further includes forming a fourth semiconductor body of a fourth vertical transistor in a third region of the semiconductor layer. The third region is adjacent to the second region in a lateral direction (eg, y direction). The second region is located between the first region and the third region.

[0070] At operation 604, a first gate structure of a first vertical transistor and a second gate structure of a second vertical transistor are formed. The first gate structure contacts at least one side of the first semiconductor body, and the second gate structure contacts at least one side of the second semiconductor body. The first gate structure may include a first conductive layer and a first gate dielectric layer disposed between the first conductive layer and the first semiconductor body. The second gate structure may include a second conductive layer and a second gate dielectric layer disposed between the second conductive layer and the second semiconductor body. The size of the second gate structure (e.g., the length, width, thickness of the dielectric layer or the conductive layer) may be different from the first gate structure. In some embodiments, operation 604 also includes a metal gate doping process to adjust the work function of the first gate structure or the second gate structure or both.

[0071] In some embodiments, operation 604 further includes: forming a third gate structure in contact with at least one side of the third semiconductor body. Operation 604 may also include: forming a fourth gate structure in contact with at least one side of the fourth semiconductor body.

[0072] At operation 606, a first storage structure is formed. The first storage structure is located above and in contact with the first end of the first semiconductor body. Operation 606 may also include: forming a second storage structure located above and in contact with the first end of the fourth semiconductor body.

[0073] In some embodiments, method 600 further includes: removing a portion of the semiconductor layer from the second side to expose a second end of the first semiconductor body opposite to the first end of the first semiconductor body, a first end of the second semiconductor body, and a first end of the third semiconductor body. Method 600 may also include: forming a first bit line in contact with the second end of the first semiconductor body, the second end of the second semiconductor body, and the second end of the third semiconductor body. The first end of the second semiconductor body may be coupled to the fourth vertical transistor. The first end of the third semiconductor body may be coupled to the fifth vertical transistor.

[0074] In some embodiments, method 600 further includes removing a portion of the semiconductor layer from the second side to expose a second end of the fourth semiconductor body opposite to the first end of the fourth semiconductor body. Method 600 may also include forming a second bit line in contact with the second end of the fourth semiconductor body.

[0075] Figure 7A-7C An example of a semiconductor layer 104 having trenches according to some aspects of the present disclosure is shown. Fig. 7A A side view of a cross section of a semiconductor layer 104 having trenches is shown in accordance with some aspects of the present disclosure. Figure 7B and Figure 7C1 and 2 show plan views of a semiconductor layer 104 having trenches according to some aspects of the present disclosure. Fig. 7A and Figure 7B As shown, a plurality of parallel trenches 702 are formed in the x-direction to form a plurality of parallel semiconductor walls 704 of the semiconductor layer 104 in the x-direction. In some embodiments, a photolithography process is performed to pattern the trenches 702 and the semiconductor walls 704 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching processes and / or wet etching processes (e.g., reactive ion etching (RIE)) are performed to etch the trenches 702 in the semiconductor layer 104. Thus, semiconductor walls 704 extending vertically (in the z-direction) in the semiconductor layer 104 can be formed. Figure 7C As shown in FIG. 1 , a plurality of parallel trenches 706 are formed in the y-direction to form an array of semiconductor bodies 708 , each of which extends vertically (in the z-direction) in the semiconductor layer 104 .

[0076] In some embodiments, the trenches 702 and 706 can be formed in two consecutive processes. Alternatively, in some embodiments, the trenches 702 and 706 can be formed in the same process. For example, the same photolithography process can be used to pattern the trenches 702 and 706, followed by the same etching process. In some embodiments, the trenches 706 can be formed in the y direction before the trenches 702 are formed in the x direction. Nevertheless, after the trenches 702 and 706 are formed, an array of semiconductor bodies 708 can be formed, and all four sides of each semiconductor body 708 can be exposed by the trenches 702 and 706. In other words, the semiconductor body 708 can be surrounded by the trenches 702 and 706.

[0077] like Figure 7A-7C As shown, semiconductor layer 104 includes region 710 and region 712. Region 710 is an example of a first region of the semiconductor layer at operation 602 of method 600. Region 712 is an example of a second region of the semiconductor layer at operation 602. Semiconductor bodies 716 in region 710 are examples of first semiconductor bodies at operation 602. Semiconductor bodies 718 in region 712 are examples of second semiconductor bodies at operation 602. In some embodiments, semiconductor bodies in region 710 belong to a memory cell array (e.g., Figure 1 The memory cell array 108 or Figure 4 In some embodiments, the semiconductor body in region 712 belongs to a peripheral circuit (e.g., Figure 1 The vertical circuit 112, Figure 4 The circuit 410 or Figure 5AA vertical transistor in circuit 504).

[0078] In some embodiments, a plurality of semiconductor bodies are formed in region 712. The plurality of semiconductor bodies includes semiconductor body 718 and semiconductor body 722. Semiconductor body 722 in region 712 is an example of a third semiconductor body in operation 602.

[0079] In some embodiments, the semiconductor layer 104 is doped to obtain a doped semiconductor body of the vertical transistor to be produced. The doping of the semiconductor body of the semiconductor layer 104 can occur before etching the trenches 702 and 706. The dopant used to dope the semiconductor layer 104 can depend on the type of vertical transistor to be produced. In some embodiments, the vertical transistors in the semiconductor layer 104 are of the same type. In this case, the same type of dopant can be applied to the entire semiconductor layer 104. For example, doping the semiconductor layer 104 with a P-type dopant can create a P-type semiconductor body for an NMOS transistor. In another example, doping the semiconductor layer 104 with an N-type dopant can create an N-type semiconductor body for a PMOS transistor.

[0080] In some embodiments, the vertical transistors in semiconductor layer 104 are of different types. For example, the semiconductor bodies in region 710 may belong to NMOS transistors (e.g. Figure 2A The semiconductor body in region 724 may belong to an NMOS transistor (e.g. Figure 2B 210 and 226 in the transistors 210 and 226 in the region 726), and the semiconductor body in the region 726 may belong to a PMOS transistor (e.g. Figure 2B 224 and 228 in the semiconductor layer 104). In this case, different regions of the semiconductor layer 104 may be doped with different dopants. For example, regions 710 and 724 may be doped with P-type dopants, and region 726 may be doped with N-type dopants.

[0081] like Figure 7C As shown in , semiconductor layer 104 may include region 714. Regions 710, 712, and 714 are located in the semiconductor layer 104 in the y direction. Region 712 is located between regions 710 and 714. Region 714 is an example of a third region in method 600. Semiconductor body 720 in region 714 is an example of a fourth semiconductor body in the third region in method 600. In some embodiments, the semiconductor body in region 714 belongs to another memory cell array (e.g., Figure 4 The memory cell array 404 or Figure 5A A vertical memory cell in a memory cell array 506).

[0082] Figure 8A-8D An example of forming a gate structure in the semiconductor layer 104 according to some aspects of the present disclosure is shown. Figure 8A-B 1 and 2 are side view and plan view examples of depositing dielectric material 802 to fill the trench of semiconductor layer 104, respectively. For example, dielectric material 802 can be silicon oxide or a high-k dielectric material. In some embodiments, dielectric material 802 is deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Thus, the gate dielectric layer (e.g., Figure 8C A gate dielectric layer 804 in the semiconductor layer 104 is formed on the semiconductor body of the semiconductor layer 104. Deposition conditions (eg, deposition rate and / or time) may be controlled to control the thickness of the gate dielectric layer 804.

[0083] Figure 8C 1 shows a side view example of depositing a conductive layer on the semiconductor layer 104. One or more gate electrodes may also be formed on the gate dielectric layer 804 to form a gate structure. In some embodiments, a conductive layer is deposited on the gate dielectric layer to form a gate electrode. Figure 8C As shown, a gate conductive layer 806 is formed on the gate dielectric layer 804. In some embodiments, the gate conductive layer 806 is formed by depositing one or more conductive materials (e.g., metals and / or metal compounds (e.g., W and TiN)) on the gate dielectric layer 804 using one or more thin film deposition processes (including but not limited to: CVD, PVD, ALD, or any combination thereof). For example, layers of TiN and W may be deposited sequentially to form the gate conductive layer 806. Deposition conditions (e.g., deposition rate and / or time) may be controlled to control the thickness of the gate conductive layer 806. The gate conductive layer 806 may be a continuous layer in the x-direction.

[0084] Fig.8D An example of a side view of adjusting the work function of different gate electrodes in the semiconductor layer 104 is shown. In some embodiments, a metal gate doping process is applied to the gate electrode in the semiconductor layer 104 to adjust the work function and threshold voltage of the vertical transistor to be fabricated. The adjustment can be based on the requirements for the vertical transistor. Fig.8D As shown, in region 712 of semiconductor layer 104, semiconductor bodies 808, 810, 812, and 814 may belong to vertical transistors with different performance requirements. For example, semiconductor bodies 808 and 810 belong to two NMOS vertical transistors (e.g., Figure 2B 210 and 226 in FIG. 1 ), and semiconductor bodies 812 and 814 belong to two PMOS vertical transistors (eg, Figure 2B In this example, the gate conductive layers on the semiconductor bodies 808, 810, 812, and 814 may be doped accordingly so that the work function of the gate conductive layers is adjusted based on the different performance requirements of the NMOS and PMOS vertical transistors.

[0085] Fig. 9 An example of forming a source and a drain for a semiconductor body in the semiconductor layer 104 according to some aspects of the present disclosure is shown. Fig. 9 As shown, for each semiconductor body 902 of the semiconductor layer 104, the upper end 904 and the lower end 906 are doped to form a source and a drain. In some embodiments, an implantation process and / or a thermal diffusion process are performed to dope a P-type dopant or an N-type dopant into the upper end 904 and the lower end 906. In some embodiments, a silicide layer is formed on the upper end 904 and the lower end 906 by performing a silicidation process. In some embodiments, different semiconductor bodies can be doped with different types of dopants. For example, the semiconductor bodies 808 and 810 can belong to NMOS vertical transistors (e.g., Figure 2B 210 and 226 in FIG. 1 ), and semiconductor bodies 812 and 814 are PMOS vertical transistors (eg, Figure 2B 224 and 228 in the transistors 224 and 228). Therefore, semiconductor bodies 808 and 810 are doped with P-type dopants, the sources and drains of semiconductor bodies 808 and 810 are doped with N-type dopants, semiconductor bodies 812 and 814 are doped with N-type dopants, and the sources and drains of semiconductor bodies 812 and 814 are doped with P-type dopants.

[0086] Figures 10A-10F 1 shows an example of forming storage structures and interconnects in semiconductor layer 104 according to some aspects of the present disclosure. Fig. 10A As shown, semiconductor layer 104 includes three regions 710, 712, and 714. Region 710 includes vertical transistor 1004, region 712 includes vertical transistor 1006, and region 714 includes vertical transistor 1008. In some embodiments, vertical transistor 1004 in region 710 belongs to a memory cell array (e.g., Figure 1 The memory cell array 108 or Figure 4 4 and 714. The vertical memory cells in the memory cell array 402 in FIG. 4 and the vertical transistors 1008 in the region 714 belong to another memory cell array (eg, Figure 4 In some embodiments, the vertical transistor 1006 in the region 712 belongs to a peripheral circuit (e.g., Figure 1 The vertical circuit 112, Figure 4The circuit 410 or Figure 5A 1004 in the circuit 504). The vertical transistor 1006 can be coupled to the interconnect 1010. For example, the interconnect 1010 can connect some of the vertical transistors 1006 together. In another example, the interconnect 1010 can connect one or more of the vertical transistors 1006 to a memory device ( Fig. 10A 1004 and other components thereof (not shown). Interconnect 1010 may be formed by a back-end-of-line (BEOL) process. For example, substrate layer 1002 is added on top of semiconductor layer 104 and contacts the source or drain (upper end) of vertical transistor 1006. Interconnect 1010 may include a conductive material deposited by one or more thin film deposition processes, including but not limited to: CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnect may include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process.

[0087] Building the vertical memory cells in regions 710 and 714 may include building a storage structure (eg, a capacitor) for each vertical transistor (eg, vertical transistor 1004 or 1008) in regions 710 and 714. Fig. 10B As shown, a hole 1012 is etched for each of the vertical transistors 1004 and 1008 so that the upper end (source or drain) of each vertical transistor is exposed. A conductive layer (also referred to as a lower capacitor electrode) 1014 is formed on the inner surface of each hole 1012 ( Fig. 10C Then, a dielectric layer 1016 is formed on top of the conductive layer 1014 ( Fig. 10D Another conductive layer 1018 is formed on top of the dielectric layer 1016 ( Fig.10E ). Each storage structure includes a dielectric layer 1016 sandwiched between a conductive layer 1014 and a conductive layer 1018. Each conductive layer 1014 is coupled to an upper end of a corresponding vertical transistor (e.g., vertical transistor 1004 or 1008). In some embodiments, each conductive layer 1018 belongs to a common conductive structure coupled to ground.

[0088] In some embodiments, the lower ends of the vertical transistors in regions 710, 712, and 714 are also coupled to an interconnect (eg, a bit line). Fig.10F As shown, a portion of the semiconductor layer 104 is removed. For example, the bottom of the semiconductor layer 104 may be removed or thinned so that the lower ends of the vertical transistors in the regions 710, 712, and 714 are exposed. The bit line 1020 (e.g., Figure 5A ) to connect the vertical transistor 1004 in the region 710 (eg, Figure 5ASimilarly, a bit line 1022 (eg, Figure 5A 514 in the region 714) to connect the vertical transistor 1008 in the region 714 through its lower end (eg, Figure 5A Other interconnects ( 1004 ) may also be formed that are coupled to vertical transistors 1006 in region 712 through their lower ends. Fig.10F not shown).

[0089] Fig.11 1 shows a block diagram of a system 1100 having a memory device according to some aspects of the present disclosure. The system 1100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Fig.11 As shown, the system 1100 may include a host 1102 and a memory system 1104 having one or more memory devices 1108 and a memory controller 1106. The host 1102 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1102 may be configured to send data to the memory device 1108 or receive data from the memory device 1108.

[0090] Memory device 1108 may be any memory device disclosed herein, such as memory devices 100, 300, 400, and 500. In some embodiments, as described in detail above, memory device 1108 includes: a memory cell array including a vertical transistor; and a peripheral circuit including another vertical transistor.

[0091] According to some embodiments, the memory controller 1106 is coupled to the memory device 1108 and the host 1102 and is configured to control the memory device 1108. The memory controller 1106 can manage the data stored in the memory device 1108 and communicate with the host 1102. The memory controller 1106 can be configured to control the operation of the memory device 1108, such as read, write and refresh operations. The memory controller 1106 can also be configured to manage various functions related to the data stored or to be stored in the memory device 1108, including but not limited to: refresh and timing control, command / request conversion, buffering and scheduling, and power management. In some embodiments, the memory controller 1106 is also configured to determine the maximum storage capacity, the number of memory groups, the memory type and speed, the memory granule data depth and data width, and other important parameters that the computer system can use. Any other suitable function can also be performed by the memory controller 1106. The memory controller 1106 can communicate with an external device (e.g., the host 1102) according to a specific communication protocol. For example, the memory controller 1106 can communicate with an external device through at least one of various interface protocols, such as: Universal Serial Bus (USB) protocol, MultiMediaCard (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0092] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims, but as descriptions of features that can be directed to specific embodiments. In the context of separate embodiments, certain features described in this specification can also be implemented in a combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented individually or in any sub-combination in multiple embodiments. In addition, although the aforementioned features can be described as working in certain combinations and even initially claimed as such, in some cases one or more features from the claimed combination can be deleted from the combination, and the claimed combination can be directed to a sub-combination or a variant of the sub-combination.

[0093] As used in this disclosure, the terms "a", "an" or "the" are used to include one or more than one, unless the context clearly indicates otherwise. Unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure without additional definition are used for descriptive purposes only and not for limiting purposes. Any use of section headings is intended to assist in reading this document and should not be construed as limiting; information related to the section heading may appear within or outside that particular section.

[0094] As used in this disclosure, the terms "about" or "approximately" can allow for a certain degree of variability in values ​​or ranges, for example, within 10%, within 5%, or within 1% of the stated value or stated range limit.

[0095] Values ​​expressed in the form of ranges should be interpreted in a flexible manner, including not only the values ​​explicitly cited as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly cited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted as including about 0.1% to about 5%, and also includes individual values ​​(e.g., 1%, 2%, 3% and 4%) and sub-ranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the range shown. Unless otherwise specified, the statement "X to Y" has the same meaning as "about X to about Y". Similarly, unless otherwise specified, the statement "X, Y or Z" has the same meaning as "about X, about Y or about Z".

[0096] Specific embodiments of the subject matter have been described. As will be apparent to those skilled in the art, other embodiments, alternatives and permutations of the described embodiments are within the scope of the following claims. Although operations are described in a particular order in the drawings and claims, it is not required to perform these operations in the particular order shown or in a sequential order in order to achieve the desired results, or it is not required to perform all of the operations shown (some operations may be considered optional). In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and is performed when deemed appropriate.

[0097] Furthermore, the separation or integration of the various system modules and components in the previously described embodiments is not required in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0098] Therefore, the exemplary embodiments described above do not define or limit the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

[0099] According to one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first array of memory cells. Each memory cell in the first array of memory cells includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The semiconductor device also includes a first peripheral circuit, which is adjacent to the first array of memory cells in a second direction perpendicular to the first direction. The first peripheral circuit includes a second vertical transistor, which is coupled to a memory cell in the first array of memory cells through the first vertical transistor of the memory cell in the first array of memory cells.

[0100] In some embodiments, the first vertical transistor includes a first semiconductor body extending along a first direction and a first gate structure contacting at least one side of the first semiconductor body, and the second vertical transistor includes a second semiconductor body extending along the first direction and a second gate structure contacting at least one side of the second semiconductor body.

[0101] In some embodiments, the first gate structure includes a first conductive layer and a first gate dielectric layer disposed between the first conductive layer and the first semiconductor body in the second direction, and the first semiconductor body includes a first terminal and a second terminal disposed at both ends of the first semiconductor body in the first direction.

[0102] In some implementations, the first terminals are coupled to storage structures of the same memory cell.

[0103] In some embodiments, the second gate structure includes a second conductive layer and a second gate dielectric layer disposed between the second conductive layer and the second semiconductor body in the second direction, and the second semiconductor body includes a third terminal and a fourth terminal disposed at both ends of the second semiconductor body in the first direction.

[0104] In some embodiments, the material of the first conductive layer and the second conductive layer includes metal.

[0105] In some embodiments, in the second direction, a width of the first gate dielectric layer is different from a width of the second gate dielectric layer.

[0106] In some embodiments, a length of the first semiconductor body is different than a length of the second semiconductor body in the first direction.

[0107] In some embodiments, the semiconductor device further includes a second array of memory cells, each memory cell including a third vertical transistor. The first peripheral circuit is disposed between the first array of memory cells and the second array of memory cells.

[0108] In some implementations, the first peripheral circuit includes at least a portion of a sense amplifier, the sense amplifier includes a latch circuit, and the latch circuit includes a second vertical transistor.

[0109] In some embodiments, the semiconductor device further comprises: a first bit line coupled to the first array of memory cells. A row in the first array of memory cells is coupled to the first bit line through a first vertical transistor in each memory cell in the row in the first array of memory cells. A second vertical transistor is coupled to the first bit line.

[0110] In some implementations, the semiconductor device further includes: a second bit line coupled to the second array of memory cells. A row in the second array of memory cells is coupled to the second bit line through a third vertical transistor in each memory cell in the row in the second array of memory cells.

[0111] In some implementations, the first peripheral circuit further includes: a fourth vertical transistor of a different type than the second vertical transistor in the latch circuit, and the second vertical transistor and the fourth vertical transistor are coupled to the first bit line.

[0112] In some implementations, one of the second vertical transistor and the fourth vertical transistor is an N-type transistor, and the other of the second vertical transistor and the fourth vertical transistor is a P-type transistor.

[0113] In some implementations, the latch circuit further includes: a fifth vertical transistor coupled to the second vertical transistor and a sixth vertical transistor coupled to the fourth vertical transistor. The fifth vertical transistor and the sixth vertical transistor are coupled to the second bit line.

[0114] In some implementations, the fifth vertical transistor and the sixth vertical transistor are coupled to the second bit line.

[0115] In some implementations, the first peripheral circuit includes at least a portion of a word line driver.

[0116] In some embodiments, the semiconductor device further comprises: a first word line coupled to the first array of memory cells. A first column in the first array of memory cells is coupled to the first word line through a first gate structure of a first vertical transistor in each memory cell in the first column in the first array of memory cells. A second vertical transistor is coupled to the first word line.

[0117] In some embodiments, the semiconductor device further comprises: a second word line coupled to the first array of memory cells. The first peripheral circuit comprises a seventh vertical transistor. The second column in the first array of memory cells is coupled to the second word line through the first gate structure of the first vertical transistor in each memory cell in the second column in the first array of memory cells. The seventh vertical transistor is coupled to the second word line.

[0118] In some embodiments, the semiconductor device further includes a second peripheral circuit including a planar transistor. The second peripheral circuit is coupled to the first array of memory cells and the first peripheral circuit.

[0119] According to another aspect of the present disclosure, a memory device is disclosed. The memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first array of memory cells. Each memory cell in the first array of memory cells includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The first semiconductor structure also includes a first peripheral circuit, which is arranged adjacent to the first array of memory cells in a second direction perpendicular to the first direction. The first peripheral circuit includes a second vertical transistor, which is coupled to a memory cell in the first array of memory cells through the first vertical transistor of the memory cell in the first array of memory cells. The second semiconductor structure includes a second peripheral circuit coupled to the first semiconductor structure.

[0120] In some embodiments, the memory device further includes: a bonding interface between the first semiconductor structure and the second semiconductor structure.

[0121] In some implementations, the first peripheral circuit includes a first portion of a sense amplifier, the first portion of the sense amplifier includes a second vertical transistor, the second peripheral circuit includes a second portion of the sense amplifier, and the second portion of the sense amplifier includes a planar transistor.

[0122] In some implementations, the first peripheral circuit includes a first portion of a sense amplifier, the first portion of the sense amplifier includes a second vertical transistor, the second peripheral circuit includes a portion of a word line driver, and the portion of the word line driver includes a planar transistor.

[0123] According to another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first array of memory cells located in a first array region. Each memory cell in the first array of memory cells includes a first vertical transistor extending along a first direction. The semiconductor device also includes a first peripheral circuit disposed in a circuit region, the circuit region being adjacent to the first array region in a second direction perpendicular to the first direction. The first peripheral circuit includes a second vertical transistor extending along the first direction and coupled to a memory cell in the first array of memory cells through the first vertical transistor of the memory cell.

[0124] In some embodiments, the semiconductor device further includes: a second array of memory cells located in the second array region. The first peripheral circuit is disposed between the first array of memory cells and the second array of memory cells.

[0125] In some implementations, the first peripheral circuit includes at least a portion of a sense amplifier, and the portion of the sense amplifier includes a second vertical transistor.

[0126] In some embodiments, the portion of the sense amplifier also includes a third vertical transistor, a fourth vertical transistor coupled to the second vertical transistor, and a fifth vertical transistor coupled to the third vertical transistor, the second vertical transistor and the fourth vertical transistor are of the first type, and the third vertical transistor and the fifth vertical transistor are of the second type.

[0127] In some implementations, one of the second vertical transistor and the third vertical transistor is an N-type transistor, and the other of the second vertical transistor and the third vertical transistor is a P-type transistor.

[0128] In some embodiments, the semiconductor device further comprises: a first bit line coupled to a first array of memory cells. A row of the first array of memory cells is coupled to the first bit line by a first vertical transistor in each memory cell in the row of the first array of memory cells. A second vertical transistor and a third vertical transistor are coupled to the first bit line. The semiconductor device further comprises a second bit line coupled to a second array of memory cells. Each memory cell in the second array of memory cells comprises a sixth vertical transistor extending in the first direction. A row of the second array of memory cells is coupled to the second bit line by a sixth vertical transistor in each memory cell in the row of the second array of memory cells. A fourth vertical transistor and a fifth vertical transistor are coupled to the second bit line.

[0129] In some embodiments, each memory cell in the row of the first array of memory cells includes a first storage structure coupled to a corresponding first vertical transistor. The corresponding first vertical transistor is located between the first storage structure and a first bit line. Each memory cell in the row of the second array of memory cells includes a second storage structure coupled to a corresponding sixth vertical transistor. The corresponding sixth vertical transistor is located between the second storage structure and a second bit line.

[0130] In some implementations, the first peripheral circuit includes at least a portion of a word line driver.

[0131] In some embodiments, the first vertical transistor includes: a first semiconductor body extending along a first direction and a first gate structure contacting at least one side of the first semiconductor body, and the second vertical transistor includes a second semiconductor body extending along the first direction and a second gate structure contacting at least one side of the second semiconductor body.

[0132] In some embodiments, the first semiconductor body and the second semiconductor body are formed in the same process.

[0133] In some embodiments, the semiconductor device further includes a second peripheral circuit including a planar transistor. The second peripheral circuit is coupled to the first peripheral circuit.

[0134] According to another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. The method includes: forming a first semiconductor body of a first vertical transistor in a first region of a semiconductor layer, and forming a second semiconductor body of a second vertical transistor in a second region adjacent to the first region of the semiconductor layer. The first semiconductor body and the second semiconductor body are formed on a first side of the semiconductor layer. The method also includes: forming a first gate structure of the first vertical transistor and a second gate structure of the second vertical transistor. The first gate structure contacts at least one side of the first semiconductor body. The second gate structure contacts at least one side of the second semiconductor body. The method also includes: forming a first storage structure, which is located above the first end of the first semiconductor body and contacts the first end of the first semiconductor body.

[0135] In some embodiments, the method further includes forming a third semiconductor body of the third vertical transistor, and forming a third gate structure in contact with at least one side of the third semiconductor body.

[0136] In some embodiments, the method also includes: doping the semiconductor layer in the first region with a P-type dopant, doping the semiconductor layer in the first part of the second region with a P-type dopant to form a second semiconductor body, and doping the semiconductor layer in the second part of the second region with an N-type dopant to form a third semiconductor body.

[0137] In some embodiments, the method further includes: removing a portion of the semiconductor layer from the second side to expose a second end of the first semiconductor body opposite to the first end of the first semiconductor body, a first end of the second semiconductor body, and a first end of the third semiconductor body. The method further includes: forming a first bit line in contact with the second end of the first semiconductor body, the second end of the second semiconductor body, and the second end of the third semiconductor body. The first end of the second semiconductor body is coupled to the fourth vertical transistor. The first end of the third semiconductor body is coupled to the fifth vertical transistor.

[0138] In some embodiments, the method further includes: forming a fourth semiconductor body of a sixth vertical transistor in the third region. The second region is located between the first region and the third region. The method further includes: forming a fourth gate structure in contact with at least one side of the fourth semiconductor body. The method further includes: forming a second storage structure, the second storage structure being located above the first end of the fourth semiconductor body and in contact with the first end of the fourth semiconductor body.

[0139] In some embodiments, the method further includes removing a portion of the semiconductor layer from the second side to expose a second end of the fourth semiconductor body opposite to the first end of the fourth semiconductor body, and forming a second bit line contacting the second end of the fourth semiconductor body.

[0140] According to another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. The method includes: providing a semiconductor layer. The semiconductor layer includes a first region and a second region adjacent to the first region in a first direction. The method also includes: forming a first vertical transistor extending in a second direction perpendicular to the first direction in the first region of the semiconductor layer. The method also includes: forming a second vertical transistor in the second region of the semiconductor layer. The method also includes: forming a first storage structure coupled to the first vertical transistor.

[0141] In some embodiments, the method further includes doping the first region of the semiconductor layer with the first type of ions, and doping the second region of the semiconductor layer with at least one of the first type of ions or the second type of ions.

[0142] In some embodiments, forming a first vertical transistor in the first region includes: forming a first semiconductor body extending along a second direction, and forming a first gate structure contacting at least one side of the first semiconductor body. The first gate structure includes a first conductive layer and a first gate dielectric layer disposed between the first conductive layer and the first semiconductor body in the first direction.

[0143] In some embodiments, forming the second vertical transistor in the second region includes: forming a second semiconductor body extending along the second direction in the same process as forming the first semiconductor body, and forming a second gate structure contacting at least one side of the second semiconductor body in the same process as forming the first gate structure. The second gate structure includes a second conductive layer and a second gate dielectric layer disposed between the second conductive layer and the second semiconductor body in the first direction.

[0144] In some embodiments, the method further includes thinning the semiconductor layer to expose the first end of the first semiconductor body and the first end of the second semiconductor body, and forming a first bit line in contact with the first end of the first semiconductor body and the first end of the second semiconductor body.

[0145] In some implementations, forming a first storage structure coupled to the first vertical transistor includes forming the first storage structure in contact with a second end of the first semiconductor body opposite the first end of the first semiconductor body.

[0146] In some embodiments, the method further includes: forming a third vertical transistor in the second region of the semiconductor layer. The third vertical transistor is of a different type than the second vertical transistor. The third vertical transistor includes a third semiconductor body extending along the second direction. The first bit line contacts the first end of the third semiconductor body.

[0147] In some embodiments, the method further includes: forming a fourth vertical transistor and a fifth vertical transistor in the second region. A second end of the second semiconductor body opposite to the first end of the second semiconductor body is coupled to the fourth vertical transistor. A second end of the third semiconductor body opposite to the first end of the third semiconductor body is coupled to the fifth vertical transistor.

[0148] In some embodiments, the semiconductor layer includes a third region. The second region is located between the first region and the third region. The method further includes: forming a sixth vertical transistor in the third region of the semiconductor layer. The sixth vertical transistor includes a sixth semiconductor body extending along the second direction. The method further includes: forming a second storage structure coupled to the first end of the sixth semiconductor body.

[0149] In some embodiments, the method further includes forming a second bit line in contact with a second end of the sixth vertical transistor opposite the first end of the sixth semiconductor body.

[0150] The above description of specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance given herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0151] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are also within the scope of the following claims.

Claims

1. A semiconductor device comprising: a first array of memory cells, each memory cell in the first array of memory cells comprising a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction; as well as A first peripheral circuit is adjacent to the first array of memory cells in a second direction perpendicular to the first direction, wherein the first peripheral circuit includes a second vertical transistor coupled to one memory cell in the first array of memory cells through the first vertical transistor of the one memory cell in the first array of memory cells.

2. The semiconductor device according to claim 1, wherein The first vertical transistor includes a first semiconductor body extending along the first direction and a first gate structure contacting at least one side of the first semiconductor body; and The second vertical transistor includes a second semiconductor body extending along the first direction and a second gate structure contacting at least one side of the second semiconductor body.

3. The semiconductor device according to claim 2, wherein: The first gate structure includes a first conductive layer and a first gate dielectric layer disposed between the first conductive layer and the first semiconductor body in the second direction; and The first semiconductor body includes a first terminal and a second terminal disposed at both ends of the first semiconductor body in the first direction.

4. The semiconductor device according to claim 3, wherein: The second gate structure includes a second conductive layer and a second gate dielectric layer disposed between the second conductive layer and the second semiconductor body in the second direction; and In the second direction, a width of the first gate dielectric layer is different from a width of the second gate dielectric layer.

5. The semiconductor device according to claim 2, wherein: In the first direction, a length of the first semiconductor body is different from a length of the second semiconductor body.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: A second array of memory cells, each of the memory cells comprising a third vertical transistor, wherein the first peripheral circuit is disposed between the first array of memory cells and the second array of memory cells.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The first peripheral circuit includes at least a portion of a sense amplifier, the sense amplifier includes a latch circuit, and the latch circuit includes the second vertical transistor.

8. The semiconductor device according to claim 7, further comprising: coupled to a first bit line of a first array of the memory cells, wherein a row of the first array of memory cells is coupled to the first bit line through the first vertical transistor in each memory cell in the row of the first array of memory cells, and the second vertical transistor is coupled to the first bit line.

9. The semiconductor device according to claim 8, further comprising: A second bit line coupled to the second array of memory cells, wherein a row in the second array of memory cells is coupled to the second bit line through the third vertical transistor in each memory cell in the row in the second array of memory cells.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The first peripheral circuit also includes a fourth vertical transistor of a different type than the second vertical transistor in the latch circuit, and the second vertical transistor and the fourth vertical transistor are coupled to the first bit line.

11. The semiconductor device according to claim 10, wherein The latch circuit further includes a fifth vertical transistor coupled to the second vertical transistor and a sixth vertical transistor coupled to the fourth vertical transistor, wherein the fifth vertical transistor and the sixth vertical transistor are coupled to the second bit line.

12. The semiconductor device according to any one of claims 1 to 11, further comprising: A second peripheral circuit includes planar transistors, wherein the second peripheral circuit is coupled to the first array of memory cells and to the first peripheral circuit.

13. A semiconductor device comprising: a first array of memory cells located in a first array region, wherein each memory cell in the first array of memory cells comprises a first vertical transistor extending along a first direction; and A first peripheral circuit is arranged in a circuit area, and the circuit area is adjacent to the first array area in a second direction perpendicular to the first direction, wherein the first peripheral circuit includes a second vertical transistor, which extends along the first direction and is coupled to the one memory cell in the first array of the memory cells through the first vertical transistor of the one memory cell in the first array of the memory cells.

14. The semiconductor device according to claim 13, further comprising: A second array of memory cells is located in a second array region, wherein the first peripheral circuit is disposed between the first array of memory cells and the second array of memory cells.

15. A method for forming a semiconductor device, comprising: forming a first semiconductor body of a first vertical transistor in a first region of a semiconductor layer, and forming a second semiconductor body of a second vertical transistor in a second region adjacent to the first region of the semiconductor layer, wherein the first semiconductor body and the second semiconductor body are formed on a first side of the semiconductor layer; forming a first gate structure of the first vertical transistor and a second gate structure of the second vertical transistor, wherein the first gate structure contacts at least one side of the first semiconductor body and the second gate structure contacts at least one side of the second semiconductor body; and A first storage structure is formed over and in contact with the first end of the first semiconductor body.

16. The method according to claim 15, further comprising: forming a third semiconductor body of a third vertical transistor; as well as A third gate structure is formed in contact with at least one side of the third semiconductor body.

17. The method according to claim 16, further comprising: doping the semiconductor layer in the first region with a P-type dopant; doping the semiconductor layer in the first portion of the second region with the P-type dopant to form the second semiconductor body; as well as The semiconductor layer in the second portion of the second region is doped with an N-type dopant to form the third semiconductor body.

18. The method according to any one of claims 15 to 17, further comprising: removing a portion of the semiconductor layer from the second side to expose a second end of the first semiconductor body opposite to the first end of the first semiconductor body, a first end of the second semiconductor body, and a first end of the third semiconductor body; as well as A first bit line is formed in contact with the second end of the first semiconductor body, the second end of the second semiconductor body, and the second end of the third semiconductor body, wherein the first end of the second semiconductor body is coupled to a fourth vertical transistor, and wherein the first end of the third semiconductor body is coupled to a fifth vertical transistor.

19. The method according to any one of claims 15 to 18, further comprising: forming a fourth semiconductor body of a sixth vertical transistor in a third region, the second region being between the first region and the third region; forming a fourth gate structure in contact with at least one side of the fourth semiconductor body; as well as A second storage structure is formed over the first end of the fourth semiconductor body and in contact with the first end of the fourth semiconductor body.

20. The method according to any one of claims 15 to 19, further comprising: removing a portion of the semiconductor layer from the second side to expose a second end of a fourth semiconductor body opposite to the first end of the fourth semiconductor body; as well as A second bit line is formed in contact with the second end of the fourth semiconductor body.

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