Voltage balancing in half-bridge voltage converters

Abstract

A controller (102) for a voltage converter (200) includes a current mode control circuit (202) having an input. The controller (102) includes a voltage imbalance correction circuit (250) that includes a subtractor (220) configured to subtract the first voltage from the second voltage to produce a third voltage. The controller (102) also includes a transconductance circuit (222) coupled to the subtractor (220). The transconductance circuit (222) has a current output and is configured to generate a current on the current output that is proportional to a third voltage. A capacitor (CLmp) is coupled to the current output and is configured. The capacitor (Cramp) is configured to be charged by the current from the current output to generate a ramp voltage. The ramp voltage is configured to at least partially control the current mode control circuit (202).

Description

Background Art

[0001] One type of voltage converter is a half-bridge voltage converter. A half-bridge voltage converter comprises a pair of transistors coupled to the primary winding of a transformer. A pair of capacitors are coupled in series between an input voltage and a ground terminal. Nominally, the voltage on the connection between the capacitors is half the input voltage. In current mode control of a half-bridge voltage converter, a slight deviation of the voltage on the connection between the capacitors from half the input voltage may lead to an increasingly large deviation of the voltage, at which point the voltage converter can no longer be used to produce a regulated output voltage. Summary of the invention

[0002] In one example, a controller for a voltage converter includes a current mode control circuit having an input. The controller includes a voltage imbalance correction circuit, the voltage imbalance correction circuit including a subtractor, the subtractor configured to subtract a first voltage from a second voltage to generate a third voltage. The controller also includes a transconductance circuit coupled to the subtractor. The transconductance circuit has a current output and is configured to generate a current proportional to the third voltage on the current output. A capacitor is coupled to the current output and configured. The capacitor is configured to be charged by a current from the current output to generate a ramp voltage. The ramp voltage is configured to at least partially control the current mode control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a schematic diagram of a half-bridge voltage converter in one embodiment.

[0004] Figure 2 is a schematic diagram of a half-bridge voltage converter in another example that includes a voltage imbalance correction circuit to help maintain a relatively constant input voltage to one half of a capacitor.

[0005] Figure 3 is a schematic diagram of another half-bridge converter in another example, which taps the voltage across the secondary winding of the transformer and also includes a voltage imbalance correction circuit to prevent the voltage of the capacitor from deviating substantially from half the input voltage.

[0006] Figure 4 is a schematic diagram of a series resonant half-bridge converter including a voltage imbalance correction circuit in another example. DETAILED DESCRIPTION

[0007] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (functionally and / or structurally) features.

[0008] Figure 11 is a schematic diagram of an example half-bridge voltage converter 100, which includes transistors Qtop and Qbottom, a transformer T1, capacitors Ctop and Cbottom, a peak current mode control (CMC) controller 102, a current sensing circuit 108, a scaling circuit 110, a rectifier 130, an output inductor Lout, and an output capacitor Cout. The voltage converter 100 converts an input voltage Vin into an output voltage Vout for supplying a load 150.

[0009] In this example, transistors Qtop and Qbottom are n-channel field effect transistors (NFETs), but may be implemented as other types of transistors as desired. The drain of transistor Qtop is coupled to input voltage terminal 101 to receive Vin. The source of transistor Qtop is coupled to the drain of transistor Qbottom at node A. The source of transistor Qbottom is coupled to ground terminal 103. Thus, transistors Qtop and Qbottom are coupled in series between Vin and ground.

[0010] Similarly, capacitors Ctop and Cbottom are coupled in series between Vin and ground. The connection between capacitors Ctop and Cbottom is node B. In one example, the capacitance of Ctop is approximately equal to the capacitance of Cbottom. Transformer T1 includes a primary winding 121 and a secondary winding 122. The primary winding is coupled between nodes A and B.

[0011] The peak CMC controller 102 generates output signals Qtop_ON and Qbottom_ON coupled to the gates of the respective transistors Qtop and Qbottom. The peak CMC controller 102 turns on one transistor or the other (or neither) at any point in time. The peak CMC controller 102 does not turn on both transistors at the same time to avoid a shoot-through condition from Vin to ground via the transistors. The current sensing circuit 108 generates a signal 109 (e.g., a voltage) that is proportional to the current through whichever of the transistors Qtop or Qbottom is turned on at any point in time. The scaling circuit 110 scales down (or amplifies) the output voltage of the current sensing circuit and provides the scaled voltage to the peak CMC controller 102. The peak CMC controller 102 turns on the transistor Qtop and then turns it off in response to the signal 109 reaching an upper threshold. Similarly, the peak CMC controller 102 turns on the transistor Qbottom and then turns it off in response to the signal 109 reaching the same upper threshold. Therefore, each transistor is turned on individually until its current reaches an upper threshold.

[0012] In response to transistor Qtop being turned on, the voltage at node A is approximately Vin. In response to transistor Qbottom, the voltage at node A is approximately 0V. Nominally, the voltage at node B is Vin / 2. Therefore, the voltage VL across the primary winding 121 of transformer T1 is +Vin / 2 or -Vin / 2, depending on which transistor Qtop or Qbottom is turned on at any point in time. When a fixed voltage is applied to an inductor, the current through the inductor increases or decreases approximately linearly. Therefore, the current I1 through transistor Qtop increases linearly in response to transistor Qtop being turned on by the peak CMC controller 102, and the current I2 through transistor Qbottom increases linearly (although in the opposite direction to the current I1) in response to transistor Qbottom being turned on by the peak CMC controller 102. If the voltage at node B (Vcenter) is approximately Vin / 2, the absolute value of the voltage VL will be approximately the same in each half cycle (in one half cycle, Qtop is turned on, and in the other half cycle, Qbottom is turned on). In this state (Vcenter is approximately Vin / 2), the rates of change of currents I1 and I2 will be approximately equal.

[0013] However, if the voltage Vcenter deviates from Vin / 2, the voltage VL is greater in one half cycle than in the other half cycle, and therefore, the rates of change of the currents I1 and I2 will not be equal. For peak current mode control of a half-bridge voltage converter, the currents I1 and I2 will take different amounts of time to reach the threshold current. Therefore, in the half cycle where the rate of change of the current (I1 or I2) is lower, the transistor (Qtop or Qbottom) implementing that particular half cycle will be turned on longer than the other transistor in the opposite half cycle. Having different durations for the half cycles can result in a "runaway" condition, where the voltage Vcenter continues to increase (or decrease) in the same direction until eventually the voltage Vcenter becomes approximately Vin or ground and remains at that voltage.

[0014] The examples described herein are directed to a voltage imbalance correction circuit that generates a signal indicating the magnitude of the difference between the voltage (Vcenter) on node B and the value that the voltage nominally may be (which is Vin / 2). The voltage imbalance correction circuit determines an error voltage approximately equal to (Vin / 2-Vcenter), converts the error voltage to an error current, and uses the error current to charge a capacitor. The voltage on the capacitor increases (ramps up) at an approximately linear rate that is a function of the error current and therefore a function of the error voltage. The summer then adds the voltage ramp to the signal from the current sensing circuit. The CMC control circuit uses the summed signal to determine when to turn off the Qbottom or Qtop transistor that would otherwise remain on for too long due to the voltage imbalance. The summed signal enables the CMC control circuit to determine that the threshold current has been reached more quickly than if the voltage ramp were not present. The overall effect is that the voltage (Vcenter) on node B remains at its target level of approximately Vin / 2.

[0015] Figure 2 is a schematic diagram of a half-bridge voltage converter 200 in another example. Figure 2 The voltage converter 200 in the example of includes transistors Qtop and Qbottom, a transformer T1 (which includes a primary coil 121 and a secondary coil 122), capacitors Ctop and Cbottom, a CMC control circuit 202, and a voltage imbalance correction circuit 250. As described above, transistors Qtop and Qbottom are coupled in series between Vin and ground. Similarly, capacitors Ctop and Cbottom are coupled in series between Vin and ground. The primary winding 121 of the transformer T1 is coupled between nodes A and B. For simplicity, the rectifier 130, the output inductor Lout, and the output capacitor Cout are not shown, but those components or another component configuration exist and are coupled to the secondary winding 122.

[0016] The CMC control circuit 202 includes a comparator 204, a set-reset (SR) flip-flop 206, and a drive steering logic 208. The comparator has a negative (inverting, -) input and a positive (non-inverting, +) input. In this example, a signal 201 from an error amplifier (not shown) is coupled to the negative input of the comparator 204. The positive input of the comparator is coupled to the output of a summer 226 of a voltage imbalance correction circuit 250 (described below). In response to a signal 227 from the summer 226 exceeding the signal 201, the output of the comparator is activated to a logic high. The output of the comparator 204 is coupled to the reset (R) of the flip-flop 206. When the R input is asserted to a logic high, the flip-flop 206 forces its Q output to a logic low. The signal from the Q output of the flip-flop is a pulse width modulated (PWM) signal that is a logic low when the flip-flop is reset and a logic high when the flip-flop is set. The flip-flop 206 is set after receiving a rising edge from the clock 209 on the set (S) input. The PWM signal output by the comparator 206 and provided to the drive steering logic 208 switches between logic low and logic high.

[0017] The drive steering logic 208 sequentially splits the PWM pulses between the Qtop and Qbottom transistors. One pulse of PWM causes the drive steering logic 208 to force Qtop_ON high to turn on transistor Qtop. Then, the next PWM pulse causes the drive steering logic 208 to force Qbottom_ON high to turn on transistor Qbottom, and so on.

[0018] The voltage imbalance correction circuit 250 includes a transformer voltage sensor 210, a subtractor 220, transconductance circuits 222 and 224, an adder 226, a capacitor C_ramp, a switch SW1, and an inverter 228. In one example, the transformer voltage sensor 210 can be implemented as a winding on a transformer. The input of the transformer voltage sensor 210 is coupled to the opposite terminal of the primary winding 121 of the transformer. The output of the transformer voltage sensor 210 is a voltage approximately equal to the voltage across the primary winding 121. The output of the transformer voltage sensor 210 is coupled to the negative input of the subtractor 220 via an absolute value circuit 242. The absolute value circuit 242 provides a positive transformer voltage sensor output voltage (positive relative to ground) to the subtractor. The absolute value circuit converts the negative transformer voltage sensor output voltage to a positive voltage and provides this positive voltage to the subtractor 220.

[0019] The input voltage Vin is coupled to a scaling circuit 240 which scales Vin down by a factor of K. In one example, K is 0.5, so the output voltage from scaling circuit 250 is approximately Vin / 2. The scaled output voltage from scaling circuit 242 is provided to the positive input of subtractor 220.

[0020] Subtractor 220 generates an output voltage (ERR1) that is the difference between the scaled voltage and the absolute value of the voltage of the primary winding. As described above, if Vcenter is approximately equal to Vin / 2, the absolute value of the voltage across the primary winding 121 (which is provided to the negative input of the subtractor) is approximately Vin / 2. In the case where the K factor is 0.5, the voltage on the positive input of subtractor 220 is also approximately Vin / 2. Therefore, if Vcenter is approximately Vin / 2, the voltage magnitude of ERR1 can be approximately 0V. As described below, if Vcenter deviates from Vin / 2, the magnitude of ERR1 will be a function of the difference between the value (Vin / 2) that Vcenter nominally can be and the value that Vcenter actually is. The actual voltage magnitude of Vcenter is represented by the voltage across the primary winding 121.

[0021] Transconductance circuit 222 converts the voltage of ERR1 into a current IERR. The magnitude of IERR is proportional to the magnitude of the voltage of ERR1 (IERR=gm*ERR1, where gm is the transconductance of transconductance circuit 222). Therefore, IERR is proportional to the difference between the target magnitude of Vcenter (Vin / 2) and the actual magnitude of Vcenter (which may deviate from Vin / 2 due to the imbalance described above).

[0022] The current IERR from the transconductance circuit 222 is provided to the capacitor C_ramp, thereby charging the capacitor. The voltage across the capacitor is designated as Vramp, which is a linearly increasing voltage. The rate at which Vramp increases with respect to time is a function of the magnitude of the current IERR and the capacitance of the capacitor C_ramp.

[0023] Vramp is coupled to one input of the summer 226. The absolute value circuit 230 receives a voltage from the current sensing circuit 108 that indicates the current through whichever transistor is turned on in any given half cycle. The voltage is rectified by the absolute value circuit 230 and provided to the other input of the summer 226 as the primary current sensing voltage 231. The summer 226 adds Vramp to the primary current sensing voltage 231. As described above, if Vcenter deviates from Vin / 2, one of the Qtop or Qbottom of the transistor will remain longer during its half cycle than the other transistor in its half cycle. By adding Vramp to the primary current sensing voltage 231, the comparator 204 will trip faster than if Vramp is not included. The output signal of the comparator 204 will transition from a logic low to a logic high faster than it would otherwise. After the output signal of comparator 204 goes to logic high, SR flip-flop 206 will be reset and the PWM signal will be forced low, thereby terminating whichever of the Qtop or Qbottom transistors is turned on at that moment. Thus, voltage Vramp at least partially controls the operation of COM control circuit 202.

[0024] In the worst case scenario of voltage imbalance, one of the capacitors Ctop or Cbottom is charged to Vin and the other capacitor is fully discharged. Because no current flows through the transistors Qtop or Qbottom associated with the fully discharged capacitor, in one example, the equation for the value of the conductance (gm) of the transconductance circuit 222 can be given as:

[0025]

[0026] Where Ipkref is the current threshold for peak current mode control, Tsw is the switching period, and Vin_min is the minimum allowed value of Vin for which the converter is rated. Equation (1) provides the relationship between gm, C_ramp, Ipkref, Tsw, and Vin_min, and this relationship can be used to select or calculate these values.

[0027] Inverter 228 inverts the PWM signal to control the on / off state of switch SW1. Switch SW1 is closed in response to PWM being logic low, otherwise it is open (PWM being logic high). When switch SW1 is closed, capacitor C_ramp discharges to start a new switching cycle and generates another ramp voltage Vramp as needed (if Vcenter has deviated from Vin / 2). The Qbar output of flip-flop 206 can be used to control the on / off state of switch SW1, in which case inverter 228 does not have to be included.

[0028] The voltage imbalance correction circuit 250 also includes a transconductance circuit 224 that can be used for slope compensation, particularly when operating at a duty cycle greater than 50%. The transconductance circuit 224 converts an input voltage controlled by a slope compensation programming signal 225 (which can be received, for example, from a programming register or other type of programming technique) into a slope compensation current that is summed with the IERR. The combined current (IERR plus the slope compensation current from the transconductance circuit 224) charges the capacitor C_ramp. Thus, Vramp includes both slope compensation and a voltage ramp to help reduce the voltage imbalance on node B.

[0029] Figure 3 3 is a schematic diagram of an example half-bridge voltage converter 300 including a voltage imbalance correction circuit 350 that monitors the voltage across the secondary winding 122 of the transformer T1 instead of the voltage across the primary winding 121 (eg, Figure 2 2. The case of the half-bridge converter 200 of FIG. 1 ). The half-bridge converter 300 includes transistors Qtop and Qbottom, a transformer T1, capacitors Ctop and Cbottom, a CMC control circuit 202, and a voltage imbalance correction circuit 350. As described above, transistors Qtop and Qbottom are coupled in series between Vin and ground. Similarly, capacitors Ctop and Cbottom are coupled in series between Vin and ground. The primary winding 121 of the transformer T1 is coupled between nodes A and B. In this example, the rectifier 130 is a full-bridge rectifier including diodes D1, D2, D3, and D4, as shown. The rectified voltage from the secondary winding 122 is labeled Vrect and is provided to one terminal of the output inductor Lout. The rectified secondary winding voltage Vrect is also provided as an input voltage to the voltage imbalance correction circuit 350.

[0030] As described above, the voltage imbalance correction circuit 350 includes a summer 226, a switch SW1, an absolute value circuit 230, and a capacitor C_ramp. The voltage imbalance correction circuit 350 also includes transconductance circuits 330 and 334, a subtractor 320, an addition 324, capacitors Csh1 and Csh2, switches SW2 and SW3, and a scaling circuit 336. The control signal of switch SW2 is a Qtop_ON signal, and the control signal of switch SW3 is a Qbottom_ON signal. The voltage Vrect is provided to the terminals of both switches SW2 and SW3, and the other terminal of the switch is coupled to the corresponding capacitors Csh1 and Csh2, as shown. When switch SW2 is closed, Vrect charges capacitor Csh1 to a voltage approximately equal to Vrect. Similarly, when switch SW3 is closed, Vrect charges capacitor Csh2 to a voltage approximately equal to Vrect. The sum of Vrect obtained during the corresponding half cycle is approximately equal to Vin divided by the turns ratio N of transformer 122. Thus, capacitors Csh1 and Csh2 maintain a voltage of Vrect during each respective half cycle. Summer 324 adds the voltages from capacitors Csh1 and Csh2 together to generate a voltage 225 approximately equal to Vin divided by the turns ratio of transformer 122. Scaling circuit 336 applies a scaling factor K (e.g., 0.5 divided by the turns ratio N of the transformer) to produce a voltage 337 nominally proportional to Vin / 2 divided by the turns ratio N of transformer 122.

[0031] The subtractor determines Vrect minus voltage 337 (Vrect-Vin / 2*N) to generate an error voltage ERR2. ERR2 is converted to a corresponding error current by transconductance circuit 334, as described above for transconductance circuit 222. Transconductance circuit 334 converts Vout into a current. The currents from transconductance circuits 330 and 334 are added together to charge capacitor C_ramp to generate a voltage ramp Vramp. Summer 226 adds the voltage ramp Vramp to the absolute value of the current sensing voltage, and the output of summer 226 is provided to the positive input of comparator 204 within CMC control circuit 202.

[0032] Other voltage converter topologies may benefit from the principles described herein. Figure 4 is a schematic diagram showing an example of a half-bridge series resonant converter 400 using the principles described above during a possible overload condition. Figure 4The series resonant converter of the embodiment includes a controller 405, which includes a current control circuit 450. In a series resonant converter such as the series resonant converter 400, transistors Q2 and Q1 are connected in series between Vin and ground and operate mutually inversely at approximately a 50% duty cycle. The resonant tank circuit includes an inductor Lres and a capacitor Cres, which have a specific resonant frequency. The switching frequency of transistors Q1 and Q2 is set to approximately the resonant frequency. The switch node between transistors Q1 and Q2 is coupled to a transformer 421 via an inductor Lres. A rectifier circuit 425 generates an output voltage Vout.

[0033] The voltage across capacitor Cres can remain approximately equal to Vin / 2. However, if an overload condition exists, the current through one or both of transistors Q1 and Q2 may become too large. Increasing the switching frequency of transistors Q1 and Q2 can help reduce the current, but an excessive switching frequency may be required for this reason. In fact, the function of the current control circuit 450 is substantially the same as described above for the voltage imbalance correction circuit 250 to prematurely terminate the conduction of one of transistors Q1 and Q2. The current sensor 448 provides a signal (e.g., a voltage) to the absolute value circuit 452, and the output of the absolute value circuit 452 is added to the ramp voltage (Vramp) by the summer 462. The comparator 464 compares the sum of the current signal and Vramp from the absolute value circuit 452 with the reference signal Iref. If the summed value exceeds Iref, the output of the comparator resets the trigger 469 in the controller 410. The Q output of flip-flop 469 is forced low, turning off whichever transistor Q1 or Q2 is on at the moment and ensuring that the transistor's current remains at a safe level.

[0034] The voltage sensor 454 senses the voltage between the switch node and the voltage across the capacitor (the voltage difference may be Vin / 2). The sensed voltage is applied to one input of a subtractor 458 via an absolute value circuit 456. A scaled (1 / 2 times) version of Vin is applied to another input of the subtractor 458. The subtractor 458 subtracts the sensed voltage from the voltage sensor 454 (which may be Vin / 2) from the scaled Vin (Vin / 2) to generate an error signal ERR3. The transconductance circuit 460 converts the voltage ERR3 into a current to charge the capacitor Cramp1, thereby generating a ramp voltage Vramp. As described above, the switch SW41 discharges the capacitor Cramp1 at each switching cycle.

[0035] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0036] Also, in this specification, the statement “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0037] A device "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be via firmware and / or software programming of the device, via the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0038] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections or their ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0039] A circuit or device described herein as including specific components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0040] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no changes to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0041] In the claims reference may be made to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0042] Reference herein to a FET being "on" means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" means that there is no conductive channel and drain current does not flow through the FET. However, an "off" FET can allow current to flow through the body diode of the transistor.

[0043] The circuits described herein can be reconfigured to include additional or different components, thereby providing functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0044] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0045] The use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately" or "substantially" before a parameter means within the + / -10% range of the parameter.

[0046] Modifications to the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. A controller for a voltage converter, the controller comprising: a subtractor having a subtractor output and first and second subtractor inputs, the subtractor being configured to subtract a first voltage at the first subtractor input from a second voltage at the second subtractor input to provide a third voltage at the subtractor output; a transconductance circuit having a voltage input and a current output, wherein the voltage input is coupled to the subtractor output, the transconductance circuit being configured to provide a first current at the current output, and the first current being proportional to the third voltage; a capacitor coupled to the current output, wherein the capacitor is configured to be charged by the first current to provide a ramp voltage across the capacitor; a summer having a summer output and first and second summer inputs, wherein the first summer input is coupled to the capacitor, the summer being configured to receive a signal at the second summer input, and the signal being proportional to the second current; as well as logic that is coupled to the summer output.

2. The controller of claim 1, wherein the logic comprises a comparator having a comparator output and first and second comparator inputs, wherein the second comparator input is coupled to the summer output.

3. The controller according to claim 1, further comprising: a first scaling circuit coupled between a first voltage input and the first subtractor input; as well as A second scaling circuit is coupled between a second voltage input and the second subtractor input. 4 . The controller of claim 1 , wherein the subtractor is configured to provide a positive voltage or a 0 voltage but not a negative voltage.

5. The controller of claim 1, wherein the first subtractor input is coupled to a primary transformer terminal.

6. The controller of claim 1 wherein the first subtractor input is coupled to a secondary transformer terminal.

7. The controller of claim 6, wherein the summer is a first summer, the summer output being a first summer output, the capacitor being a first capacitor, and the controller further comprising: First switch; a second capacitor coupled to the first switch; Second switch; a third capacitor coupled to the second switch; and a second summer having a second summer output and third and fourth summer inputs, wherein the third summer input is coupled to the second capacitor, the fourth summer input is coupled to the third capacitor, and the second summer is configured to provide the second voltage at the second summer output. 8 . The controller of claim 1 , wherein the voltage converter comprises a half-bridge converter or a series resonant half-bridge converter.

9. A controller for a voltage converter, the controller comprising: a current mode control circuit having a control input and a control output; A voltage imbalance correction circuit, comprising: a subtractor having a subtractor output and first and second subtractor inputs, the subtractor being configured to subtract a first voltage at the first subtractor input from a second voltage at the second subtractor input to provide a third voltage at the subtractor output; a transconductance circuit having a voltage input and a current output, wherein the voltage input is coupled to the subtractor output, the transconductance circuit being configured to provide a current at the current output, and the current being proportional to the third voltage; and A capacitor is coupled to the current output and the control input, wherein the capacitor is configured to be charged by the current to provide a ramped voltage across the capacitor, and the current mode control circuit is configured to provide a signal at the control output in response to the ramped voltage.

10. The controller of claim 9, further comprising a summer having a summer input and a summer output, the summer input coupled to the capacitor and the summer output coupled to the control input.

11. The controller of claim 10 wherein the first voltage is proportional to a current through the voltage converter, the summer input is a first summer input, and the summer has a second summer input coupled to the first subtractor input.

12. The controller of claim 10, wherein the current mode control circuit comprises a comparator having a comparator output and first and second comparator inputs, and wherein the second comparator input is coupled to the summer output.

13. The controller of claim 10, wherein the summer is a first summer, the summer output is a first summer output, the capacitor is a first capacitor, and the controller further comprises: First switch; a second capacitor coupled to the first switch; Second switch; a third capacitor coupled to the second switch; as well as a second summer having a second summer output and third and fourth summer inputs, wherein the third summer input is coupled to the second capacitor, the fourth summer input is coupled to the third capacitor, and the second summer is configured to provide the second voltage at the second summer output.

14. The controller according to claim 9, wherein the third voltage is zero or positive.

15. The controller of claim 9, wherein the first subtractor input is coupled to a transformer terminal. 16 . The controller of claim 9 , wherein the voltage converter comprises a half-bridge converter or a series resonant half-bridge converter.

17. A voltage converter, comprising: a first transistor; a second transistor coupled to the first transistor; a transformer coupled to at least one of the first or second transistors; a current mode control circuit having a control input and first and second control outputs, wherein the first control output is coupled to the first transistor and the second control output is coupled to the second transistor; as well as A voltage imbalance correction circuit, comprising: a subtractor having a subtractor output and first and second subtractor inputs, the subtractor being configured to subtract a first voltage at the first subtractor input from a second voltage at the second subtractor input to provide a third voltage at the subtractor output; a transconductance circuit having a voltage input and a current output, wherein the voltage input is coupled to the subtractor output, the transconductance circuit being configured to provide a current at the current output, and the current being proportional to the third voltage; and a capacitor coupled to the current output and the control input, wherein the capacitor is configured to be charged by the current to provide a ramped voltage across the capacitor, and the current mode control circuit is configured to provide signals at the first and second control outputs in response to the ramped voltage.

18. The voltage converter of claim 17, further comprising a summer having a summer input and a summer output, the summer input coupled to the capacitor and the summer output coupled to the control input.

19. The voltage converter of claim 18, wherein the first voltage is proportional to a current through at least one of the first or second transistors, the summer input is a first summer input, and the summer has a second summer input coupled to the first subtractor input.

20. The voltage converter of claim 18, wherein the current mode control circuit comprises a comparator having a comparator output and first and second comparator inputs, and the second comparator input is coupled to the summer output.

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