Vertical transfer field effect transistor with backside source / drain connection

Abstract

A VTFET is provided on a wafer. A backside power delivery network is on the backside of the wafer. A first backside contact is connected to a bottom source / drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to the top source / drain region of the VTFET and a second portion of the backside power delivery network.

Description

Background Art

[0001] The present invention relates generally to the field of semiconductor device fabrication and, more particularly, to a vertical transfer field effect transistor (VTFET) having top and bottom source / drain regions connected to a backside power delivery network.

[0002] Semiconductor devices are manufactured by sequentially depositing insulating (dielectric), conductive, and semiconducting layers of material over a semiconductor substrate and patterning the various layers using photolithography to form circuit components and elements thereon. Typically, these semiconductor devices include multiple circuits forming an integrated circuit (IC) manufactured on a semiconductor substrate.

[0003] The VTFET device allows current to flow vertically from the bottom source / drain region to the top source / drain region. In the VTFET device, the bottom source / drain region is located closest to the wafer, the gate region is located on top of the bottom source / drain region, and the top source / drain region is located on top of the gate region. The bottom source / drain region is located closest to the wafer on which the circuit is formed, and the top source / drain region is located farthest from the wafer on which the circuit is formed. Therefore, it is necessary to contact the backside power delivery network through the top source / drain region. Summary of the invention

[0004] In a first embodiment, a vertical transfer field effect transistor (VTFET) is provided on a wafer. In the first embodiment, a backside power delivery network is on the backside of the wafer. In the first embodiment, a first backside contact is connected to a bottom source / drain region of the VTFET and a first portion of the backside power delivery network. In the first embodiment, a second backside contact is connected to a top source / drain region of the VTFET and a second portion of the backside power delivery network.

[0005] In a first embodiment, the VTFET has a first width, and wherein the first width is a contacted poly pitch (CPP). In a first embodiment, the second backside contact is at least the first width away from the VTFET. In a first embodiment, the second backside contact is twice the first width away from the VTFET. In a first embodiment, the backside power delivery network is selected from the group consisting of a clock, power, or an output signal.

[0006] Embodiments of the present invention provide increased size backside contacts to the top source / drain region to increase resistance. Embodiments of the present invention provide high drive and low resistance paths from the device to the backside power distribution network. Embodiments of the present invention provide increased area efficiency by using a single CPP for multiple connections. Embodiments of the present invention provide for distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate region of a VTFET through a backside power delivery network.

[0007] In a second embodiment, a plurality of vertical transfer field effect transistors (VTFETs) are provided on a wafer. In the second embodiment, a backside power delivery network is provided on a backside of the wafer. In the second embodiment, a first backside contact is connected to a bottom source / drain region of each VTFET of the plurality of VTFETs and a first portion of the backside power delivery network. In the second embodiment, a second backside contact is connected to a top source / drain region of each VTFET of the plurality of VTFETs and a second portion of the backside power delivery network.

[0008] In a second embodiment, a VTFET in the plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP). In a second embodiment, a second backside contact is at least the first width away from a first VTFET of the plurality of VTFETs. In a second embodiment, the second backside contact is twice the first width away from the first VTFET of the plurality of VTFETs. In a second embodiment, the first backside contact is connected to an active region layer. In a second embodiment, a backside power delivery network is selected from the group consisting of a clock, power, or an output signal. In a second embodiment, a height of the second backside contact is a height of a VTFET cell of the plurality of VTFETs.

[0009] Embodiments of the present invention provide bundled NFET and PFET devices with full cell height contacts. Embodiments of the present invention provide solutions to avoid RX or active area layers in front-side to back-side connections to obtain lower resistance. Embodiments of the present invention provide distribution or delivery of any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate regions of the VTFET through a back-side power delivery network.

[0010] In a third embodiment, the first plurality of VTFETs are in a first row on a wafer. In a third embodiment, the second plurality of VTFETs are in a second row on a wafer, and the first row is vertically adjacent to the second row. In a third embodiment, the first shared backside contact is connected to a top source / drain region of each VTFET of the first plurality of VTFETs. In a third embodiment, the second shared backside contact is connected to a top source / drain region of each VTFET of the second plurality of VTFETs. In a third embodiment, the second backside contact is connected to the first shared backside contact, the second shared backside contact, and a backside power delivery network. In a third embodiment, the backside power delivery network is on the back side of the wafer.

[0011] In a third embodiment, the first shared bottom contact connects a bottom source / drain region of each VTFET of the first plurality of VTFETs. In a third embodiment, the second shared bottom contact connects a bottom source / drain region of each VTFET of the second plurality of VTFETs. In a third embodiment, the first shared bottom contact connects to a first portion of a backside power delivery network, and wherein the second shared bottom contact connects to a second portion of the backside power delivery network.

[0012] In a third embodiment, the shared bottom contact connects a bottom source / drain region of each VTFET of the first plurality of VTFETs and a bottom source / drain region of each VTFET of the second plurality of VTFETs.In a third embodiment, the shared bottom contact connects to a backside power delivery network.

[0013] In a third embodiment, each VTFET of the first plurality of VTFETs and the second plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP). In a third embodiment, the second backside contact may be at least the first width away from a first VTFET of the plurality of first plurality of VTFETs. In a third embodiment, the second backside contact is twice the first width away from a first VTFET of the first plurality of VTFETs. In a third embodiment, the backside power delivery network is selected from the group consisting of a clock, power, or an output signal.

[0014] Embodiments of the present invention provide increased size backside contacts to the top source / drain region to increase resistance. Embodiments of the present invention provide high drive and low resistance paths from the device to the backside power distribution network. Embodiments of the present invention provide increased area efficiency by using a single CPP for multiple connections. Embodiments of the present invention provide bundled NFET and PFET devices with full cell height contacts. Embodiments of the present invention provide solutions to avoid RX or active area layers in the front-side to backside connections to obtain lower resistance. Embodiments of the present invention provide for distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate regions of a VTFET through a backside power delivery network. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and advantages of various embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings.

[0016] Figure 1 Depicted is a cross-sectional view of a VTFET semiconductor structure having frontside contacts for top source / drain regions, bottom source / drain regions, and a gate region in accordance with a first embodiment of the present invention.

[0017] Figure 2Depicted is a cross-sectional view of a VTFET semiconductor structure having frontside contacts for top source / drain and gate regions and backside contacts for bottom source / drain regions in accordance with a first embodiment of the present invention.

[0018] Figure 3 Depicted is a cross-sectional view of a VTFET semiconductor structure having frontside contacts for top source / drain and backside contacts for bottom source / drain and gate regions in accordance with a first embodiment of the present invention.

[0019] Figure 4A A top view of a semiconductor structure including four VTFETs connected in parallel according to a first embodiment of the present invention is depicted.

[0020] Figure 4B Depicted is a cross-sectional view of a portion A of a semiconductor structure including four VTFETs connected in parallel according to a first embodiment of the present invention.

[0021] Figure 5A A top view of a semiconductor structure including four VTFETs connected in parallel according to a second embodiment of the present invention is depicted.

[0022] Figure 5B Depicted is a cross-sectional view of a portion B of a semiconductor structure including four VTFETs connected in parallel according to a second embodiment of the present invention.

[0023] Fig. 6A A top view of a semiconductor structure according to a first embodiment of the present invention is depicted, depicting two sets of four VTFETs connected in parallel.

[0024] Figure 6B A semiconductor structure according to a first embodiment of the present invention is depicted Fig. 6A A cross-sectional view of portion X depicting two sets of four VTFETs connected in parallel.

[0025] Figure 6C A semiconductor structure according to a first embodiment of the present invention is depicted. Fig. 6A A cross-sectional view of portion Y depicting two sets of four VTFETs connected in parallel.

[0026] Fig. 7A A top view of a semiconductor structure according to a second embodiment of the present invention is depicted, depicting two sets of four VTFETs connected in parallel.

[0027] Figure 7B A semiconductor structure according to a second embodiment of the present invention is depicted. Fig. 7A A cross-sectional view of portion X depicting two sets of four VTFETs connected in parallel.

[0028] Figure 7C A semiconductor structure according to a second embodiment of the present invention is depicted. Fig. 7A A cross-sectional view of portion Y depicting two sets of four VTFETs connected in parallel.

[0029] Figure 8 Depicted is a top view of a semiconductor structure having a shared output region for multiple rows of semiconductor structures in accordance with a first embodiment of the present invention.

[0030] Fig. 9 Depicted is a top view of a semiconductor structure having a shared output region for multiple rows of semiconductor structures in accordance with a second embodiment of the present invention.

[0031] Fig.10 A top view of a semiconductor structure having a shared output region for multiple rows of semiconductor structures according to a third embodiment of the present invention is depicted.

[0032] Fig.11 A top view of a semiconductor structure having a shared output region for multiple rows of semiconductor structures in accordance with a fourth embodiment of the present invention is depicted. DETAILED DESCRIPTION

[0033] Embodiments of the present invention recognize that a vertical transfer field effect transistor (VTFET) has a vertical current flow. Embodiments of the present invention recognize that a VTFET includes a bottom source / drain region and a top source / drain region. Embodiments of the present invention recognize that the bottom source / drain region is closer to the back side of the VTFET (closer to the wafer), and the top source / drain region is closer to the front side of the VTFET (closer to conventional interconnect wiring). Embodiments of the present invention recognize that the input will go to one source / drain region, and the output will go to one source / drain region, and therefore one of the input or output will be on the back side of the device, and one of the input or output will be on the front side of the device. Therefore, embodiments of the present invention recognize that the top source / drain on the front side of the VTFET needs to reach the back side of the semiconductor device. Embodiments of the present invention recognize that in conventional VTFETs, the spacing (or width) between gates in adjacent devices in the same semiconductor layer is typically referred to as a contacted gate pitch (CGP) or a contacted polysilicon pitch (CPP).

[0034] Embodiments of the present invention provide increased size backside contacts to the top source / drain region to increase resistance. Embodiments of the present invention provide high drive and low resistance paths from the device to the backside power distribution network. Embodiments of the present invention provide increased area efficiency by using a single CPP for multiple connections. Embodiments of the present invention provide bundled NFET and PFET devices with full cell height contacts. Embodiments of the present invention provide solutions to avoid RX or active area layers in the front-side to backside connections to obtain lower resistance. Embodiments of the present invention provide for distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate regions of a VTFET through a backside power delivery network.

[0035] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the present disclosure have been shown. However, the present disclosure can be implemented in various ways and should not be construed as being limited to the embodiments disclosed herein. Reference will now be made in detail to embodiments of the present invention, examples of which are shown in the accompanying drawings, in which the same reference numerals represent the same elements throughout.

[0036] An overview is presented below to provide a basic understanding of one or more embodiments of the present disclosure. This summary is not intended to identify key or important elements or to delineate any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a preface to a more detailed description presented later. It should be understood that various aspects of the present invention will be described according to a given illustrative architecture; however, other architectures, structures, substrate materials, process features, and steps may vary within the scope of various aspects of the present invention.

[0037] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The present embodiment can be practiced in conjunction with integrated circuit manufacturing techniques currently used in the art, for advanced semiconductor devices, and includes only as many commonly practiced process steps as are necessary to understand the described embodiments. The accompanying drawings represent cross-sectional portions of a portion of an advanced semiconductor device after manufacture, and are not drawn to scale, but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as restrictive, but merely as a representative basis for teaching those skilled in the art to employ the methods and structures disclosed herein in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0038] It will also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0039] For the purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. The terms "covering", "above", "over", "on", "located on", or "located on top of" refer to the presence of a first element on a second element, wherein intervening elements, such as interface structures, may exist between the first element and the second element. The term "direct contact" refers to the connection of the first element and the second element without any intervening conductive, insulating or semiconducting layer at the interface of the two elements.

[0040] In order not to obscure the presentation of embodiments of the present invention, in the detailed description below, some processing steps, materials or operations known in the art may have been combined for the purpose of presentation and illustration, and may not be described in detail in some cases. In addition, for the sake of brevity and to maintain focus on the distinctive features of the elements of the present invention, the description of the materials, processes and structures previously discussed may not be repeated with respect to subsequent figures. In other cases, some known processing steps or operations may not be described. It should be understood that the following description is quite focused on the distinguishing features or elements of various embodiments of the present invention.

[0041] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or a virtual hard drive such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may transmit the resulting design to such an entity directly or indirectly by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for manufacturing photolithography masks, which typically include multiple copies of the chip design in question to be formed on a wafer. Photolithography masks are used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0042] The method as described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), bare die, or packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with either or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0043] It should also be understood that material compounds will be described in terms of listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound, for example, SiGe includes SixGe1-x, where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function according to the present principles. Compounds with additional elements will be referred to herein as alloys.

[0044] References in the specification to "one embodiment" or "an embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc. described in conjunction with the embodiment is included in at least one embodiment. Therefore, the appearance of the phrases "in one embodiment" or "in an embodiment" and any other variations appearing in various places throughout the specification do not necessarily refer to the same embodiment.

[0045] References in the specification to "one embodiment," "other embodiments," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it should be understood that it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0046] It should be understood that, for example, in the case of "A / B", "A and / or B", and "at least one of A and B", the use of any of the following " / ", "and / or", and "at least one of" is intended to cover selection of only the first listed option (A), or only the second listed option (B), or both options (A and B). As another example, in the case of "A, B, and / or C" and "at least one of A, B, and C", such wording is intended to cover selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C). Or selection of all three options (A and B and C). As will be readily apparent to one of ordinary skill in the art and related arts, this can be extended to many of the listed items.

[0047] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the example embodiments. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] For ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that in addition to the orientation shown in the figure, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as being "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "below" can include both above and below orientations. In addition, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0049] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of the present concept, the first element discussed below can be referred to as the second element.

[0050] Generally, the various processes used to form semiconductor chips are divided into four major categories, namely film deposition, removal / etching, semiconductor doping and patterning / lithography. Deposition is any process of growing, coating or otherwise transferring materials to a wafer. Available technologies include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently, atomic layer deposition ("ALD"), among others. Another deposition technique is plasma enhanced chemical vapor deposition ("PECVD"), which is a process that uses the energy within a plasma to initiate a reaction on the surface of the wafer that would otherwise require the higher temperatures associated with conventional CVD. High-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0051] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. The pattern produced by lithography or photolithography is often used to define or protect selected surfaces and portions of semiconductor structures during subsequent etching processes.

[0052] Removal is any process that removes material from a wafer, such as etching or chemical mechanical planarization ("CMP"). Examples of etching processes include wet (e.g., chemical) or dry etching processes. One example of a removal process or dry etching process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material through a physically inert gas and / or chemically reactive gas device. Like other dry plasma etching techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry etching process is reactive ion etching ("RIE"). Typically, RIE uses a chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma attack the wafer surface and react with the surface material to remove the surface material.

[0053] Deposition processes for metal liners and sacrificial materials include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which a deposited material is formed due to a chemical reaction between gaseous reactants at a temperature above room temperature (e.g., from about 25°C to about 900°C). The solid product of the reaction is deposited on the surface of the film, coating, or layer to be formed into a solid product. Variations of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metal organic CVD (MOCVD), and combinations thereof may also be employed. In alternative embodiments using PVD, the sputtering apparatus may include a DC diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In alternative embodiments using GCIB deposition, high pressure gas is allowed to expand in a vacuum and then condensed into clusters. The clusters can be ionized and directed onto the surface, providing highly anisotropic deposition.

[0054] Vertical transfer field effect transistors (VTFETs) scale semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to a viable device option for 5 nanometer (nm) nodes and larger nodes. VTFET devices include one or more fin channels with source / drain regions at the ends of the fin channels on the top and bottom sides of the fins. Current flows through the fin channels in a vertical direction (e.g., perpendicular to the substrate), for example, from the bottom source / drain region to the top source / drain region. Vertical transfer architecture devices are designed to address the limitations of horizontal device architectures in, for example, density, performance, power consumption, and integration, such as by decoupling gate length from contact gate spacing, providing fin FET equivalent density with a larger contact poly pitch (CPP), and providing lower mid-line (MOL) resistance.

[0055] In the first embodiment, Figure 1 VTFET 100 is shown having contacts 114, 124, and 134 directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 100. In a second embodiment, Figure 2 VTFET 200 is shown having contacts 214 and 234 directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 200, and contact 224 directly connected to interconnect wiring and / or a power delivery network (not shown) on the back side of VTFET 200. In a third embodiment, Figure 3A VTFET 300 is shown having a contact 314 directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of the VTFET 300, and a contact 324 and a contact 334 directly connected to interconnect wiring and / or a power delivery network (not shown) on the back side of the VTFET 300.

[0056] Figure 1 1 is a cross-sectional view of a VTFET 100 formed on a bulk substrate 102. The substrate 102 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be employed as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. In one illustrative embodiment, the substrate 102 is silicon.

[0057] VTFET 100 includes STI region 104 including a dielectric material such as silicon oxide or silicon oxynitride and is formed by methods known in the art. For example, in one illustrative embodiment, STI region 104 is a shallow trench isolation oxide layer.

[0058] The VTFET 100 includes a top source / drain region 110 and a bottom source / drain region 120 on either end of the fin 130. In an embodiment, the top source / drain region 110 is formed between dielectric layers 170. In an embodiment, the bottom source / drain region 120 is formed in the substrate 102 between shallow trench isolation regions 104. The top source / drain region 110 and the bottom source / drain region 120 are formed by, for example, an epitaxial growth process. The epitaxially grown top source / drain region 110 and the bottom source / drain region 120 may be in-situ doped, meaning that dopants are incorporated into the epitaxial film during the epitaxial process. Other alternative doping techniques may be used, including but not limited to, for example, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, etc., and the dopants may include, for example, various concentrations of n-type dopants selected from the group of phosphorus (P), arsenic (As), and antimony (Sb), and p-type dopants selected from the group of boron (B), gallium (Ga), indium (In), and thallium (Tl). For example, in a non-limiting example, the dopant concentration may range from 1x10 18 / cm 3 to 1x10 21 / cm 3According to an embodiment, the bottom source / drain region 120 may be boron-doped SiGe for a p-type field effect transistor (P-FET) or phosphorus-doped silicon for an n-type field effect transistor (N-FET). It should be understood that the term "source / drain region" as used herein means that a given source / drain region may be a source region or a drain region, depending on the application.

[0059] Terms such as "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of semiconductor material on a deposition surface of semiconductor material, wherein the grown semiconductor material has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and does not deposit material on dielectric surfaces (such as silicon dioxide or silicon nitride surfaces).

[0060] Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of the epitaxial deposition process can range from 500° C. to 900° C. Although higher temperatures generally result in faster deposition, faster deposition may result in crystal defects and film cracking.

[0061] Many different sources can be used for epitaxial growth of compressive strained layers. In some embodiments, the gas source for depositing epitaxial semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source, which includes but is not necessarily limited to silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source, which includes but is not necessarily limited to germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. An epitaxial silicon-germanium alloy layer can be formed using a combination of these gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. After epitaxial formation, a drive-in anneal can be applied to bring the dopant closer to the bottom of the fin channel.

[0062] In an embodiment, as used herein, a "semiconductor fin" or fin 130 refers to a semiconductor material including a pair of vertical sidewalls parallel to each other. As used herein, a surface is "vertical" if there is a surface deviation from a vertical plane that does not exceed three times the root mean square roughness of the surface. In an embodiment, each fin 130 has a height ranging from about 20nm to about 200nm and a width ranging from about 5nm to about 30nm. Other heights and / or widths less than or greater than the ranges mentioned herein may also be used in the present application. Each fin 130 is spaced apart from its nearest neighboring fin 130 by a pitch ranging from about 20nm to about 100nm; the pitch is measured from one point or reference surface of a semiconductor fin to the exact same point or reference surface on an adjacent semiconductor fin. In addition, the fins 130 are generally oriented parallel to each other. Although a single fin 108 is described and shown in the present application, any number of fins with gate regions surrounding them may be used, and the fins may be of any shape.

[0063] The fin 130 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be used as additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. In one illustrative embodiment, the fin 130 is silicon.

[0064] In an embodiment, a bottom spacer 140 is formed on the STI region 104 and the bottom source / drain region 120. In an embodiment, the bottom spacer 140 is formed around the fin 130. Suitable materials for the bottom spacer 140 include, for example, silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), silicon oxycarbon nitride (SiOCN), SiN, and SiO x The bottom spacer layer 140 can be deposited using, for example, a directional deposition technique, such as high density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition preferably deposits the spacer material on exposed horizontal surfaces, but not on lateral sidewalls. Alternatively, the bottom spacer layer 140 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recessing.

[0065] In an embodiment, a top spacer layer 160 is formed on the gate region between the fin 130 and the dielectric layer 170. In an embodiment, the top spacer layer 160 is formed around the fin 130. Suitable materials for the top spacer layer 160 include, for example, silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), silicon oxycarbon nitride (SiOCN), SiN, and SiO x The bottom spacer layer 140 can be deposited using, for example, a directional deposition technique, such as high density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition preferably deposits the spacer material on exposed horizontal surfaces, but not on lateral sidewalls. Alternatively, the top spacer layer 160 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recessing.

[0066] The gate region is formed on the bottom spacer layer 140 and around the fin 130. In an illustrative embodiment, the gate region is deposited on the bottom spacer layer 140 and around the fin 130 using, for example, ALD, CVD, RFCVD, plasma enhanced CVD (PECVD), physical vapor deposition (PVD), or molecular layer deposition (MLD). The gate region may include a gate dielectric layer 150 and a gate conductor layer 132. The gate dielectric layer 150 may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate conductor layer 132 may include a metal gate or a work function metal (WFM). The WFM used for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a stack including a barrier layer (e.g., a barrier layer of TiN, TaN, etc.) followed by one or more of the foregoing WFM materials, etc. It should be understood that various other materials may be used for the gate conductor layer 132 as desired.

[0067] In an embodiment, the dielectric layer 170 may be made of, for example, silicon oxide (SiO x), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-κ dielectric layer, a chemical vapor deposition (CVD) low-κ dielectric layer, or any combination thereof. As described above, the term "low-κ" as used herein refers to a material having a relative dielectric constant κ lower than that of silicon dioxide. In an embodiment, the dielectric layer 170 may be formed using a deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin coating, or sputtering.

[0068] In an embodiment, the top source / drain region 110, the bottom source / drain region 120, and the gate region are connected to interconnect wiring and / or a power delivery network (not shown) through contacts 114, 124, and 134, respectively. Figure 1 As shown, contacts 114, 124, and 134 are formed to connect directly to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 100. In an embodiment, contacts 114, 124, and 134 may include any suitable conductive material, such as, for example, copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that may be used include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques may be used to form contacts 114, 124, and 134.

[0069] In the second embodiment, Figure 2 VTFET 200 is shown having contacts 214 and 234 directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 200, and contact 224 directly connected to interconnect wiring and / or a power delivery network (not shown) on the back side of VTFET 200. In the second embodiment, VTFET 200 shares substantially similar features to those described above with reference to VTFET 100. For example, top source / drain region 210 is substantially similar to top source / drain region 110. It should be noted that although Figure 2 Not shown in Figure 1 102 shown in FIG. 1 , but those skilled in the art will appreciate that VTFET 200 will be formed on a substrate similar to Figure 1 On the substrate 102 shown in .

[0070] In the second embodiment, the orientation of the contacts in VTFET 200 is the primary difference compared to VTFET 100. In the second embodiment, contacts 214 and 234 are directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 200, and contact 224 is directly connected to interconnect wiring and / or a power delivery network (not shown) on the back side of VTFET 200.

[0071] In the third embodiment, Figure 3 VTFET 300 is shown having contact 314 directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 300, and contact 324 and contact 334 directly connected to interconnect wiring and / or a power delivery network (not shown) on the back side of VTFET 300. In the third embodiment, VTFET 300 shares substantially similar features to those described above with reference to VTFET 100 and VTFET 200. For example, top source / drain region 310 is substantially similar to top source / drain region 110 and top source / drain region 210. It should be noted that although Figure 3 Not shown in Figure 1 102 shown in FIG. 1 , but those skilled in the art will appreciate that VTFET 300 will be formed on a substrate similar to Figure 1 On the substrate 102 shown in .

[0072] In the third embodiment, the orientation of the contacts in VTFET 300 is the primary difference compared to VTFET 100 and VTFET 200. In the third embodiment, contact 314 is directly connected to the interconnect wiring and / or power delivery network (not shown) on the front side of VTFET 300, and contacts 324 and contacts 334 are directly connected to the interconnect wiring and / or power delivery network (not shown) on the back side of VTFET 300.

[0073] Figure 4A A top view of a semiconductor structure 400A including four VTFETs in parallel is depicted according to a first embodiment of the present invention. In other words, a shared input is provided to the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET, and a shared output extends from the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET. In this embodiment, the bottom source / drain region is the input and the top source / drain region is the output. In an alternative embodiment, the bottom source / drain region is the output and the top source / drain region is the input. As Figure 4A As shown, the first VTFET includes a shared bottom source / drain region 420A, a fin 430A, and a top source / drain region (not shown). Figure 4AAs shown, the second VTFET includes a shared bottom source / drain region 420A, a fin 432A, and a top source / drain region (not shown). Figure 4A As shown, the third VTFET includes a shared bottom source / drain region 420A, a fin 434A, and a top source / drain region (not shown). Figure 4A As shown, the fourth VTFET includes a shared bottom source / drain region 420A, a fin 436A, and a top source / drain region (not shown). As described above, for the sake of simplicity of the drawings, the top source / drain region of each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 420A can be connected to a backside power delivery network (not shown). In an alternative embodiment, the shared bottom source / drain region 420A can be connected to a frontside power delivery network (not shown). In an embodiment, the shared bottom source / drain region 420A can be any number of separate bottom source / drain regions connected by a shared bottom contact, such as Figure 4B , the shared bottom contact is connected to a front or back power delivery network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have a top source / drain region (not shown) connected to the shared front contact 480A. In an embodiment, the shared front contact 480A is connected to the back contact 482A. In an embodiment, the back contact 482 is connected to the back power delivery network (not shown). In an embodiment, as shown here, the shared front contact 480A extends to the left edge of the gate region 440A. In alternative embodiments, as known in the art, the shared front contact 480A can extend any horizontal distance as long as the shared front contact 480A is at least electrically connected to the top source / drain region, as described below.

[0074] like Figure 4AAs shown, in an embodiment, the first VTFET includes a gate region 440A surrounding at least a portion of the fin 430A. In an embodiment, the second VTFET includes a gate region 442A surrounding at least a portion of the fin 432A. In an embodiment, the semiconductor structure 400A includes a shared gate region 472 connected to both the gate region 440A and the gate region 442A. In an embodiment, the shared gate region 472 is connected to a gate contact 474, and the gate contact 474 is connected to a front-side or back-side power delivery network (not shown). In an alternative embodiment, the shared gate region 472 may not exist, and both the gate region 440A and the gate region 442A may have their own gate contacts (not shown) connected to the front-side or back-side power delivery network (not shown). In an embodiment, the third VTFET includes a gate region 444A surrounding at least a portion of the fin 434A. In an embodiment, the fourth VTFET includes a gate region 446A surrounding at least a portion of the fin 436A. In an embodiment, semiconductor structure 400A includes a shared gate region 476 connected to both gate region 444A and gate region 446A. In an embodiment, shared gate region 476 is connected to gate contact 478, and gate contact 478 is connected to a front-side or back-side power delivery network (not shown). In an alternative embodiment, shared gate region 476 may not be present, and both gate region 444A and gate region 446A may have their own gate contacts (not shown) that are connected to the front-side or back-side power delivery network (not shown). In another alternative embodiment, a single shared gate contact (not shown) may be connected to gate regions 440A, 442A, 444A, and 446A, and the single shared gate contact (not shown) is connected to the front-side or back-side power delivery network (not shown).

[0075] Figure 4B 4 is a cross-sectional view of a portion A of a semiconductor structure 400B including four VTFETs connected in parallel according to a first embodiment of the present invention. Figure 4B As shown, the first VTFET includes a shared bottom source / drain region 420B, a fin 430B, a top source / drain region 410B, and a gate region 440B surrounding a portion of the fin 430B. Figure 4B As shown, the second VTFET includes a shared bottom source / drain region 420B, a fin 432B, a top source / drain region 412B, and a gate region 442B surrounding a portion of the fin 432B. Figure 4B As shown, the third VTFET includes a shared bottom source / drain region 420B, a fin 434B, a top source / drain region 414B, and a gate region 444B surrounding a portion of the fin 434B. Figure 4BAs shown, the fourth VTFET includes a shared bottom source / drain region 420B, a fin 436B, a top source / drain region 416B, and a gate region 446B surrounding a portion of the fin 436B. It should be noted that in alternative embodiments, each VTFET or any combination of VTFETs may have a separate / separate bottom source / drain region connected to a backside contact 481. In an embodiment, the shared bottom source / drain region 420B is connected to the backside contact 481, and the backside contact 481 may be connected to a backside power delivery network (not shown). In an embodiment, the top source / drain regions 410B, 412B, 414B, and 416B are connected to a shared front side contact 480B. In an embodiment, the shared front side contact 480B is connected to a backside contact 482B. In an embodiment, the backside contact 482B is connected to a backside power delivery network contact 486, and the backside power delivery network contact 486 is connected to a backside power delivery network (not shown). In alternative embodiments, the backside contact 482B and the backside power delivery network contact 486 may be a single metal contact or any number of metal layers.

[0076] Figure 5A A top view of a semiconductor structure 500A including four parallel VTFETs according to a second embodiment of the present invention is depicted. In other words, a shared input is provided to the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET, and a shared output extends from the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET. In this embodiment, the bottom source / drain region is the input and the top source / drain region is the output. In an alternative embodiment, the bottom source / drain region is the output and the top source / drain region is the input. As Figure 5A As shown, the first VTFET includes a shared bottom source / drain region 520A, a fin 530A, and a top source / drain region (not shown). Figure 5A As shown, the second VTFET includes a shared bottom source / drain region 520A, a fin 532A, and a top source / drain region (not shown). Figure 5A As shown, the third VTFET includes a shared bottom source / drain region 520A, a fin 534A, and a top source / drain region (not shown). Figure 5A As shown, the fourth VTFET includes a shared bottom source / drain region 520A, a fin 536A, and a top source / drain region (not shown). As described above, for the sake of simplicity of the drawings, the top source / drain region of each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 520A can be connected to a backside power delivery network (not shown). In an alternative embodiment, the shared bottom source / drain region 520A can be connected to a frontside power delivery network (not shown). In an embodiment, the shared bottom source / drain region 520A can be composed of Figure 5B , which are connected to a front-side or back-side power delivery network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have a top source / drain region (not shown) connected to the shared front contact 580A. In an embodiment, the shared front contact 580A is connected to the back contact 582A. In an embodiment, the back contact 582 is connected to the back-side power delivery network (not shown). In an embodiment, as shown here, the shared front contact 580A extends to the left edge of the gate region 540A. In alternative embodiments, as known in the art, the shared front contact 480A can extend any horizontal distance as long as the shared front contact 580A is at least electrically connected to the top source / drain region, as described below.

[0077] like Figure 5A As shown, in an embodiment, the first VTFET includes a gate region 540A surrounding at least a portion of the fin 530A. In an embodiment, the second VTFET includes a gate region 542A surrounding at least a portion of the fin 532A. In an embodiment, the semiconductor structure 500A includes a shared gate region 572 connected to both the gate region 540A and the gate region 542A. In an embodiment, the shared gate region 572 is connected to a gate contact 574, and the gate contact 574 is connected to a front-side or back-side power delivery network (not shown). In an alternative embodiment, the shared gate region 572 may not exist, and the gate region 540A and the gate region 542A may both have their own gate contacts (not shown) that are connected to the front-side or back-side power delivery network (not shown). In an embodiment, the third VTFET includes a gate region 544A surrounding at least a portion of the fin 534A. In an embodiment, the fourth VTFET includes a gate region 546A surrounding at least a portion of the fin 536A. In an embodiment, semiconductor structure 500A includes a shared gate region 576 connected to both gate region 544A and gate region 546A. In an embodiment, shared gate region 576 is connected to gate contact 578, and gate contact 578 is connected to a front-side or back-side power delivery network (not shown). In an alternative embodiment, shared gate region 576 may not exist, and gate region 544A and gate region 546A may each have their own gate contact (not shown) that is connected to a front-side or back-side power delivery network (not shown). In another alternative embodiment, a single shared gate contact (not shown) may be connected to gate regions 540A, 542A, 544A, and 546A, and the single shared gate contact (not shown) is connected to a front-side or back-side power delivery network (not shown).

[0078] Figure 5B4 is a cross-sectional view of a portion B of a semiconductor structure 500B including four VTFETs connected in parallel according to a second embodiment of the present invention. Figure 5B As shown, the first VTFET includes a shared bottom source / drain region 520B, a fin 530B, a top source / drain region 510B, and a gate region 540B surrounding a portion of the fin 530B. Figure 5B As shown, the second VTFET includes a shared bottom source / drain region 520B, a fin 532B, a top source / drain region 512B, and a gate region 542B surrounding a portion of the fin 532B. Figure 5B As shown, the third VTFET includes a shared bottom source / drain region 520B, a fin 534B, a top source / drain region 514B, and a gate region 544B surrounding a portion of the fin 534B. Figure 5B As shown, the fourth VTFET includes a shared bottom source / drain region 520B, a fin 536B, a top source / drain region 516B, and a gate region 546B surrounding a portion of the fin 536B. It should be noted that in alternative embodiments, each VTFET or any combination of VTFETs may have a separate / separate bottom source / drain region connected to a backside contact 581. In an embodiment, the shared bottom source / drain region 520B is connected to the backside contact 581, and the backside contact 581 may be connected to a backside power delivery network (not shown). In an embodiment, the top source / drain regions 510B, 512B, 514B, and 516B are connected to a shared front side contact 580B. In an embodiment, the shared front side contact 580B is connected to the backside contact 582B. In an embodiment, the backside contact 482B is connected to the RX layer 584B. In an embodiment, the RX layer 584B may be connected to any number of other devices (not shown). In an embodiment, the RX layer 584B is connected to the backside power delivery network contact 586 , and the backside power delivery network contact 586 is connected to a backside power delivery network (not shown).

[0079] Fig. 6AA top view of a semiconductor structure 600A according to a first embodiment of the present invention is depicted, depicting two sets of four VTFETs in parallel. In other words, a shared input is provided to the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET, and a shared output extends from the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET. In addition, a shared input is provided to the fifth VTFET, the sixth VTFET, the seventh VTFET, and the eighth VTFET, and a shared output extends from the fifth VTFET, the sixth VTFET, the seventh VTFET, and the eighth VTFET. In this embodiment, the bottom source / drain region is the output, and the top source / drain region is the input. In an alternative embodiment, the bottom source / drain region is the input, and the top source / drain region is the output.

[0080] like Fig. 6A As shown, the first VTFET includes a shared bottom source / drain region 620A, a fin 630A, and a top source / drain region (not shown). Fig. 6A As shown, the second VTFET includes a shared bottom source / drain region 620A, a fin 632A, and a top source / drain region (not shown). Fig. 6A As shown, the third VTFET includes a shared bottom source / drain region 620A, a fin 634A, and a top source / drain region (not shown). Fig. 6A As shown, the fourth VTFET includes a shared bottom source / drain region 620A, a fin 636A, and a top source / drain region (not shown). As mentioned above, for the sake of simplicity of the drawing, the top source / drain region of each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 620A is connected to the Figure 6B and Figure 6C 8A. In an embodiment, the shared bottom source / drain region 620A may be any number of separate bottom source / drain regions connected by a shared bottom contact connected to the backside power delivery network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have a top source / drain region (not shown) electrically connected to the shared front side contact 608A.

[0081] like Fig. 6A As shown, the fifth VTFET includes a shared bottom source / drain region 621A, a fin 631A, and a top source / drain region (not shown). Fig. 6A As shown, the sixth VTFET includes a shared bottom source / drain region 621A, a fin 633A, and a top source / drain region (not shown). Fig. 6AAs shown, the seventh VTFET includes a shared bottom source / drain region 621A, a fin 635A, and a top source / drain region (not shown). Fig. 6A As shown, the eighth VTFET includes a shared bottom source / drain region 621A, a fin 637A, and a top source / drain region (not shown). As mentioned above, for the sake of simplicity of the drawing, the top source / drain region of each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 621A is connected to the Figure 6B and Figure 6C 9A and 9B. In an embodiment, the shared bottom source / drain region 620A may be any number of separate bottom source / drain regions connected by a shared bottom contact connected to the backside power delivery network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have a top source / drain region (not shown) electrically connected to the shared front side contact 609A.

[0082] like Fig. 6A As shown, in an embodiment, the first VTFET includes a gate region 640A surrounding at least a portion of the fin 630A. In an embodiment, the second VTFET includes a gate region 642A surrounding at least a portion of the fin 632A. In an embodiment, the third VTFET includes a gate region 644A surrounding at least a portion of the fin 634A. In an embodiment, the fourth VTFET includes a gate region 646A surrounding at least a portion of the fin 636A. In an embodiment, the fifth VTFET includes a gate region 641A surrounding at least a portion of the fin 631A. In an embodiment, the sixth VTFET includes a gate region 643A surrounding at least a portion of the fin 633A. In an embodiment, the seventh VTFET includes a gate region 645A surrounding at least a portion of the fin 635A. In an embodiment, the eighth VTFET includes a gate region 647A surrounding at least a portion of the fin 637A.

[0083] In an embodiment, semiconductor structure 600A includes a shared gate region 682A connected to gate regions 640A, 641A, 642A, 643A, 644A, 645A, 646A, and 647A. In an embodiment, shared gate region 682A is connected to gate contact 680A. In an embodiment, gate contact 680A is connected to a front-side or back-side power delivery network (not shown).

[0084] Figure 6B The semiconductor structure 600B according to the first embodiment of the present invention is depicted. Fig. 6A A cross-sectional view of a portion X of FIG. 1 depicts two sets of four VTFETs connected in parallel. Figure 6BAs shown, the first VTFET includes a shared bottom source / drain region 620B, a fin 630B, a top source / drain region 610B, and a gate region 640B surrounding a portion of the fin 630B. Figure 6B As shown, the second VTFET includes a shared bottom source / drain region 620B, a fin 632B, a top source / drain region 612B, and a gate region 642B surrounding a portion of the fin 632B. Figure 6B As shown, the third VTFET includes a shared bottom source / drain region 620B, a fin 634B, a top source / drain region 614B, and a gate region 644B surrounding a portion of the fin 634B. Figure 6B As shown, the fourth VTFET includes a shared bottom source / drain region 620B, a fin 636B, a top source / drain region 616B, and a gate region 646B surrounding a portion of the fin 636B. In an embodiment, the shared bottom source / drain region 620B is connected to a backside contact 690B, and the backside contact 690B can be connected to a backside power delivery network (not shown). It should be noted that in alternative embodiments, each VTFET or any combination of VTFETs can have a separate / separate bottom source / drain region connected to the backside contact 690B. In an embodiment, the top source / drain regions 610B, 612B, 614B, and 616B are connected to the frontside contact 608B, and the frontside contact 608B can be connected to a frontside or backside power delivery network (not shown).

[0085] Figure 6C The semiconductor structure 600C according to the first embodiment of the present invention is depicted. Fig. 6A A cross-sectional view of a portion Y of FIG. 1 depicts two sets of four VTFETs connected in parallel. Figure 6C As shown, the first VTFET includes a shared bottom source / drain region 620C, a fin 630C, a top source / drain region 610C, and a gate region 640C surrounding a portion of the fin 630C. Figure 6C As shown, the fifth VTFET includes a shared bottom source / drain region 610C, a fin 631C, a top source / drain region 611C, and a gate region 641C surrounding a portion of the fin 631C. In an embodiment, the gate region 640C and the gate region 641C are connected to the shared gate region 682A. In an embodiment, the shared gate region 682C is connected to the gate contact 680C. In an embodiment, the gate contact 680C is connected to a front side or back side power delivery network (not shown). In an embodiment, the shared bottom source / drain region 620C and the shared bottom source / drain region 621C are connected to the back side contact 690C, and the back side contact 690C can be connected to the back side power delivery network (not shown). In an embodiment, the top source / drain region 611C is connected to the front side contact 609C. In an embodiment, the top source / drain region 610C is connected to the front side contact 608C.

[0086] Fig. 7A A top view of a semiconductor structure 700A according to a second embodiment of the present invention is depicted, depicting two sets of four VTFETs in parallel. In other words, a shared input is provided to the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET, and a shared output extends from the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET. In addition, a shared input is provided to the fifth VTFET, the sixth VTFET, the seventh VTFET, and the eighth VTFET, and a shared output extends from the fifth VTFET, the sixth VTFET, the seventh VTFET, and the eighth VTFET. In this embodiment, the bottom source / drain region is the output, and the top source / drain region is the input. In an alternative embodiment, the bottom source / drain region is the input, and the top source / drain region is the output.

[0087] like Fig. 7A As shown, the first VTFET includes a shared bottom source / drain region 720A, a fin 730A, and a top source / drain region (not shown). Fig. 7A As shown, the second VTFET includes a shared bottom source / drain region 720A, a fin 732A, and a top source / drain region (not shown). Fig. 7A As shown, the third VTFET includes a shared bottom source / drain region 720A, a fin 734A, and a top source / drain region (not shown). Fig. 7A As shown, the fourth VTFET includes a shared bottom source / drain region 720A, a fin 736A, and a top source / drain region (not shown). As mentioned above, for the sake of simplicity of the drawing, the top source / drain region of each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 720A is connected to the Figure 7B and Figure 7C 8A). In an embodiment, the shared bottom source / drain region 720A may be any number of separate bottom source / drain regions connected by a shared bottom contact member connected to the backside power delivery network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have a top source / drain region (not shown) electrically connected to the shared front side contact 708A.

[0088] like Fig. 7A As shown, the fifth VTFET includes a shared bottom source / drain region 721A, a fin 731A, and a top source / drain region (not shown). Fig. 7A As shown, the sixth VTFET includes a shared bottom source / drain region 721A, a fin 733A, and a top source / drain region (not shown). Fig. 7A As shown, the seventh VTFET includes a shared bottom source / drain region 721A, a fin 735A, and a top source / drain region (not shown). Fig. 7A As shown, the eighth VTFET includes a shared bottom source / drain region 721A, a fin 737A, and a top source / drain region (not shown). As mentioned above, for the sake of simplicity of the drawing, the top source / drain region of each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 721A is connected to the Figure 7B and Figure 7C 9A and 9B. In an embodiment, the shared bottom source / drain region 720A may be any number of separate bottom source / drain regions connected by a shared bottom contact member connected to the backside power delivery network (not shown). In an embodiment, the fifth VTFET, the sixth VTFET, the seventh VTFET, and the eighth VTFET each have a top source / drain region (not shown) electrically connected to the shared front side contact 709A.

[0089] like Fig. 7A As shown, in an embodiment, the first VTFET includes a gate region 740A surrounding at least a portion of the fin 730A. In an embodiment, the second VTFET includes a gate region 742A surrounding at least a portion of the fin 732A. In an embodiment, the third VTFET includes a gate region 744A surrounding at least a portion of the fin 734A. In an embodiment, the fourth VTFET includes a gate region 746A surrounding at least a portion of the fin 736A. In an embodiment, the fifth VTFET includes a gate region 741A surrounding at least a portion of the fin 731A. In an embodiment, the sixth VTFET includes a gate region 743A surrounding at least a portion of the fin 733A. In an embodiment, the seventh VTFET includes a gate region 745A surrounding at least a portion of the fin 735A. In an embodiment, the eighth VTFET includes a gate region 747A surrounding at least a portion of the fin 737A.

[0090] In an embodiment, semiconductor structure 700A includes a shared gate region 782A connected to gate regions 740A, 741A, 742A, 743A, 744A, 745A, 746A, and 747A. In an embodiment, shared gate region 782A is connected to gate contact 780A. In an embodiment, gate contact 780A is connected to a front-side or back-side power delivery network (not shown).

[0091] Figure 7B The semiconductor structure 700B according to the second embodiment of the present invention is depicted. Fig. 7A A cross-sectional view of a portion X of FIG. 1 depicts two sets of four VTFETs connected in parallel. Figure 7BAs shown, the first VTFET includes a shared bottom source / drain region 720B, a fin 730B, a top source / drain region 710B, and a gate region 740B surrounding a portion of the fin 730B. Figure 7B As shown, the second VTFET includes a shared bottom source / drain region 720B, a fin 732B, a top source / drain region 712B, and a gate region 742B surrounding a portion of the fin 732B. Figure 7B As shown, the third VTFET includes a shared bottom source / drain region 720B, a fin 734B, a top source / drain region 714B, and a gate region 744B surrounding a portion of the fin 734B. Figure 7B As shown, the fourth VTFET includes a shared bottom source / drain region 720B, a fin 736B, a top source / drain region 716B, and a gate region 746B surrounding a portion of the fin 736B. In an embodiment, the shared bottom source / drain region 720B is connected to a backside contact 790B, and the backside contact 790B can be connected to a backside power delivery network (not shown). It should be noted that in alternative embodiments, each VTFET or any combination of VTFETs can have a separate / separate bottom source / drain region connected to the backside contact 790B. In an embodiment, the top source / drain regions 710B, 712B, 714B, and 716B are connected to the frontside contact 708B, and the frontside contact 708B can be connected to a frontside or backside power delivery network (not shown).

[0092] Figure 7C The semiconductor structure 700C according to the second embodiment of the present invention is depicted. Fig. 7A A cross-sectional view of a portion Y of FIG. 1 depicts two sets of four VTFETs connected in parallel. Figure 7C As shown, the first VTFET includes a shared bottom source / drain region 720C, a fin 730C, a top source / drain region 710C, and a gate region 740C surrounding a portion of the fin 730C. Figure 7CAs shown, the fifth VTFET includes a shared bottom source / drain region 710C, a fin 731C, a top source / drain region 711C, and a gate region 741C surrounding a portion of the fin 731C. In an embodiment, the gate region 740C and the gate region 741C are connected to the shared gate region 782A. In an embodiment, the shared gate region 782C is connected to the gate contact 780C. In an embodiment, the gate contact 780C is connected to a front side or back side power delivery network (not shown). In an embodiment, the shared bottom source / drain region 720C is connected to the back side contact 790C, and the back side contact 790C can be connected to the back side power delivery network (not shown). In an embodiment, the shared bottom source / drain region 721C is connected to the back side contact 792C, and the back side contact 792C can be connected to the back side power delivery network (not shown). In an embodiment, the top source / drain region 711C is connected to the front side contact 709C. In an embodiment, the top source / drain region 710C is connected to the front side contact 708C.

[0093] Figure 8 8 illustrates a top view of a semiconductor structure 800 according to a first embodiment of the present invention, the semiconductor structure 800 having a shared output region for multiple rows of semiconductor structures 800. Figure 8 As shown, in an embodiment, the semiconductor structure 800 includes a first row 802 of parallel VTFETs 820, 822, 824, and 826. In an embodiment, the semiconductor structure 800 includes a second row 812 of parallel VTFETs 830, 832, 834, and 836. In an embodiment, the semiconductor structure 800 includes a third row 804 of parallel VTFETs 840, 842, 844, and 846. In an embodiment, the semiconductor structure 800 includes a fourth row 814 of parallel VTFETs 850, 852, 854, and 856. In other words, each group of four parallel VTFETs includes a shared input (source / drain region or contact region) and a shared output (source / drain region or contact region). VTFETs 820, 822, 824, 826, 830, 832, 834, 836, 840, 842, 844, 846, 850, 852, 854, and 856 are similar to the VTFET structures described herein and include similar features. It should be noted that, as described above, semiconductor structure 800 represents a single structure and layout of a VTFET circuit and does not limit embodiments of the present invention to that structure and layout. In one embodiment, any other structure and layout of a VTFET circuit may be included, including but not limited to other field effect transistors, although not shown. It should be noted that for ease of discussion, Figure 8 , source / drain region contacts are not included.

[0094] In an embodiment, the first row 802 of VTFETs and the third row 804 of VTFETs include a first gate region 806. In an embodiment, the third row 812 of VTFETs and the fourth row 814 of VTFETs include a second gate region 816. In an embodiment, the first gate region 806 and the second gate region 816 are connected to a front-side or back-side power delivery network (not shown). In an embodiment, the first row 802 of VTFETs includes a first top contact 864 that is electrically connected to a top source / drain region (not shown) of each VTFET in the first row 802. In an embodiment, the second row 812 of VTFETs includes a second top contact 866 that is electrically connected to a top source / drain region (not shown) of each VTFET in the second row 812. In an embodiment, the third row 804 of VTFETs includes a third top contact 860 that is electrically connected to a top source / drain region (not shown) of each VTFET in the third row 804. In an embodiment, the fourth row 814 of VTFETs includes a fourth top contact 862 that is electrically connected to the top source / drain region (not shown) of each VTFET in the fourth row 814. In an embodiment, the first top contact 864, the second top contact 866, the third top contact 860, and the fourth top contact 862 are connected to a shared top contact 868. In an embodiment, the center of the shared top contact 868 is 1 CPP away from the center of the fins of the VTFETs 826, 830, 846, and 850. In an embodiment, the shared top contact 868 is connected to a front-side or back-side power delivery network (not shown).

[0095] Fig. 9 1 depicts a top view of a semiconductor structure 900 according to a first embodiment of the present invention, the semiconductor structure 900 having a shared output region for multiple rows of semiconductor structures 900. Fig. 9As shown, in an embodiment, the semiconductor structure 900 includes a first row 902 of parallel VTFETs 920, 922, 924, and 926. In an embodiment, the semiconductor structure 900 includes a second row 912 of parallel VTFETs 930, 932, 934, and 936. In an embodiment, the semiconductor structure 900 includes a third row 904 of parallel VTFETs 940, 942, 944, and 946. In an embodiment, the semiconductor structure 900 includes a fourth row 914 of parallel VTFETs 950, 952, 954, and 956. In other words, each group of four parallel VTFETs includes a shared input (source / drain region or contact region) and a shared output (source / drain region or contact region). VTFETs 920, 922, 924, 926, 930, 932, 934, 936, 940, 942, 944, 946, 950, 952, 954, and 956 are similar to the VTFET structures described herein and include similar features. It should be noted that, as described above, semiconductor structure 900 represents a single structure and layout of a VTFET circuit and does not limit embodiments of the present invention to that structure and layout. In embodiments, any other structure and layout of a VTFET circuit may be included, including but not limited to other field effect transistors, although not shown. It should be noted that for ease of discussion, Fig. 9 , source / drain region contacts are not included.

[0096] In an embodiment, the first row 902 of VTFETs and the third row 904 of VTFETs include a first gate region 906. In an embodiment, the third row 912 of VTFETs and the fourth row 914 of VTFETs include a second gate region 916. In an embodiment, the first gate region 906 and the second gate region 916 are connected to a front-side or back-side power delivery network (not shown). In an embodiment, the first row 902 of VTFETs includes a first top contact 964 connected to a top source / drain region (not shown) of each VTFET in the first row 902. In an embodiment, the second row 912 of VTFETs includes a second top contact 966 connected to a top source / drain region (not shown) of each VTFET in the second row 912. In an embodiment, the third row 904 of VTFETs includes a third top contact 960 connected to a top source / drain region (not shown) of each VTFET in the third row 904. In an embodiment, the fourth row 914 of VTFETs includes a fourth top contact 962 connected to a top source / drain region (not shown) of each VTFET in the fourth row 914. In an embodiment, the first top contact 964, the second top contact 966, the third top contact 960, and the fourth top contact 962 are connected to the shared top contact 868. In an embodiment, the center of the shared top contact 968 is 2CPP, with reference Figure 8This allows for a larger shared top contact 968 distance from the center of the fins of the VTFETs 926, 930, 946, and 950 than the embodiments discussed. In an embodiment, the shared top contact 968 is connected to a front-side or back-side power delivery network (not shown).

[0097] Fig.10 A top view of a semiconductor structure 1000 having a shared output region for multiple rows of semiconductor structures according to a third embodiment of the present invention is depicted. Fig.10 As shown, in an embodiment, the semiconductor structure 1000 includes a first row 1002 of parallel VTFETs 1020, 1022, 1024, and 1026. In an embodiment, the semiconductor structure 1000 includes a second row 1012 of parallel VTFETs 1030, 1032, 1034, and 1036. In an embodiment, the semiconductor structure 1000 includes a third row 1004 of parallel VTFETs 1040, 1042, 1044, and 1046. In an embodiment, the semiconductor structure 1000 includes a fourth row 1014 of parallel VTFETs 1050, 1052, 1054, and 1056. In other words, each group of four parallel VTFETs includes a shared input (source / drain region or contact region) and a shared output (source / drain region or contact region). VTFETs 1020, 1022, 1024, 1026, 1030, 1032, 1034, 1036, 1040, 1042, 1044, 1046, 1050, 1052, 1054, and 1056 are similar to the VTFET structures described herein and include similar features. It should be noted that, as described above, semiconductor structure 1000 represents a single structure and layout of a VTFET circuit and does not limit embodiments of the present invention to that structure and layout. In embodiments, any other structure and layout of a VTFET circuit may be included, including but not limited to other field effect transistors, although not shown. It should be noted that for ease of illustration, Fig.10 The discussion does not include source / drain region contacts.

[0098] In an embodiment, the first row 1002 of VTFETs and the third row 1004 of VTFETs include a first gate region 1006. In an embodiment, the third row 1012 of VTFETs and the fourth row 1014 of VTFETs include a second gate region 1016. In an embodiment, the first gate region 1006 and the second gate region 1016 connect the gate regions of the VTFETs 1020, 1022, 1024, 1026, 1030, 1032, 1034, 1036, 1040, 1042, 1044, 1046, 1050, 1052, 1054, and 1056 to a front-side or back-side power delivery network (not shown). In an embodiment, the first row 1002 of VTFETs includes a first top contact connected to a top source / drain region (not shown) of each VTFET in the first row 1002. In an embodiment, the second row 1012 of VTFETs includes a second top contact connected to a top source / drain region (not shown) of each VTFET in the second row 1012. In an embodiment, the third row 1004 of VTFETs includes a third top contact connected to a top source / drain region (not shown) of each VTFET in the third row 1004. In an embodiment, the fourth row 1014 of VTFETs includes a fourth top contact connected to a top source / drain region (not shown) of each VTFET in the fourth row 1014.

[0099] In an embodiment, the first top contact is connected to the first metal layer 1062 through the first front side metal layer contact 1074. Fig.10 As shown, in an embodiment, the shape of the first front metal layer contact 1074 is square. In alternative embodiments, the first front metal layer contact 1074 can be circular (e.g., a through hole) or any other shape. In an embodiment, the second top contact is connected to the first metal layer 1062 through the second front metal layer contact 1075. Fig.10 As shown, in an embodiment, the second front metal layer contact 1075 is square in shape. In alternative embodiments, the second front metal layer contact 1075 can be circular (e.g., a through hole) or any other shape. In an embodiment, the third top contact is connected to the second metal layer 1060 through the third front metal layer contact 1070. Fig.10 As shown, in an embodiment, the third front metal layer contact 1070 is square in shape. In alternative embodiments, the third front metal layer contact 1070 may be circular (e.g., a through hole) or any other shape. In an embodiment, the fourth top contact is connected to the second metal layer 1060 via the fourth front metal layer contact 1071. Fig.10As shown, in an embodiment, the shape of the fourth front metal layer contact 1071 is square. In alternative embodiments, the fourth front metal layer contact 1071 can be circular (e.g., a through hole) or any other shape. In an embodiment, the first metal layer 1062 and the second metal layer 1060 are metal lines in the same vertical metal layer above the contact layer.

[0100] In an embodiment, the first metal layer 1062 is connected to the shared top contact 1064 through the first shared metal layer contact 1076. Fig.10 As shown, in an embodiment, the shape of the first shared metal layer contact 1076 is a square. In alternative embodiments, the first shared metal layer contact 1076 can be circular, such as a through hole, or any other shape. In an embodiment, the second metal layer 1060 is connected to the shared top contact 1064 through the second shared metal layer contact 1072. Fig.10 As shown, in an embodiment, the second shared metal layer contact 1072 is square in shape. In alternative embodiments, the second shared metal layer contact 1072 may be circular, such as a via, or any other shape. In an embodiment, the center of the shared top contact 1064 is 1 CPP away from the center of the fin of the VTFETs 1026, 1030, 1046, and 1050. In an embodiment, the shared top contact 1064 is connected to a front-side or back-side power delivery network (not shown).

[0101] Fig.11 A top view of a semiconductor structure 1100 having a shared output region for multiple rows of semiconductor structures according to a fourth embodiment of the present invention is depicted. Fig.11As shown, in an embodiment, the semiconductor structure 1100 includes a first row 1101 of VTFETs 1110, 1111, 1112, and 1113 connected in parallel. In an embodiment, the semiconductor structure 1100 includes a second row 1102 of VTFETs 1122, 1123, 1124, and 1125 connected in parallel. In an embodiment, the semiconductor structure 1100 includes a third row 1104 of VTFETs 1114, 1115, 1116, and 1117 connected in parallel. In an embodiment, the semiconductor structure 1100 includes a fourth row 1105 of VTFETs 1126, 1127, 1128, and 1129 connected in parallel. In an embodiment, the semiconductor structure 1100 includes a fifth row 1107 of VTFETs 1118, 1119, 1120, and 1121 connected in parallel. In an embodiment, the semiconductor structure 1100 includes a sixth row 1108 of parallel VTFETs 1130, 1131, 1132, and 1133. In other words, each group of four parallel VTFETs includes a shared input (source / drain region or contact region) and a shared output (source / drain region or contact region). VTFETs 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, and 1133 are similar to the VTFET structures described herein and include similar features. It should be noted that, as described above, semiconductor structure 1100 represents a single structure and layout of a VTFET circuit, and does not limit embodiments of the present invention to this structure and layout. In embodiments, any other structure and layout of a VTFET circuit may be included, including but not limited to other field effect transistors, although not shown. It should be noted that for ease of discussion Fig.11 , source / drain region contacts are not included.

[0102] In an embodiment, the first row 1101 of VTFETs and the second row 1102 of VTFETs include a first gate region 1003. In an embodiment, the third row 1104 of VTFETs and the fourth row 1105 of VTFETs include a second gate region 1106. In an embodiment, the fifth row 1107 of VTFETs and the sixth row 1108 of VTFETs include a third gate region 1109. In an embodiment, the first gate region 1006, the second gate region 1016, and the third gate region 1109 connect the VTFETs 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, and 1133 to a front-side or back-side power delivery network (not shown). In an embodiment, the first row 1101 of VTFETs includes a first top contact connected to a top source / drain region (not shown) of each VTFET in the first row 1101. In an embodiment, the second row 1102 of VTFETs includes a second top contact connected to a top source / drain region (not shown) of each VTFET in the second row 1102. In an embodiment, the third row 1104 of VTFETs includes a third top contact connected to a top source / drain region (not shown) of each VTFET in the third row 1104. In an embodiment, the fourth row 1105 of VTFETs includes a fourth top contact connected to a top source / drain region (not shown) of each VTFET in the fourth row 1105. In an embodiment, the fifth row 1107 of VTFETs includes a fifth top contact connected to a top source / drain region (not shown) of each VTFET in the fifth row 1107. In an embodiment, the sixth row 1108 of VTFETs includes a sixth top contact connected to a top source / drain region (not shown) of each VTFET in the sixth row 1108.

[0103] In an embodiment, the first top contact is connected to the first metal layer 1140 through the first front side metal layer contact 1150. Fig.11 As shown, in an embodiment, the shape of the first front metal layer contact 1150 is square. In alternative embodiments, the first front metal layer contact 1150 can be circular (e.g., a through hole) or any other shape. In an embodiment, the second top contact is connected to the second metal layer 1142 through the second front metal layer contact 1151. Fig.11As shown, in an embodiment, the second front metal layer contact 1151 is square in shape. In alternative embodiments, the second front metal layer contact 1151 may be circular (e.g., a through hole) or any other shape. In an embodiment, the third top contact is connected to the first metal layer 1140 via the third front metal layer contact 1152. Fig.11 As shown, in an embodiment, the third front metal layer contact 1152 is square in shape. In alternative embodiments, the third front metal layer contact 1152 may be circular (e.g., a through hole) or any other shape. In an embodiment, the fourth top contact is connected to the second metal layer 1142 via the fourth front metal layer contact 1153. Fig.10 As shown, in an embodiment, the shape of the fourth front metal layer contact 1153 is square. In alternative embodiments, the fourth front metal layer contact 1153 can be circular (e.g., a through hole) or any other shape. In an embodiment, the fifth top contact is connected to the third metal layer 1146 through the fifth front metal layer contact 1154. Fig.11 As shown, in an embodiment, the fifth front metal layer contact 1154 is square in shape. In alternative embodiments, the fifth front metal layer contact 1154 may be circular (e.g., a through hole) or any other shape. In an embodiment, the sixth top contact is connected to the fourth metal layer 1144 via the sixth front metal layer contact 1155. Fig.11 As shown, in an embodiment, the shape of the sixth front metal layer contact 1155 is square. In alternative embodiments, the sixth front metal layer contact 1155 can be circular (e.g., a through hole) or any other shape. In an embodiment, the first metal layer 1140, the second metal layer 1142, the third metal layer 1146, and the fourth metal layer 1144 are on the same metal level. In an embodiment, the first metal layer 1140, the second metal layer 1142, the third metal layer 1146, and the fourth metal layer 1144 are metal lines in the same vertical metal layer above the contact layer.

[0104] In an embodiment, the first metal layer 1140 is connected to the shared bottom contact 1148 through the bottom contact 1156. Fig.11 As shown, in an embodiment, the shape of the bottom contact 1156 is square. In alternative embodiments, the first shared bottom contact 1156 can be circular, such as a through hole, or any other shape. In an embodiment, the center of the shared bottom contact 1148 is 1 CPP away from the center of the fin of the VTFET 1113, 1114. In an embodiment, the shared bottom contact 1148 is connected to the backside power delivery network (not shown). In an embodiment, the second metal layer 1142 is connected to the shared bottom contact 1148 through the bottom contact 1157. As shown in FIG. Fig.10As shown, in an embodiment, the shape of the bottom contact 1157 is square. In alternative embodiments, the bottom contact 1157 can be circular, such as a through hole, or any other shape. In an embodiment, the center of the shared bottom contact 1148 is 1 CPP away from the center of the fin of the VTFET 1125, 1126. In an embodiment, the shared bottom contact 1148 is connected to the backside power delivery network (not shown).

[0105] In an embodiment, the third metal layer 1146 is connected to the metal layer two 1160 through a contact (not shown). In an embodiment, the contact (not shown) may be at least partially within a vertical plane of the fifth front metal layer contact 1154. In an embodiment, the fourth metal layer 1144 is connected to the metal layer two 1160 through a contact (not shown). In an embodiment, the contact (not shown) may be at least partially within a vertical plane of the sixth front metal layer contact 1155. In an embodiment, the metal layer two 1160 is on a metal layer above the metal layers of the first metal layer 1140, the second metal layer 1142, the third metal layer 1146, and the fourth metal layer 1144. In an embodiment, the metal layer two 1160 is connected to the first metal layer 1140 and / or the second metal layer 1142 through a contact (not shown). In an embodiment, the metal layer two 1160 is connected to the shared bottom contact 1148 by connecting the metal layer two 1160 to the first metal layer 1140 or the second metal layer 1142. It should be noted that any number of contact configurations may be used to connect an upper metal layer to a lower metal layer, as is known in the art, including other metal contacts and / or lines on metal layers above and / or below the metal layers shown for illustrative purposes.

[0106] The description of various embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device, comprising: Vertical transfer field effect transistors (VTFETs) on wafers; a backside power delivery network on a backside of the wafer; a first backside contact, wherein the first backside contact is connected to a bottom source / drain region of the VTFET and a first portion of the backside power delivery network; as well as A second backside contact, wherein the second backside contact is connected to a top source / drain region of the VTFET and a second portion of the backside power delivery network.

2. The semiconductor device according to claim 1, further comprising: wherein the VTFET has a first width, and wherein the first width is a contacted poly pitch (CPP); and The second backside contact is spaced at least the first width from the VTFET.

3. The semiconductor device according to claim 1, further comprising: wherein the VTFET has a first width, and wherein the first width is a contacted poly pitch (CPP); and The second backside contact is twice as far away from the VTFET as the first width. 4 . The semiconductor device according to claim 1 , wherein a height of the second backside contact is a height of a cell of the VTFET.

5. The semiconductor device according to claim 1, wherein The first backside contact is connected to the active area layer.

6. The semiconductor device according to claim 1, wherein The backside power delivery network is selected from the group consisting of a clock, power, or an output signal.

7. A semiconductor device comprising: a plurality of vertical transfer field effect transistors (VTFETs) on a wafer; a backside power delivery network on a backside of the wafer; a first backside contact, wherein the first backside contact is connected to a bottom source / drain region of each VTFET of the plurality of VTFETs and a first portion of the backside power delivery network; as well as A second backside contact, wherein the second backside contact is connected to a top source / drain region of each VTFET of the plurality of VTFETs and a second portion of the backside power delivery network.

8. The semiconductor device according to claim 7, further comprising: wherein each VTFET of the plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP); and The second backside contact is spaced at least the first width from a first VTFET of the plurality of VTFETs.

9. The semiconductor device according to claim 7, further comprising: wherein each VTFET of the plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP); and The second backside contact is spaced two times the first width from a first VTFET of the plurality of VTFETs. 10 . The semiconductor device according to claim 7 , wherein a height of the second backside contact is a height of a VTFET cell of the plurality of VTFETs. 11 . The semiconductor device of claim 7 , wherein the first backside contact is connected to an active region layer.

12. The semiconductor device of claim 7, wherein the backside power delivery network is selected from the group consisting of a clock, power, or an output signal.

13. The semiconductor device according to claim 7, further comprising: wherein each VTFET of the plurality of VTFETs has a top source / drain region connected to a shared backside contact; and The shared back side contact is connected to the second back side contact.

14. A semiconductor device comprising: a first plurality of vertical transfer field effect transistors (VTFETs) in a first row on the wafer; a second plurality of VTFETs in a second row on the wafer, wherein the first row is vertically adjacent to the second row; a backside power delivery network on a backside of the wafer; a first shared backside contact over the first plurality of VTFETs, wherein the first shared backside contact is connected to a top source / drain region of each VTFET of the first plurality of VTFETs; a second shared backside contact over the second plurality of VTFETs, wherein the second shared backside contact is connected to a top source / drain region of each VTFET of the second plurality of VTFETs; as well as A second back side contact, wherein the second back side contact is connected to the first shared back side contact, the second shared back side contact and the back side power delivery network.

15. The semiconductor device according to claim 14, further comprising: a first shared bottom contact connected to a bottom source / drain region of each VTFET of the first plurality of VTFETs; as well as a second shared bottom contact connected to a bottom source / drain region of each VTFET of the second plurality of VTFETs; and Wherein the first shared bottom contact is connected to a first portion of the backside power delivery network, and wherein the second shared bottom contact is connected to a second portion of the backside power delivery network.

16. The semiconductor device according to claim 14, further comprising: a shared bottom contact connecting a bottom source / drain region of each VTFET of the first plurality of VTFETs and a bottom source / drain region of each VTFET of the second plurality of VTFETs; and Wherein the shared bottom contact is connected to the backside power delivery network.

17. The semiconductor device according to claim 14, further comprising: wherein each VTFET of the first plurality of VTFETs and the second plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP); and Wherein the second backside contact is spaced at least the first width from a first VTFET in the first plurality of VTFETs.

18. The semiconductor device according to claim 14, further comprising: wherein each VTFET of the first plurality of VTFETs and the second plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP); and The second backside contact is spaced two times the first width from a first VTFET of the first plurality of VTFETs.

19. The semiconductor device according to claim 14, wherein: The backside power delivery network is selected from the group consisting of a clock, power, or an output signal.

20. The semiconductor device according to claim 14, further comprising: a first metal line in a first metal layer, wherein the first metal line is over a first shared backside contact; a second metal line in the first metal layer, wherein the second metal line is a second shared backside contact; a first connection between the first metal line and the first shared backside contact; a second connection between the second metal line and the second shared backside contact; and The first metal line and the second metal line are connected to the backside power delivery network.

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