Method for inspecting display panel and method for inspecting display device

Abstract

The invention discloses a method for inspecting a display panel and a method for inspecting a display device. The method for inspecting the display device includes: forming a backplane, an organic light emitting layer, an encapsulation layer, and a polarizing film in a display area; bonding a driver circuit to the non-display area, and covering the driver circuit with a protective layer; coating a shielding resin between the polarizing film and the protective layer, and coating a test pattern made of the same material as that of the shielding resin to a dummy area of the non-display area; irradiating the test pattern with ultraviolet light using an illumination device, and determining an angle and an amount of light of the illumination device that causes the ultraviolet light reflected from the test pattern to satisfy a specified optical condition; irradiating the shielding resin with ultraviolet light based on the determined angle and light amount; and determining whether the shielding resin is properly coated by analyzing the ultraviolet light reflected from the shielding resin.

Description

Technical Field

[0001] Embodiments relate to a method for inspecting a display panel and a method for inspecting a display device. Background Art

[0002] With the development of information society, various demands on display devices are increasing. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode as a light-emitting element or an inorganic light-emitting display device including an inorganic light-emitting diode as a light-emitting element.

[0003] Display devices are widely using display panels using flexible substrates. Display panels using flexible substrates can be bent, folded or curled, and can therefore be applied to electronic devices of various form factors. The display panel using a flexible substrate includes a display area that is substantially flat and displays an image and a non-display area arranged outside the display area, and the driver circuit is joined at the non-display area. When the display panel is observed from the top (or in a plan view), a portion of the non-display area can be bent toward the back side of the display panel to reduce the frame width. The portion of the non-display area of ​​the display panel can be covered by a protective layer so that damage can be prevented. In the display panel, a shielding resin is applied at the boundary between the covering area covered by the protective layer and the polarizing film of the display area to prevent damage to the display panel caused by the introduction of static electricity. In the case where the shielding resin is not properly applied at the boundary between the covering area covered by the protective layer and the polarizing film of the display area, damage to the display panel may occur due to the introduction of static electricity. In view of the above, what is needed is a technology for easily checking whether the shielding resin is properly applied. Summary of the invention

[0004] Aspects of the present disclosure provide a method for inspecting a display panel and a method for inspecting a display device, which provide a convenient and accurate inspection for verifying whether a shielding resin is properly applied. The shielding resin can prevent damage to the display panel due to the introduction of static electricity.

[0005] According to an embodiment, a method for inspecting a display device may include: forming a backplane, an organic light-emitting layer, an encapsulation layer, and a polarizing film in a display area of ​​a substrate; bonding a driver circuit to a non-display area of ​​the substrate, and covering the driver circuit with a protective layer; applying a shielding resin to a boundary area between the polarizing film and the protective layer, and applying a test pattern made of the same material as the shielding resin to a dummy area of ​​the non-display area disposed at an outermost position of the substrate; irradiating the test pattern with ultraviolet light using an illumination device, and determining an angle and an amount of light of the illumination device at which ultraviolet light reflected from the test pattern satisfies specified optical conditions; irradiating the shielding resin with ultraviolet light based on the determined angle and the determined amount of light; and determining whether the shielding resin is properly coated by analyzing the ultraviolet light reflected from the shielding resin.

[0006] The non-display area may include a bending area bent to overlap with the display area, wherein the driver circuit is engaged in the bending area. The bending area may include: a shielding area, a plurality of fan-out lines extending from the display area to the driver circuit and a shielding resin covering the plurality of fan-out lines are provided at the shielding area; and a dummy area provided at each of the ends of the shielding area.

[0007] The fan-out line may not be disposed in the dummy region.

[0008] Determining the angle and light amount of the lighting device so that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions may include: setting multiple optical conditions as a combination of multiple angle conditions related to the angle of the lighting device and multiple light amount conditions related to the light amount of the lighting device; irradiating ultraviolet light to the substrate according to each of the optical conditions, and measuring the first reflected light reflected from the polarizing film, the second reflected light reflected from the test pattern, and the third reflected light reflected from the protective layer; calculating the average value of the first reflected light and the third reflected light, and calculating the deviation between the second reflected light and the calculated average value of the first reflected light and the third reflected light; and calculating the deviation between the second reflected light and the average value for each of the optical conditions, and determining that the optical condition with the smallest deviation between the second reflected light and the average value satisfies the specified optical condition.

[0009] For each wafer group manufactured under the same conditions, determination of the angle and light amount of the illumination device such that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions is performed.

[0010] Determination of the angle and light amount of the lighting device such that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions is performed for each batch manufactured under the same conditions.

[0011] For each unit manufactured under the same conditions, determination of the angle and light amount of the lighting device such that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions is performed.

[0012] The angle condition related to the angle of the lighting device may be set within a range of about 10 degrees to about 30 degrees.

[0013] The light quantity condition related to the light quantity of the lighting device may be set within a range of about 10W to about 30W.

[0014] The determination of whether the shielding resin is properly applied may include: calculating irregularities of ultraviolet light reflected from the shielding resin; and determining that the shielding resin is not properly applied if the irregularities exceed a reference threshold.

[0015] According to an embodiment, a method for inspecting a display panel may include: forming a backplane, an organic light-emitting layer, an encapsulation layer, and a polarizing film in a display area of ​​a substrate; bonding a driver circuit to a non-display area of ​​the substrate, and covering the driver circuit with a protective layer; applying a shielding resin to a boundary area between the polarizing film and the protective layer, and applying a test pattern made of the same material as the shielding resin to a dummy area of ​​the non-display area disposed at an outermost position of the substrate; irradiating the test pattern with ultraviolet light using an illumination device, and determining an angle and an amount of light of the illumination device at which ultraviolet light reflected from the test pattern satisfies specified optical conditions; irradiating the shielding resin with ultraviolet light based on the determined angle and the determined amount of light; and determining whether the shielding resin is properly coated by analyzing the ultraviolet light reflected from the shielding resin.

[0016] The non-display area may include a bending area bent to overlap with the display area, wherein the driver circuit is engaged in the bending area. The bending area may include: a shielding area, a plurality of fan-out lines extending from the display area to the driver circuit and a shielding resin covering the plurality of fan-out lines are provided at the shielding area; and a dummy area provided at each of the ends of the shielding area.

[0017] The fan-out line may not be disposed in the dummy region.

[0018] Determining the angle and light amount of the lighting device so that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions may include: setting multiple optical conditions as a combination of multiple angle conditions related to the angle of the lighting device and multiple light amount conditions related to the light amount of the lighting device; irradiating ultraviolet light to the substrate according to each of the optical conditions, and measuring the first reflected light reflected from the polarizing film, the second reflected light reflected from the test pattern, and the third reflected light reflected from the protective layer; calculating the average value of the first reflected light and the third reflected light, and calculating the deviation between the second reflected light and the average value of the first reflected light and the third reflected light; and calculating the deviation between the second reflected light and the average value for each of the optical conditions, and determining that the optical condition with the smallest deviation between the second reflected light and the average value satisfies the specified optical condition.

[0019] For each wafer group manufactured under the same conditions, determination of the angle and light amount of the illumination device such that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions is performed.

[0020] Determination of the angle and light amount of the lighting device such that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions is performed for each batch manufactured under the same conditions.

[0021] For each unit manufactured under the same conditions, determination of the angle and light amount of the lighting device such that the ultraviolet light reflected from the test pattern satisfies the specified optical conditions is performed.

[0022] The angle condition related to the angle of the lighting device may be set within a range of about 10 degrees to about 30 degrees.

[0023] The light quantity condition related to the light quantity of the lighting device may be set within a range of about 10W to about 30W.

[0024] The determination of whether the shielding resin is properly applied may include: calculating irregularities of ultraviolet light reflected from the shielding resin; and determining that the shielding resin is not properly applied if the irregularities exceed a reference threshold.

[0025] According to the embodiments of the present disclosure, it may be easily checked whether the shielding resin is properly applied, which prevents damage to the display panel due to introduction of static electricity in the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0028] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment.

[0029] Figure 3 is a schematic diagram conceptually illustrating a display unit and a touch driver according to an embodiment.

[0030] Figure 4 is a schematic plan view showing a display unit of a display device according to an embodiment.

[0031] Figure 5 is a schematic plan view showing a touch unit of a display device according to an embodiment.

[0032] Figure 6 yes Figure 5 An enlarged schematic diagram of area A1.

[0033] Figure 7 is an enlarged schematic diagram showing a part of the display device according to the embodiment.

[0034] Figure 8 It is along Figure 7 A schematic cross-sectional view of a display device according to an embodiment taken along line II'.

[0035] Fig. 9 is a schematic diagram showing a part of the exterior of a display panel according to an embodiment.

[0036] Fig.10 is a diagram illustrating a portion of a dummy area of ​​a display panel according to an embodiment, along Fig. 9 Schematic cross-sectional view taken along line AA'.

[0037] Fig.11 is a diagram illustrating a portion of a boundary area between an encapsulation area of ​​an encapsulation layer provided on a display panel and a covering area of ​​a protective layer according to an embodiment, along Fig. 9 Schematic cross-sectional view taken along line BB'.

[0038] Fig.12 It is along Fig. 9 Schematic cross-sectional view taken along line CC'.

[0039] Fig.13 is a flowchart for illustrating a method of testing a display panel according to an embodiment.

[0040] Fig.14 is a schematic diagram showing optical characteristics measured from each of an encapsulation region of an encapsulation layer, a covering region of a protection layer, and a boundary region provided therebetween. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor do they need to limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0042] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0043] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of cross-hatching or shading will not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0044] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical connection, electrical connection, and / or fluid connection with or without an intervening element. For the purposes of this disclosure, "at least one of A and B" may be understood to refer to only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0045] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0046] Spatially relative terms such as "below," "beneath," "under," "below," "above," "on," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes to describe the relationship of one element to another (or some) elements as illustrated in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the term "below" can include both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore the spatially relative descriptors used herein should be interpreted accordingly.

[0047] The term used herein is used to describe the purpose of a particular embodiment, and is not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular form "one" and "the / said" are intended to also include plural forms. In addition, when used in this specification, the term "includes" and / or "comprising" and its variants specify the existence of the feature, integral body, step, operation, element, part and / or its group, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or its group. It should also be noted that, as used in this article, the term "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, and are therefore used to explain the measured values, calculated values ​​and / or the inherent deviation of the provided value that those of ordinary skill in the art will recognize.

[0048] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations, which are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein need not necessarily be construed as limited to the shapes of the particular illustrated zones, but will include deviations in shapes resulting from, for example, manufacturing. In this way, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and therefore, are not necessarily intended to be limiting.

[0049] According to the convention in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also expected that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0050] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0051] Figure 1 is a schematic perspective view of a display device according to an embodiment. Figure 2 is a schematic cross-sectional view of a display device according to an embodiment.

[0052] In the drawings, the first direction X refers to a direction parallel to one side of the display device 10 when viewed from the top (or in a plan view), for example, the direction of the shorter side of the display device 10. The second direction Y refers to a direction parallel to another side of the display device 10 intersecting the side when viewed from the top (or in a plan view), for example, the direction of the longer side of the display device 10. The third direction Z refers to the thickness direction of the display device 10. It should be understood that the directions indicated in the embodiments are relative directions, and the embodiments are not limited to the mentioned directions.

[0053] The display device 10 may include various electronic devices that provide a display screen. For example, the display device 10 may be adopted by portable electronic devices such as mobile phones, smart phones, tablet PCs, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be used as a display unit DU of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IOT) device. For example, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted display (HMD) devices.

[0054] refer to Figure 1 , when viewed from the top (or in a plan view), the display device 10 may have a shape similar to a rectangle. For example, when viewed from the top (or in a plan view), the display device 10 may have a shape similar to a quadrilateral having a shorter side in the first direction X and a longer side in the second direction Y. The corner where the shorter side in the first direction X intersects the longer side in the second direction Y may be rounded with a selected curvature, or may be a right angle. The shape of the display device 10 when viewed from the top (or in a plan view) is not limited to a rectangular shape, but may have a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0055] At least one of the front surface and the rear surface of the display device 10 may be a display surface. For example, the front surface refers to a surface located on one side of a plane, for example, a surface located on the side indicated by an arrow of the third direction Z in the drawings. The rear surface refers to a surface located on the opposite side of a plane, for example, a surface located on the opposite side of the side indicated by an arrow of the third direction Z in the drawings. The display device 10 may be a double-sided display device 10 in which images are displayed on both the front surface and the rear surface. In the following description, according to an embodiment, the display surface may be located on the front side of the display device 10.

[0056] The display device 10 may include a display panel 100 providing a display screen, a display driver 200, a circuit board 300, and a touch driver 400. The touch driver 400 may be an element sensing a user's touch input and may be referred to as a 'touch detection device'.

[0057] When viewed from the top (or in a plan view), the display panel 100 may have a shape similar to a rectangular shape. For example, when viewed from the top, the display panel 100 may have a shape similar to a quadrilateral having a shorter side in a first direction X and a longer side in a second direction Y. The corner where the shorter side in the first direction X intersects with the longer side in the second direction Y may be rounded with a selected curvature, or may be a right angle. The shape of the display panel 100 when viewed from the top (or in a plan view) is not limited to a rectangular shape, but may have a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. For example, the display panel 100 may be formed to be flexible so that it can be bent or folded.

[0058] The display panel 100 may include a main area MA and an auxiliary area (or a bending area) SBA.

[0059] The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA located around the display area DA. The display area DA may output light from an emission area or an opening area. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0060] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be defined as an edge portion of the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line of the display panel 100.

[0061] The auxiliary area SBA may extend from one side of the main area MA. The auxiliary area SBA may be bent so that the auxiliary area SBA may overlap with the main area MA in the third direction Z. The auxiliary area SBA may include pads connected (eg, electrically connected) to the display driver 200 and the circuit board 300.

[0062] In some embodiments, the non-display area NDA may be included not only in the main area MA but also in the auxiliary area SBA. For example, the non-display area NDA may extend from the main area MA to the auxiliary area SBA and may include all areas except the display area DA.

[0063] refer to Figure 2 , the display panel 100 may include a display unit DU and a touch unit TSU.

[0064] The display unit DU may include pixels PX (see Figure 3). Each of the pixels PX may be a unit for displaying an image. A pixel (e.g., a single pixel) PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, but the embodiment is not limited thereto. When viewed from the top (or in a plan view), the pixels PX may be arranged alternately. For example, the pixels PX may be arranged in a matrix, but the embodiment is not limited thereto.

[0065] The touch unit TSU may be disposed on the display unit DU, but the embodiment is not limited thereto. For example, the touch unit TSU may be formed together with the display unit DU using an in-cell touch technology. The touch unit TSU may include a touch electrode SEN (e.g., Figure 5 The sensing electrodes RE and the driving electrodes TE in the touch driver 400 are connected to the driving electrodes TE and the touch driving lines TL (see FIG. Figure 5 ) and a touch sensing line RL (see Figure 5 ). The touch unit TSU may be a layer for detecting a touch input and may work as a touch member. The touch unit TSU may determine whether a touch input exists and may calculate the touch input coordinates of the position. Figures 4 to 7 The display unit DU and the touch unit TSU are described in detail.

[0066] The display unit DU and the touch unit TSU may overlap each other. For example, the display area DA may display an image on a screen and may detect a touch input.

[0067] The auxiliary area SBA of the display panel 100 may extend from one side of the main area MA. The auxiliary area SBA may include a bendable, foldable, or rollable flexible material. For example, a portion of the auxiliary area SBA may be bent at one side of the main area MA, and another portion of the auxiliary area SBA extending from the bent portion of the auxiliary area SBA may overlap the main area MA in the third direction Z. The auxiliary area SBA may include a pad connected (e.g., electrically connected) to the display driver 200 and the circuit board 300.

[0068] refer to Figure 1 , the display driver 200 may be disposed in the auxiliary area SBA of the display panel 100. For example, the display driver 200 may be implemented as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) technology or a chip on plastic (COP) technology.

[0069] The display driver 200 may output data signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to data lines of the display panel 100. The display driver 200 may supply power voltages to voltage lines of the display panel 100, and may supply gate control signals to a gate driver.

[0070] The circuit board 300 may be disposed in the auxiliary area SBA of the display panel 100. Leads of the circuit board 300 may be connected (eg, electrically connected) to pad areas of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0071] The circuit board 300 may include a conductive layer that transmits a signal from the main circuit board to the display driver 200 or electrically connects the touch driver 400 with the driving electrodes TE and the sensing electrodes RE of the touch unit TSU.

[0072] The touch driver 400 may be disposed in the auxiliary area SBA of the display panel 100. In another example, the touch driver 400 may be mounted on the circuit board 300.

[0073] The touch driver 400 can determine whether there is a touch input and find the coordinates of the touch input by sensing the amount of change in capacitance between the touch electrodes SEN. The touch driver 400 can be implemented as an integrated circuit (IC) and can be mounted on the display panel 100 by a chip on glass (COG) technology or a chip on plastic (COP) technology.

[0074] Figure 3 is a schematic diagram conceptually illustrating a display unit and a touch driver according to an embodiment. Figure 4 is a schematic plan view showing a display unit of a display device according to an embodiment.

[0075] refer to Figure 3 and Figure 4 , the display device 10 may include a display panel 100 including pixels PX, a display driver 200 and a touch driver 400 .

[0076] The display driver 200 may include a data driver 230 and a display controller 220 .

[0077] The display controller 220 may receive input data R, G and B and timing control signals from an external source (e.g., a host). The timing control signals may include a vertical synchronization signal Vsync indicating a frame period, a horizontal synchronization signal Hsync indicating a horizontal period, and a main clock MCLK repeated in a selected cycle. The input data R, G and B may be RGB data including red image data, green image data and blue image data. The display controller 220 may generate output data signals DR, DG and DB and internal control signals using the input data R, G and B and the timing control signals. The internal control signals may include a data driver control signal DCS and a gate driver control signal GCS.

[0078] The display controller 220 may control the operation of the data driver 230 by providing the data driver control signal DCS to the data driver 230. The display controller 220 may control the operation of the gate driver 210 by providing the gate driver control signal GCS to the gate driver 210.

[0079] The data driver 230 may receive the output data signals DR, DG, and DB and the data driver control signal DCS from the display controller 220. The data driver 230 may generate data signals using the output data signals DR, DG, and DB and the data driver control signal DCS. The data driver 230 may provide the generated data signals to the display panel 100. The data driver 230 may generate data signals through the data lines DL1 to DLm ( Figure 4 DL) in the pixel PX is provided with a data signal.

[0080] The gate driver 210 may receive a gate driver control signal GCS from the display controller 220. The gate driver 210 may generate a gate signal using the received gate driver control signal GCS. The gate driver 210 may provide the generated gate signal to the display panel 100. The gate driver 210 may generate a gate signal by means of gate lines SL1 to SLn ( Figure 4 The gate signal GL in the pixel PX is provided to the pixel PX. Figure 4 The data lines DL1 to DLm and the gate lines SL1 to SLn are described in detail. Here, n and m are natural numbers greater than 0.

[0081] Despite Figure 3In the example shown in FIG. 1 , the display driver 200 does not include the gate driver 210, but the embodiment is not limited thereto. For example, the gate driver 210 may be included in the display driver 200 that controls the operation of the display panel 100. The gate driver 210, the data driver 230, and the display controller 220 may be implemented as an integrated circuit (IC). The gate driver 210 may be formed together during the process of manufacturing the thin film transistor of the display panel 100. The display controller 220 and the data driver 230 may be merged to form a timing controller embedded driver (TED) integrated circuit.

[0082] The display panel 100 may include a plurality of layers connected (eg, electrically connected) to the data lines DL (see Figure 4 ) and the gate line GL (see Figure 4 ) pixel PX.

[0083] The frame rate at which the display driver 200 drives the display panel 100 may be variable. For example, the frame rate may vary within a range of about 1 Hz to about 240 Hz according to a selection of a host or a user. The display driver 200 may drive the display panel 100 at about 60 Hz in one period, and may change the frame rate to about 120 Hz in another period according to a user's needs.

[0084] The touch area TSA may include touch electrodes SEN (eg, Figure 5 The driving electrodes TE and sensing electrodes RE in the touch driving line TL (see Figure 5 ) and the touch sensing line RL (see Figure 5 ). The touch area TSA may detect a touch input by receiving an electrical signal Tx from a touch driver 400 provided on the circuit board 300 via a touch driving line TL, or by transmitting an electrical signal Rx sensed from a sensing electrode RE to the touch driver 400 via a touch sensing line RL. For example, the touch driver 400 may detect a touch input by converting an analog electrical signal Rx detected by the touch area TSA into a digital signal. Figure 5 The touch driver 400 is described in detail.

[0085] refer to Figure 4 The display unit DU may include a display area DA and a non-display area NDA. The display unit DU may include pixels PX and gate lines GL and data lines DL connected (eg, electrically connected) to the pixels PX.

[0086] The gate lines GL may supply the pixels PX with gate signals received from the gate driver 210. The gate lines GL may extend in a first direction X, and may be spaced apart from each other in a second direction Y intersecting the first direction X.

[0087] The data lines DL may supply the output data signals DR, DG, and DB and the data signals received from the display driver 200 to the pixels PX. The data lines DL may extend in the second direction Y and may be spaced apart from each other in the first direction X.

[0088] The non-display area NDA may surround the display area DA. For example, the non-display area NDA may include a gate driver 210 for applying a gate signal to the gate line GL, a fan-out line FOL for connecting the data line DL with the display driver 200, and a display pad DP connected (e.g., electrically connected) to the circuit board 300.

[0089] The display driver 200 may supply the gate driver control signal GCS to the gate driver 210 through the gate control line GCL. The gate driver 210 may generate a gate signal based on the gate driver control signal GCS, and may sequentially supply the gate signal to the gate lines GL in a selected order.

[0090] The display driver 200 may supply a first power supply voltage to the first voltage line VL and a second power supply voltage to the second voltage line through the data driver 230. Each of the pixels PX may receive the first power supply voltage through the first voltage line VL and may receive the second power supply voltage through the second voltage line. The first power supply voltage may be a reference high level voltage, and the second power supply voltage may be a voltage lower than the first power supply voltage.

[0091] The display pad area DPA and the touch pad area TPA may be disposed at an edge portion of the display panel 100. The display pad area DPA may include a display pad DP. The display pad DP may be connected (e.g., electrically connected) to the main processor through the circuit board 300. The display pad DP may be connected (e.g., electrically connected) to the circuit board 300 to receive digital video data, and the digital video data may be supplied to the display driver 200.

[0092] Figure 5 is a schematic plan view showing a touch unit of a display device according to an embodiment.

[0093] refer to Figure 5 The touch unit TSU may include a touch area TSA for sensing a user's touch and a touch peripheral area TRA disposed around the touch area TSA. The touch area TSA may overlap the display area DA of the display panel 100, and the touch peripheral area TRA may overlap the non-display area NDA of the display panel 100.

[0094] The touch unit TSU may include a driving electrode TE, a sensing electrode RE, a touch driving line TL, and a touch sensing line RL.

[0095] The circuit board 300 may include first circuit pads DCPD connected (e.g., electrically connected) to display pads DP of the display panel 100, second circuit pads TCPD connected (e.g., electrically connected) to touch pads TP of the display panel 100, and touch circuit lines 212 connecting (e.g., electrically connected) the second circuit pads TCPD to the touch driver 400. The driving electrodes TE and the sensing electrodes RE of the touch area TSA may be connected (e.g., electrically connected) to the touch driver 400 on the circuit board 300. The touch area TSA may receive an electrical signal from the touch driver 400 provided on the circuit board 300 through the touch driving lines TL and the touch sensing lines RL, or may transmit an electrical signal sensed from the driving electrodes TE or the sensing electrodes RE to the touch driver 400 through the touch driving lines TL and the touch sensing lines RL.

[0096] The driving electrodes TE may be arranged in the first direction X and the second direction Y. The driving electrodes TE may be spaced apart from each other in the first direction X and the second direction Y. The driving electrodes TE adjacent to each other in the second direction Y may be connected (eg, electrically connected) by a bridge electrode CE.

[0097] The driving electrode TE may be connected (e.g., electrically connected) to the touch pad TP through the touch driving line TL. Some of the touch driving lines TL may pass through the lower side of the touch peripheral area TRA and may extend to the touch pad TP. Others of the touch driving lines TL may pass through the upper side, the left side, and the lower side of the touch peripheral area TRA and may extend to the touch pad TP. The touch pad TP may be connected (e.g., electrically connected) to the touch driver 400 through the circuit board 300.

[0098] The display pad area DPA and the touch pad area TPA may be disposed at edge portions of the auxiliary area SBA of the display panel 100. The display pad area DPA and the touch pad area TPA may be connected (eg, electrically connected) to the circuit board 300 by using a low resistance and high reliability material such as an anisotropic conductive film.

[0099] The sensing electrodes RE may extend in the first direction X and may be spaced apart from each other in the second direction Y. The sensing electrodes RE may be arranged in the first direction X and the second direction Y, and the sensing electrodes RE adjacent to each other in the first direction X may be connected (eg, electrically connected) by a connection portion.

[0100] The sensing electrode RE may be connected (e.g., electrically connected) to the touch pad TP through the touch sensing line RL. For example, the sensing electrode RE disposed on the right side of the touch area TSA may be connected (e.g., electrically connected) to the touch pad TP through the touch sensing line RL. The touch sensing line RL may extend to the touch pad TP via the right side and the lower side of the touch peripheral area TRA. The touch pad TP may be connected (e.g., electrically connected) to the touch driver 400 through the circuit board 300.

[0101] The driving electrode TE and the sensing electrode RE may include a planar pattern formed of a transparent conductive layer or may include an opaque metal along a path where the light emitting diode ED is not provided (see FIG. Figure 8 ) areas, and thus they may not block the progress of (or may not hinder the passage of) light emitted from the display area DA.

[0102] A touch drive signal may be applied from the touch driver 400 to each of the drive electrodes TE through one of the touch drive lines TL. When the touch drive signal is applied to the drive electrode TE, mutual capacitance may be formed between adjacent drive electrodes TE and sensing electrodes RE. In the presence of a touch input from the outside, the mutual capacitance between adjacent drive electrodes TE and sensing electrodes RE may change. The change in mutual capacitance between adjacent drive electrodes TE and sensing electrodes RE may be transmitted to the touch driver 400 through the touch sensing line RL. Accordingly, the touch driver 400 may determine whether there is a touch input, and may calculate the touch input coordinates of the position. The touch may be sensed by mutual capacitance sensing, but the embodiment is not limited thereto.

[0103] exist Figure 5 In the embodiment, the ground line GND may be formed on the circuit board 300 .

[0104] The dummy electrode (or dummy pattern) DME is also Figure 5 The driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME may be disposed on the same layer and may be spaced apart from each other.

[0105] Figure 6 yes Figure 5 An enlarged schematic diagram of area A1. Figure 7 is an enlarged schematic diagram showing a part of the display device according to the embodiment.

[0106] refer to Figure 6 and Figure 7 , the driving electrodes TE may be arranged in the first direction X and the second direction Y. The driving electrodes TE may be spaced apart from each other in the first direction X and the second direction Y. The driving electrodes TE adjacent to each other in the second direction Y may be connected (eg, electrically connected) by a bridge electrode CE.

[0107] The sensing electrodes RE may extend in the first direction X and may be spaced apart from each other in the second direction Y. The sensing electrodes RE may be arranged in the first direction X and the second direction Y, and the sensing electrodes RE adjacent to each other in the first direction X may be connected (e.g., electrically connected) by a connection portion RCE. For example, the connection portion RCE of the sensing electrode RE may pass between the driving electrodes TE adjacent to each other.

[0108] The bridging electrode CE may be disposed at a different layer from the driving electrode TE and the sensing electrode RE. Each of the bridging electrodes CE may include a first portion CEa and a second portion CEb. For example, the second portion CEb of the bridging electrode CE may be connected (e.g., electrically connected) to the driving electrode TE disposed on one side through the first contact hole CNT1, and may extend in the direction DR2. The first portion CEa of the bridging electrode CE may be bent from the second portion CEb at a position where it overlaps with the sensing electrode RE to extend in the direction DR1, and may be connected (e.g., electrically connected) to the driving electrode TE disposed on the other side through the first contact hole CNT1. For example, the direction DR1 may refer to a direction between the first direction X and the second direction Y, and the direction DR2 may refer to a direction intersecting with the direction DR1. For example, each of the bridging electrodes CE may be connected (e.g., electrically connected) between the driving electrodes TE adjacent to each other along the second direction Y.

[0109] According to an embodiment, when viewed from the top (or in a plan view), the driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see FIG. Figure 5 ) may be formed in a grid pattern or a mesh pattern. The driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see Figure 5 ) may not overlap with the first to third emission areas EA1, EA2, and EA3 of the pixel PX. The bridging electrode CE may not overlap with the first to third emission areas EA1, EA2, and EA3. Accordingly, the display device 10 can prevent the brightness of light emitted from the emission areas EA1, EA2, and EA3 from being reduced by the touch unit TSU.

[0110] Each of the driving electrodes TE may include a first portion TEa extending in the direction DR1 and a second portion TEb extending in the direction DR2. Each of the sensing electrodes RE may include a first portion REa extending in the direction DR1 and a second portion REb extending in the direction DR2.

[0111] According to another embodiment, when viewed from the top (or in a plan view), the driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see FIG. Figure 5) may be formed as the entire surface instead of a grid pattern or a mesh pattern. In this case, the driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see Figure 5 ) may include transparent conductive materials with high light transmittance such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0112] The pixel PX may include first to third sub-pixels. The first to third sub-pixels may include first to third emission areas EA1, EA2, and EA3, respectively. For example, the first emission area EA1 may emit light of a first color or red light, the second emission area EA2 may emit light of a second color or green light, and the third emission area EA3 may emit light of a third color or blue light. However, it will be understood that the embodiment is not limited thereto.

[0113] A single pixel PX may include one first emission area EA1, two second emission areas EA2, and one third emission area EA3 to represent (or depict) black and white / grayscale. Accordingly, black and white / grayscale may be represented (or depicted) by a combination of light emitted from one first emission area EA1, light emitted from two second emission areas EA2, and light emitted from one third emission area EA3.

[0114] Figure 8 It is along Figure 7 Schematic cross-sectional view taken along line II'.

[0115] refer to Figure 8 The display panel 100 may include a display unit DU and a touch unit TSU. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, an emission material layer EML, and an encapsulation layer TFEL.

[0116] The substrate SUB may support the display panel 100. The substrate SUB may be a base substrate or a base member and may be made of an insulating material such as a polymer resin. For example, the substrate SUB may be a flexible substrate that is bendable, foldable, or rollable. As another example, the substrate SUB may include a flexible material and a rigid material.

[0117] The thin film transistor layer TFTL may include first and second buffer layers BF1 and BF2, a thin film transistor TFT, a gate insulator GI, a first interlayer dielectric layer ILD1, a capacitor electrode CPE, a second interlayer dielectric layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0118] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include inorganic films alternately stacked on each other.

[0119] The light shielding layer BML may be disposed on the first buffer layer BF1. For example, the light shielding layer BML may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For another example, the light shielding layer BML may be an organic layer including a black pigment.

[0120] The second buffer layer BF2 may cover the first buffer layer BF1 and the light shielding layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include inorganic films alternately stacked on each other.

[0121] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may form a pixel circuit of each of the pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor region ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0122] The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be disposed on the second buffer layer BF2. The semiconductor region ACT may overlap the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulator GI. The source electrode SE and the drain electrode DE may be formed by converting the material of the semiconductor region ACT into a conductor.

[0123] The gate electrode GE may be disposed on the gate insulator GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulator GI interposed therebetween.

[0124] The gate insulator GI may be disposed on the semiconductor region ACT, the source electrode SE, and the drain electrode DE. For example, the gate insulator GI may cover the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2, and may insulate the semiconductor region ACT from the gate electrode GE. The gate insulator GI may include a contact hole through which the first connection electrode CNE1 passes.

[0125] The first interlayer dielectric layer ILD1 may cover the gate electrode GE and the gate insulator GI. The first interlayer dielectric layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer dielectric layer ILD1 may be connected to the contact hole of the gate insulator GI and the contact hole of the second interlayer dielectric layer ILD2.

[0126] The capacitor electrode CPE may be disposed on the first interlayer dielectric layer ILD1 . The capacitor electrode CPE may overlap the gate electrode GE in the third direction Z.

[0127] The second interlayer dielectric layer ILD2 may cover the capacitor electrode CPE and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer dielectric layer ILD2 may be connected to the contact hole of the first interlayer dielectric layer ILD1 and the contact hole of the gate insulator GI.

[0128] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer ILD2. The first connection electrode CNE1 may connect (e.g., electrically connect) the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulator GI to contact the drain electrode DE of the thin film transistor TFT.

[0129] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer dielectric layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0130] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may connect (e.g., electrically connect) the first connection electrode CNE1 to the first electrode AND of the light emitting diode (or light emitting element) ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0131] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include a contact hole through which the first electrode AND of the light emitting diode ED passes.

[0132] The emission material layer EML may be disposed on the thin film transistor layer TFTL. The emission material layer EML may include a light emitting diode ED and a pixel defining layer PDL. The light emitting diode ED may include a first electrode AND, an emission layer EL, and a second electrode CAT.

[0133] The first electrode AND may be disposed on the second passivation layer PAS2. The first electrode AND may overlap one of the first to third emission areas EA1, EA2, and EA3 defined by the pixel defining layer PDL. The first electrode AND may be connected (e.g., electrically connected) to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0134] The emission layer EL may be disposed on the first electrode AND. For example, the emission layer EL may be an organic emission layer made of an organic material, but the embodiment is not limited thereto. In the case where the emission layer EL is an organic emission layer, when the thin film transistor TFT applies a reference voltage to the first electrode AND of the light emitting diode ED and the second electrode CAT of the light emitting diode ED receives a common voltage or a cathode voltage, holes and electrons may move to the organic emission layer through the hole transport layer and the electron transport layer, respectively, and they are recombined in the organic emission layer to emit light.

[0135] The second electrode CAT may be disposed on the emission layer EL. For example, the second electrode CAT may be implemented as a common electrode disposed across all pixels, rather than being disposed as a separate electrode for each of the pixels. For example, the second electrode CAT may be disposed on the emission layer EL, in the first to third emission areas EA1, EA2, and EA3, and may be disposed on the pixel defining layer PDL, in other areas except the first to third emission areas EA1, EA2, and EA3.

[0136] The pixel defining layer PDL may define first to third emission areas EA1, EA2, and EA3. The pixel defining layer PDL may separate and insulate a first electrode AND of one of the light emitting diodes ED from a first electrode AND of another of the light emitting diodes ED.

[0137] The encapsulation layer TFEL may be disposed on the second electrode CAT to cover the light emitting diode ED. The encapsulation layer TFEL may include at least one inorganic layer for preventing oxygen or moisture from penetrating into the emission material layer EML. The encapsulation layer TFEL may include at least one organic layer for protecting the emission material layer EML from foreign matter such as dust.

[0138] The touch unit TSU may be disposed on the encapsulation layer TFEL. The touch unit TSU may include a third buffer layer BF3, a bridge electrode CE, a first insulating layer SIL1, a driving electrode TE, a sensing electrode RE, and a second insulating layer SIL2.

[0139] The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may be insulating and may have an optical function. The third buffer layer BF3 may include at least one inorganic layer. In another example, the third buffer layer BF3 may be excluded.

[0140] The bridge electrode CE may be disposed on the third buffer layer BF3. The bridge electrode CE may be disposed in a different layer from the driving electrode TE and the sensing electrode RE, and may be connected (eg, electrically connected) to the driving electrode TE and the sensing electrode RE along the second direction (eg, Figure 7 The bridging electrode CE is formed between adjacent driving electrodes TE in the second direction Y in the direction Y of the electrode. For example, the bridging electrode CE may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may be formed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu).

[0141] The first insulating layer SIL1 may cover the bridge electrode CE and the third buffer layer BF3. The first insulating layer SIL1 may have an insulating function and an optical function. For example, the first insulating layer SIL1 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0142] The driving electrode TE and the sensing electrode RE may be disposed on the first insulating layer SIL1. Each of the driving electrode TE and the sensing electrode RE may not overlap with any of the first to third emission areas EA1, EA2, and EA3. Each of the driving electrode TE and the sensing electrode RE may be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be composed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0143] The second insulating layer SIL2 may cover the driving electrode TE, the sensing electrode RE, and the first insulating layer SIL1. The second insulating layer SIL2 may have insulating characteristics and optical characteristics. The second insulating layer SIL2 may be made of one of the materials listed above as the material of the first insulating layer SIL1.

[0144] Despite Figure 8 In the embodiment, the bridge electrode CE is formed in a layer below the driving electrode TE and the sensing electrode RE, but the embodiment is not limited thereto. For example, the bridge electrode CE may be formed in a layer above the driving electrode TE and the sensing electrode RE.

[0145] Fig. 9 is a schematic diagram showing a part of the exterior of a display panel according to an embodiment. Fig.10 is a schematic cross-sectional view of a portion of a dummy region of a display panel according to an embodiment. Fig.11 is a schematic cross-sectional view of a portion of a boundary region between an encapsulation region of an encapsulation layer of a display panel and a covering region of a protection layer according to an embodiment.

[0146] Fig.12 is a schematic cross-sectional view of a portion of a bending region of a display panel according to an embodiment. For example, Fig.10 It is taken along the line A-A' Fig. 9 Schematic cross-sectional view of a display panel shown in FIG. Fig.11 It is taken along the line B-B' Fig. 9 Schematic cross-sectional view of a display panel shown in FIG. Fig.12 It is along Fig. 9 Schematic cross-sectional view taken along line CC'.

[0147] refer to Figures 9 to 11 , the display panel 100 may include a display area DA and a non-display area NDA, and may be manufactured with a bendable, foldable, or rollable substrate SUB as a base.

[0148] Backplane 1010, insulating layer 1020, organic light emitting layer 1030, encapsulation layer 1040 (eg, Figure 8 The encapsulation layer TFEL) and the polarizing film 1050 are arranged in the display area DA of the substrate SUB. The back panel 1010 may include the above reference Figure 8 A thin film transistor TFT and at least one signal line and / or at least one voltage line connected (eg, electrically connected) to the thin film transistor TFT are described.

[0149] The non-display area NDA of the substrate SUB may be located outside the display area DA. Fig. 9 A driver circuit (eg, Figure 2 The display driver 200) is joined at the bending region where it is (eg, Figure 2 For example, the non-display area NDA may include a bending area SBA bent to overlap a portion of the display area DA, at which the driver circuit 200 is bonded.

[0150] According to an embodiment, the bending area SBA, which is a portion of the non-display area NDA, may include a bending protection layer (BPL) area 1303 (see FIG. 1 ) where the protection layer 913 covering the driver circuit 200 is disposed. Fig.14) (eg, the first region) and a shielding region (eg, the second region) at which a shielding resin 911 in the form of an electrical shielding resin is applied to prevent introduction of static electricity.

[0151] In a case where the substrate SUB is viewed from the top (or in a plan view), the shielding resin 911 in the shielding area may be disposed between the protective layer 913 in the BPL area 1303 and the polarizing film 1050 in the display area DA.

[0152] According to an embodiment, the bending area SBA may further include a dummy area 1302 (see FIG. 1 ) disposed adjacent to the shielding resin 911. Fig.14 When the substrate SUB is viewed from the top (or in a plan view), the dummy area 1302 may be located between the protective layer 913 in the BPL area 1303 and the polarizing film 1050 in the display area DA, and may be positioned adjacent to at least one side of the shielding resin 911.

[0153] For example, the bending area SBA may include a shielding area where a fan-out line FOL extending from the display area DA to the driver circuit 200 of the backplane 1010 and a shielding resin 911 covering the fan-out line FOL are disposed, and a dummy area 1302 located at each of ends (e.g., opposite ends) of the shielding area. In the dummy area 1302, a test pattern 912 may be coated.

[0154] For example, the dummy area 1302 may be defined as an area where the fan-out line FOL is not disposed.

[0155] For example, the dummy area 1302 may be located at an end (or at least one side) of the shielding area where the shielding resin 911 is applied, and may be defined as an area where an alignment key is provided.

[0156] For example, the dummy area 1302 may be a portion of the non-display area NDA where the pixel PX is not disposed, and may be a portion of the non-display area NDA that remains bent. A test pattern 912 made of a material substantially the same as that of the shielding resin 911 is coated in the dummy area 1302. For example, the test pattern 912 may be disposed adjacent to an alignment key.

[0157] The test pattern 912 may be used as an indicator for setting the optimal optical condition in the process of checking whether the shielding resin 911 is properly coated (or formed). For example, the process of checking whether the shielding resin 911 is properly coated (or formed) may include irradiating the test pattern 912 with ultraviolet light UV according to a plurality of optical conditions, and determining the optimal optical condition based on the ultraviolet light reflected from the test pattern 912.

[0158] The optimal optical condition may mean a condition that allows a shielding region where the shielding resin 911 is set to be easily distinguished from the BPL region 1303 .

[0159] The optimal optical condition may mean a condition that allows a shielding area where the shielding resin 911 is disposed to be easily distinguished from a display area DA where the polarizing film 1050 is attached.

[0160] After the optimal optical condition is determined, it may be checked whether the shielding resin 911 is properly coated (or formed) by irradiating the shielding resin 911 with ultraviolet light UV according to the determined optimal optical condition.

[0161] In the case where the shielding resin 911 is not properly coated (or formed), irregularity (which is the opposite of uniformity) of ultraviolet light reflected from the shielding resin 911 may exceed a reference threshold.

[0162] The inspection process according to an embodiment may include determining whether the shielding resin 911 is properly coated (or formed) according to whether irregularity (which is the opposite of uniformity) of ultraviolet light reflected from the shielding resin 911 exceeds a specified threshold.

[0163] Despite Fig.10 In the embodiment, a portion of the encapsulation layer 1040 is disposed between the test pattern 912 and the substrate SUB, but the embodiment is not limited thereto. In another example, the encapsulation layer 1040 may not be disposed between the test pattern 912 and the substrate SUB.

[0164] Fig.10 An insulating layer 1020 (eg, Figure 8 The first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2).

[0165] Despite Fig.11 In the embodiment, a portion of the encapsulation layer 1040 is disposed between the shielding resin 911 and the substrate SUB, but the embodiment is not limited thereto. In another example, the encapsulation layer 1040 may not be disposed between the shielding resin 911 and the substrate SUB.

[0166] In the following, we will combine Fig.13 and Fig.14 A method of checking whether the shielding resin 911 may be properly coated (or formed) using the test pattern 912 is described in more detail.

[0167] For example, the test pattern 912 may be referred to as a test element group (Teg) pattern or similar terms. In the following description, the test pattern 912 will be referred to as Teg 912 for ease of explanation.

[0168] Fig.13is a flowchart for illustrating a method of testing a display panel according to an embodiment. Fig.14 is a schematic diagram showing optical characteristics measured from each of an encapsulation region of an encapsulation layer, a covering region of a protection layer, and a boundary region therebetween.

[0169] refer to Fig.13 , a backplane 1010, an organic light emitting layer 1030, and an encapsulation layer 1040 are formed on the substrate SUB (step 1210). The backplane 1010, the organic light emitting layer 1030, the encapsulation layer 1040, and the polarizing film 1050 are arranged in the display area DA of the substrate SUB. The backplane 1010 may include Figure 8 A thin film transistor TFT and at least one signal line and / or at least one voltage line connected (eg, electrically connected) to the thin film transistor TFT are described.

[0170] refer to Fig.13 The driver circuit 200 may be bonded to the non-display area NDA of the substrate SUB, and the driver circuit 200 may be covered with a protective layer 913 (step 1220).

[0171] The non-display area NDA of the substrate SUB may be located outside the display area DA. Fig. 9 A portion of the non-display area NDA including the bending area SBA where the driver circuit 200 is bonded is shown. For example, the non-display area NDA may include a bending area SBA bent to overlap a portion of the display area DA where the driver circuit 200 is bonded.

[0172] According to an embodiment, the bending area SBA which is a part of the non-display area NDA may include a bending protection layer (BPL) area 1303 (e.g., a first area) where a protection layer 913 covering the driver circuit 200 is disposed and a shielding area (e.g., a second area) where a shielding resin 911 is coated to prevent the introduction of static electricity.

[0173] When the substrate SUB is viewed from the top (or in a plan view), the shielding resin 911 in the shielding area may be disposed between the protective layer 913 in the BPL area 1303 and the polarizing film 1050 in the display area DA.

[0174] According to an embodiment, the bending area SBA may further include a dummy area 1302 positioned adjacent to the shielding resin 911. When the substrate SUB is viewed from the top (or in a plan view), the dummy area 1302 may be located between the protective layer 913 in the BPL area 1303 and the polarizing film 1050 in the display area DA, and may be positioned adjacent to at least one side of the shielding resin 911.

[0175] refer to Fig.13 , a shielding resin 911 may be coated at a boundary area (e.g., a shielding area) between the polarizing film 1050 and the protective layer 913, and a Teg 912 made of the same material as the shielding resin 911 may be coated at a dummy area 1302 of a non-display area NDA located at the outermost position of the substrate SUB (step 1230).

[0176] The dummy area 1302 may be defined as an area where the fan-out line FOL is not disposed. The dummy area 1302 may be defined as an area located at the end (or at least one side) of the shielding area where the shielding resin 911 is coated. The dummy area 1302 may be a portion of the non-display area NDA where the pixel PX is not disposed, and may be a portion of the non-display area NDA that remains bent. A test pattern 912 made of a material substantially the same as that of the shielding resin 911 may be coated in the dummy area 1302.

[0177] refer to Fig.13 , ultraviolet light UV may be irradiated to Teg 912 using a lighting device LD, and an angle θ and a light amount of the lighting device LD may be determined so that the ultraviolet light UV reflected from Teg 912 may meet a specified optical condition (step 1240).

[0178] According to an embodiment, determining the angle θ and the light amount of the lighting device LD so that the ultraviolet light UV reflected from the Teg 912 satisfies a specified optical condition may include the following steps.

[0179] Initially, the plurality of optical conditions may be set as a combination of a plurality of angle conditions related to the angle θ of the lighting device LD and a plurality of light quantity conditions related to the light quantity of the lighting device LD.

[0180] Referring to Table 1, a plurality of angle conditions related to the angle θ of the lighting device LD may be set within a range of about 10 degrees to about 30 degrees. A plurality of light quantity conditions related to the light quantity of the lighting device LD may be set within a range of about 10W to about 30W.

[0181] [Table 1]

[0182]

[0183]

[0184] Although 10 degrees, 15 degrees, 20 degrees, 25 degrees, and 30 degrees are mentioned in Table 1 as angle conditions related to the angle θ of the lighting device LD, the embodiment is not limited thereto.

[0185] Although 10 W, 15 W, 20 W, 25 W, and 30 W are mentioned in Table 1 as the light amount conditions related to the light amount of the lighting device LD, the embodiment is not limited thereto.

[0186] Although 25 optical conditions C1 to C25 are mentioned in Table 1 as combinations of the angle θ and the light amount of the lighting device LD, the embodiment is not limited thereto.

[0187] Subsequently, ultraviolet light UV may be irradiated to the substrate SUB according to each of the optical conditions C1 to C25, so that the first reflected light reflected from the polarizing film 1050, the second reflected light reflected from the test pattern 912, and the third reflected light reflected from the protective layer 913 are measured. Subsequently, the average value of the first reflected light and the third reflected light may be calculated, and the deviation between the average value and the second reflected light may be calculated. The process of calculating the deviation between the average value of the first reflected light and the third reflected light and the second reflected light may be sequentially performed for each of the optical conditions C1 to C25. For example, the process of calculating the deviation between the average value of the first reflected light and the third reflected light and the second reflected light may be performed for each of the 25 optical conditions C1 to C25 shown in Table 1.

[0188] Fig.14 An example is shown in which first reflected light reflected from a boundary 1301 of the display region where the polarizing film 1050 is placed, second reflected light reflected from a test pattern 912 in a dummy region, and third reflected light reflected from a protective layer 913 in a BPL region 1303 are measured.

[0189] For example, an optical condition having the smallest deviation (or smallest irregularity) between the average value of the first reflected light and the third reflected light and the second reflected light may be selected from among the optical conditions.

[0190] The optical condition with the minimum deviation between the average value of the first reflected light and the third reflected light and the second reflected light means that the optical condition is the optimal optical condition allowing the shielding area where the shielding resin 911 is set to be easily distinguished from the BPL area 1303.

[0191] The optical condition having the minimum deviation between the average value of the first reflected light and the third reflected light and the second reflected light means that the optical condition is the optimal optical condition allowing the shielding area where the shielding resin 911 is set to be easily distinguished from the display area DA where the polarizing film 1050 is attached.

[0192] After determining the optimal optical conditions, it is possible to check whether the shielding resin 911 is properly coated (or formed) by irradiating the shielding resin 911 with ultraviolet light UV according to the determined optimal optical conditions. In the case where the shielding resin 911 is not properly coated (or formed), irregularities (which are the opposite of uniformity) of ultraviolet light reflected from the shielding resin 911 may exceed a reference threshold.

[0193] According to an embodiment, for each wafer group manufactured under the same conditions, the angle θ and the light amount of the illumination device LD that make the ultraviolet light UV reflected from the test pattern 912 meet the specified optical conditions can be determined. According to an embodiment, the optimal optical conditions for checking whether the shielding resin 911 is properly coated (or formed) can be set for each wafer group, so that the reliability of the inspection process can be improved.

[0194] According to an embodiment, for each batch manufactured under the same conditions, the angle θ and the light amount of the lighting device LD that make the ultraviolet light UV reflected from the test pattern 912 meet the specified optical conditions can be determined. According to an embodiment, the optimal optical conditions for checking whether the shielding resin 911 may be properly coated (or formed) are set for each batch, so that the reliability of the inspection process can be improved.

[0195] According to an embodiment, for each unit manufactured under the same conditions, the angle θ and the light amount of the lighting device LD that make the ultraviolet light UV reflected from the test pattern 912 meet the specified optical conditions can be determined. According to an embodiment, the optimal optical conditions for checking whether the shielding resin 911 may be properly coated (or formed) can be set for each unit, so that the reliability of the inspection process can be improved.

[0196] refer to Fig.13 , ultraviolet light UV can be irradiated to the shielding resin 911 based on the determined angle θ and light amount (step 1250). For example, once an optical condition having the minimum deviation between the average value of the first reflected light and the third reflected light and the second reflected light can be selected from among the optical conditions, ultraviolet light UV can be irradiated to the shielding resin 911 based on the optical condition. In the case where condition C1 having a brightness of 10 W and an angle of 10 degrees has the minimum deviation between the average value of the first reflected light and the third reflected light and the second reflected light among the 25 optical conditions shown in Table 1, ultraviolet light UV can be irradiated to the shielding resin 911 based on the conditions that the brightness is 10 W and the angle is 10 degrees.

[0197] refer to Fig.13, it can be determined whether the shielding resin 911 is properly coated (or formed) by analyzing the ultraviolet light reflected from the shielding resin 911 (step 1260). Initially, the irregularity (which is the opposite of uniformity) of the ultraviolet light reflected from the shielding resin 911 can be calculated. In the case where the ultraviolet light reflected from the shielding resin 911 can be uniform, this means that the shielding resin 911 is uniformly coated on the substrate SUB. In the case where the ultraviolet light reflected from the shielding resin 911 is uneven, this means that the shielding resin 911 is not uniformly coated on the substrate SUB. Accordingly, in the case where the irregularity (which is the opposite of uniformity) exceeds a reference threshold, it can be determined that the shielding resin 911 is not properly coated (or formed).

[0198] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without substantially departing from the principles of the invention. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A method for inspecting a display device, the method comprising: forming a backplane, an organic light emitting layer, an encapsulation layer and a polarizing film in a display region of the substrate; bonding a driver circuit to a non-display area of ​​the substrate, and covering the driver circuit with a protective layer; applying a shielding resin to a boundary area between the polarizing film and the protective layer, and applying a test pattern made of the same material as that of the shielding resin to a dummy area of ​​the non-display area disposed at an outermost position of the substrate; irradiating the test pattern with ultraviolet light using an illumination device, and determining an angle and a light amount of the illumination device at which the ultraviolet light reflected from the test pattern satisfies a specified optical condition; irradiating the shielding resin with ultraviolet light based on the determined angle and the determined amount of light; as well as Whether the shielding resin is properly applied is determined by analyzing the ultraviolet light reflected from the shielding resin.

2. The method according to claim 1, wherein: The non-display area includes a bent area bent to overlap the display area, The driver circuit is engaged in the bending region, and The bending area includes: a shielding region at which a plurality of fan-out lines extending from the display region to the driver circuit and the shielding resin covering the plurality of fan-out lines are provided; and A dummy region is provided at each of the ends of the shield region.

3. The method according to claim 2, wherein: The fan-out line is not disposed in the dummy region.

4. The method according to claim 1, wherein: The determining of the angle and the light amount of the lighting device so that the ultraviolet light reflected from the test pattern satisfies the specified optical condition includes: setting a plurality of optical conditions as a combination of a plurality of angle conditions related to the angle of the lighting device and a plurality of light quantity conditions related to the light quantity of the lighting device; irradiating ultraviolet light to the substrate according to each of the optical conditions, and measuring first reflected light reflected from the polarizing film, second reflected light reflected from the test pattern, and third reflected light reflected from the protective layer; calculating an average value of the first reflected light and the third reflected light, and calculating a deviation between the second reflected light and the calculated average value of the first reflected light and the third reflected light; and The deviation between the second reflected light and the average value is calculated for each of the optical conditions, and an optical condition having a minimum deviation between the second reflected light and the average value among the optical conditions is determined to satisfy the designated optical condition.

5. The method according to claim 4, wherein: The determination of the angle and the light amount by the illumination device at which the ultraviolet light reflected from the test pattern satisfies the specified optical condition is performed for each wafer group manufactured under the same conditions.

6. The method according to claim 4, wherein: The determining of the angle and the light amount of the lighting device at which the ultraviolet light reflected from the test pattern satisfies the specified optical condition is performed for each batch manufactured under the same conditions.

7. The method according to claim 4, wherein: The determination of the angle and the light amount of the lighting device at which the ultraviolet light reflected from the test pattern satisfies the specified optical condition is performed for each unit manufactured under the same conditions.

8. The method according to claim 4, wherein: The angle condition related to the angle of the lighting device is set within a range of 10 degrees to 30 degrees.

9. The method according to claim 4, wherein: The light quantity condition related to the light quantity of the lighting device is set within a range of 10W to 30W.

10. The method according to any one of claims 1 to 9, wherein: The determination of whether the shielding resin is properly applied includes: calculating irregularities of the ultraviolet light reflected from the shielding resin; and In case the irregularity exceeds a reference threshold value, it is determined that the shielding resin is not properly applied.

11. A method for inspecting a display panel, the method comprising: forming a backplane, an organic light emitting layer, an encapsulation layer and a polarizing film in a display region of the substrate; bonding a driver circuit to a non-display area of ​​the substrate, and covering the driver circuit with a protective layer; applying a shielding resin to a boundary area between the polarizing film and the protective layer, and applying a test pattern made of the same material as that of the shielding resin to a dummy area of ​​the non-display area disposed at an outermost position of the substrate; irradiating the test pattern with ultraviolet light using an illumination device, and determining an angle and a light amount of the illumination device at which the ultraviolet light reflected from the test pattern satisfies a specified optical condition; irradiating the shielding resin with ultraviolet light based on the determined angle and the determined amount of light; as well as Whether the shielding resin is properly applied is determined by analyzing the ultraviolet light reflected from the shielding resin.

12. The method according to claim 11, wherein: The non-display area includes a bent area bent to overlap the display area, The driver circuit is engaged in the bending region, and The bending area includes: a shielding region at which a plurality of fan-out lines extending from the display region to the driver circuit and the shielding resin covering the plurality of fan-out lines are provided; and A dummy region is provided at each of the ends of the shield region.

13. The method according to claim 12, wherein: The fan-out line is not disposed in the dummy region.

14. The method according to claim 11, wherein: The determining of the angle and the light amount of the lighting device so that the ultraviolet light reflected from the test pattern satisfies the specified optical condition includes: setting a plurality of optical conditions as a combination of a plurality of angle conditions related to the angle of the lighting device and a plurality of light quantity conditions related to the light quantity of the lighting device; irradiating ultraviolet light to the substrate according to each of the optical conditions, and measuring first reflected light reflected from the polarizing film, second reflected light reflected from the test pattern, and third reflected light reflected from the protective layer; calculating an average value of the first reflected light and the third reflected light, and calculating a deviation between the second reflected light and the average value of the first reflected light and the third reflected light; and The deviation between the second reflected light and the average value is calculated for each of the optical conditions, and an optical condition having a minimum deviation between the second reflected light and the average value among the optical conditions is determined to satisfy the designated optical condition.

15. The method according to claim 14, wherein: The determination of the angle and the light amount by the illumination device at which the ultraviolet light reflected from the test pattern satisfies the specified optical condition is performed for each wafer group manufactured under the same conditions.

16. The method according to claim 14, wherein: The determining of the angle and the light amount of the lighting device at which the ultraviolet light reflected from the test pattern satisfies the specified optical condition is performed for each batch manufactured under the same conditions.

17. The method according to claim 14, wherein: The determination of the angle and the light amount of the lighting device at which the ultraviolet light reflected from the test pattern satisfies the specified optical condition is performed for each unit manufactured under the same conditions.

18. The method according to claim 14, wherein: The angle condition related to the angle of the lighting device is set within a range of 10 degrees to 30 degrees.

19. The method according to claim 14, wherein: The light quantity condition related to the light quantity of the lighting device is set within a range of 10W to 30W.

20. The method according to any one of claims 11 to 19, wherein: The determination of whether the shielding resin is properly applied includes: calculating irregularities of the ultraviolet light reflected from the shielding resin; and In a case where the irregularity of the ultraviolet light exceeds a reference threshold value, it is determined that the shielding resin is not properly applied.

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