Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. The display device includes: a display panel including a plurality of pixels, each pixel having a light emitting element emitting light by a current corresponding to a data voltage; and a timing controller configured to set an EVDD level required to display the input image data, set an automatic current limiting (ACL) value of the display panel according to the EVDD level, and adjust a luminance gain of the input image data according to the ACL value to generate a data voltage.

Description

Technical Field

[0001] The present disclosure relates to a display device and a driving method thereof, and more particularly, for example but not limited to, to a display device and a driving method thereof that can reduce the power supply circuit cost by reducing the maximum power consumption when variably controlling the EVDD level. Background Art

[0002] An organic light emitting diode display (hereinafter referred to as "OLED display device") is a self-luminous device that emits light in an organic light emitting layer through the recombination of electrons and holes, and since the OLED display device has high brightness and low driving voltage and can form an ultra-thin film, it is expected to be used as a next-generation device.

[0003] Each pixel included in the OLED display device has an OLED and a pixel circuit that independently drives the OLED. The pixel circuit controls the brightness of the OLED by adjusting the current for a thin film transistor (TFT) according to a data voltage to drive the OLED. The driving TFT supplies a high potential voltage EVDD to the OLED, and the amount of current flowing to the OLED can be controlled according to the voltage difference between the source and the gate caused by the data voltage.

[0004] The high potential voltage EVDD supplied to the pixel is supplied to have a sufficiently large voltage level to be able to supply both the driving voltage of the driving TFT applied to the source electrode-drain electrode of the driving TFT and the driving voltage of the OLED. Therefore, in order to reduce power consumption, a dynamic power control (DPC) technique for controlling the high potential voltage EVDD according to an input image has been applied.

[0005] The descriptions provided in the background art section should not be assumed to be prior art merely because they are mentioned in the background art section or are associated with the descriptions in the background art section. The descriptions in the background art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0006] The inventors have recognized that conventional OLED display devices only control the level of the high potential voltage EVDD, so when high brightness is required, the level of the high potential voltage EVDD rises, resulting in an increase in the maximum power consumption. Therefore, since an expensive high-power EVDD power supply circuit needs to be provided, there is a problem of increased cost. Therefore, the present disclosure relates to a display device and a driving method thereof that substantially eliminate one or more problems caused by the limitations and disadvantages of the related art.

[0007] The present disclosure provides a display device and a driving method thereof that can reduce the power supply circuit cost by reducing the maximum power consumption when variably controlling the EVDD level.

[0008] According to an exemplary embodiment of the present disclosure, a display device and a driving method thereof can improve the luminance reduced due to the reduction of EVDD by setting the ACL value to low when the EVDD level is high and setting the ACL value to high within the limit of maintaining the target power consumption when the EVDD level is low, so that the degradation of image quality can be minimized while maintaining the power consumption effect.

[0009] According to an exemplary embodiment of the present disclosure, a display device and a driving method thereof can maintain the target power consumption by controlling the ACL value inversely proportional to the change in the EVDD level, thereby improving the efficiency of the power system.

[0010] Additional advantages, objects, and features of the present disclosure will be partly set forth in the description which follows, and partly will be obvious to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and attained by means of the structures particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0011] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including a plurality of pixels, each pixel having a light-emitting element that emits light through a current corresponding to a data voltage; and a timing controller configured to set an EVDD level required to display input image data, set an automatic current limiting (ACL) value of the display panel according to the EVDD level, and adjust a luminance gain of the input image data according to the ACL value to generate a data voltage.

[0012] The timing controller may set the ACL value such that the ACL value is inversely proportional to the change in the EVDD level.

[0013] The timing controller may set the ACL value such that a target power calculated as a product of the EVDD level and the ACL value is constant.

[0014] The timing controller may be configured to detect a peak luminance of the input image data based on a peak luminance control (PLC) curve that defines the peak luminance of pixels according to an average picture level (APL) of a frame of the input image data, set the EVDD level in units of a frame according to the detected peak luminance, and set the ACL value in units of a frame according to the EVDD level to generate a data voltage of the input image data.

[0015] The timing controller can calculate a target power based on the EVDD level set when the APL is 100% and the ACL value set when the APL is 100%, and set the ACL value such that the target power is maintained using an ACL value inversely proportional to the change in the EVDD level.

[0016] The timing controller can calculate a target power based on the EVDD level set when the APL is 0% and the ACL value set when the APL is 0%, and set the ACL value such that the target power is maintained using an ACL value inversely proportional to the change in the EVDD level.

[0017] The timing controller can detect the peak brightness of the PLC curve set in the input image data to set the ACL value and EVDD level required to display the input image data, and set the ACL value such that when the EVDD level changes according to the change in the PLC curve, the ACL value is inversely proportional to the change in the EVDD level.

[0018] The timing controller can include: a peak brightness detector configured to detect the peak brightness of the input image data; an EVDD controller configured to set the EVDD level according to the peak brightness to output an EVDD level setting signal; an ACL controller configured to set the ACL value according to the EVDD level; and a data voltage generator configured to adjust the brightness gain of the input image data according to the ACL value to generate a data voltage.

[0019] The peak brightness detector can include an APL calculation and PLC controller configured to detect the peak brightness of the input image data based on a PLC curve that defines the peak brightness of pixels based on the APL of a frame of the input image data.

[0020] The peak brightness detector can include a PLC peak brightness detector configured to detect the peak brightness of the PLC curve set in the input image data.

[0021] The ACL controller can calculate a target power based on the EVDD level set when the APL is 100% and the ACL value set when the APL is 100%, and set the ACL value such that the target power is maintained using an ACL value inversely proportional to the change in the EVDD level.

[0022] The ACL controller can calculate a target power based on the EVDD level set when the APL is 0% and the ACL value set when the APL is 0%, and set the ACL value such that the target power is maintained using an ACL value inversely proportional to the change in the EVDD level.

[0023] In another aspect of the present disclosure, a method of controlling a display device, the display device including a display panel including a plurality of pixels, each pixel having a light-emitting element that emits light through a current corresponding to a data voltage, the method includes: detecting a peak brightness of input image data; setting an EVDD level required to display the input image data according to the detected peak brightness; setting an ACL value of the display panel such that a target power value calculated as a product of the EVDD level and the ACL value is constant; and adjusting a brightness gain of the input image data according to the ACL value to generate a data voltage.

[0024] Setting the ACL value may include setting the ACL value such that the ACL value is inversely proportional to a change in the EVDD level.

[0025] Detecting the peak brightness of the input image data may include: detecting the peak brightness of the input image data based on a peak brightness control (PLC) curve that defines the peak brightness of a pixel based on an average picture level (APL) of a frame of the input image data.

[0026] Setting the EVDD level required to display the input image data according to the detected peak brightness may include: setting the EVDD level in units of a frame according to the detected peak brightness.

[0027] Setting the ACL value of the display panel may include: setting the ACL value in units of a frame according to the EVDD level.

[0028] It should be understood that the foregoing general description and the following detailed description of the present disclosure are both exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate example embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0030] Figure 1 is a block diagram schematically showing a configuration of a display device according to an example embodiment of the present disclosure;

[0031] Figure 2 is schematically showing Figure 1 a configuration diagram of a sub-pixel shown;

[0032] Figure 3 is a diagram showing a PLC curve defined for PLC driving;

[0033] Figure 4is a graph showing methods of controlling an EVDD level and an ACL value for a comparative example and an exemplary embodiment of the present disclosure;

[0034] Figure 5 is a graph showing a method of controlling an EVDD level and an ACL value according to a comparative example and the resulting power change;

[0035] Figure 6 is a graph showing a method of controlling an EVDD level and an ACL value according to a first exemplary embodiment of the present disclosure and the resulting power change;

[0036] Figure 7 is a graph showing a method of controlling an EVDD level and an ACL value according to a second exemplary embodiment of the present disclosure and the resulting power change;

[0037] Figure 8 is a block diagram schematically showing a configuration of a timing controller of a display device according to an exemplary embodiment of the present disclosure;

[0038] Figure 9 is a control flowchart of a timing controller according to a first exemplary embodiment of the present disclosure;

[0039] Figure 10 is a graph showing characteristics of an EVDD level and a PLC curve according to a mode definition; and

[0040] Figure 11 is a control flowchart of a timing controller according to a second exemplary embodiment of the present disclosure.

[0041] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Description

[0042] With reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving the advantages and features will become apparent. However, the present disclosure is not limited to the exemplary embodiments disclosed below and can be implemented in various different forms, and the present exemplary embodiments allow the present disclosure to be complete and be provided to fully inform those of ordinary skill in the art to which the present disclosure pertains.

[0043] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. disclosed in the accompanying drawings for describing the exemplary embodiments of the present disclosure are illustrative, and thus the present disclosure is not limited to the elements shown. Throughout the specification, the same reference signs refer to the same elements. When using terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed by", "composed of", etc. in this specification, there may be other parts unless "only" is used. When an element is expressed in the singular, the case including the plural is included unless otherwise clearly stated.

[0044] The dimensions including the size and thickness of each component shown in the accompanying drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions including the relative size, position, and thickness of the components shown in each of the accompanying drawings submitted here are part of the present disclosure.

[0045] When interpreting an element, it will be interpreted as including an error range even when there is no separate and explicit description thereof.

[0046] In the case of describing a positional relationship, for example, when using terms such as "on", "above", "over", "under", "below", "beside", "beneath", "near", "close to", "adjacent to", "on the side of", "proximate to", etc. to describe the positional relationship between two parts, unless "immediately" or "directly" is used, one or more other parts may be located between these two parts.

[0047] Spatially relative terms such as "under", "below", "beneath", "lower", "above", "upper", etc. may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of the element during use or operation. For example, if the element in the figure is inverted, the element described as "under" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" may include both the orientation of below and above. Similarly, the exemplary terms "above" or "over" may include the orientations of "above" and "below".

[0048] When describing a temporal relationship, terms such as "after", "subsequently", "next", "then", "before", etc. may include the case where any two events are not consecutive unless terms such as "immediately", "exactly", or "directly" are explicitly used.

[0049] Although terms such as "first", "second", "A", "B", "a", and "b" are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element referred to below may be a second element within the spirit of the present disclosure.

[0050] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to define the nature, order, or sequence of the corresponding component, but only to distinguish the corresponding component from other components. In the case where a certain structural element or layer is "connected", "coupled", "adhered", or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer may be "connected", "coupled", "adhered", or "joined" to the structural element or layer directly or indirectly.

[0051] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of more than two elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0052] The term "device" used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements and the like. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, and complete product or final product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including light-emitting elements and the like, such as mobile electronic devices such as smart phones or electronic tablets, but the embodiments of the present disclosure are not limited thereto.

[0053] The features of the various exemplary embodiments of the present disclosure may be partially or completely attached to or combined with each other, and may be interlocked and operated in various technical ways, and the exemplary embodiments may be executed independently or in association with each other.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in a common dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] Throughout the specification, the same reference numerals denote substantially the same elements. Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of known functions or configurations related to the present disclosure may unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted.

[0056] Figure 1 is a block diagram schematically showing the configuration of a display device according to an exemplary embodiment of the present disclosure, and Figure 2 is schematically showing Figure 1 a configuration diagram of the sub-pixels shown.

[0057] Referring to Figure 1 , a display device according to an exemplary embodiment of the present disclosure may include a host system 200, a user input unit 210, a display panel 100, a data driver 120, a gate driver 140, a power supply 150, and a timing controller 300.

[0058] The host system 200 may be implemented as various systems, such as a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer, a home theater system, and a telephone system. The host system 200 converts image data supplied from the outside or image data stored in an internal memory into a format suitable for the resolution of the display panel 100. The host system 200 may transmit a timing control signal together with the image data to the timing controller 300. The timing control signal may include a dot clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc. related to the image data. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of a display screen, and the vertical synchronization signal is a signal indicating the time taken for displaying one frame of a screen. The data enable signal may correspond to a signal indicating a period for supplying a data voltage to a pixel.

[0059] The host system 200 may receive a brightness mode for selecting the overall brightness of an image through the user input unit 210. The host system 200 may adjust the brightness of the image data according to the brightness mode selected through the user input unit 210, and then provide the image data to the timing controller 300.

[0060] The user input unit 210 may be implemented as a remote controller having a wireless communication function, a key button, a keypad, a touchpad, a keyboard, a mouse, an on-screen display (OSD), etc.

[0061] The timing controller 300 generates a data timing control signal DDC for controlling the operation timing of the data driver 120 and a gate control signal GDC for controlling the operation timing of the gate driver 140 based on the timing control signal input from the host system 200. The timing controller 300 may supply the data signal DATA supplied from the host system 200 to the data driver 120 together with the data timing control signal DDC, and supply the gate control signal GDC to the gate driver 140. The timing controller 300 may be formed as an IC (integrated circuit) and mounted on a printed circuit board, but is not limited thereto.

[0062] The data driver 120 may sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 300, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the converted analog data voltage. In addition, when the data voltage VDATA is supplied from the timing controller 300, the data driver 120 may supply the corresponding data voltage VDATA to the sub-pixels SP included in the display panel 100 through the data lines DL. The data driver 120 may be formed as an IC and mounted on the display panel 100 or a printed circuit board, and some or all of its components may be built into the timing controller 300. However, the present disclosure is not limited thereto.

[0063] The gate driver 140 may output a scan signal in response to the gate timing control signal GDC supplied from the timing controller 300. The gate driver 140 may supply at least one scan signal to the sub-pixels SP included in the display panel 100 through the gate lines GL. The gate driver 140 may be formed as an IC using an in-panel gating method or directly formed on the display panel 100.

[0064] The display panel 100 includes a plurality of data lines DL and a plurality of gate lines GL formed to cross each other, and sub-pixels SP are arranged in a matrix form in the crossing areas to form a pixel array. As Figure 2As shown, the sub-pixel SP may include an OLED, a driving element DT, and a programming circuit PRC. The OLED emits light with a brightness proportional to the driving current Ids. The OLED may include, but is not limited to, an organic light-emitting layer. The programming circuit PRC includes a first switch connected to the data line DL, at least one second switch connected to the gate line GL, at least one capacitor, etc., to set the gate-source voltage of the driving element DT according to driving conditions. The driving element DT generates the driving current Ids according to driving conditions and supplies the driving current Ids to the OLED. The data voltage Vdata may be reflected in the gate-source voltage of the driving element DT, and the high-potential voltage EVDD may be reflected in the drain-source voltage of the driving element DT. Therefore, the data voltage Vdata and the high-potential voltage EVDD may affect the magnitude of the driving current Ids that determines the brightness of the sub-pixel SP.

[0065] The power supply 150 may convert the power supplied from the outside into the power required to drive the display device and output the power under the control of the timing controller 300. For example, the power supply 150 may convert the power supplied from the outside into the high-potential voltage EVDD, the low-potential voltage EVSS, etc., and output the voltage, and may generate and output the voltage required to drive the gate driver 140 (for example, the gate voltage including the gate high voltage and the gate low voltage), the voltage required to drive the data driver 120 (the drain voltage including the drain voltage and the half-drain voltage), etc.

[0066] In addition, the display device may further include a display controller. The display controller may control the data driver 120 and the gate driver 140. The display controller may control the data driver 120 and the gate driver 140 by providing various driving control signals to the data driver 120 and the gate driver 140.

[0067] The display controller may start scanning according to the timing implemented in each frame, convert the externally input image data into the data signal format used in the data driver 120, output the converted image data, and control the data driving at an appropriate time according to the scanning.

[0068] The display controller may receive various timing signals and input image data including, for example, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a clock signal, etc. from an external device (for example, a host system).

[0069] The display controller can not only convert the input image data input from the outside to a data signal format suitable for use in the data driver 120 and output the converted image data, but also control the data driver 120 and the gate driver 140, receive timing signals such as a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, or a clock signal, and generate various drive control signals and output them to the data driver 120 and the gate driver 140.

[0070] In order to reduce power consumption, the display device according to an exemplary embodiment of the present disclosure having such a configuration can perform a DPC operation to change the EVDD level of the display panel 100 according to the peak brightness set in the input image and change the ACL in combination with the change in EVDD.

[0071] In order to perform the DPC operation, the timing controller 300 can analyze the image input from the host system 200 in units of one frame and detect the APL. The timing controller 300 can set the peak brightness of each pixel according to the detected APL. The peak brightness according to the APL can be set according to a preset PLC curve.

[0072] Figure 3 is a diagram showing the PLC curve. The PLC curve defines the peak brightness of the pixel according to the APL, and the sub-pixel SP of the display panel 100 emits light at a brightness less than or equal to the peak brightness limited by the PLC curve.

[0073] Reference Figure 3 , in a coordinate system where the vertical axis is the peak brightness and the horizontal axis is the APL, the PLC curve maintains the peak brightness at the maximum value in the part where the APL is less than a preset reference APL (APL_R). For example, the PLC curve maintains the peak brightness at the maximum value and maintains a constant peak brightness L in the part where the APL is less than the preset reference APL (APL_R). In the part where the APL is greater than the preset reference APL (APL_R), the brightness value is defined such that the peak brightness of the pixel decreases as the APL increases.

[0074] That is, when the APL is high, the corresponding target peak brightness is low, and conversely, when the APL is low, the corresponding target peak brightness is high. In this way, the higher the APL of a frame, the lower the peak brightness of the frame, thereby reducing power consumption. The PLC curve can be preset and stored according to the brightness, current, driving characteristics, etc. of the display panel 100.

[0075] The timing controller 300 may calculate the APL of a frame of an image and set the peak brightness of the frame based on the PLC curve. The timing controller 300 may obtain the EVDD level according to the peak brightness of each frame by applying the pre-stored EVDD setting information according to the PLC curve. The EVDD level according to the peak brightness may have a form similar to the PLC curve. That is, as the APL becomes larger (the image becomes brighter), the peak brightness and the EVDD level may gradually decrease, and as the APL becomes smaller (the image becomes darker), the peak brightness and the EVDD level may gradually increase. The timing controller 300 may control the EVDD level by controlling the power supply 150 based on the EVDD setting information according to the peak brightness.

[0076] In addition, each sub-pixel SP controls the magnitude of the current Ids flowing through the EVDD to the OLED using the switch of the driving transistor according to the data voltage, so that the OLED emits light with a desired brightness, thereby displaying an image. Therefore, the current flowing through the display panel 100 changes according to the input image. For example, in the case of a completely black image, very little current flows through the display panel 100, but in the case of a completely white image, a large amount of current flows through the display panel 100. Therefore, when the power required by the display panel 100 (power (P) = voltage (V) * current (I)) increases, and thus the power supply 150 outputs a high power greater than or equal to a certain value, a power-off phenomenon occurs. To prevent this phenomenon, an ACL for controlling the current flowing through the display panel 100 may be applied.

[0077] Figure 4 is a graph showing methods of controlling the EVDD level and the ACL value in a comparative example and an exemplary embodiment of the present disclosure.

[0078] Reference Figure 4 to the graph of the comparative example of, in the conventional display device, the ACL value is kept constant when performing the DPC operation of variably controlling the EVDD level according to the APL of the input image.

[0079] Reference Figure 4 to the graph of the exemplary embodiment of, in the exemplary embodiment of the present disclosure, the display device may variably control the ACL value in combination with the change of the EVDD level. Since voltage and current are inversely proportional to each other for a specific power value, for example, when the power value is a specific value, the higher the voltage, the lower the current. Therefore, when the EVDD level is high, the ACL value needs to be kept low. However, when the EVDD level decreases, a margin for increasing the ACL value is ensured.

[0080] Therefore, the display device of the exemplary embodiment of the present disclosure may perform a control operation to decrease the ACL value when the EVDD level increases, and increase the ACL value when the EVDD level decreases. The ACL value may be set to be inversely proportional to the EVDD level.

[0081] Figure 5 is a graph showing a method of controlling an EVDD level and an ACL value according to a comparative example and the resulting power change.

[0082] Referring to Figure 5 (a) of, the display device according to the comparative example maintains the EVDD level at the maximum value in a portion where the APL is less than the reference APL (APL_R). For example, the display device according to the comparative example maintains the EVDD level at the maximum value and the EVDD level is constant in a portion where the APL is less than the reference APL (APL_R). In a portion where the APL is greater than the preset reference APL (APL_R), a control operation is performed such that the EVDD level decreases as the APL increases. The display device according to the comparative example maintains the ACL constant even when the EVDD level changes. For example, the display device according to the comparative example maintains the ACL constant regardless of whether the EVDD level changes.

[0083] Figure 5 (b) of is Figure 5 (a) of the graph for calculating the power consumed when controlling the EVDD level and the ACL value. The power can be calculated as voltage (EVDD) * current (ACL). According to the comparative example, since the ACL is maintained at a constant value, the power has a maximum value (Pmax) in a portion where the APL is less than the reference APL (APL_R) and the EVDD level is maintained at the maximum value. In a portion where the APL is greater than the reference APL (APL_R), as the APL increases and the EVDD level decreases, the power also decreases.

[0084] Figure 6 is a graph showing a method of controlling an EVDD level and an ACL value according to the first exemplary embodiment of the present disclosure and the resulting power change.

[0085] Referring to Figure 6 (a) of, the display device according to the first exemplary embodiment maintains the EVDD level at the maximum value in a portion where the APL is less than the reference APL (APL_R). For example, the display device according to the first exemplary embodiment maintains the EVDD level at the maximum value and the EVDD level is constant in a portion where the APL is less than the reference APL (APL_R). In a portion where the APL is greater than the preset reference APL (APL_R), a control operation is performed such that the EVDD level decreases as the APL increases.

[0086] In the display device according to the first exemplary embodiment, the ACL value is set in inverse proportion to the EVDD level. Therefore, in a portion where the APL is less than the reference APL (APL_R), the ACL value remains constant, and in a portion where the APL is greater than the preset reference APL (APL_R), as the EVDD level decreases, the ACL value increases in inverse proportion to the EVDD level.

[0087] In the first exemplary embodiment, referring to the maximum value of the reference ACL value, the ACL value when the APL is 100% (APL_100%) corresponding to the screen where the maximum current flows through the display panel can be set as the maximum value. Therefore, the power when the APL is 100% (EVDD_100% * ACL_100%) can be the maximum power (Pmax). In a portion where the APL is less than 100% (APL_xx%), the EVDD is variably controlled to a preset value, so the ACL value can be calculated based on the maximum power (Pmax) (ACL_xx% = Pmax / EVDD_xx%) according to the EVDD in the portion where the APL is less than 100% (APL_100%) (APL_xx%). For example, when the APL is 80% (APL_80%), the ACL value (ACL_80%) can be calculated by calculating the EVDD level (EVDD_80%) set when the APL is 80% (Pmax / EVDD_80%) and Pmax.

[0088] Figure 6 of (b) is when according to Figure 6 The graph in (a) shows the calculation of power when controlling the EVDD level and the ACL value. In the first exemplary embodiment, since the ACL value is adjusted in inverse proportion to the EVDD level based on the maximum power (Pmax), the power value remains constant at Pmax.

[0089] In the first exemplary embodiment, since the maximum power (Pmax) is set as the ACL value when the APL is 100%, in a portion where the APL is less than the reference APL (APL_R), the ACL value is set lower than the ACL value in the comparative example. As a result, as Figure 6 shown in (b), the maximum power (Pmax) can be set lower than the maximum power in the comparative example. Therefore, there is no need to provide an expensive power supply circuit to supply high power, and the cost of the power supply circuit can be reduced. In addition, the maximum power can be reduced to improve the effect of reducing power consumption.

[0090] Figure 7 is a graph showing a method of controlling the EVDD level and the ACL value according to the second exemplary embodiment of the present disclosure and the resulting power change. The difference from the first exemplary embodiment is that the maximum power (Pmax) is set based on when the APL is 0%.

[0091] Reference Figure 7 In (a) of the reference, in a portion where the APL is less than the reference APL (APL_R), the EVDD level is maintained at the maximum value in the display device according to the second exemplary embodiment. For example, in a portion where the APL is less than the reference APL (APL_R), the display device according to the second exemplary embodiment maintains the EVDD level at the maximum value and the EVDD level is constant. In a portion where the APL is greater than the preset reference APL (APL_R), a control operation is performed such that the EVDD level decreases as the APL increases.

[0092] In the display device according to the second exemplary embodiment, the ACL value is set inversely proportional to the EVDD level. Therefore, in a portion where the APL is less than the reference APL (APL_R), the ACL value remains constant, and in a portion where the APL is greater than the preset reference APL (APL_R), as the EVDD level decreases, the ACL value increases inversely proportional to the EVDD level.

[0093] In the second exemplary embodiment, referring to the maximum value of the ACL value, the ACL value when the APL is 100% corresponding to the screen where the minimum current flows through the display panel can be set as the maximum value. Therefore, the power when the APL is 0% (EVDD_0% * ACL_0%) can be the maximum power (Pmax). In a portion where the APL is greater than the preset reference APL (APL_R), the EVDD level decreases to a preset value, and thus the ACL value increases inversely proportional to the maximum power (Pmax) with respect to the EVDD level (ACL_xx% = Pmax / EVDD_xx%). Therefore, when the APL of the display device according to the second exemplary embodiment is 100%, the ACL value can be set to be greater than the ACL value of the comparative example. Therefore, even when the EVDD level decreases, the current amount can be increased by increasing the ACL value, so that the brightness decrease can be prevented even when the EVDD level decreases.

[0094] Figure 7 (b) of is when according to Figure 7 The graph in (a) controls the graph for calculating the power when the EVDD level and the ACL value. In the second exemplary embodiment, since the ACL value is adjusted inversely proportional to the EVDD level based on the maximum power (Pmax), the power value remains constant at Pmax.

[0095] In the second exemplary embodiment, the maximum power (Pmax) is set to the ACL value when the APL is 0%, and thus in a portion where the APL is greater than the reference APL (APL_R), the ACL value is set to be greater than the ACL value of the comparative example. Therefore, as Figure 7As shown in (b), in the portion where the APL is greater than the reference APL (APL_R), the maximum power (Pmax) can be set to be greater than the maximum power of the comparative example. Therefore, while keeping the power level constant, even when the EVDD level decreases, the current amount can be increased by increasing the ACL value, so that the brightness decrease can be prevented even when the EVDD level decreases.

[0096] Figure 8 FIG. is a block diagram schematically showing the configuration of a timing controller 300 of a display device according to an exemplary embodiment of the present disclosure. The timing controller 300 according to the exemplary embodiment of the present disclosure performs a DPC operation to change the EVD Delve, and can variably control the ACL value in combination with the change of the EVDD level.

[0097] Reference Figure 8 , the timing controller 300 may include a peak brightness detector 310, an EVDD controller 320, an image processor 330, a data voltage generator 340, and an ACL controller 350.

[0098] The peak brightness detector 310 obtains the peak brightness of the image data supplied from the host system 200 and provides the peak brightness to the EVDD controller 320. The image data supplied from the host system 200 may be image data that needs to be displayed by variably controlling the EVDD level in units of one image frame by using DPC control, or may be mode setting image data that needs to be displayed by fixing the EVDD level according to the brightness mode selected through the user input unit 210. The peak brightness detector 310 may include: an APL calculation and PLC controller (APL calculation & PLC controller) 312, which detects the peak brightness of the image data to be displayed by variably controlling the EVDD level; and a PLC Max detector 314, which detects the peak brightness of the mode setting image data to be displayed by fixing the EVDD level. Therefore, the peak brightness detector 310 obtains the peak brightness of the image data by using the APL calculation and PLC controller 312 or the PLC maximum detector (PLC Max detector) 314 according to the type of the image data supplied from the host system 200, and provides the obtained peak brightness to the EVDD controller 320.

[0099] The APL calculation and PLC controller 312 analyzes the image data input from the host system 200 in units of one image frame and calculates the APL for each image frame. The APL calculation and PLC controller 312 may obtain the peak brightness corresponding to the APL of one image frame based on the previously stored PLC curve. Therefore, the APL calculation and PLC controller 312 obtains the peak brightness in units of one image frame and provides the obtained peak brightness to the EVDD controller 320.

[0100] The PLC Max detector 314 can detect the peak brightness from the PLC curve data input together with the mode setting image data from the host system 200. Since the mode setting image data is displayed according to the brightness mode set by the user, the peak brightness can be changed when the brightness mode is changed by the user input unit 210. Therefore, the PLC Max detector 314 obtains the peak brightness from the PLC curve data input together with the mode setting image data, and provides the obtained peak brightness to the EVDD controller 320.

[0101] The EVDD controller 320 can receive the input of the peak brightness, and determine the EVDD level required to display the peak brightness based on the pre-stored EVDD setting information. The pre-stored EVDD setting information may include the EVDD level according to the peak brightness, and the EVDD level according to the peak brightness may have a form similar to the form of the PLC curve. The EVDD controller 320 outputs the EVDD setting information determined according to the peak brightness to the power supply 150, so that the power supply 150 can supply EVDD to the display panel 100 according to the EVDD setting information.

[0102] The ACL controller 350 can receive the EVDD setting information determined by the EVDD controller 320, and calculate the ACL value suitable for the set EVDD level. The ACL controller 350 can calculate and set the ACL value such that as the EVDD level decreases, the ACL value increases. The ACL controller 350 can calculate the ACL value using a preset calculation formula according to the set EVDD level. For example, the ACL controller 350 can calculate the ACL value by multiplying the target power by the reciprocal of the EVDD level. In addition, in order to reduce the computational load of the system, the ACL value according to the EVDD level can be implemented as a look-up table (LUT). For example, the EVDD level and the ACL value can be correspondingly recorded in the look-up table (LUT), but not limited thereto.

[0103] The image processor 330 can correct the image data to improve the image quality of the image data. For example, the image processor 330 can correct the image data according to the change of the electrical characteristics of the display panel 100, but not limited thereto.

[0104] The data voltage generator 340 may generate a data voltage VDATA based on the image data corrected by the image processor 330. When generating the data voltage VDATA, the data voltage generator 340 may use the ACL value provided by the ACL controller 350 to adjust the brightness gain. The ACL value is the total current value of an image frame and is set inversely proportional to the EVDD level according to an exemplary embodiment of the present disclosure. Therefore, when the EVDD level decreases compared to the previous frame, the ACL value increases, and thus the brightness gain may also increase. As a result, the decrease in the brightness of the image displayed on the display panel 100 can be minimized by using the ACL to increase the brightness gain of the brightness decreased due to the decrease in the EVDD level. The data voltage generator 340 may output the data voltage VDATA reflecting the ACL value provided by the ACL controller 350 to the data driver integrated circuit (DIC) of the display panel 100.

[0105] The above description shows a case where each control block is implemented in the timing controller 300 and the timing controller 300 performs a series of control processes. However, this is only an exemplary embodiment, and the functions performed by each control block may be implemented in various ways, such as by combining two or more of the host system 200, the timing controller 300, and the data driver 120 or by providing separate control blocks.

[0106] Figure 9 is a control flowchart of the timing controller according to the first exemplary embodiment of the present disclosure, and shows the control flow of the timing controller 300 when displaying the image data supplied from the host system 200 by variably controlling the EVDD level in units of one image frame using the DPC control in the first exemplary embodiment.

[0107] When image data is input from the host system 200 (S110), the timing controller 300 calculates the APL in units of one image frame (S112). The APL calculation of the timing controller 300 and the PLC controller 312 may calculate the APL for each image frame by analyzing the input image data in units of one image frame.

[0108] The timing controller 300 obtains the peak brightness according to the calculated APL (S114). The APL calculation and the PLC controller 312 may obtain the peak brightness from a preset PLC curve according to the APL of the corresponding frame. The PLC curve may be preset and stored according to the brightness, current, driving characteristics, etc. of the display panel 100. The APL calculation and the PLC controller 312 may provide the obtained peak brightness to the EVDD controller 320.

[0109] The timing controller 300 sets the EVDD level according to the peak brightness (S116). The EVDD controller 320 of the timing controller 300 can receive the peak brightness and determine the EVDD level required to display the peak brightness based on pre-stored EVDD setting information. The EVDD level required according to the peak brightness can be obtained and pre-stored in a trial-and-error manner. For example, the EVDD level according to the peak brightness can have a shape similar to the shape of the PLC curve. That is, as the APL becomes larger (the image becomes brighter), the peak brightness and the EVDD level can gradually decrease, and as the APL becomes smaller (the image becomes darker), the peak brightness and the EVDD level can gradually increase.

[0110] The timing controller 300 can control the EVDD level supplied to the display panel by outputting EVDD level setting information to the PMIC of the power supply according to the peak brightness (S118).

[0111] In addition, the timing controller 300 can calculate the ACL value according to the EVDD level setting information (S120). The ACL controller 350 of the timing controller 300 can calculate the ACL value suitable for the set EVDD level. The ACL controller 350 can calculate the ACL value according to the set EVDD level using a pre-designed calculation formula, and can store the ACL value as a look-up table according to the EVDD level and apply the ACL value.

[0112] The timing controller 300 can generate a data voltage by reflecting the ACL value (S122). The data voltage generator 340 of the timing controller 300 can generate a data voltage with a brightness gain adjusted using the ACL value provided by the ACL controller 350.

[0113] The timing controller 300 can output the data voltage VDATA reflecting the ACL value to the data driver IC (DIC) of the display panel 100 (S124).

[0114] Therefore, the display panel 100 can display an image that variably controls the EVDD level and the ACL value in units of one image frame. Therefore, the power circuit cost can be reduced by reducing the maximum power consumption when variably controlling the EVDD level.

[0115] Figure 10 and Figure 11 is a diagram for describing a method of controlling a timing controller according to a second exemplary embodiment of the present disclosure. The second exemplary embodiment shows the control flow of the timing controller 300 when displaying mode setting image data for fixing the EVDD level according to the brightness mode selected by the user input unit 210.

[0116] The host system 200 may receive an input for selecting a brightness mode for adjusting the overall brightness of an image through the user input unit 210. The host system 200 may adjust the brightness of the image data according to the brightness mode selected through the user input unit 210, and then provide the image data to the timing controller 300. The image data for which the mode is set needs to be displayed by fixing the EVDD level according to the brightness mode selected through the user input unit 210, and the EVDD level may also change when the mode changes.

[0117] Figure 10 is a graph showing the characteristics of the EVDD level and the PLC curve defined according to the brightness mode.

[0118] The first brightness mode MODE1, the second brightness mode MODE2, and the third brightness mode MODE3 may be provided according to the peak brightness, and the user may select a desired brightness mode through the user input unit 210.

[0119] Referring to Figure 10 in (a) of, the peak brightness in the first brightness mode MODE1 may be set to 500 nits (nit), the peak brightness in the second brightness mode MODE2 may be set to 400 nits, and the peak brightness in the third brightness mode MODE3 may be set to 300 nits.

[0120] In the first brightness mode MODE1, the PLC curve may be set such that the peak brightness is set to 500 nits in the portion where the APL is less than the reference APL (APL_R1), and the peak brightness of the pixel decreases as the APL increases in the portion where the APL is greater than the reference APL (APL_R1).

[0121] In the second brightness mode MODE2, the PLC curve may be set such that the peak brightness is set to 400 nits in the portion where the APL is less than the reference APL (APL_R2), and the peak brightness of the pixel decreases as the APL increases in the portion where the APL is greater than the reference APL (APL_R2).

[0122] In the third brightness mode MODE3, the PLC curve may be set such that the peak brightness is set to 300 nits in the portion where the APL is less than the reference APL (APL_R3), and the peak brightness of the pixel decreases as the APL increases in the portion where the APL is greater than the reference APL (APL_R3).

[0123] The user may set the brightness of the image by selecting any one of the first brightness mode MODE1, the second brightness mode MODE2, and the third brightness mode MODE3.

[0124] Refer to Figure 10In (b), as the peak brightness increases, the EVDD level can increase. The EVDD level required according to the peak brightness can be obtained and pre-stored in a trial-and-error manner.

[0125] When the peak brightness of the first brightness mode MODE1 is set to 500 nits, the peak brightness of the second brightness mode MODE2 is set to 400 nits, and the peak brightness of the third brightness mode MODE3 is set to 300 nits, EVDD1 with the highest level can be set in the first brightness mode MODE1 with the highest peak brightness. In the second brightness mode MODE2 with the second-highest peak brightness, EVDD2 with the second-highest level can be set, and in the third brightness mode MODE3 with the lowest peak brightness, EVDD3 with the lowest level can be set.

[0126] The host system 200 can adjust the brightness of the image data by correcting the PLC curve according to the brightness mode selected through the user input unit 210, and then provide the image data and the PLC curve data to the timing controller 300.

[0127] Figure 11 is a flowchart for describing the control flow of the timing controller according to the second exemplary embodiment of the present disclosure. The second exemplary embodiment shows the control flow of the timing controller 300 when displaying mode-setting image data that needs to be displayed by fixing the EVDD level according to the brightness mode selected through the user input unit 210.

[0128] When the mode-setting image data with the brightness mode set is input from the host system 200 (S210), the timing controller 300 detects the peak brightness of the PLC curve of the image data (S212). The PLC Max detector 314 of the timing controller 300 can obtain the peak brightness from the PLC curve data input together with the mode-setting image data from the host system 200, and provide the peak brightness to the EVDD controller 320.

[0129] The timing controller 300 sets the EVDD level according to the peak brightness (S216). The EVDD controller 320 of the timing controller 300 can receive the input of the peak brightness, and determine the EVDD level required to display the peak brightness based on the pre-stored EVDD setting information. The EVDD level required according to the peak brightness can be obtained and pre-stored in a trial-and-error manner.

[0130] The timing controller 300 can control the EVDD level supplied to the display panel by outputting the EVDD level setting information to the PMIC of the power supply according to the peak brightness (S218).

[0131] In addition, the timing controller 300 may calculate an ACL value based on the EVDD level setting information (S220). The ACL controller 350 of the timing controller 300 may calculate an ACL value suitable for the set EVDD level. The ACL controller 350 may calculate the ACL value according to a preset calculation formula based on the set EVDD level, and may store the ACL value as a lookup table according to the EVDD level and apply the ACL value.

[0132] The timing controller 300 may generate a data voltage by reflecting the ACL value (S222). The data voltage generator 340 of the timing controller 300 may generate a data voltage, and the luminance gain of the data voltage is adjusted using the ACL value provided by the ACL controller 350.

[0133] The timing controller 300 may output the data voltage VDATA reflecting the ACL value to the data driver IC (DIC) of the display panel 100 (S224).

[0134] Therefore, the display panel 100 may set the EVDD level according to the brightness mode selected by the user, and display an image by applying an ACL value suitable for the set EVDD level.

[0135] As described above, the display device and its driving method according to the exemplary embodiments of the present disclosure may variably control the EVDD level to the peak brightness set in the input image, and change the ACL in combination with the change of the EVDD.

[0136] The display device and its driving method according to the exemplary embodiments of the present disclosure may set the ACL value for controlling the current flowing through the display panel to be low when the EVDD level is high, thereby reducing the maximum power consumption, so that the cost of providing an expensive power supply circuit can be saved.

[0137] The display device and its driving method according to the exemplary embodiments of the present disclosure may improve the brightness reduced due to the decrease of the EVDD by setting the ACL value to be low when the EVDD level is high and setting the ACL value to be high within the limit of maintaining the target power consumption when the EVDD level is low, so that the image quality degradation can be minimized while maintaining the power consumption effect.

[0138] The exemplary embodiments of the present disclosure have the following effects:

[0139] The display device and its driving method according to the exemplary embodiments of the present disclosure may set the ACL value for controlling the current flowing through the display panel to be low when the EVDD level is high to reduce the maximum power consumption, thereby eliminating the cost of providing an expensive power supply circuit.

[0140] The display device and its driving method according to an exemplary embodiment of the present disclosure can improve the brightness reduced due to the decrease in EVDD by setting the ACL value to low when the EVDD level is high and setting the ACL value to high within the limit of maintaining the target power consumption when the EVDD level is low, so that the degradation of image quality can be minimized while maintaining the power consumption effect.

[0141] The display device and its driving method according to an exemplary embodiment of the present disclosure can maintain the target power consumption by controlling the ACL value inversely proportional to the change in the EVDD level, thereby improving the efficiency of the power system.

[0142] The effects of the present disclosure are not limited to those shown above, and more various effects are included within the present disclosure.

[0143] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these exemplary embodiments, and various modifications and implementations can be made without departing from the technical spirit of the present disclosure. Therefore, the exemplary embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit, and the scope of the technical spirit of the present disclosure is not limited by these exemplary embodiments. Therefore, the above exemplary embodiments should be understood as illustrative in all respects and not restrictive. The protection scope of the present disclosure should be interpreted according to the scope of the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the claims of the present disclosure.

[0144] Cross - reference to related applications

[0145] This application claims the priority benefit of Korean Patent Application No. 10 - 2023 - 0160972, filed on November 20, 2023, the entire contents of which are incorporated herein for all purposes.

Claims

1. A display device, comprising: A display panel including a plurality of pixels, each pixel having a light emitting element that emits light by a current corresponding to a data voltage; as well as A timing controller is configured to set an EVDD level required for displaying input image data, set an automatic current limiting ACL value of the display panel according to the EVDD level, and adjust a brightness gain of the input image data according to the ACL value to generate a data voltage.

2. The display device according to claim 1, wherein: The timing controller sets the ACL value such that the ACL value is inversely proportional to a change in the EVDD level.

3. The display device according to claim 1, wherein: The timing controller sets the ACL value so that a target power calculated as a product of the EVDD level and the ACL value is constant.

4. The display device according to claim 1, wherein: The timing controller is configured as follows: detecting the peak brightness of the input image data based on a peak brightness control PLC curve defining the peak brightness of the pixel according to an average picture level APL of one frame of the input image data, and setting the EVDD level in units of the one frame according to the detected peak brightness, and The ACL value is set in units of the one frame according to the EVDD level to generate a data voltage of the input image data.

5. The display device according to claim 4, wherein: The timing controller calculates a target power based on an EVDD level set when the APL is 100% and an ACL value set when the APL is 100%, and sets the ACL value so that the target power is maintained with the ACL value inversely proportional to a change in the EVDD level.

6. The display device according to claim 4, wherein: The timing controller calculates a target power based on an EVDD level set when the APL is 0% and an ACL value set when the APL is 0%, and sets the ACL value so that the target power is maintained with the ACL value inversely proportional to a change in the EVDD level.

7. The display device according to claim 1, wherein: The timing controller detects the peak brightness of the peak brightness control PLC curve set in the input image data to set the EVDD level and the ACL value required to display the input image data, and sets the ACL value so that when the EVDD level changes according to the change of the PLC curve, the ACL value is inversely proportional to the change of the EVDD level.

8. The display device according to claim 1, wherein: The timing controller comprises: a peak brightness detector configured to detect a peak brightness of the input image data; an EVDD controller configured to set the EVDD level according to the peak brightness to output an EVDD level setting signal; an ACL controller configured to set the ACL value according to the EVDD level; and A data voltage generator is configured to adjust a brightness gain of the input image data according to the ACL value to generate a data voltage.

9. The display device according to claim 8, wherein: The peak brightness detector includes an APL calculation and a PLC controller configured to detect the peak brightness of the input image data based on a PLC curve that defines the peak brightness of the pixel according to an average picture level APL of one frame of the input image data.

10. The display device according to claim 8, wherein: The peak brightness detector includes a PLC peak brightness detector configured to detect a peak brightness of a PLC curve set in the input image data.

11. The display device according to claim 8, wherein: The ACL controller calculates a target power based on an EVDD level set when the APL is 100% and an ACL value set when the APL is 100%, and sets the ACL value so that the target power is maintained with the ACL value inversely proportional to a change in the EVDD level.

12. The display device according to claim 8, wherein: The ACL controller calculates a target power based on an EVDD level set when the APL is 0% and an ACL value set when the APL is 0%, and sets the ACL value so that the target power is maintained with the ACL value inversely proportional to a change in the EVDD level.

13. A method for controlling the display device according to any one of claims 1 to 12, the method comprising the following steps: Detecting the peak brightness of the input image data; setting the EVDD level required for displaying the input image data according to the detected peak brightness; setting the ACL value of the display panel so that a target power value calculated as a product of the EVDD level and the ACL value is constant; and The brightness gain of the input image data is adjusted according to the ACL value to generate the data voltage.

14. A method for controlling a display device, the display device comprising a display panel, the display panel comprising a plurality of pixels, each pixel having a light emitting element that emits light by a current corresponding to a data voltage, the method comprising the following steps: Detecting peak brightness of input image data; setting an EVDD level required for displaying the input image data according to the detected peak brightness; setting an ACL value of the display panel so that a target power value calculated as a product of the EVDD level and the ACL value is constant; and The brightness gain of the input image data is adjusted according to the ACL value to generate a data voltage.

15. The method according to claim 14, wherein: The step of detecting the peak brightness of the input image data comprises: The peak brightness of the input image data is detected based on a peak brightness control PLC curve, which defines the peak brightness of the pixel according to an average picture level APL of one frame of the input image data.

16. The method according to claim 15, wherein: The step of setting the EVDD level required for displaying the input image data according to the detected peak brightness comprises: The EVDD level is set in units of the one frame according to the detected peak brightness.

17. The method according to claim 16, wherein: The step of setting the ACL value of the display panel includes: The ACL value is set in units of the one frame according to the EVDD level.

18. The method according to claim 14, wherein: The step of setting the ACL value includes setting the ACL value so that the ACL value is inversely proportional to a change in the EVDD level.

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