Devices, systems, and methods for decoding metadata locations during read operations

Abstract

The present disclosure relates to devices, systems, and methods for decoding metadata locations during read operations. The memory device stores data and associated metadata. During a read operation, the memory receives a column address and decodes it into a column select value. A metadata block containing the associated metadata is read based on a range of values containing the column selection value. The memory subtracts a minimum value of the range of values from the column selection value to determine a metadata location value. The metadata position value indicates a relative position of the associated metadata within the block of metadata, and the data and the associated metadata are read out.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor memory devices. Specifically, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Background Art

[0002] Information can be stored on individual memory cells of a memory as physical signals (e.g., charge on a capacitive element). During an access operation, an access command can be received together with address information specifying which memory cells should be accessed.

[0003] There is increasing interest in enabling a memory to store additional information in an array associated with several data items. For example, error correction information and / or metadata can be stored in the array together with its associated data. During a read operation, a large data block containing metadata associated with several different data addresses can be read. It may be necessary to quickly and easily locate the metadata associated with the current read address within the block. Summary of the Invention

[0004] According to an aspect of the present disclosure, a device is provided. The device includes: a memory array; a column decoder configured to decode a column address into a value of a column select signal and read a block of metadata bits from the memory array based on a value range in which the value of the column select signal falls; and a metadata position decoder circuit configured to identify a relative position of the value of the column select signal within the value range and configured to select a portion of the block of metadata bits based on the relative position.

[0005] According to another aspect of the present disclosure, a device is provided. The device includes: a memory array; a decoder circuit configured to decode a column address into a first column select value, identify a value range in which the first column select value falls, generate a second column select value based on the identified range, and read a metadata block from the memory array based on the second column select value; and a subtractor circuit configured to subtract a minimum value of the identified value range from the first column select value to generate a relative position value, wherein a portion of the metadata block is selected based on the relative position value.

[0006] According to yet another aspect of the present disclosure, a method is provided. The method includes: decoding a column address into a column select value as part of a read operation; identifying a value range containing the column select value; reading a metadata block associated with the value range; subtracting a minimum value of the value range from the column select value to generate a relative position value; and selecting a portion of the metadata block based on the relative position value and providing the selected portion as part of the read operation. Brief Description of the Drawings

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of an access circuit according to some embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of a metadata location decoder circuit according to some embodiments of the present disclosure.

[0011] Figure 5 is a flowchart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the present invention system and method, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration specific embodiments in which the described system and method may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Additionally, for clarity, details of certain features will not be described when they are obvious to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. Accordingly, the following detailed description is not to be considered as limiting, and the scope of the present disclosure is defined only by the appended claims.

[0013] A memory array typically may include a number of memory cells arranged at intersections of word lines (rows) and bit lines / digit lines (columns). Columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns within each of the active column planes to provide data. When an access command is received, the memory may prefetch a memory word (e.g., a number of data bits) and one or more associated bits from the memory, and replace the prefetched data with new data (e.g., as part of a write operation) or provide the prefetched data from the memory device (e.g., as part of a read operation).

[0014] A memory device may store additional information associated with each codeword. For example, the additional information may include parity bits that are part of an error correction scheme, metadata that contains information about the data codeword (or is part of information about a larger data set that contains the codeword), or a combination thereof. During an example read operation, the memory may first prefetch a metadata block and store it. This metadata block may contain metadata associated with several different data codewords. For example, if the data prefetch is 256 bits and there are 16 metadata bits for every 256 data bits, the prefetched metadata block may contain 256 metadata bits or 16 groups of 16 metadata bits, each metadata bit associated with a different data codeword. When reading data, the memory may use the column address associated with the data to locate the metadata associated with the data within the stored metadata block, and thus the data and metadata may be provided together. This operation may need to be performed quickly and without a large amount of circuitry.

[0015] This disclosure relates to an apparatus, system, and method for decoding a metadata location during a read operation. During a read operation, a memory receives a column address and decodes it into a CS signal. The CS signal falls within a CS value range, and the range is associated with a metadata block. The metadata block associated with the range is read from an array and stored in a plurality of metadata latches. A metadata location decoder circuit subtracts a minimum value of the CS value range from the CS signal to generate a metadata location. Based on the metadata location, a metadata set from the block is read from the latch and provided together with the data. In this way, the metadata location decoder circuit determines the relative position of the CS value within the CS value range and uses the relative position to locate the relevant metadata set within the metadata block. This may be useful because subtraction may be a fast and easy way to locate relevant metadata within a block.

[0016] For example, the memory may receive a read command and a column address, which is decoded into CS1. The CS value (CS1) falls within a first range of CS values from CS0 to CS15. The memory reads the metadata blocks associated with CS0 to CS15 and stores them in 16 sets of latches, with each set of latches storing a metadata set. The metadata location decoder subtracts the minimum value from the range (0) from the current value (1) to obtain the value 1. Thus, the metadata location decoder indicates that the metadata set in the set of latches with index "1" is the set associated with the data read in response to CS1. In another example operation, the column address may be decoded into CS17. The CS value falls within a second range (CS16 to CS31), and thus different metadata blocks are read and stored in the metadata latches. The metadata location decoder subtracts the minimum value of the range (16) from the value (17) and obtains 1. Thus, the metadata is still stored in the set of latches with index "1", but the metadata will be different because different metadata blocks (associated with different ranges of CS values) are read.

[0017] Locating metadata in a memory that performs consecutive accesses to different CS values within a CS range in this way can be particularly useful. For example, in a low-power memory such as an LPDDR5 memory, to save power, the memory may activate a row and then perform multiple consecutive read operations along different CS values on that row. If the CS values are accessed sequentially (or nearly so), the same metadata block may still be stored in the metadata latches and the metadata location circuit will only need to identify the set of latches storing the metadata associated with the current read operation.

[0018] As used herein, the term data may represent any bit of information that a controller desires to store and / or retrieve from a memory. The term metadata may represent any bit of information about the data that the controller writes to and / or receives from the memory. For example, metadata may be information generated by the controller about the data, about the way or location in which the data is stored in the memory, about the number of errors detected in the data, and so on. The data and metadata together represent the information that is written to the memory by the controller and then also read from the memory by the controller, where the data and metadata differ in content and in the way they are generated, because the metadata is based on information about the data. The term parity may represent any bit generated by an error correction circuit of the memory based on the data, metadata, or a combination thereof. The parity is typically retained within the memory. In some embodiments, the amount of data and / or metadata retrieved as part of a single access operation may represent a group of bits that is a larger piece of information. For example, the metadata bits (e.g., 4 bits) retrieved as part of a single access operation may not have any meaning by themselves, but may have meaning when combined with a group of metadata bits retrieved as part of other access operations (e.g., to other memory arrays and / or to the same array at different times).

[0019] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The device may be operated by a host or a controller (e.g., a processor). In some embodiments, the memory and its controller may be separate components. In some embodiments, for example, the memory and the controller may be integrated together in a single-chip system.

[0020] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of banks. In Figure 1 the embodiment shown, the memory array 118 is shown as including eight banks BANK0 to BANK7. More or fewer banks may be included in the memory array 118 of other embodiments. For example, there may be 4, 16, 32, or other numbers of banks. In some embodiments, the plurality of banks (and their associated circuits) may operate together, as described in more detail herein.

[0021] Each bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC disposed at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder 108 based on a row address XADD, and the selection of the bit lines BL is performed by a column decoder 110 based on a column address YADD. In Figure 1In an embodiment, the row decoder 108 includes a respective row decoder for each bank and the column decoder 110 includes a respective column decoder for each bank.

[0022] The bit lines BL are coupled to respective sense amplifiers (SAMP). During an example read operation, the word lines are activated and data from the memory cells is coupled to the intersecting bit lines BL where the data is amplified by the sense amplifiers SAMP and transferred to the ECC circuit 120 via local data lines (LIO), transfer gates (TG), and global data lines (GIO). Conversely, write data output from the ECC circuit 120 is transferred to the bit lines BL via complementary main data lines GIO, transfer gates TG, and complementary local data lines LIO, amplified by the sense amplifiers, and written to the memory cells MC coupled to the bit lines BL at the intersection with the active word line WL.

[0023] The semiconductor device 100 may employ a plurality of external terminals, such as pads, which include command and address (C / A) terminals coupled to command and address buses to receive commands and addresses, clock terminals for receiving clocks CK and / CK, data terminals DQ coupled to data buses to provide data, and power terminals for receiving power potentials VDD, VSS, VDDQ, and VSSQ.

[0024] The clock terminals are supplied with external clocks CK and / CK provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operations of the circuits included in the input / output circuit 122, for example, provided to a data receiver to time the reception of write data. The input / output circuit 122 may include several interface connections, each of which may be coupled to one of the DQ pads (e.g., pads that can serve as external connections to the device 100).

[0025] As part of an access operation, the C / A terminals may be supplied with a memory address. The memory address supplied to the C / A terminals is transmitted via the command / address input circuit 102 to the address decoder 104. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The row address XADD can be used to determine which row should be opened (e.g., which word line should be activated), which can cause data in the memory cells along the word line to be coupled to the intersecting bit lines. The column decoder 110 can provide one or more column select signals CS based on the column address, which can be used to determine which bit lines are coupled to the LIO. The address decoder 104 can also supply the decoded bank address BADD, which can indicate one or more banks of the memory array 118 in which the access operation should be performed.

[0026] The C / A terminals may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0027] The command may be provided as an internal command signal via the command / address input circuit 102 to the command decoder 106. The command decoder 106 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide signals indicating whether to read, write data, etc.

[0028] The memory device 100 may store different types of information in the array 118. For example, the controller may read and write data to the array. The data may have associated metadata (which may indicate one or more pieces of information about the data, for example) that is also written and read by the controller to and from the controller. The memory device 100 includes an error correction code (ECC) circuit 120, which generates parity bits based on the data and / or metadata when writing the data and / or metadata. When reading the data and / or metadata and its associated parity, the ECC circuit 120 uses the associated parity to locate errors in the data and / or parity.

[0029] When the metadata is enabled, the memory device 100 may use a two-pass access system to retrieve the data and metadata together. The device 100 accesses a metadata block in the first pass and stores the metadata block in the metadata latch 123 (which is in Figure 1in the component shown as the IO circuit 122 in FIG. 1, and then accesses the data in a second pass. In some embodiments, for consistency in the memory architecture, the metadata block may be the same size (e.g., the same number of bits) as the amount of data read during an access operation. However, since data and metadata typically do not match at a 1:1 ratio, the metadata block may contain metadata corresponding to many different column addresses of the data. Thus, the metadata location decoder circuit 111 (which is shown as the column decoder 110 in Figure 1 the component shown in FIG. 2) is used to determine which portion of the metadata block is the metadata associated with the data.

[0030] During a read operation, the column decoder 110 may decode the column address YADD into a value of a column select signal associated with the bit line storing the data. Based on the CS value, the column decoder 110 also generates a value of the CS signal associated with the location storing the MD, and the CS value storing the metadata may be based on a range of CS values that includes the CS value where the data is located. For example, a first range may be associated with a first CS value of the metadata, a second range may be associated with a second CS value of the metadata, and so on. If the CS value of the metadata is different from a previous access operation, then the CS value of the metadata is provided by the column decoder 110 and the metadata is read out and stored in the metadata latch 123, and then the CS value of the data is provided by the column decoder and the data is read out. If the CS value of the metadata is the same as a previous access operation, then only the CS value of the data is provided and only the data is read out. When the data is read out, the metadata location decoder circuit determines the relative position of the data CS value within the CS value range and generates a relative position signal or metadata location signal MD_Loc, which is used to determine which metadata latch 123 stores the metadata associated with the data.

[0031] For example, when a read command (along with row, column, and bank addresses) is received, the row decoder 108 activates a word line based on the row address XADD. The column decoder decodes the column address YADD into a data CS value. The column decoder 110 generates a metadata CS value based on the data CS value (e.g., the range into which the data CS value falls), and if the value of the metadata CS value is different from a previous metadata CS value, the metadata CS value is provided to the array 118. In response to the metadata CS value, a metadata block along with its associated parity can be read out to the ECC circuit 120 and any errors can be detected / corrected. The corrected metadata block is stored in the metadata latch 123. Then, the column decoder 110 provides a data CS signal, and data along with its associated parity can be read out and the ECC circuit 120 can detect / correct errors in the data. The metadata position decoder 111 determines which portion of the metadata block stored in the metadata latch 123 is associated with the data, and provides a metadata relative position signal MD_Loc to the metadata latch. The corrected data and the portion of the stored metadata block associated with MD_Loc are provided to the DQ terminals.

[0032] During an example write operation, the memory device 100 receives a write command and data (or metadata) to be written (along with row, column, and bank addresses). The ECC circuit 120 generates parity bits based on the data (or metadata). The row decoder activates a word line based on the row address XADD. The column decoder decodes the column address YADD into a CS value. The data (or metadata) and parity are written to memory cells at the intersections of the bit lines selected by the CS value and the active word lines.

[0033] In some memory implementations (such as low-power memories (e.g., LPDDR)), access operations can typically be performed on several consecutive CS values (for data) along a single row. For example, a read sequence can be performed with a row address provided and the word line activated, and then data is read from CS0, CS1, CS2, etc. When the read operation sequence is performed in this way, if the read operations are all associated with the same metadata block, the metadata block can be read once and stored in the metadata latch 123, and then when the data is read, it is matched to the associated portion of the stored metadata by the metadata position decoder circuit 111. During a write operation, the controller can write a data sequence to sequential CS values along the row, and then provide the metadata block to be written.

[0034] The device 100 includes a refresh control circuit 116, each refresh control circuit 116 being associated with a bank of the memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated bank. The refresh control circuit 116 provides a refresh address RXADD (along with one or more refresh signals,Figure 1 (not shown in the figure). The row decoder 108 performs a refresh operation on one or more word lines associated with RXADD. The refresh control circuit 116 can perform various types of refresh operations, which can determine how to generate the address RXADD and other details such as the number of word lines associated with the address RXADD.

[0035] The ECC circuit 120 can detect and / or correct errors in the accessed data. As part of a write operation, the ECC circuit 120 can receive bits from the IO circuit 122 and generate parity bits based on the received bits. The received bits and the parity bits are written to the memory array 118. During an example read operation, the ECC circuit 120 receives a set of bits and their associated parity bits from the array 118 and uses them to locate and / or correct errors. For example, in a single error correction (SEC) scheme, up to one error bit can be located and detected. In a single error correction double error detection (SECDED) scheme, up to one error bit can be corrected, but two errors can be detected (however, the bits causing the errors are not individually located and thus cannot be corrected). The ECC circuit 120 can correct the information and then provide the corrected information (and / or a signal indicating the detected error) to the IO circuit 122. Usually, the parity bits may not be provided to the IO circuit 122.

[0036] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0037] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals can be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals can be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0038] Figure 2 is a block diagram of an access circuit according to some embodiments of the present disclosure. In some embodiments, the access circuit 200 can implement a memory device (such as Figure 1a portion of the memory device 100). The access circuit 200 shows components and signals related to performing read operations and locating relevant portions of metadata. Figure 2 Certain components and signals (such as a row decoder, row address XADD, etc.) that are still available as part of the described access operations are not shown.

[0039] The access circuit 200 includes a column decoder 210 (e.g., Figure 1 110 of) and a metadata location decoder circuit 212 (e.g., Figure 1 111 of). The column decoder 210 provides a column select signal CS to one or more banks 220 (e.g., Figure 1 118 of). The bank 220 provides data and / or metadata through one or more associated ECC circuits 222 (e.g., Figure 1 120 of). The metadata is stored in a metadata latch 230 (e.g., Figure 1 123 of) and then a portion of the stored metadata is matched with the read data D based on the metadata relative position signal MD_Loc provided by the metadata location decoder circuit 212.

[0040] In Figure 2 an example implementation, access operations can be performed on two banks 220 (here labeled Bank A and Bank B) at a time. The two banks 220 can represent two banks selected by a bank address. The banks can act together during an access operation. The two banks 220 can act effectively as if they were a single bank that is twice the size of a single bank.

[0041] During an example read operation, the column decoder 210 receives a column address YADD. The column decoder 210 decodes the column address YADD into a column select signal. The value into which the column address YADD is decoded can represent a column select value CS_D associated with the data to be read. The column decoder 210 can in turn generate a metadata column select signal CS_MD, which is associated with a metadata block MD_Block that contains metadata associated with the data to be read. The metadata CS value CS_MD can be generated based on the value CS_D. For example, if the value CS_D falls within a first value range (e.g., 0 ≤ CS_D < i - 1), then CS_MD can have a first value CS_MD = X, if the value CS_D falls within a second value range (e.g., i ≤ CS_D < j - 1), then CS_MD can have a second value CS_MD = Y, if the value CS_D falls within a third value range (j ≤ CS_D < k - 1), then CS_MD can have a third value CS_MD = Z, and so on.

[0042] If the value of CS_MD is different from the previous value of CS_MD (e.g., CS_D is in a different range than the previous access operation), then column decoder 210 may first perform an access pass based on CS_MD to read out the metadata block MD_Block associated with the value of CS_MD. Column decoder 210 provides CS_MD to bank 220 and reads out the metadata block and the parity associated with the metadata block to the ECC circuit. For example, in response to CS_MD, 256 metadata bits and 16 parity bits may be read out to ECC circuit 222 (128 MDs and 8 parity from each bank). ECC circuit 222 may detect / correct errors in metadata block MD_Block and store the metadata block in metadata latch 230. Metadata latch 230 includes an array of different latches 232. Each group of latches stores a portion of metadata block MD_Block associated with a different data block (e.g., different CS_D values). The number of latch groups 232 may be based on the amount of metadata associated with the data block. For example, if metadata block MD_Block is 256 and there are 16 bits of MD for each data block, then there will be 16 groups of latches 232, each group of latches 232 having 16 individual latch circuits. If there are 8 bits of MD for each data block, then there will be 32 groups of latches 232, each group of latches 232 having 8 individual latch circuits, and so on.

[0043] As a second access pass (or as a first access pass if CS_MD is the same value as the previous value of CS_MD), data may be read. Signals provided as part of this data access pass are shown in dashed lines. Column decoder 210 provides the data CS value CS_D. In response thereto, bank 220 provides the data and its associated parity. For example, 256 data bits and 16 parity bits may be read (128 data and 8 parity from each bank). ECC circuit 222 detects / corrects errors in the data and passes the corrected data D.

[0044] Metadata position decoder circuit 212 generates a metadata relative position signal MD_Loc based on the data CS value CS_D and the value range associated with the metadata CS value CS_MD. Metadata position decoder circuit 212 may subtract the minimum value of the range from the data CS_D value to obtain the value of the relative position signal MD_Loc. For example, referring to the above values, if the value of CS_D is in the first range, then MD_Loc = CS_D – 0, if the value of CS_D is in the second range, then MD_Loc = CS_D – i, if the value of CS_D is in the third range, then MD_Loc = CS_D – j, and so on.

[0045] The metadata location decoder circuit 212 provides the value of MD_Loc to the metadata latch 230. Each of the latch banks 232 is indexed by the value of MD_Loc. Thus, if MD_Loc has a first value, the first set of latch banks 232(0) can be accessed. If MD_Loc has a second value, the second set of latch banks 232(1) can be accessed. In this way, the value of MD_Loc can represent the relative position of the metadata within the metadata block. The set of latch banks indexed by the value of MD_Loc provides the metadata MD (e.g., along the metadata bus), which is provided together with the data D.

[0046] Figure 3 is a block diagram of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 300 may represent Figure 1 the memory device 100 and / or Figure 2 a portion of the memory device 200. Figure 3 The view of Figure 1 118 and / or Figure 2 220 of Figure 1 120 and / or Figure 2 222 of Figure 1 122 of

[0047] Figure 3 shows the bank 302 (e.g., Figure 3 as described for the single bank 302 in

[0048] The bank 302 is organized into several column planes 310 to 314. Each of the column planes 310 to 314 represents a portion of the bank. Each column plane 310 to 314 contains several memory cells at the intersections of word lines WL and bit lines. The word lines can extend across multiple column planes 310 to 314. For example, when a row is activated, it can activate the memory cells in each of the column planes 310 to 314. The bit lines can be specific to a single column plane.

[0049] The bit lines can be grouped together into groups that are jointly activated by the value of the CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column selection group; however, there may be multiple bit lines accessed by the value of the CS. For example, each vertical line can represent 8 individual bit lines, all of which are jointly accessed by the value of the CS. As used herein, the "value" of the CS can refer to the decoded signal provided to the group of bit lines. Thus, the first value can represent the first value of the multi-bit CS signal, or the first value after decoding the valid signal along the signal line associated with the valid value.

[0050] During an access operation, a row decoder (e.g., Figure 1 108) can decode the row address and activate the selected one of the word lines. Memory cells along the activated word line can be coupled to their respective bit lines. Sense amplifiers 320 to 324 coupled to the bit lines amplify the signal stored in the coupled memory cells onto the bit lines (or write an external bit onto the bit lines). The CS signal determines which bit lines are coupled to the ECC circuit 332 via LIO and GIO.

[0051] Memory bank 302 includes a set of data column planes 310 and an additional column plane 312. The additional column plane 312 can be used to store additional information, such as error correction parity bits. In some embodiments, the memory bank 302 may also include an optional global column redundancy (GCR) column plane 314. In some embodiments, the data column planes 310 and the additional column plane 312 may be substantially similar to each other. In some embodiments, the GCR plane 314 may have fewer memory cells (e.g., fewer column selection groups) than the data column plane 210. The GCR CP 314 includes several redundant columns that can be used as part of a repair operation. If the value of the CS signal is recognized as including a defective memory cell in one of the data column planes 310, then the memory can be remapped such that the data that would otherwise be stored in the column plane for the value of the CS is instead stored in the GCR CP 314.

[0052] In an example implementation, the bank 302 may include 16 data column planes 310(0) through 310(15). Each of the data column planes 310 includes 64 groups of bitlines activated by the value of a column select signal, and each group of bitlines includes 8 bitlines. Thus, when a wordline is opened in response to a row address and the column select signal is provided to each of the 16 column planes, then 8 bits are accessed from each of the 16 column planes, for a total of 128 bits. The column select signal is also provided to an additional column plane 312, and for an additional 8 bits, the column select signal may be the same or a different value than the column select signal provided to the data column planes 310. If a repair has been performed, then the GCR CP 314 may also be accessed and the value on the GCR LIO may be used while ignoring the LIO of the column plane it replaces. Thus, during a typical access pass, the access operation may read or write 128 bits from the data column planes 310 (8 bits replaced from the GCR CP 314 if a repair exists) and 8 additional bits from the additional CP 312.

[0053] In an example write operation, the controller may provide 128 information bits (per bank), whether data or metadata, depending on what is written through the I / O circuit 334. The ECC circuit 332 generates 8 parity bits based on the 128 information bits. The row decoder activates wordlines based on the row address. The column decoder provides the value of the CS signal based on the provided column address. The column select groups are coupled to sense amplifiers, which write the 128 information bits and 8 parity bits to memory cells at the intersection of selected bitlines and active wordlines. Data or metadata may be written to the data column planes 310, and parity may be written to the additional column plane 312.

[0054] In some example embodiments (e.g., LPDDR), the wordlines may remain active and the controller may perform consecutive operations on consecutive column select values. For example, the controller may provide a row address to activate the wordlines and then write to a first CS value, then write to a second (consecutive) CS value, and so on.

[0055] Since the information is written in 128-bit chunks (per bank), and the ratio of metadata to data is typically less than 1:1, the controller can perform several data write operations and then write the metadata. For example, if the ratio of metadata to data is 1:16 (e.g., 128 data bits and 8 metadata bits per bank), then the controller can perform up to 16 write operations along the word line before writing the metadata block that contains the written data. As described in more detail herein, certain CS values can be reserved to store metadata. In some embodiments, during a write operation, the controller can directly write the metadata by providing the column address associated with the metadata CS value. In some embodiments, the controller can indicate the range of metadata write operations and their associated data CS values, and the column decoder can generate the CS values for writing the metadata.

[0056] Unlike the write operation in which data and metadata can be written separately, during a read operation, the data and its associated metadata are provided together. Thus, during a read operation, the controller can provide the row and column addresses associated with the location of the data, and the memory can identify the metadata associated with the data such that the metadata can be provided together with the data.

[0057] During an example read operation, the memory can receive the row and column addresses. The row address can be decoded by the row decoder. The column address can be decoded into a data column select value CS_D that indicates the column selection group in the data column plane 310 that stores the data. Based on the data column address CS_D, the column decoder can also generate a metadata column select value CS_MD. The metadata column select value CS_MD can be based on the mapping of how the memory stores the data and metadata. For example, the value of CS_MD can be based on the range of values that CS_D falls into. In an example implementation, if each CS value accesses 128 bits (per bank), and there are 8 metadata bits for each data access (per data CS value), then each CS value for the metadata stores the equivalent of 16 data CS values of metadata. Since there are 64 possible CS values, four CS values can be reserved for the metadata, with each CS value associated with 16 CS values for the data. For example, the metadata can be stored in the last four CS values (CS60 to CS63). Thus, when CS_D is between 0 and 15, CS_MD is CS60, when CS_D is between 16 and 31, CS_MD is CS61, and so on. Other mappings can be used in other example embodiments, and more or fewer CS values can be reserved for the metadata based on other ratios of data to metadata, other numbers of bit lines per CS group, etc.

[0058] After the CS_MD value is generated, if the previous operation was a read operation, the column decoder may compare it to the previous value of CS_MD. If there is no match, a two-pass operation may be performed, first for metadata and then for data. If there is a match, the metadata block containing the associated metadata has been stored in the metadata latch 336 (e.g., Figure 1 123 and / or Figure 2 230) and can only perform a single access operation on the data.

[0059] In a two-pass operation, as part of the first pass, the column decoder provides a metadata CS value CS_MD and the bit line associated with CS_MD is coupled to the ECC circuit 332. In response to CS_MD, 128 metadata bits (per memory bank) are read out from the data column plane 310, and 8 parity bits are read out from the additional column plane 312. The ECC circuit 332 detects / corrects errors in the metadata based on parity. For example, the ECC circuit 332 may implement single error correction (SEC), in which at most one erroneous bit may be located and corrected. The 128 corrected metadata bits represent all or part of a metadata block (e.g., Figure 2 MD_Block) and stored in metadata latch 336. For example, if each access operation accesses two memory banks, the 128 corrected metadata bits may represent half of the metadata block and the other half may come from the other memory bank accessed.

[0060] In a one-pass operation, or in the second pass of a two-pass operation, the column decoder provides a data CS value CS_D, and the bit line associated with CS_D is coupled to the ECC circuit 332. In response to CS_D, 128 data bits are read out from the data column plane 310 and 8 parity bits are read out from the additional column plane 312. The ECC circuit 332 detects / corrects errors in the data and provides the corrected data to the IO circuit 334. In embodiments where multiple memory banks are accessed, the data may be combined with data provided from other memory banks accessed simultaneously. Metadata location decoder circuits (e.g., Figure 1 111 and / or Figure 2 212) provides a metadata location signal MD_Loc to the metadata latches, which indicates which metadata latch contains metadata associated with this read operation. The selected portion of the metadata is provided to the DQ terminal along with the read data.

[0061] Figure 4 is a block diagram of a metadata position decoder circuit according to some embodiments of the present disclosure. In some embodiments, the metadata position decoder circuit 310 may implement Figure 1 metadata location decoder circuit 111 and / or Figure 2The metadata location decoder circuit 212. The metadata location decoder circuit 310 shows an arrangement of components that can be part of a column decoder (e.g., Figure 1 110 of Figure 2 and / or 210 of Figure 4 Also shown in is a set of metadata latches 420, which can implement Figure 1 the metadata latch 123 of Figure 2 and / or the metadata latch 230 of Figure 3 and / or the metadata latch 336 of

[0062] The metadata location decoder 410 includes a decoder circuit 412 that determines the data CS value CS_D and the minimum value CSMD_Min of the value range associated with the metadata CS value into which the CS_D value falls. The metadata location decoder 410 also includes a subtractor circuit 414 that subtracts CSMD_Min from CS_D to generate a metadata location signal MD_Loc. The latch decoder circuit 416 decodes the metadata location signal MD_Loc to determine which set of latches 422 of the metadata latches 420 is coupled to the metadata bus.

[0063] The decoder circuit 412 receives a row address and generates a data CS value CS_D based on the row address. Based on the mapping of data to metadata, the decoder 412 also generates a metadata CS value based on the value range into which CS_D falls. For example, referring again to the example implementation discussed with respect to Figure 3 if the value of CS_D is between 0 and 15, then CS_MD can have a first value (e.g., CS60), if the value of CS_D is between 16 and 31, then CS_MD can have a second value (e.g., CS61), if the value of CS_D is between 32 and 47, then CS_MD can have a third value (e.g., CS62), and if the value of CS_D is between 48 and 59 (since CS60 to CS63 are used for MD), then CS_MD can have a fourth value (e.g., CS63). Based on the range used to determine CS_MD, the decoder circuit 412 can also provide the minimum value CSMD_Min, which represents the minimum value of the CS_MD value range into which the value of CS_D falls. For example, using the above example implementation, if CS_D is between 0 and 15, then CSMD_Min will be 0. If CS_D is between 16 and 31, then CSMD_Min will be 16, and so on.

[0064] The subtractor circuit 414 determines the value of the MD location signal MD_Loc based on the data CS value CS_D and the minimum value CSMD_Min. The value of MD_Loc can be determined based on Equation 1 below:

[0065] MD_Loc = CS_D – CSMD_Min Equation 1

[0066] In this way, the value of MD_Loc can represent the relative position of the value of CS_D within the value range associated with the value of CS_MD used.

[0067] The latch decoder circuit 416 decodes the value of MD_Loc into a signal that activates one of the latch groups 422 of the metadata latch 420. For example, there may be N + 1 groups of latches 422(0) to 422(N), and each group of latches stores K metadata bits (e.g., each group may include latches 0 to K - 1). The N + 1 groups of latches can represent N + 1 possible values of MD_Loc or the number of different CS_D values in a range. Based on the decoded value of MD_Loc, one of the latch groups is activated and its K bits are provided to the metadata bus for reading out to the DQ terminals.

[0068] Figure 5 is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 500 may be implemented by one or more of the devices or systems described herein. For example, method 500 may be performed by Figure 1 memory device 100, Figure 2 memory device 200, and / or Figure 3 memory device 300. Specifically, method 500 may be performed by a metadata position decoder circuit (e.g., Figure 1 111 of Figure 2 212 of Figure 4 410 of ).

[0069] Method 500 starts at block 510, which describes decoding a column address into a column select value (e.g., a data column select value CS_D) as part of a read operation. Block 510 may be followed by block 520, which describes identifying a value range that includes the column select value. For example, method 500 may include determining whether the column select value falls within a first range, a second range, a third range, etc. Method 500 may include generating a second column select value (e.g., a metadata column select value CS_MD) based on the identified range. Method 500 may include comparing the second column select value with a previous second column select value from a previous read operation. If there is no match, then the method may proceed to block 530. If there is a match, then the method may include skipping block 530 and instead proceeding to block 540.

[0070] Block 530 describes reading a metadata block associated with a value range. The metadata block may include several sections, each section associated with a different data block that can be read from a different CS value within the CS value range associated with the metadata block. The method may include providing a second CS value and reading the metadata block based on the second CS value. The method may include reading a plurality of parity bits as well as the metadata block and using an error correction circuit (e.g., Figure 1 120 of Figure 2 222 of Figure 3 and / or 332 of

[0071] to correct / detect errors in the metadata block based on the plurality of parity bits. Figure 1 123 of Figure 2 222 of Figure 3 and / or 336 of Figure 4 420 of

[0072] Method 500 may include storing the metadata block in a metadata latch circuit (e.g.,

[0073] Method 500 may include storing different portions of the metadata block in different sets of latches of the metadata latch circuit. Figure 1 111 of Figure 2 212 of Figure 4 and / or 410 of Figure 4 414 of

[0074] Block 530 is typically followed by block 540, which describes subtracting the minimum value of the value range from the column select value to produce a relative position value (e.g., MD_Loc). For example, the subtraction may be performed by a subtractor circuit (e.g.,

[0075] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes or separated and / or performed in separate devices or device parts according to the systems, apparatuses, and methods of the present invention.

[0076] Finally, the foregoing discussion is intended to illustrate only the system of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Accordingly, while the system of the present invention has been described in particular detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments may be devised by those of ordinary skill in the art without departing from the broader and intended spirit and scope of the system of the present invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: Memory array; a column decoder configured to decode a column address into a value of a column select signal and to read a block of metadata bits from the memory array based on a range of values ​​within which the value of the column select signal falls; A metadata position decoder circuit is configured to identify a relative position of the value of the column select signal within the range of values ​​and is configured to select a portion of the block of metadata bits based on the relative position.

2. The apparatus of claim 1, wherein the metadata position decoder circuit comprises a subtractor circuit configured to subtract a minimum value of the range of values ​​from the value of the column select signal to generate a relative position signal.

3. The apparatus of claim 1, wherein the column decoder is further configured to read a plurality of data bits from the memory array based on the column select signal value, wherein the selected portion of the block of metadata bits is associated with the plurality of data bits.

4. The apparatus of claim 1, further comprising metadata latch circuitry comprising multiple sets of latches, wherein one of the multiple sets of latches is selected based on the relative position value.

5. The apparatus of claim 1, wherein the column decoder is configured to generate a second column select value based on the range of values, the metadata block being read from the memory array based on the second column select value. 6 . The apparatus of claim 5 , wherein the column decoder is configured to compare the second column select value with a previous column select value and not read a plurality of metadata if they match.

7. The apparatus of claim 1, wherein the memory array comprises first and second memory banks, and wherein the metadata bit blocks are read from the first and second memory banks.

8. A device comprising: Memory array; a decoder circuit configured to decode a column address into a first column select value, identify a range of values ​​within which the first column select value falls, generate a second column select value based on the identified range, and read a metadata block from the memory array based on the second column select value; and A subtractor circuit is configured to subtract a minimum value of the identified range of values ​​from the first column selection value to produce a relative position value, wherein a portion of the metadata block is selected based on the relative position value.

9. The apparatus of claim 8, further comprising metadata latch circuitry comprising a plurality of sets of latches configured to store the metadata block.

10. The apparatus of claim 9, further comprising a second decoder circuit configured to select one of the plurality of sets of latches based on the relative position value.

11. The apparatus of claim 8, wherein the decoder circuit is configured to read a plurality of data bits from the memory array based on the first column select value.

12. The apparatus of claim 11, wherein the metadata block is 256 metadata bits, the portion of the metadata block is 16 bits, and the plurality of data bits is 256 data bits.

13. The apparatus of claim 8, wherein the decoder circuit is further configured to read a plurality of parity bits based on the second column select value, The apparatus further includes an error correction code (ECC) circuit configured to receive a metadata block and the plurality of parity bits and to correct errors in the metadata block based on the plurality of parity bits.

14. A method comprising: decoding a column address into a column select value as part of a read operation; identifying a range of values ​​that includes the column selection value; reading a metadata block associated with the value range; subtracting a minimum value of the range of values ​​from the selected value of the column to produce a relative position value; A portion of the metadata block is selected based on the relative position value and the selected portion is provided as part of the read operation.

15. The method according to claim 14, further comprising: generating a second column of selected values ​​based on the value range; and The metadata block is read based on the second column selection value.

16. The method according to claim 15, further comprising: comparing the second column select value to a previous second column select value from a previous read operation; and If the second column select value matches the previous second column select value, then reading the metadata block is skipped.

17. The method of claim 14, further comprising: reading a plurality of data bits based on the column select value; and The plurality of data bits and the selected portion of the metadata block are provided as part of the read operation.

18. The method of claim 14, further comprising: storing portions of the metadata block in corresponding sets of latches of a metadata latch circuit; and One of the sets of latches is selected based on the relative position value.

19. The method of claim 14, further comprising reading the metadata block from a first memory bank and a second memory bank of a memory array.

20. The method of claim 14, further comprising: reading a plurality of parity bits associated with the metadata block; and Errors in the metadata block are detected or corrected based on the plurality of parity bits.

Images