Memory system, operating method thereof, and storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a storage medium. A memory system includes: a memory device including a plurality of memory blocks, the memory blocks including a plurality of memory cells; a memory controller coupled to the memory device and configured to: determine a storage mode of the memory block based on a total amount of valid data for each of the plurality of memory blocks; wherein the different storage modes carry out data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to a memory system, an operation method thereof, and a storage medium. Background Art

[0002] A memory device is a storage device used to store information in modern information technology. As a typical non-volatile semiconductor memory, a NAND (Not-And) type memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production cost, appropriate programming / erasing speed, and retention characteristics. Summary of the Invention

[0003] Based on this, embodiments of the present application propose a memory system, an operation method thereof, and a storage medium.

[0004] Embodiments of the present application propose a memory system, including: a memory device including a plurality of storage blocks, and each storage block includes a plurality of storage units; a memory controller coupled to the memory device and configured to: determine a storage mode of the storage block based on the total amount of valid data in each of the plurality of storage blocks; wherein different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

[0005] In some embodiments, the memory controller is configured to: obtain the total amount of valid data in each of the plurality of storage blocks; calculate a ratio of the total amount of valid data to the total storage space of the plurality of storage blocks to obtain a valid data ratio; and determine a storage mode of a newly to-be-activated storage block based on the valid data ratio.

[0006] In some embodiments, the storage mode includes a first mode and a second mode; wherein, in the first mode, each storage unit in the storage block stores one data bit; in the second mode, each storage unit in the storage block stores multiple data bits; the memory controller is configured to: when the valid data ratio is greater than or equal to a first threshold, dynamically configure the number of storage blocks adopting the first mode; when the valid data ratio is greater than or equal to a second threshold, stop dynamically configuring the number of storage blocks adopting the first mode; the first threshold is less than the second threshold.

[0007] In some embodiments, the memory controller is configured to: when the proportion of valid data is the first proportion, configure the number of memory blocks adopting the first mode as the first number; when the proportion of valid data is the second proportion, configure the number of memory blocks adopting the first mode as the second number; when the proportion of valid data is the third proportion, configure the number of memory blocks adopting the first mode as the third number; wherein, the first proportion is less than the second proportion, and the second proportion is less than the third proportion; the first number is greater than the second number, and the second number is greater than the third number.

[0008] In some embodiments, between the first proportion and the second proportion, and between the second proportion and the third proportion, there is a linear relationship between the proportion of valid data and the number of memory blocks adopting the first mode; the ratio between the difference between the second number and the first number and the difference between the second proportion and the first proportion is different from the ratio between the difference between the third number and the second number and the difference between the third proportion and the second proportion.

[0009] In some embodiments, the memory controller is configured to: utilize the proportion of valid data to query a target mapping table and determine the number of memory blocks adopting the first mode; the target mapping table includes the corresponding relationship between different values of the proportion of valid data and the corresponding number of memory blocks adopting the first mode.

[0010] In some embodiments, the memory controller is further configured to: before querying the target mapping table, screen out the target mapping table from multiple mapping tables; each mapping table among the multiple mapping tables includes a different corresponding relationship between the proportion of valid data and the corresponding number of memory blocks adopting the first mode.

[0011] In some embodiments, the memory controller is further configured to: in response to the need to open a new memory block for data writing; when the number of memory blocks adopting the first mode determined based on the proportion of valid data is greater than the current actual number of memory blocks adopting the first mode, configure the new memory block to adopt the first mode for data writing; when the number of memory blocks adopting the first mode determined based on the proportion of valid data is less than or equal to the current actual number of memory blocks adopting the first mode, configure the new memory block to adopt the second mode for data writing.

[0012] In some embodiments, the memory block includes multiple memory pages; the memory controller is further configured to: obtain the count of the valid data occupying the memory pages in each of the multiple memory blocks to obtain the total amount of the valid data.

[0013] In some embodiments, the valid data includes data that has not been erased by the host system and indicates data to be erased, updated, or rewritten.

[0014] An embodiment of the present application also provides an operation method for a memory system. The operation method includes: determining a storage mode of each storage block in a plurality of storage blocks in a memory device of the memory system based on the total amount of valid data in each storage block; wherein different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

[0015] In some embodiments, the method further includes: obtaining the total amount of valid data in each of the plurality of storage blocks; calculating a ratio of the total amount of valid data to the total storage space of the plurality of storage blocks to obtain a valid data ratio; and determining a storage mode of a new storage block to be enabled based on the valid data ratio.

[0016] In some embodiments, the storage mode includes a first mode and a second mode; wherein, in the first mode, each storage unit in the storage block stores one data bit; in the second mode, each storage unit in the storage block stores multiple data bits; determining the storage mode of the storage block based on the valid data ratio includes: when the valid data ratio is greater than or equal to a first threshold, dynamically configuring the number of storage blocks adopting the first mode; when the valid data ratio is greater than or equal to a second threshold, stopping dynamically configuring the number of storage blocks adopting the first mode; the first threshold is less than the second threshold.

[0017] In some embodiments, the method further includes: when the valid data ratio is a first ratio, configuring the number of storage blocks adopting the first mode to be a first number; when the valid data ratio is a second ratio, configuring the number of storage blocks adopting the first mode to be a second number; when the valid data ratio is a third ratio, configuring the number of storage blocks adopting the first mode to be a third number; wherein the first ratio is less than the second ratio, the second ratio is less than the third ratio; the first number is greater than the second number, and the second number is greater than the third number.

[0018] In some embodiments, between the first ratio and the second ratio, and between the second ratio and the third ratio, the valid data ratio and the number of storage blocks adopting the first mode both exhibit a linear relationship; the ratio of the difference between the second number and the first number to the difference between the second ratio and the first ratio is different from the ratio of the difference between the third number and the second number to the difference between the third ratio and the second ratio.

[0019] In some embodiments, the method further includes: querying a target mapping table by using the ratio of valid data, and determining the number of storage blocks adopting the first mode; the target mapping table includes the correspondence between different values of the ratio of valid data and the corresponding number of storage blocks adopting the first mode.

[0020] In some embodiments, the method further includes: before querying the target mapping table, screening out the target mapping table from multiple mapping tables; each mapping table in the multiple mapping tables has a different correspondence between different ratios of valid data and the corresponding number of storage blocks adopting the first mode.

[0021] In some embodiments, the method further includes: in response to a need to open a new storage block for data writing; when the number of storage blocks adopting the first mode determined based on the ratio of valid data is greater than the current actual number of storage blocks adopting the first mode, configuring the new storage block to adopt the first mode for data writing; when the number of storage blocks adopting the first mode determined based on the ratio of valid data is less than or equal to the current actual number of storage blocks adopting the first mode, configuring the new storage block to adopt the second mode for data writing.

[0022] In some embodiments, the storage block includes a plurality of storage pages; obtaining the total amount of valid data of each storage block among the plurality of storage blocks includes: obtaining the count of the storage pages occupied by the valid data of each storage block among the plurality of storage blocks, so as to obtain the total amount of the valid data.

[0023] In some embodiments, the valid data includes data that has not been erased by the host system and indicates data to be erased, updated, or rewritten.

[0024] An embodiment of the present application further provides a storage medium, on which executable instructions are stored, and when the executable instructions are executed, the steps of the method according to the embodiments of the present application can be implemented.

[0025] In the embodiments of the present application, the memory controller in the memory system determines the storage mode of the storage block based on the total amount of valid data of each storage block among the plurality of storage blocks of the memory device; wherein, different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block. Determining the storage mode of the storage block based on the total amount of valid data of each storage block among the plurality of storage blocks of the memory device in the embodiments of the present application can avoid misjudgment when the valid data distribution of most or each storage block is very low, so as to be applicable to a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1Schematic diagram of an exemplary system with a memory system according to an embodiment of the present application;

[0027] Figure 2a Schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present application;

[0028] Figure 2b Schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present application;

[0029] Figure 3a Schematic diagram of the distribution of memory cells of a 3D NAND-type memory according to an embodiment of the present application;

[0030] Figure 3b Schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0031] Figure 4 Schematic cross-sectional view of a memory cell array including NAND-type memory strings according to an embodiment of the present application;

[0032] Figure 5 Schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0033] Figure 6 Schematic diagram of an exemplary composition structure with a memory system provided by an embodiment of the present application;

[0034] Figure 7A Schematic diagram of an exemplary relationship between the number of storage blocks and the proportion of valid data in the first mode provided by an embodiment of the present application Figure 1 ;

[0035] Figure 7B Second schematic diagram of an exemplary relationship between the number of storage blocks and the proportion of valid data in the first mode provided by an embodiment of the present application;

[0036] Figure 7C Third schematic diagram of an exemplary relationship between the number of storage blocks and the proportion of valid data in the first mode provided by an embodiment of the present application;

[0037] Figure 8 Block diagram schematic of a readable storage medium provided by an embodiment of the present application.

[0038] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed implementation manners

[0039] Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be fully conveyed to those skilled in the art.

[0040] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, well-known features of the art are not described in order to avoid obscuring the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0041] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0042] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. And when discussing the second element, component, region, layer, or portion, it does not necessarily imply that there is a first element, component, region, layer, or portion in the present application.

[0043] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0045] In order to be able to understand the features and technical content of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of the present application.

[0046] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory. For ease of understanding, the three-dimensional NAND type memory is taken as an example for description.

[0047] Figure 1 A block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present application is shown. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1As shown, system 100 may include a host system 108 and a memory system 102, and the memory system 102 has one or more memory devices 104 and a memory controller 106. The host system 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). The host system 108 may be configured to send data to or receive data from the memory device 104.

[0048] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host system 108 and is configured to control the memory device 104. The memory controller 106 may manage the data stored in the memory device 104 and communicate with the host system 108. In some embodiments, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high-duty-cycle environment, such as a Solid State Disk (SSD) or an embedded multimedia card (eMMC), and the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0049] The memory controller 106 may be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding the data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process the error correction code (ECC) regarding the data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host system 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0050] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example as shown in Figure 2a , the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (such as the Figure 1 host system 108). In another example as shown in Figure 2b , the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (such as the Figure 1 host system 108). In some embodiments, the storage capacity and / or operating speed of the SSD 206 are greater than those of the memory card 202.

[0051] Figure 3a An exemplary structural schematic diagram of a memory cell array of a three-dimensional NAND-type memory is given, as shown in Figure 3a . The memory cell array of the three-dimensional NAND-type memory is composed of several rows of memory cell rows parallel and staggered with a gate isolation structure. Every several rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks (Blocks). Multiple second gate isolation structures can divide the memory blocks into multiple finger storage areas (Fingers). The upper select gate isolation structure provided in each finger storage area can divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a One memory block shown in

[0052] contains 6 memory slices. In practical applications, the number of memory slices in a memory block is not limited to this.

[0053] It should be noted that Figure 3a The number of rows of memory cell arrays between the gate isolation structure and the upper select gate isolation structure given in [] is only an exemplary demonstration and is not used to limit the number of rows of memory cell arrays included in one finger storage area of the three-dimensional NAND memory in this application. In actual applications, the number of rows of memory cell arrays included in one finger storage area can be adjusted according to actual situations, such as 2, 4, 8, 16, etc.

[0054] Figure 3b FIG. shows a schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit according to some aspects of the present application. The memory device 300 can be an example of the memory device 104 in [] Figure 1 The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. Taking the memory cell array 301 as a three-dimensional NAND memory cell array as an example for illustration, wherein the memory cell 306 is a NAND type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, and each memory string 308 extends vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 can hold a continuous analog value, for example, voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0055] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can thus store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that is capable of storing more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value can be used for the erased state.

[0056] As Figure 3bAs shown, each memory string 308 may include a lower select transistor 310 (also referred to as a source side select transistor, which includes a source select gate BSG) at its source extreme and an upper select transistor 312 (also referred to as a drain side select transistor, which includes a drain select gate TSG) at its drain extreme. The source select transistor BSG 310 and the drain select transistor TSG 312 may be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all the memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0057] As Figure 3b shown, the memory strings 308 may be organized into a plurality of memory blocks 304, and each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all the memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source line 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 may be coupled through word lines 318, and the word lines 318 select which row of the memory cells 306 is affected by read and program operations. In some embodiments, in combination with the foregoing Figure 3a, multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. Multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged in multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper select gate isolation structure. Among them, the memory cells in a memory slice sharing the same word line form a physical page. Each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical pages can constitute the basic data units for programming operations and read operations.

[0058] Reference Figure 3a , Figure 3b , each of the multiple memory cells, i.e., memory cell 306, is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding select transistor (such as upper select transistor (TSG) 312).

[0059] Figure 4 FIG. shows a cross-sectional schematic view of an exemplary memory cell array 301 including memory strings 308 exemplified by NAND according to some aspects of the present application. As Figure 4 shown, the NAND memory cell array 301 may include a stacked structure 410, and the stacked structure 410 includes multiple gate layers 411 and multiple insulating layers 412 that are alternately stacked in sequence, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412. Among them, the channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the multiple gate layers in the stacked structure 410 to form the memory string 308. The gate layer 411 and the insulating layer 412 may be alternately stacked, and adjacent two gate layers 411 are separated by one insulating layer 412.

[0060] The constituent material of the gate layer 411 may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 at the top of the stacked structure 410 may extend horizontally as an upper select gate line, and the gate layer 411 at the bottom of the stacked structure 410 may extend horizontally as a lower select gate line, and the gate layer 411 extending horizontally between the upper select gate line and the lower select gate line may serve as a word line layer.

[0061] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0062] In some embodiments, the memory string 308 includes a channel structure that extends vertically through the stacked structure 410. In some implementations, the channel structure includes channel holes filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0063] Return reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in Figure 5 may also be included.

[0064] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the data to be programmed (write data) to the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bits stored in the memory cells 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying the bit line voltages generated from the voltage generator 510.

[0065] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect the memory blocks 304 of the memory cell array 301 and select / deselect the word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 with the word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, channel boost voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0066] The control logic 512 can be coupled to each other part of the peripheral circuits described above, and is configured to control the operations of each other part of the peripheral circuits. The register 514 can be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. The interface 516 can be coupled to the control logic 512, and acts as a control buffer to buffer control commands received from a host system (not shown) and relay them to the control logic 512, and buffer status information received from the control logic 512 and relay it to the host system. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory cell array 301.

[0067] Considering that the read and write of storage blocks in the memory device in the SLC mode is faster and more durable, some storage blocks in the memory device with multi-bit memory cells such as MLC, TLC, QLC, or PLC are configured to be accessed in the SLC mode as a cache (which can be called SLC cache or SLC high-speed cache) for caching data. When the memory device starts to write data, it can first write to the SLC cache, and then when the space configured as the SLC cache is full or about to be full, move the data in the SLC cache to MLC, TLC, QLC, or PLC to release the SLC cache space.

[0068] Here, when performing read and write operations on the memory cells with multiple storage bits in the storage block (such as MLC, TLC, QLC, or PLC, etc.) according to their corresponding storage bits, the corresponding storage mode is called the normal storage mode; while when performing read and write operations on the memory cells with multiple storage bits (such as MLC, TLC, QLC, or PLC, etc.) according to one storage bit, the corresponding storage mode is called the high-speed storage mode, or SLC mode. It can be understood that when the memory cells adopt the high-speed storage mode, the read and write speed is relatively fast, but there is a loss in the utilization rate of the storage space; while when the memory cells adopt the normal storage mode, the utilization rate of the storage space is relatively high, but the read and write speed is relatively slow. Therefore, how to allocate the proportion of the two in the memory device to optimize the performance of the memory device has practical significance. Generally, the storage mode is determined in units of storage blocks, that is, all the memory cells in a storage block are determined to adopt a certain storage mode, such as the normal storage mode or the high-speed storage mode, etc.

[0069] Dynamic SLC Cache is an algorithm for storage mode allocation. As a key algorithm, it is an important means for storage devices to accelerate performance and is applied to more and more storage devices. Therefore, a simple and general Dynamic SLC Cache algorithm has great practical application significance.

[0070] In some embodiments, the Dynamic SLC Cache algorithm uses the number of free blocks as the input parameter of the Dynamic SLC Cache algorithm, and uses the start threshold and the stop threshold as the thresholds for starting and stopping the SLC Cache, linearly controlling the number of storage blocks used as the SLC Cache. Here, when writing user data into the memory device, generally a storage block is filled up before opening a new storage block. A free block refers to a blank storage block without written data. In contrast, a storage block with written data stores data including valid data and invalid data. Here, valid data includes data that has not been erased by the host system, has not been indicated by the host system to be erased, has not been updated by the host system, or has not been rewritten by the host system, etc.; conversely, invalid data is opposite to valid data, and invalid data includes data that has been erased by the host system, has been indicated by the host system to be erased, has been updated by the host system, or has been rewritten by the host system.

[0071] However, when the number of storage blocks with written data is large, and the proportion of valid data in most or even each storage block with written data is relatively low, although the number of free blocks is small, the actual available storage space of the memory system is still relatively large. That is to say, in this application scenario, the number of free blocks cannot accurately reflect the actual storage space of the memory device. At this time, using the number of free blocks as the input parameter of the Dynamic SLC Cache algorithm may cause misjudgment of the algorithm, that is, it is judged that the available storage space of the memory system is insufficient and it is not suitable to allocate storage blocks using the high-speed storage mode anymore. This is manifested as a problem of performance degradation not long after writing on the memory system, and the root cause is that the Dynamic SLC Cache algorithm is distorted due to misjudgment. In addition, simply using two fixed thresholds, the start threshold and the stop threshold, as the trigger conditions for starting and stopping the SLC cache is too rigid and not flexible enough.

[0072] Based on one or more of the above problems, embodiments of the present application provide a memory system, an operation method thereof, and a storage medium. Among them, the memory system 102 includes: a memory device 104, including a plurality of storage blocks, and the storage blocks include a plurality of storage units; a memory controller 106, coupled to the memory device 104 and configured to: determine the storage mode of the storage block based on the total amount of valid data in each storage block of the plurality of storage blocks; wherein, different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

[0073] In some specific embodiments, as Figure 6 shown, the memory system 102 is coupled to a host system (HOST) and executes various feedbacks in response to instructions from the host system. The memory system 102 may include: a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform operations such as reading, writing, and erasing. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner. The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, an error correction module 1064, a data buffer 1067, and a second bus 1060. Among them, the host interface 1061 is a connection interface between the host 108 and the memory controller 106. The host interface 1061 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to overall control the memory system 106. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The error correction module 1064 may further include an encoding unit 1065 and a decoding unit 1066; the encoding unit 1065 is used to encode the data to be stored to obtain check data, and the decoding unit 1066 is used to decode the check data to detect and correct possible error data during data transmission. The buffer 1067 is used to cache data.

[0074] In some embodiments, valid data refers to data that has practical significance in use. Specifically, it may include data that has not been erased by the host system, data that has not been indicated by the host system to be erased, data that has not been updated by the host system, or data that has not been rewritten by the host system, etc. The storage mode is related to the number of storage bits actually used by the storage units in a storage block. Different storage modes correspond to different actual used storage bit numbers of the storage units, and different actual used storage bit numbers of the storage units correspond to different read / write speeds. Exemplarily, when performing read / write operations on one storage bit among multiple storage bits corresponding to a storage unit with multiple storage bits (such as MLC, TLC, QLC, or PLC, etc.), the read / write speed is relatively fast; while when performing read / write operations on multiple storage bits corresponding to a storage unit with multiple storage bits (such as MLC, TLC, QLC, or PLC, etc.), the read / write speed is relatively slow.

[0075] As previously mentioned, there is invalid data relative to the valid data. Invalid data refers to data that has no practical significance in use. Specifically, it may include data that has been erased by the host system, data that has been indicated by the host system to be erased, data that has been updated by the host system, or data that has been rewritten by the host system, etc. It can be understood that for invalid data, the memory system will, when idle, reclaim the storage space occupied by the invalid data through garbage collection, internal data migration (Copyback), etc. That is to say, for the storage block where data is written, the part of the storage space occupied by the invalid data it contains can be reused. Based on this, the total amount of valid data in each of the multiple storage blocks of the memory system can more objectively reflect the actual storage situation of the memory system compared to the number of all free storage blocks among the multiple storage blocks of the memory system.

[0076] In the embodiments of the present application, the method of determining the storage mode of a storage block by using the total amount of valid data in each of the multiple storage blocks of the memory system can exclude the influence of invalid data on the actual available storage space, and is more accurate and covers a wider range of application scenarios compared to the method of determining the storage mode of a storage block by using the number of free storage blocks of the memory device.

[0077] In some embodiments, the memory controller 106 is configured to: obtain the total amount of valid data in each of the multiple storage blocks; calculate the ratio of the total amount of valid data to the total storage space of the multiple storage blocks to obtain the valid data ratio; and determine the storage mode of the new storage block to be activated based on the valid data ratio.

[0078] Considering that the total amount of valid data in each storage block of the memory system 102 is an absolute value, it is inconvenient to make a unified comparison for memory systems with different total storage spaces. Therefore, the concept of the proportion of valid data is given here. Here, the proportion of valid data refers to the ratio of the sum of the valid data in each storage block used to store user data in a memory system 102 to the total storage space of the memory system 102 used to store user data.

[0079] As previously mentioned, when writing user data into the memory device 104, generally a storage block is filled up before opening a new storage block for data storage. It should be noted that in the embodiments of the present application, the storage block for which the storage mode is to be determined is the new storage block to be opened. That is to say, the new storage block to be opened first determines the storage mode, and then stores data according to the determined storage mode.

[0080] In some embodiments, the storage block includes a plurality of storage pages; the memory controller 106 is further configured to: obtain the count of the storage pages occupied by the valid data in each storage block among the plurality of storage blocks, so as to obtain the total amount of the valid data.

[0081] Here, the storage page refers to a logical page. In some specific embodiments, the count of the storage pages occupied by the valid data in each storage block can be obtained by retrieving the record in the firmware (FW) regarding the count of the storage pages occupied by the valid data in each storage block. After that, the counts of the storage pages occupied by the valid data in each storage block among the plurality of storage blocks are summed up to obtain the total amount of the valid data.

[0082] In some embodiments, the storage mode includes a first mode and a second mode; wherein, in the first mode, the number of data bits stored in each storage unit in the storage block is one bit; in the second mode, the number of data bits stored in each storage unit in the storage block is multiple bits; the memory controller is configured to: when the proportion of valid data is greater than or equal to a first threshold, dynamically configure the number of storage blocks adopting the first mode; when the proportion of valid data is greater than or equal to a second threshold, stop dynamically configuring the number of storage blocks adopting the first mode; the first threshold is less than the second threshold.

[0083] In the embodiments of the present application, taking the total amount of the current valid data of the memory system as an input parameter can effectively track the effectively written data of the memory system. When the total amount of the valid data reaches the first threshold, start the Dynamic SLC Cache algorithm, and when the total amount of the valid data reaches the second threshold, stop the Dynamic SLC Cache algorithm.

[0084] Here, the first mode can correspond to the aforementioned high-speed storage mode, and the second mode can correspond to the aforementioned normal storage mode. The read and write speeds corresponding to the first mode are greater than those corresponding to the second mode. The first threshold can be understood as the critical value of the proportion of valid data at which the number of storage blocks adopting the first mode starts to be dynamically configured, and the second threshold can be understood as the critical value of the proportion of valid data at which the number of storage blocks adopting the first mode stops being dynamically configured. The first threshold and the second threshold can be adjusted according to actual empirical data. In some specific embodiments, the range of the first threshold is: 0% - 5%, and the range of the second threshold is: 40% - 70%. Exemplarily, the first threshold is 0% and the second threshold is 50%.

[0085] It should be noted that the first threshold is less than the second threshold. When comparing the proportion of valid data with the first threshold and the second threshold, if the proportion of valid data is less than the first threshold or greater than the second threshold, the storage mode of the new storage block to be opened can be directly determined as the second mode. If the proportion of valid data is between the first threshold and the second threshold, the configuration scheme of the number of storage blocks adopting the first mode can be further refined.

[0086] In some embodiments, the memory controller 106 is configured to: when the proportion of valid data is the first proportion, configure the number of storage blocks adopting the first mode as the first number; when the proportion of valid data is the second proportion, configure the number of storage blocks adopting the first mode as the second number; when the proportion of valid data is the third proportion, configure the number of storage blocks adopting the first mode as the third number; where the first proportion is less than the second proportion, and the second proportion is less than the third proportion; the first number is greater than the second number, and the second number is greater than the third number.

[0087] Here, the values of the first proportion, the second proportion, and the third proportion increase in sequence and are all between the first threshold and the second threshold. For different proportions of valid data, the configuration of the number of storage blocks adopting the first mode is different. As the proportion of valid data increases, the number of storage blocks adopting the first mode decreases.

[0088] It should be noted that if the relationship between the proportion of valid data between the first threshold and the second threshold and the number of storage blocks adopting the first mode is curve-fitted, a fitted line is obtained. The first point corresponding to the first proportion and the first number, the second point corresponding to the second proportion and the second number, and the third point corresponding to the third proportion and the third number are all located on this fitted line. This fitted line can be a curve, can be a multi-segment broken line, etc., and can be adjusted accordingly according to the empirical data obtained in actual different scenarios.

[0089] It should be noted that in the embodiments of the present disclosure, considering the flexibility of the memory system, different fitting lines can be used to fit the actual situation of the memory system. The following will be combined with Figures 7A to 7C to give several examples.

[0090] In some specific embodiments, between the first ratio and the second ratio, and between the second ratio and the third ratio, the ratio of valid data and the number of storage blocks adopting the first mode are both linearly related; the ratio of the difference between the second quantity and the first quantity to the difference between the second ratio and the first ratio is different from the ratio of the difference between the third quantity and the second quantity to the difference between the third ratio and the second ratio.

[0091] Exemplarily, as Figure 7A shown, Figure 7A where the ordinate represents the number of storage blocks adopting the first mode, the abscissa represents the ratio of valid data (POVD), and the fitting line of the number of storage blocks adopting the first mode and the ratio of valid data POVD is two-segment broken line. At this time, the first threshold coincides with the first ratio, the second threshold coincides with the third ratio, and the number of storage blocks adopting the first mode and POVD are linearly related between the first point corresponding to the first ratio and the first quantity and the second point corresponding to the second ratio and the second quantity. Specifically, when POVD is 0, 90 storage blocks are used as slc cache; when POVD is 30%, 70 storage blocks are used as SLC cache; when POVD is 50%, 0 storage blocks are used as SLC cache.

[0092] Exemplarily, as Figure 7B shown, Figure 7B where the ordinate represents the number of storage blocks adopting the first mode, the abscissa represents the ratio of valid data POVD, and the fitting line of the number of storage blocks adopting the first mode and the ratio of valid data POVD is four-segment broken line. At this time, the first ratio, the second ratio and the third ratio are located between the first threshold and the second threshold. Specifically, when POVD is 0, 90 storage blocks are used as SLC cache; when POVD is 20%, 85 storage blocks are used as SLC cache; when POVD is 35%, 70 storage blocks are used as SLC cache; when POVD is 45%, 42 storage blocks are used as SLC cache; when POVD is 50%, 0 storage blocks are used as SLC cache.

[0093] It should be noted that Figure 7A 、 Figure 7BThe first threshold, the first ratio, the second ratio, the third ratio, and the second threshold shown are only examples and are not used to limit the specific values of the first threshold, the first ratio, the second ratio, the third ratio, and the second threshold in the embodiments of the present application. The specific values of the first threshold, the first ratio, the second ratio, the third ratio, and the second threshold in the embodiments of the application can be adjusted according to the actual situation.

[0094] It should be noted that in some other embodiments, the fitting line of the number of storage blocks adopting the first mode and the proportion of valid data (POVD) may further include more segments of broken lines.

[0095] In some specific implementations, for the fitting line with multiple segments of broken lines: First, define a one-dimensional array threshold[N], where N represents the number of required segments of broken lines plus 1, and then initialize each threshold value as needed. Each time when a new storage block (open New block) is to be opened, according to the current POVD of the memory system, interpolate and calculate the number of SLC cache blocks allowed by the current memory system. If it is found that the number of existing slc blocks in the memory system is greater than the calculated number of slc cache blocks, the system cannot open an slc block as a data block at this time, otherwise open an slc block as a data block.

[0096] Exemplarily, as Figure 7C shown, Figure 7C in the vertical axis represents the number of storage blocks adopting the first mode, the horizontal axis represents the proportion of valid data POVD, and the fitting line of the number of storage blocks adopting the first mode and the proportion of valid data POVD is a curve.

[0097] It should be noted that Figure 7A 、 Figure 7B 、 7C the fitting line of the number of storage blocks adopting the first mode and the proportion of valid data (POVD) shown is only an example and is not used to limit the mapping relationship between the number of storage blocks adopting the first mode and the proportion of valid data (POVD) in the embodiments of the present application.

[0098] Given that when the fitting line of the number of storage blocks adopting the first mode and the proportion of valid data (POVD) is a curve or contains a large number of segments of broken lines, directly calculating the number of storage blocks adopting the first mode according to the current POVD of the memory system may be time-consuming, and the method of querying the mapping table can be used to obtain the number of storage blocks adopting the first mode.

[0099] In some embodiments, the memory controller 106 is configured to: query a target mapping table by using the effective data ratio, and determine the number of memory blocks adopting the first mode; the target mapping table includes the correspondence between different values of the effective data ratio and the corresponding number of memory blocks adopting the first mode.

[0100] Here, according to actual test data, it is necessary to obtain in advance a target mapping table including the correspondence between different values of the effective data ratio and the corresponding number of memory blocks adopting the first mode, and store the target mapping table in the memory device 104 or firmware.

[0101] In some embodiments, the memory controller 106 is further configured to: screen out the target mapping table from a plurality of mapping tables before querying the target mapping table; each mapping table in the plurality of mapping tables includes a different correspondence between the effective data ratio and the corresponding number of memory blocks adopting the first mode.

[0102] Here, considering that in different application scenarios, the correspondence between different values of the effective data ratio and the corresponding number of memory blocks adopting the first mode may be different, when obtaining a mapping table including the correspondence between different values of the effective data ratio and the corresponding number of memory blocks adopting the first mode, the corresponding mapping table for each scenario can be obtained according to different application scenarios, and then the target mapping table to be used can be determined at the moment when the memory system is powered on or other moments before querying the target mapping table.

[0103] It can be understood that the method of storing in advance the corresponding mapping table for each scenario and then selecting the corresponding mapping table according to actual needs can be applied to more scenarios, and the dynamic adjustment is more flexible and effective.

[0104] In some embodiments, the memory controller 106 is further configured to: in response to the need to open a new memory block for data writing; when the number of memory blocks adopting the first mode determined based on the effective data ratio is greater than the current actual number of memory blocks adopting the first mode, configure the new memory block to adopt the first mode for data writing; when the number of memory blocks adopting the first mode determined based on the effective data ratio is less than or equal to the current actual number of memory blocks adopting the first mode, configure the new memory block to adopt the second mode for data writing.

[0105] Here, before a new storage block needs to be enabled, first determine the number of storage blocks adopting the first mode according to the proportion of valid data POVD in the current memory system; then count the number of storage blocks actually adopting the first mode in the current memory system, and compare the number of storage blocks actually adopting the first mode in the current memory system with the number of storage blocks adopting the first mode determined by the proportion of valid data. If the number of storage blocks actually adopting the first mode is less than the number of storage blocks adopting the first mode determined based on the proportion of valid data, it indicates that the storage blocks actually used as SLC cache in the memory system have not reached the upper limit allowed by the memory system. At this time, the storage mode of the new storage block can be determined as the first mode, that is, the new storage block is used as SLC cache; if the number of storage blocks actually adopting the first mode is greater than or equal to the number of storage blocks adopting the first mode determined based on the proportion of valid data, it indicates that the storage blocks actually used as SLC cache in the memory system have reached the upper limit allowed by the memory system. At this time, the storage mode of the new storage block can be determined as the second mode, that is, the new storage block is used as the normal storage mode.

[0106] In some embodiments, the memory system includes a Universal Flash Storage (UFS) or a Solid State Disk (SSD). The memory device includes a NAND-type memory.

[0107] In the embodiments of the present application, the memory controller in the memory system determines the storage mode of the storage block based on the total amount of valid data in each storage block of the plurality of storage blocks of the memory device; wherein, different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block. Determining the storage mode of the storage block based on the total amount of valid data in each storage block of the plurality of storage blocks of the memory device in the embodiments of the present application can avoid misjudgment when the valid data distribution of most or each storage block is very low, so as to be applicable to a wider range of application scenarios.

[0108] The embodiments of the present application also propose an operation method for a memory system, and the operation method includes: determining the storage mode of the storage block based on the total amount of valid data in each storage block of the plurality of storage blocks of the memory device in the memory system; wherein, different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

[0109] In some embodiments, the method further includes: obtaining the total amount of valid data in each of the multiple storage blocks; calculating a ratio of the total amount of valid data to the total storage space of the multiple storage blocks to obtain a valid data ratio; and determining a storage mode of a new storage block to be activated based on the valid data ratio.

[0110] In some embodiments, the storage mode includes a first mode and a second mode; wherein, in the first mode, each storage unit in the storage block stores one data bit; in the second mode, each storage unit in the storage block stores multiple data bits; determining the storage mode of the storage block based on the valid data ratio includes: when the valid data ratio is greater than or equal to a first threshold, dynamically configuring the number of storage blocks adopting the first mode; when the valid data ratio is greater than or equal to a second threshold, stopping dynamically configuring the number of storage blocks adopting the first mode; the first threshold is less than the second threshold.

[0111] In some embodiments, the method further includes: when the valid data ratio is a first ratio, configuring the number of storage blocks adopting the first mode to be a first number; when the valid data ratio is a second ratio, configuring the number of storage blocks adopting the first mode to be a second number; when the valid data ratio is a third ratio, configuring the number of storage blocks adopting the first mode to be a third number; wherein, the first ratio is less than the second ratio, the second ratio is less than the third ratio; the first number is greater than the second number, and the second number is greater than the third number.

[0112] In some embodiments, between the first ratio and the second ratio, and between the second ratio and the third ratio, the valid data ratio and the number of storage blocks adopting the first mode are both linearly related; a ratio of a difference between the second number and the first number to a difference between the second ratio and the first ratio is different from a ratio of a difference between the third number and the second number to a difference between the third ratio and the second ratio.

[0113] In some embodiments, the method further includes: querying a target mapping table using the valid data ratio to determine the number of storage blocks adopting the first mode; the target mapping table includes a correspondence between different values of the valid data ratio and the corresponding number of storage blocks adopting the first mode.

[0114] In some embodiments, the method further includes: before querying the target mapping table, screening out the target mapping table from multiple mapping tables; each mapping table in the multiple mapping tables includes a different correspondence between the valid data ratio and the corresponding number of storage blocks adopting the first mode.

[0115] In some embodiments, the method further includes: in response to a need to open a new storage block for data writing; when the number of storage blocks adopting the first mode determined based on the valid data ratio is greater than or equal to the current actual number of storage blocks adopting the first mode, configuring the new storage block to adopt the second mode for data writing; when the number of storage blocks adopting the first mode determined based on the valid data ratio is less than the current actual number of storage blocks adopting the first mode, configuring the new storage block to adopt the first mode for data writing.

[0116] In some embodiments, the storage block includes a plurality of storage pages; the obtaining the total amount of valid data in each of the plurality of storage blocks includes: obtaining the count of the storage pages occupied by the valid data in each of the plurality of storage blocks to obtain the total amount of the valid data.

[0117] In some embodiments, the valid data includes data that has not been erased by the host system and indicates data to be erased, updated, or rewritten.

[0118] It should be noted that the operation method of the memory system in the above embodiments can be specifically understood with reference to the specific implementation scheme of the storage mode determination described in the memory system in the foregoing embodiments.

[0119] An embodiment of the present application further provides a storage medium, on which executable instructions are stored, and when the executable instructions are executed, the steps of the method described in the embodiments of the present application can be implemented.

[0120] In some specific embodiments, the storage medium may be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it may also be various devices including one or any combination of the above memory devices.

[0121] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as a stand-alone program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0122] As an example, the executable instructions may or may not correspond to a file in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, stored in a single file dedicated to the program being discussed, or, stored in multiple cooperating files (e.g., files that store one or more modules, subroutines, or portions of code).

[0123] As an example, the executable instructions may be deployed to execute on one electronic device, or on multiple electronic devices located at one location, or, on multiple electronic devices distributed at multiple locations and interconnected by a communication network.

[0124] Figure 8 The block diagram shows a schematic of a readable storage medium provided by an embodiment of the present application. An embodiment of the present application provides a readable storage medium. The storage medium 800 stores executable instructions 801. When the executable instructions 801 are executed by a processor, the operation method of the memory system in the above technical solution can be implemented. The operation method includes: determining the storage mode of the storage block based on the total amount of valid data in each of the multiple storage blocks; wherein, different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

[0125] The methods disclosed in the method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments. It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of the phrase "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present application, the order numbers of the above processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0126] In the method embodiments disclosed in several method embodiments provided in this application, they can be arbitrarily combined without conflict to obtain new method embodiments.

[0127] As mentioned above, it is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art in the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A memory system, characterized in that: include: A memory device comprising a plurality of memory blocks, wherein the memory blocks include a plurality of memory cells; a memory controller coupled to the memory device and configured to: Based on the total amount of valid data in each storage block in the multiple storage blocks, a storage mode of the storage block is determined; wherein different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

2. The memory system according to claim 1, wherein: The memory controller is configured to: Acquire the total amount of valid data of each storage block in the plurality of storage blocks; Calculating the ratio of the total amount of the valid data to the total storage space of the plurality of storage blocks to obtain a valid data ratio; Based on the effective data ratio, a storage mode of a new storage block to be enabled is determined.

3. The memory system according to claim 2, wherein: The storage mode includes a first mode and a second mode; wherein, in the first mode, each storage unit in the storage block stores one data bit; and in the second mode, each storage unit in the storage block stores multiple data bits; The memory controller is configured to: When the valid data ratio is greater than or equal to a first threshold, dynamically configuring the number of storage blocks using the first mode; When the valid data ratio is greater than or equal to a second threshold, the dynamic configuration of the number of storage blocks using the first mode is stopped; and the first threshold is less than the second threshold.

4. The memory system according to claim 3, characterized in that: The memory controller is configured to: When the valid data ratio is the first ratio, the number of storage blocks using the first mode is configured to be the first number; When the valid data ratio is the second ratio, the number of storage blocks using the first mode is configured to be the second number; When the valid data ratio is a third ratio, the number of storage blocks using the first mode is configured to be a third number; Among them, the first proportion is smaller than the second proportion, and the second proportion is smaller than the third proportion; the first number is larger than the second number, and the second number is larger than the third number.

5. The memory system according to claim 4, characterized in that: Between the first proportion and the second proportion, and between the second proportion and the third proportion, the effective data proportion and the number of storage blocks using the first mode are both in a linear relationship; The ratio of the difference between the second quantity and the first quantity to the difference between the second proportion and the first proportion is different from the ratio of the difference between the third quantity and the second quantity to the difference between the third proportion and the second proportion.

6. The memory system according to claim 3, characterized in that: The memory controller is configured to: The effective data ratio is used to query a target mapping table to determine the number of storage blocks using the first mode; the target mapping table includes a correspondence between different effective data ratio values ​​and the corresponding number of storage blocks using the first mode.

7. The memory system according to claim 6, characterized in that: The memory controller is further configured to: Before querying the target mapping table, the target mapping table is screened out from a plurality of mapping tables; each of the plurality of mapping tables contains a different correspondence between a different effective data ratio and a corresponding number of storage blocks using the first mode.

8. The memory system according to claim 3, characterized in that: The memory controller is further configured to: In response to a need to open a new storage block for data writing; When the number of storage blocks using the first mode determined based on the valid data ratio is greater than the number of storage blocks currently actually using the first mode, configuring the new storage block to use the first mode for data writing; When the number of storage blocks using the first mode determined based on the valid data ratio is less than or equal to the number of storage blocks currently actually using the first mode, the new storage block is configured to use the second mode for data writing.

9. The memory system according to claim 2, wherein: The storage block includes a plurality of storage pages; The memory controller is further configured to: A count of the number of storage pages occupied by valid data of each storage block in the plurality of storage blocks is obtained to obtain a total amount of the valid data.

10. The memory system according to claim 1, wherein: The valid data includes data that has not been erased by the host system and is indicated to be erased, updated, or rewritten.

11. A method for operating a memory system, characterized in that: The operation method comprises: Based on the total amount of valid data in each of the multiple storage blocks in the memory device of the memory system, the storage mode of the storage block is determined; wherein different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

12. The operating method according to claim 11, characterized in that: The method further comprises: Acquire the total amount of valid data of each storage block in the plurality of storage blocks; Calculating the ratio of the total amount of the valid data to the total storage space of the plurality of storage blocks to obtain a valid data ratio; Based on the effective data ratio, a storage mode of a new storage block to be enabled is determined.

13. The operating method according to claim 12, characterized in that: The storage mode includes a first mode and a second mode; wherein, in the first mode, each storage unit in the storage block stores one data bit; and in the second mode, each storage unit in the storage block stores multiple data bits; The determining the storage mode of the storage block based on the effective data proportion includes: When the valid data ratio is greater than or equal to a first threshold, dynamically configuring the number of storage blocks using the first mode; When the valid data ratio is greater than or equal to a second threshold, the dynamic configuration of the number of storage blocks using the first mode is stopped; and the first threshold is less than the second threshold.

14. The operating method according to claim 13, characterized in that: The method further comprises: When the valid data ratio is the first ratio, the number of storage blocks using the first mode is configured to be the first number; When the valid data ratio is the second ratio, the number of storage blocks using the first mode is configured to be the second number; When the valid data ratio is a third ratio, the number of storage blocks using the first mode is configured to be a third number; Among them, the first proportion is smaller than the second proportion, and the second proportion is smaller than the third proportion; the first number is larger than the second number, and the second number is larger than the third number.

15. The operating method according to claim 14, characterized in that: Between the first proportion and the second proportion, and between the second proportion and the third proportion, the effective data proportion and the number of storage blocks using the first mode are both in a linear relationship; The ratio of the difference between the second quantity and the first quantity to the difference between the second proportion and the first proportion is different from the ratio of the difference between the third quantity and the second quantity to the difference between the third proportion and the second proportion.

16. The operating method according to claim 13, characterized in that: The method further comprises: The effective data ratio is used to query a target mapping table to determine the number of storage blocks using the first mode; the target mapping table includes a correspondence between different effective data ratio values ​​and the corresponding number of storage blocks using the first mode.

17. The operating method according to claim 16, characterized in that: The method further comprises: Before querying the target mapping table, the target mapping table is screened out from a plurality of mapping tables; each of the plurality of mapping tables contains a different correspondence between a different effective data ratio and a corresponding number of storage blocks using the first mode.

18. The operating method according to claim 13, characterized in that: The method further comprises: In response to a need to open a new storage block for data writing; When the number of storage blocks using the first mode determined based on the valid data ratio is greater than the number of storage blocks currently actually using the first mode, configuring the new storage block to use the first mode for data writing; When the number of storage blocks using the first mode determined based on the valid data ratio is less than or equal to the number of storage blocks currently actually using the first mode, the new storage block is configured to use the second mode for data writing.

19. The operating method according to claim 12, characterized in that: The storage block includes a plurality of storage pages; The obtaining the total amount of valid data of each storage block in the plurality of storage blocks comprises: A count of the number of storage pages occupied by valid data of each storage block in the plurality of storage blocks is obtained to obtain a total amount of the valid data.

20. The operating method according to claim 11, characterized in that: The valid data includes data that has not been erased by the host system and is indicated to be erased, updated, or rewritten.

21. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed, the steps of the method described in any one of claims 11 to 20 can be implemented.

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