Semiconductor processing apparatus and semiconductor processing method thereof

Abstract

The invention discloses a semiconductor processing system and a semiconductor processing method thereof. A semiconductor processing apparatus includes a first chamber portion and a second chamber portion. And the first chamber part and / or the second chamber part are / is provided with a groove channel. The groove channel can form a closed channel by means of blocking of the surface of the wafer; and the target fluid is driven to enter the closed channel, and the fluid entering the closed channel can advance along the closed channel and flow out of the closed channel. Within a period of time, multiple sections of target fluid are arranged in the closed channel, and every two adjacent sections of target fluid are isolated through interval fluid. Therefore, under the condition that the volume of the target fluid is not increased and the scanning time is almost not increased, the effective contact time of the target fluid at each point of the wafer can be increased, and the extraction efficiency of pollutants on the surface of the wafer is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor processing apparatus and a semiconductor processing method thereof.

Background Art

[0002] With the further reduction of semiconductor size, the impurities contained in the wafer silicon material itself have become requirements that need to be detected and monitored in quality control. However, the current wafer contamination detection technology is limited to the extraction and detection of impurities on the wafer surface or the destructive detection of the entire wafer material.

[0003] Chinese Patent Application No. 201510836143.0 discloses a method for detecting wafer contamination using a closed channel in a microchamber. As Figure 8 shown, the closed channel 813 communicates with the outside through the first through hole 811 and the second through hole 812. A certain volume of extraction solution 820 is driven through the first through hole 811 into the closed channel 813. The extraction solution entering the closed channel 813 is pushed by nitrogen gas and guided forward along the closed channel (i.e., spirally forward in the direction R1), and the extraction solution 820 flowing through the surface of the wafer flows out through the second through hole 812 and is extracted. That is, the surface of the wafer is scanned with a certain volume of extraction solution 820, so that the contaminated impurities on the surface of the wafer can be extracted and detected by using a certain volume of extraction solution 820. However Figure 8 in the traditional extraction method shown, only one section of extraction solution 820 can be uploaded each time of scanning. The volume of the extraction solution is generally 1 ml, and the nitrogen gas pushing speed is generally 20 ml / min. It can be calculated that the contact time of each point on the wafer with the extraction solution is 1 ml / (20 ml / min) = 0.05 min = 3 s. The contact time of each point on the wafer has a great influence on the poorly soluble contamination. Generally speaking, the longer the contact time, the less the contamination remaining on the wafer and the higher the extraction efficiency. In order to improve the extraction efficiency, a feasible method is to increase the volume of the extraction solution or reduce the nitrogen gas pushing speed. However, increasing the solution volume will increase the detection limit of the equipment, and reducing the nitrogen gas pushing rate will increase the scanning time and affect the production capacity.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application.

Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor processing system and a semiconductor processing method thereof, which can increase the effective contact time of the target fluid at each point of the wafer and improve the extraction efficiency of contaminants on the wafer surface without increasing the volume of the target fluid and with almost no increase in the scanning time.

[0006] To achieve the above object, the present invention provides a semiconductor processing apparatus, which includes: a first chamber portion, and a second chamber portion that can move relative to the first chamber portion between an open position and a closed position. When the second chamber portion is located at the closed position relative to the first chamber portion, a microchamber is formed between the first chamber portion and the second chamber portion, and a wafer can be accommodated in the microchamber. When the second chamber portion is located at the open position relative to the first chamber portion, the wafer can be taken out or put in. The first chamber portion and / or the second chamber portion has a groove formed by being recessed from the inner wall surface of the corresponding chamber portion, a first through hole passing through the corresponding chamber portion from the outside to communicate with a first position of the groove, and a second through hole passing through the corresponding chamber portion from the outside to communicate with a second position of the groove. When the second chamber portion is located at the closed position relative to the first chamber portion and the wafer is accommodated between the first chamber portion and the second chamber portion, at this time, the groove forms a closed channel by the blockage of the surface of the wafer, and the closed channel communicates with the outside through the first through hole and the second through hole; driving the target fluid to enter the closed channel through the first through hole, and the target fluid entering the closed channel can move forward along the closed channel. At this time, the target fluid can contact a partial area of the surface of the wafer, and the target fluid flowing through the surface of the wafer flows out through the second through hole and is extracted. During a period of time, there are multiple segments of target fluid in the closed channel, and adjacent two segments of target fluid are isolated by spacer fluid.

[0007] According to another aspect of the present invention, the present invention provides a semiconductor processing method based on the above-mentioned semiconductor processing apparatus, which includes: dividing the target fluid into multiple segments, and isolating adjacent two segments of target fluid by spacer fluid; making the multiple segments of target fluid isolated by spacer fluid enter a closed channel through the first through hole, so that during a period of time, there are multiple segments of target fluid in the closed channel, and adjacent two segments of target fluid are isolated by spacer fluid; driving the multiple segments of target fluid isolated by spacer fluid in the closed channel to flow out of the closed channel through the second through hole by driving fluid; and merging the multiple segments of target fluid flowing out of the closed channel for detection

[0008] Compared with the prior art, the present invention divides the target fluid into multiple segments and uses spacer fluid to isolate adjacent segments of the target fluid, thereby obtaining multiple segments of target fluid isolated by the spacer fluid, and driving the multiple segments of target fluid isolated by the spacer fluid into the closed channel. In this way, without increasing the volume of the target fluid and with almost no increase in the scanning time, the effective contact time of the target fluid at each point of the wafer can be increased, and the extraction efficiency of contaminants on the wafer surface can be improved.

[0009] Therefore, it should be understood that providing this general overview is only for the purpose of summarizing some embodiments in order to provide a basic understanding of some aspects of the present invention. Therefore, the above embodiments are merely examples and should not be construed as narrowing the scope or concept of the present invention in any way. By reading the following detailed description and the accompanying drawings, the features, appearances, and advantages of each embodiment will be obvious, and the accompanying drawings show the principles of some embodiments by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] With reference to the accompanying drawings and the following detailed description, the present invention will be more easily understood, where the same reference numerals correspond to the same structural components, and:

[0011] Figure 1a is a cross-sectional schematic view of the semiconductor processing device in the present invention in one embodiment;

[0012] Figure 1b is Figure 1a an enlarged schematic view of circle A in

[0013] Figure 1c is Figure 1a an enlarged schematic view of circle B in

[0014] Figure 2a is a top view of the second chamber part in the present invention in one embodiment;

[0015] Figure 2b is Figure 2a an enlarged schematic view of circle C in

[0016] Figure 2c is Figure 2a an enlarged schematic view of circle D in

[0017] Figure 2d is a cross-sectional schematic view along the section line A-A in Figure 2a ;

[0018] Figure 2e is Figure 2d an enlarged schematic view of circle E in

[0019] Figure 2f is Figure 2a an enlarged schematic view of circle F in

[0020] Figure 3a Top view of the first chamber part in one embodiment of the present invention;

[0021] Figure 3b is Figure 3a An enlarged schematic view of the circle G in;

[0022] Figure 3c is Figure 3a An enlarged schematic view of the circle H in;

[0023] Figure 3d is along Figure 3a A cross-sectional schematic view along the section line B-B in;

[0024] Figure 3e is Figure 3d An enlarged schematic view of the circle I in;

[0025] Figure 3f is Figure 3a An enlarged schematic view of the circle J in;

[0026] Figure 4a Cross-sectional schematic view of the semiconductor processing apparatus in another embodiment of the present invention;

[0027] Figure 4b Figure 4a An enlarged schematic view of the circle K in;

[0028] Figure 5a Top view of the first chamber part in one embodiment of the present invention;

[0029] Figure 5b is along Figure 5a A cross-sectional schematic view along the section line C-C in;

[0030] Figure 5c is Figure 5a An enlarged schematic view of the circle L in;

[0031] Figure 6a Top view of the second chamber part in another embodiment of the present invention;

[0032] Figure 6b is along Figure 6a An enlarged schematic view of the circle M in;

[0033] Figure 7 Flow schematic diagram of the semiconductor processing method in one embodiment of the present invention.

[0034] Figure 8 Structural schematic diagram for detecting wafer contamination using a closed channel in a microchamber in the prior art;

[0035] Figure 9 The structural schematic diagram of the semiconductor processing apparatus in the present invention for detecting wafer contamination using a closed channel;

[0036] Figure 10 The flowchart of the semiconductor processing method of the present invention in an embodiment.

Specific Embodiment

[0037] Some embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments are listed. In fact, the various embodiments of the present invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. For example, unless otherwise stated, referring to something as first, second, etc. should not be construed as implying a particular order. Additionally, something may be described as above something (unless otherwise stated) while actually being below it, and vice versa; similarly, something described as on the left may be on the right, and vice versa. The same reference numeral always represents the same element.

[0038] Combined with the description of the specific embodiments of the present invention and the accompanying drawings, the details of the present invention can be more clearly understood. However, the specific embodiments of the present invention described herein are for the purpose of explaining the present invention only and should not be construed in any way as a limitation of the present invention. Under the teachings of the present invention, those skilled in the art can conceive of any possible variations based on the present invention, and these should all be regarded as falling within the scope of the present invention. It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there can also be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element at the same time. The terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal communication of two elements. It can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances. The terms "vertical", "horizontal", "upper", "lower", "left", "right", and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0040] The first part

[0041] In order to better extract and detect the contaminated impurities in the wafer, a semiconductor processing device is also proposed in this application.

[0042] Figure 1a It is a schematic cross-sectional view of the semiconductor processing device 100 in an embodiment of the present invention. Figure 1b It is Figure 1a an enlarged schematic view of the circle A in Figure 1c It is Figure 1a an enlarged schematic view of the circle B in Figure 1a As shown, the semiconductor processing device 100 includes a first chamber portion 110 and a second chamber portion 120. In this embodiment, the first chamber portion 110 is the upper chamber portion, and the second chamber portion 120 is the lower chamber portion. In other embodiments, the lower chamber portion may also be defined as the first chamber portion, and the upper chamber portion may be defined as the second chamber portion.

[0043] The first chamber portion 110 includes an upper chamber plate 111 and a first flange 112 extending downward from the periphery of the upper chamber plate. The second chamber portion 120 includes a lower chamber plate 121 and a first groove 122 recessed downward from the periphery of the lower chamber plate 121.

[0044] The first chamber portion 110 can move relative to the second chamber portion 120 between an open position and a closed position. When the first chamber portion 110 is in the open position relative to the second chamber portion 120, the wafer can be placed on the inner wall surface of the second chamber portion 120, or the wafer can be taken out from the inner wall surface of the second chamber portion 120. When the first chamber portion 110 is in the closed position relative to the second chamber portion 120, when the first chamber portion 110 is in the closed position relative to the second chamber portion 120, the first flange 112 cooperates with the first groove 122 to form a sealed microchamber between the upper chamber plate and the lower chamber plate, and the wafer can be accommodated in the microchamber and wait to be processed subsequently.

[0045] Figure 2a It is a top view of the second chamber portion 120 in an embodiment of the present invention. Figure 2b It is Figure 2a an enlarged schematic view of the circle C in Figure 2c It is Figure 2a an enlarged schematic view of the circle D in Figure 2d It is a schematic cross-sectional view along the section line A-A in Figure 2a Figure 2e It is Figure 2d an enlarged schematic view of the circle E in Figure 2f It is Figure 2a ​Enlarged schematic view of the circle F in

[0046] Combined with Figure 2a - 2f As shown, the second chamber portion 120 has a groove 124 formed by recessing from the inner wall surface 123 of the second chamber portion 120 facing the microchamber, a first through hole 125 passing through the second chamber portion from the outside and communicating with a first position of the groove 124, and a second through hole 126 passing through the second chamber portion from the outside and communicating with a second position of the groove 124. The cross-section of the groove 124 can be U-shaped, V-shaped or semi-circular, and can also be other shapes. The number of through holes in the groove 124 can be greater than or equal to 1.

[0047] As Figure 1a 、 1b and 1c show that when the first chamber portion 110 is in the closed position relative to the second chamber portion 120 and the wafer 200 is accommodated in the microchamber, one surface (lower surface) of the wafer 200 abuts against the inner wall surface 123 forming the groove 124. At this time, the groove 124 forms a closed channel by the blockage of the surface of the wafer 200, and this closed channel communicates with the outside through the first through hole 125 and the second through hole 126. In application, the processing fluid can enter the closed channel through the first through hole 125, and the fluid entering the closed channel can travel along the closed channel. At this time, the processing fluid can contact and process a partial area of the surface of the wafer 200, and the fluid that has processed the surface of the wafer 200 can flow out through the second through hole 126 and be extracted. In this way, not only can the flow direction and flow velocity of the processing fluid be precisely controlled, but also the usage amount of the processing fluid can be greatly saved.

[0048] In one embodiment, as Figure 2a 、 2b and 2c show that the groove 124 is formed in a spiral shape, where the first through hole 125 is located in the central area of the spiral groove (the area of circle D), and the second through hole 126 is located in the peripheral area of the spiral groove 124 (the area of circle C). The first through hole 125 can be used as an inlet, and the second through hole 126 can be used as an outlet. In other embodiments, it is also possible that the second through hole is located in the central area of the spiral groove, and the second through hole is located in the peripheral area of the spiral groove.

[0049] In one embodiment, as Figure 2d 、 2eAs shown in FIGS. 2f, the first through hole 125 includes a first buffer opening 125a that communicates directly with the groove channel 124 and is deeper and wider than the groove channel 124, and a first through hole portion 125b that communicates directly with the first buffer opening 125a. Since the first buffer opening 125a is provided, it is possible to avoid the central region of the wafer being over-processed due to the excessive initial velocity of the processing fluid entering through the first through hole 125. The second through hole 126 includes a second buffer opening 126a that communicates directly with the groove channel 124 and is deeper and wider than the groove channel 124, and a second through hole portion 126b that communicates directly with the second buffer opening 126a. Since the second buffer opening 126a is provided, it is possible to prevent the processing fluid from overflowing due to the inability to be discharged from the second through hole 126 in time. Preferably, the first buffer opening 125a may be a tapered groove, and the second buffer opening 126a may be a cylindrical groove.

[0050] Figure 3a FIG. 4 is a top view of the first chamber portion 110 in one embodiment of the present invention; Figure 3b is Figure 3a an enlarged schematic view of the circle G in Figure 3c is Figure 3a an enlarged schematic view of the circle H in Figure 3d is a cross-sectional schematic view along the section line B-B in Figure 3a ; Figure 3e is Figure 3d an enlarged schematic view of the circle I in Figure 3f is Figure 3a an enlarged schematic view of the circle J in

[0051] Combined with Figure 3a to 3f shown, the first chamber portion 110 includes an upper chamber plate 111 and a first flange 112 extending downward from the periphery of the upper chamber plate 111. The first chamber portion 110 has a groove channel 113 recessed from the inner wall surface 113 of the first chamber portion facing the microchamber, and the groove wall (the portion between adjacent groove channels 114) of the groove channel 114 formed on the inner wall surface 113 of the first chamber portion corresponds to the groove wall (the portion between adjacent groove channels 124) of the groove channel 124 formed on the inner wall surface 123 of the second chamber portion ( Figure 1b , Figure 1c) In this way, when the first chamber part 110 is in the closed position relative to the second chamber part 120 and the wafer 200 is accommodated in the microchamber, the groove wall of the groove channel 114 of the first chamber part 110 can press against the corresponding position of the wafer 200, and make the wafer 200 more tightly abut against the groove wall of the groove channel 124 of the second chamber part 120, so that the sealing performance of the finally formed closed channel is better. In addition, the groove walls (the parts between adjacent groove channels 114) of the groove channels 114 formed on the inner wall surface 113 of the first chamber part and the groove walls (the parts between adjacent groove channels 124) of the groove channels 124 formed on the inner wall surface 123 of the second chamber part 120 can also be arranged in an interleaved manner.

[0052] In another modified embodiment, the structures of the first chamber part 110 and the second chamber part can be interchanged or have the same structure. At this time, the upper surface of the wafer 200 will form a closed channel together with the groove channels of the first chamber part 110. Processing fluid flowing in the closed channel can process the upper surface or the lower surface of the wafer 200, or process both the upper and lower surfaces simultaneously.

[0053] Figure 4a It is a schematic cross-sectional view of the semiconductor processing device in the present invention in another embodiment 200; Figure 4b Figure 4a The enlarged schematic view of the circle K in. As the semiconductor processing device 400 in 4a is compared with the Figure 1a The difference of the semiconductor processing device in is that: Figure 4a The first chamber part 410 in and Figure 1a The structure of the first chamber part 110 in is different. Figure 5a It is a top view of the first chamber part 410 in an embodiment of the present invention; Figure 5b It is along Figure 5a The schematic cross-sectional view of the section line C-C in; Figure 5c It is Figure 5a The enlarged schematic view of the circle L in. As Figure 5a to 5c shown, the first chamber part 410 includes an upper chamber plate 411, a first flange 412, a first inner wall surface 413 facing the microchamber, a second groove 414, a second flange 415 located between the first inner wall surface 413 and the second groove 414, and a channel 416 located at the center of the first inner wall surface 413. A closed space is formed by the second flange 415 abutting against the wafer 200 and the first inner wall surface 413, and is communicated with the outside through the channel 416. Fluid can enter this closed space through the channel 416 to generate pressure, and make the wafer 200 more tightly abut against the groove wall of the groove channel 124 of the second chamber part 120, so that the sealing performance of the finally formed closed channel is better.

[0054] Figure 6a Top view of the second chamber portion in another embodiment 620 of the present invention; Figure 6b Along the Figure 6a Enlarged schematic view of the circle M in. A plurality of groove channels 624 are formed by recessing from the inner wall surface 623 of the second chamber portion 620 facing the microchamber, Figure 6a There are 5 in, and in other embodiments, there may be other numbers. Each groove channel 624 corresponds to a first through hole 625 and a second through hole 626. Different groove channels 624 of the second chamber portion 620 are located in different regions of the inner wall surface 623. In this way, different treatments can be performed on different regions, and they are independent of each other.

[0055] The present invention also proposes a semiconductor processing method using the above semiconductor processing apparatus. As Figure 7 Shown, the semiconductor processing method 700 includes the following steps.

[0056] Step 710, place the second chamber portion 120 in an open position relative to the first chamber portion 110;

[0057] Step 720, place the wafer between the second chamber portion 120 and the second chamber portion 110;

[0058] Step 730, place the second chamber portion 120 in a closed position relative to the first chamber portion 110;

[0059] Step 740, inject fluid into the groove channel 124 through the first through hole 125;

[0060] Step 750, drive the fluid to travel along the closed channel until the second through hole 126;

[0061] Step 760, extract the fluid from the second through hole 126.

[0062] In one embodiment, element detection can be performed based on the extracted fluid, so that the elements remaining on the surface of the wafer and their concentrations can be obtained.

[0063] In one embodiment, the fluid is a liquid, and the fluid is an extraction fluid. The extraction fluid can extract the contamination impurities on the surface of the wafer in contact.

[0064] The fluid can be driven to travel in the closed channel by a driving fluid. The driving fluid is an inert ultra-pure gas, such as nitrogen, helium, argon, ultrapure water, acetone, carbon tetrachloride, etc.

[0065] In another embodiment, the first through hole 125 can also be used as a fluid outlet, and the second through hole 126 as a fluid inlet.

[0066] The second part

[0067] As Figure 8 shown, it is a conventional method for extracting wafer surface contamination. Figure 8 The closed channel 813, the first through hole 811, and the second through hole 812 in [] can refer to the closed channel, the first through hole, and the second through hole in the semiconductor processing device described above. As mentioned in the background, in the prior art, only one segment of the extraction solution 820 can be uploaded each time of scanning, and this method has low extraction efficiency.

[0068] Therefore, the present invention provides a semiconductor processing device and a semiconductor processing method capable of solving the above problems.

[0069] Figure 9 It is a schematic structural diagram of the semiconductor processing device in the present invention for detecting wafer contamination by using a closed channel. As Figure 9 shown, the semiconductor processing device includes a first chamber part and a second chamber part. The first chamber part and / or the second chamber part has a groove formed by being recessed from the inner wall surface of the corresponding chamber part, a first through hole 911 passing through the corresponding chamber part from the outside to communicate with a first position of the groove, and a second through hole 913 passing through the corresponding chamber part from the outside to communicate with a second position of the groove. When the second chamber part is in the closed position relative to the first chamber part and the wafer is accommodated between the first chamber part and the second chamber part, at this time, the groove forms a closed channel 913 by the blockage of the surface of the wafer, and the closed channel 913 communicates with the outside through the first through hole 911 and the second through hole 912. The semiconductor processing device in the present invention can refer to the semiconductor processing device mentioned above in terms of structure, and will not be repeated here.

[0070] Figure 10 It is a schematic flow diagram of the semiconductor processing method based on the semiconductor processing device in an embodiment of the present invention. Combining Figure 9 and Figure 10 shown, the semiconductor processing method includes the following steps.

[0071] Step 950, divide the target fluid into multiple segments, and use spacer fluids to isolate adjacent segments of the target fluid.

[0072] In one embodiment, the spacer fluid is a gas and the target fluid is a liquid. For example, the spacer fluid is nitrogen. The target fluid can be an extraction solution, and the extraction solution can be used to extract contaminants on the surface of the wafer. The target fluid can also be referred to as the target extraction solution or the extraction solution. For example, the extraction solution can react with contaminants (such as metal impurities or metal contaminants) and dissolve them in the extraction solution.

[0073] Step 960: The multi-segment target fluid separated by the spacer fluid 930 enters a closed channel 913 through the first through-hole 911, so that within a period of time, there is multi-segment target fluid 920 (920-1, 920-2, 920-3 respectively) in the closed channel, and adjacent segments of the target fluid are separated by the spacer fluid.

[0074] As Figure 9 shown, there are three segments of target fluid, and there is spacer fluid 930 between every two adjacent segments of the target fluid. In other embodiments, there may also be 2, 4 or more segments of target fluid. It should be specifically noted that the three segments of target fluid 920 are in the same closed channel, rather than in multiple closed channels respectively.

[0075] Step 970: The multi-segment target fluid separated by the spacer fluid in the closed channel is driven by the driving fluid to flow out of the closed channel through the second through-hole.

[0076] In one embodiment, the driving fluid is a gas. For example, the gas can also be nitrogen. The driving fluid and the spacer fluid can be the same gas.

[0077] Step 980: The multi-segment target fluid flowing out of the closed channel is merged and detected.

[0078] In one embodiment, the driving speed of the driving fluid is less than 40 ml / min, for example, it can be 20 ml / min, or 25 ml / min, etc. The total volume of the target fluid in the multi-segment target fluid is less than 3 ml (milliliters), for example, it can be 1 ml, 2 ml, etc.

[0079] Flowing multiple segments of target fluid once through the closed channel can be referred to as performing a scan using the multiple segments of target fluid in the closed channel. In one embodiment, the total volume of the target solution used for pollutant extraction using multiple segments of target fluid can be the same as that used for pollutant extraction using a single segment of target fluid in the prior art, so it will not affect the detection limit of the device. When the first-stage extraction solution 920-1 flows through the insoluble pollutants on the surface of the wafer, a trace amount of extraction liquid remains on the insoluble pollutants on the surface of the wafer and continues to react with the insoluble pollutants (i.e., dissolve the pollutants) until the second-stage extraction solution flow 920-2 passes through the insoluble pollutants. That is to say, during the period between the first-stage extraction solution 920-1 and the second-stage extraction solution flow 920-2, the remaining trace amount of extraction solution will still react with the insoluble pollutants in a dissolving manner, which is equivalent to greatly extending the contact time between the pollutants at the same point and the extraction solution. Therefore, the effective contact time of the extraction solution at each point on the wafer (here referring to each point on the wafer facing the closed channel) is the duration of the multiple-stage extraction solution flowing through this point (such as 3 s) plus the total interval time of the interval fluid flowing through this point between the multiple-stage extraction solutions. The pushing speed of the driving gas (such as nitrogen) can remain unchanged, such as 20 ml / min, and the effective contact time of the extraction solution at each point on the wafer is greatly increased. It can be seen that through the multi-stage scanning method, by only increasing a small amount of the time interval between the multiple-stage extraction solutions for introducing the interval fluid, the effective contact time of the extraction solution at each point on the wafer can be significantly increased, and the pollution extraction efficiency during a single scan is improved.

[0080] The present invention can be achieved without changing the existing mechanical and electrical design, only by modifying the existing formula. The present invention can significantly increase the effective contact time of the extraction solution at each point on the surface of the wafer and improve the extraction efficiency of insoluble metal pollution without increasing the volume of the extraction solution and only by increasing a small amount of the total scanning time.

[0081] The above description is intended to be illustrative, not restrictive. Although the present invention has been described with reference to specific illustrative examples, it should be understood that the present invention is not limited to the described embodiments. The scope of the present invention should be determined with reference to the claims and the entire scope of the equivalents authorized by the claims.

[0082] As used herein, "an example (embodiment)" or "example (embodiment)" means that a particular feature, structure, or characteristic related to the embodiment can be included in at least one implementation of the present invention. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it have to be a separate or alternative embodiment that is mutually exclusive with other embodiments. The terms "a plurality" and "several" in the present invention mean two or more. The term "and / or" in the present invention means "and" or "or". In addition, the terms "first", "second", "third", "fourth", etc. used herein are intended as labels for distinguishing different elements, and may not necessarily have an order meaning according to their numerical designations. Therefore, the terms used herein are only for the purpose of describing a specific implementation and are not intended to be limiting.

[0083] It should also be noted that in some alternative embodiments, the indicated functions / actions may not occur in the order indicated in the figures. For example, depending on the functions / actions involved, two consecutively shown figures may actually be executed substantially simultaneously or sometimes in the reverse order.

[0084] Although method operations are described in a specific order, it should be understood that other operations may be performed between the described operations. The described operation process can be adjusted so that they occur at slightly different times, or the described operations can be distributed across the system. The system allows for the simultaneous processing of multiple unrelated programs.

[0085] Many modifications and other embodiments of the present invention will occur to those of ordinary skill in the art, who have relevant industry knowledge and some of the original data. Therefore, it should be understood that the present invention is not limited to the specific embodiments disclosed, but also includes other embodiments modified within the scope of the appended claims. In addition, although the foregoing description and the related drawings describe the implementation of specific combinations of elements and functions, within the scope of the appended claims, different combinations of elements and functions through alternative implementations are also included. The appended claims also include combinations of elements and functions different from those specifically described above. Although specific terms are used herein, they are only intended to be generally descriptive and not for limiting purposes.

Claims

1. A semiconductor processing device, characterized in that: It includes: a first chamber portion, a second chamber portion movable relative to the first chamber portion between an open position and a closed position, wherein when the second chamber portion is located at the closed position relative to the first chamber portion, a micro chamber is formed between the first chamber portion and the second chamber portion, and a wafer can be accommodated in the micro chamber; when the second chamber portion is located at the open position relative to the first chamber portion, the wafer can be taken out or put in; the first chamber portion and / or the second chamber portion has a groove channel formed by a depression on the inner wall surface of the corresponding chamber portion, a first through hole passing through the corresponding chamber portion from the outside to communicate with the first position of the groove channel, and a second through hole passing through the corresponding chamber portion from the outside to communicate with the second position of the groove channel; when the second chamber portion is located at the closed position relative to the first chamber portion and the wafer is accommodated between the first chamber portion and the second chamber portion, the groove channel forms a closed channel by means of the obstruction of the surface of the wafer, and the closed channel communicates with the outside through the first through hole and the second through hole; The target fluid is driven to enter the closed channel through the first through hole. The target fluid entering the closed channel can move along the closed channel. At this time, the target fluid can contact a partial area of ​​the surface of the wafer. The target fluid flowing through the surface of the wafer flows out through the second through hole and is extracted. Wherein, within a period of time, there are multiple sections of target fluid in the closed channel, and two adjacent sections of target fluid are isolated by a spacer fluid.

2. The semiconductor processing device according to claim 1, wherein: The spacer fluid is gas, the target fluid is liquid, each segment of the target fluid is driven by a driving fluid, the driving fluid is gas, and within a period of time, the multiple segments of the target fluid are in the same closed channel.

3. The semiconductor processing device according to claim 2, characterized in that The target fluid in each section of the target fluid is the same, and the target fluid is used to extract contaminants on the surface of the wafer.

4. The semiconductor processing device according to claim 2, wherein: The driving fluid is nitrogen gas, and the spacer fluid is nitrogen gas.

5. The semiconductor processing device according to claim 2, wherein: The driving speed of the driving fluid is less than 40 ml / min, and the total volume of the target fluid in the multiple sections of the target fluid is less than 3 ml.

6. The semiconductor processing device according to claim 1, wherein: Each groove track is spirally formed, wherein one of the first through hole and the second through hole is located in a central area of ​​the spiral groove track, and the other of the first through hole and the second through hole is located in a peripheral area of ​​the spiral groove track.

7. A semiconductor processing method based on the semiconductor processing device according to any one of claims 1 to 6, characterized in that: It includes: Dividing the target fluid into multiple sections, and isolating two adjacent sections of the target fluid using a spacer fluid; Allowing multiple sections of target fluid separated by a spacer fluid to enter a closed channel through a first through hole, so that within a period of time, the closed channel has multiple sections of target fluid, and two adjacent sections of target fluid are separated by the spacer fluid; Using a driving fluid to drive multiple sections of target fluid separated by a spacing fluid in the closed channel to flow out of the closed channel through the second through hole; and The multiple sections of target fluid flowing out of the closed channel are combined for detection.

8. The semiconductor processing method according to claim 7, characterized in that: The spacer fluid is a gas, the target fluid is a liquid, and the driving fluid is a gas. During a period of time, the multiple sections of target fluid are in the same closed channel, and the target fluid is used to extract pollutants on the surface of the wafer.

9. The semiconductor processing method according to claim 8, characterized in that: The driving fluid is nitrogen gas, and the spacer fluid is nitrogen gas.

10. The semiconductor processing method according to claim 8, characterized in that: The driving speed of the driving fluid is less than 40 ml / min, and the total volume of the target fluid in the multiple sections of the target fluid is less than 3 ml.

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