Command configuration method, unit, display processor and electronic device

Abstract

This application provides a command configuration method, unit, display processor, and electronic device, relating to the field of data transmission. The command configuration unit includes: a read data channel comprising a buffer and a selector, the buffer being configured with multiple buffer areas; multiple command interfaces, each command interface being configured to correspond to a different buffer area; each command interface being used to connect to an image processing module; the selector being configured to receive the read data and store the read data into a corresponding buffer area according to identification information; each command interface being configured to retrieve the read data from the corresponding buffer area and configure the image processing module based on the configuration commands in the read data. The command configuration unit can improve the utilization of bus bandwidth, thereby improving the efficiency of command configuration for each module of the display processor.

Description

Technical Field

[0001] This application relates to the field of data transmission, and more specifically, to a command configuration method, unit, display processor, and electronic device. Background Technology

[0002] The DPU (Display Processor Unit) configures the parameters of each image processing module within the DPU according to the control commands sent by the CPU (Central Processing Unit), thereby processing the image data and sending it to the display device.

[0003] Currently, the DPU can use DMA (Direct Memory Access) to transmit control commands. The DPU reads control commands from DRAM (Dynamic Random Access Memory) through DMA technology and sends them back to the DPU. After parsing the control commands, the DPU obtains the configuration parameters. Each image processing module of the DPU is configured according to the configuration parameters, thereby enabling the DPU to perform the corresponding functions.

[0004] The DMA technology can read control commands from DRAM with a bus bandwidth of 128 bits or 256 bits, while the DPU's interface bus width for receiving control commands is only 32 bits. This means that the DMA technology can only use 32 bits of bus bandwidth to transmit control commands to the DPU, and the bus bandwidth cannot be fully utilized.

[0005] As the requirements for dynamic range, frame rate, and resolution of images increase, the number of image processing modules required by the DPU also increases, thus increasing the CPU's burden in configuring the DPU. Furthermore, the DPU shares a command configuration system with other modules or circuits in the device, all based on DMA reading commands from DRAM. If the DPU cannot fully utilize its own transmission bandwidth or bus bandwidth, it will also affect the overall performance of the device in which the DPU resides. Summary of the Invention

[0006] In view of this, this application aims to provide a command configuration method, unit, display processor, and electronic device to improve the bandwidth utilization of the display processor and improve the efficiency of command configuration of each module of the display processor.

[0007] In a first aspect, embodiments of this application provide a command configuration method, comprising: a read data channel including a buffer and a selector, the buffer being connected to the selector, the buffer being configured with multiple buffer areas; the selector being connected to a memory for outputting read data, the read data including configuration commands and identification information, the configuration commands including parameters for configuring each image processing module in a display processor, the identification information representing the buffer area corresponding to the read data; multiple command interfaces, each command interface being connected to the buffer and configured to correspond to a different buffer area; each command interface being connected to the image processing module; wherein, the selector is configured to receive the read data and store the read data into a corresponding buffer area according to the identification information; each command interface is configured to obtain the read data from the corresponding buffer area and configure the image processing module based on the configuration commands in the read data.

[0008] In this embodiment, the command interface can obtain configuration commands from the read data and configure the image processing module. Therefore, when transmitting read data and read requests, it is not necessary to transmit read data according to the interface bandwidth of the image processing module; transmission can be based on the bandwidth of the transmission bus. Since the bandwidth of the transmission bus is greater than the interface width of the image processing module, the utilization rate of the transmission bandwidth can be improved, thereby increasing the configuration efficiency of the display processor. Furthermore, through the aforementioned command configuration unit, multiple configuration command requests or parsing can be performed in parallel, further improving the configuration efficiency of the display processor.

[0009] In one embodiment, the command configuration unit further includes: a read request channel, the read request channel including a plurality of read request generators, each of the read request generators corresponding to a different command interface; each of the read request generators is used to send a read request to the memory; the memory is configured to send the read data to the buffer in response to the read request.

[0010] In this embodiment, multiple read request generators are configured in the read request channel, and different read request generators correspond to different command interfaces. Thus, each read request channel can generate read requests corresponding to different command interfaces. The generation and issuance of multiple read requests are carried out in parallel. Compared with the method of generating and issuing read requests one by one, the generation efficiency of read requests can be effectively improved, thereby improving the efficiency of obtaining configuration commands for each image processing module, and further improving the configuration efficiency of the image processing module.

[0011] In one embodiment, the read request channel further includes a read request arbitrator; the read request arbitrator is connected to each of the read request generators and is used to connect to the memory; the read request arbitrator is configured to control the output order of each read request based on a preset output priority rule.

[0012] Some image processing modules have high real-time requirements, while the memory needs to receive read requests one by one. Therefore, in this embodiment, a read request arbitrator is set in the read request channel so that the read requests corresponding to the command interfaces with higher priority can be output to the memory to read the read data, so as to meet the real-time requirements of each image processing module for obtaining configuration commands.

[0013] In one embodiment, the read data channel further includes: an address buffer connected to the buffer and each of the command interfaces, wherein the address buffer is configured to store the write address of the read data in the buffer area and the read address of the read data read from the buffer area; the command interface is configured to read the read data from the buffer area according to the write address; and the selector is configured to store the read data into the corresponding buffer area according to the read address and the identification information.

[0014] In this embodiment, an address buffer is used to record the read address and the write address. This enables the command interface to accurately retrieve read data from the buffer, thereby improving the accuracy of configuring the image processing module.

[0015] In one embodiment, the read data channel further includes a base address memory group, which includes multiple base address memories. The address buffer is connected to each of the command interfaces through each of the base address memories. The base address memory is used to provide the write address to the command interface connected to the base address memory after the read data is stored in the buffer area.

[0016] In this embodiment, the write address is recorded based on the base address memory group, so that the command interface only needs to receive the write address stored in the corresponding base address memory, without the need to configure additional judgment logic, thus improving the configuration efficiency of the command interface. In one embodiment, the read data channel further includes a buffered read arbitrator; the buffered read arbitrator is connected to the buffer and each of the command interfaces respectively; the buffered read arbitrator is configured to instruct each of the command interfaces to obtain the read data from the buffer.

[0017] In this embodiment of the application, at any given time, only one command interface is typically allowed to read from the buffer. A buffer read arbitrator is set up to instruct each command interface to sequentially obtain read data from the buffer, thereby reducing the possibility of data loss and read errors and improving the accuracy of display processor configuration.

[0018] In one embodiment, each of the command interfaces includes a command buffer 121 and a command parser. The command buffer 121 is connected to the buffer, and the command parser is also connected to the command buffer. The command parser is used to connect to the image processing module. The command buffer 121 is used to store the read data obtained from the buffer. The command parser is used to output the read data to the image processing module in a preset format to configure the image processing module.

[0019] In this embodiment, the command buffer 121 can temporarily store data output to the display processor module, enabling the command parser to read data from the command buffer 121 according to a preset format and output it. Through the command buffer 121 and the command parser, the command interface can perform data conversion, converting configuration commands into data that the image processing module can use. Therefore, the bandwidth of the read data before it is transmitted to the image processing module can be greater than the bandwidth of the image processing module, so as to make full use of the bandwidth of the transmission bus and improve the configuration efficiency of the image processing module.

[0020] In one embodiment, the command parser includes a first parser or a second parser; the configuration command includes a coefficient command for configuring an image processing module with a three-dimensional lookup table; the second parser is configured to output the read data to the image processing module according to the output bandwidth of the second parser; the output bandwidth of the second parser in each command interface is matched with the bandwidth of each image processing module with the three-dimensional lookup table in the display processor.

[0021] In this embodiment, an image processing module including a 3D LUT (3D Look Up Table) is included. The received coefficient commands configure the 3D look up table. However, different coefficient commands have different bandwidths. If the coefficient commands are transmitted with the same bandwidth, the transmission bandwidth may not be fully utilized. Therefore, a second parser is configured in the command interface, and the output bandwidth of each second parser is matched with the bandwidth of each image processing module in the display processor that has a 3D look up table. Thus, for image processing modules with different bandwidths, there is a corresponding second parser to parse them, so that the output coefficient commands can be matched with each image processing module. The configuration of system commands is completed in one go, without the need for multiple configurations or the introduction of invalid data, thus making full use of the bandwidth.

[0022] In one embodiment, the buffer regions corresponding to each command interface share the storage space of the buffer, and the storage space of each buffer region is allocated according to the amount of read data corresponding to each command interface in the buffer.

[0023] In this embodiment, the size of the storage space corresponding to the cache area is dynamically allocated according to the amount of data read. Under different read data transmission conditions, sufficient storage space can be allocated for read data, thereby meeting the read data transmission needs in different scenarios and expanding the applicability of the command configuration unit.

[0024] This application embodiment also provides a command configuration method applied to a command configuration unit, the command configuration unit comprising: a read data channel, the read data channel including a buffer and a selector, the buffer being connected to the selector, the buffer being configured with multiple buffer areas; the selector being used to connect to a memory for outputting read data, the read data including configuration commands and identification information, the configuration commands including parameters for configuring a display processor, the identification information representing the buffer area corresponding to the read data; multiple command interfaces, each command interface being connected to the buffer and configured to correspond to a different buffer area; each command interface being used to connect to the display processor; the command configuration method comprising: receiving the read data through the selector; storing the read data into a corresponding buffer area through the selector according to the identification information of the received read data; obtaining the read data from the buffer area corresponding to the command interface through the command interface; and configuring the display processor based on the configuration commands in the read data through the command interface.

[0025] Thirdly, embodiments of this application provide a display processor, including: a command configuration unit as described in any of the first aspects; and a plurality of image processing modules, each connected to the command configuration unit.

[0026] Fourthly, embodiments of this application provide an electronic device, including: a display processor as described in the third aspect; a controller and a memory, the memory being connected to the controller and the display processor respectively; the controller being configured to generate the read data and store the read data in the memory; the memory being used to output the read data to the display processor in response to a read request from the display processor.

[0027] In one embodiment, the memory is configured with multiple storage areas, each storage area corresponding to a different command interface; each storage area is configured to store read data corresponding to each command interface.

[0028] Fifthly, embodiments of this application provide an image display system, comprising: an electronic device as described in any of the fourth aspects; and a display device communicatively connected to the electronic device for displaying image data output by the display processor. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of a command configuration unit provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of the buffer storage space provided in an embodiment of this application;

[0032] Figure 3 An extended schematic diagram of a command configuration unit provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the buffered read arbitrator provided in one embodiment of this application.

[0034] Figure 5 This is a schematic diagram of the operation of a read request channel provided in an embodiment of this application;

[0035] Figure 6 This is a schematic diagram of read data reception and parsing provided in an embodiment of this application;

[0036] Figure 7 A flowchart illustrating a command configuration method provided in an embodiment of this application;

[0037] Figure 8 A schematic diagram of a display processor provided in an embodiment of this application;

[0038] Figure 9 A schematic diagram of an electronic device provided according to an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of an image display system provided in an embodiment of this application.

[0040] Icons: Command configuration unit 100; Read data channel 110; Selector 111; Buffer 112; Address buffer 113; Base address memory group 114; Buffered read arbitrator 115; Command interface 120; Command buffer 121; First parser 122; Second parser 123; Read request channel 130; Read request generator 131; Read request arbitrator 132; Display processor 200; Image processing module 210; Electronic device 300; Controller 310; Memory 320; Display system 400; Display device 410. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0042] Please see Figure 1 , Figure 1 This is a schematic diagram of a command configuration unit 100 provided in an embodiment of this application. The command configuration unit 100 includes a read data channel 110 and a plurality of command interfaces 120.

[0043] The read data channel 110 includes a buffer 112 and a selector 111. The buffer 112 is connected to the selector 111 and is configured with multiple buffer areas. The selector 111 is used to connect to the memory that outputs read data.

[0044] The buffer 112 can be various types of memory, such as SRAM (Static Random-Access Memory), DRAM (Dynamic Random Access Memory), PSRAM (Pseudo Static Random-Access Memory), etc.

[0045] After generating configuration commands, the DPU stores them in memory for later retrieval. The image processor (DPU) comprises multiple image processing modules, and the configuration commands are used to configure different image processing modules.

[0046] Please see Figure 2 , Figure 2 This is a schematic diagram of the buffer storage space provided in one embodiment of this application. In this implementation, since the command interface 120 includes multiple interfaces, the storage space of the buffer 112 can be divided into multiple buffer regions, each corresponding to one command interface 120, thereby storing the read data corresponding to each command interface 120 in each buffer region. The size of the buffer region can be set according to requirements; for example, the size of a buffer region can be 256 bytes, 512 bytes, etc.

[0047] In some embodiments, each command interface's corresponding buffer area shares the space of the buffer, and the storage space corresponding to each buffer area is dynamically allocated according to the number of read data corresponding to each command interface in the buffer. For example, there are 10 command interfaces, corresponding to 10 buffer areas, and the 10 buffer areas share the storage space of one buffer. One buffer can store 10 read data. If the storage space is evenly distributed, the 10 buffer areas are allocated space to store 1 read data. In this embodiment, however, the storage space of each buffer area can be allocated according to the number of read data in the input buffer and the command interface corresponding to each read data. The maximum storage space allocated to a buffer area can be equal to the storage space of the buffer, and the minimum can be 0. For example, when 9 read data are from command interface 1 and 1 read data is from command interface 2, the buffer area corresponding to command interface 1 can be allocated storage space to store 9 read data, the buffer area corresponding to command interface 2 can be allocated storage space to store 1 read data, and other buffer areas are not allocated storage space, i.e., 0. The above are merely examples and should not be construed as limiting this application.

[0048] In this embodiment, the read data includes configuration commands and identification information. The configuration commands include parameters for configuring each image processing module in the display processor; specific details can be found in existing technologies and will not be elaborated here. The identification information represents the buffer area corresponding to the read data and can be information that can represent the buffer area, such as an address or number. Furthermore, since the buffer area corresponds to the command interface, the identification information can also represent the command interface.

[0049] Meanwhile, in order to ensure that each read data can be stored in the corresponding buffer area, a selector 111 can be set between the buffer 112 and the memory outside the command configuration unit 100. The selector 111 can store the corresponding buffer area according to the identification information.

[0050] Multiple command interfaces 120 are provided, each of which is connected to the buffer 112 and is configured to correspond to a different buffer region; each of the command interfaces 120 is used to connect to the image processing module.

[0051] In the embodiments of this application, selector 111 is configured to receive read data and store the read data into the corresponding buffer area according to the identification information; each command interface 120 is configured to obtain read data from the corresponding buffer area and configure the image processing module based on the configuration command in the read data. Thus, before the configuration command is output to each image processing module of the display processor, the memory and buffer 112 can transmit read data according to the bandwidth of the transmission bus (e.g., 128 bits, 256 bits, etc.) and store it in the delay buffer 112. Each command interface 120 is connected to the image processing module to convert the read data into data that conforms to the bandwidth of the image processing module (e.g., 32 bits). Through the parallel operation of multiple command interfaces 120, the transmitted read data can be processed in a timely manner. The buffer 112 enables better utilization of the transmission bus bandwidth for read data transmission, and the command interface 120 enables the transmitted read data to be used. The parallel operation of multiple command interfaces 120 can improve the configuration efficiency of multiple image processing modules. Thus, the command configuration unit 100 can improve bandwidth utilization and the configuration efficiency of image processing modules.

[0052] In some embodiments, the command configuration unit 100 is configured with a control unit (not shown in the figure). The control unit may be a single control circuit or a combination of multiple control circuits. The control unit is configured with various control logics to control the coordinated operation of the various parts in the command configuration unit 100. In some embodiments, the control unit may be a controller for a display processor.

[0053] Please see Figure 3 , Figure 3 This is an extended schematic diagram of a command configuration unit 100 provided in an embodiment of this application.

[0054] In one embodiment, the command configuration unit 100 may further include: a read request channel 130, which includes a plurality of read request generators 131, each of which corresponds to a different command interface 120; each read request generator 131 is used to send a read request to the memory; the memory is configured to send read data to the buffer 112 in response to the read request.

[0055] The display processor obtains configuration commands by sending read requests to external memory. However, in this embodiment, there are multiple command interfaces 120. If the display processor still generates read requests one by one, the efficiency of generating read requests is low, and the utilization rate of the transmission bus bandwidth remains low. Therefore, in this embodiment, multiple read request generators 131 can be set for different command interfaces 120 to generate multiple read requests in parallel, and then send read requests to memory to obtain read data. This reduces the waiting time when generating read requests, improves the efficiency of reading request generation, and thus improves the configuration efficiency of the image processing module.

[0056] In the aforementioned embodiments, the number of read request generator 131, command interface 120, and buffer area can be the same as the number of image processing modules in the display processor.

[0057] In one embodiment, the read request channel 130 may further include a read request arbitrator 132; the read request arbitrator 132 is connected to each read request generator 131 and is used to connect to the memory; the read request arbitrator 132 is configured to control the output order of each read request based on a preset output priority rule.

[0058] Display processors typically read memory one request at a time, meaning read requests are usually issued sequentially. For example, when using an AXI (Advanced eXtensible Interface, a bus protocol) bus as the transmission bus, the AXI interface only allows one read request to be issued at a time. However, some image processing modules in the display processor have high real-time requirements. If multiple read requests are generated simultaneously, and these requests are configured to wait for output, the subsequently acquired read data may not meet the needs of those image processing modules.

[0059] Therefore, for this type of image processing module, a read request arbitrator 132 can be configured, connecting the output of each read request generator 131 to the read request arbitrator 132. Read requests are then arbitrated by the read request arbitrator 132 before being output to the memory. Output priority rules are configured in the read request arbitrator 132 to control the output order of each read request based on these rules.

[0060] Priority rules can be configured according to the needs of the image processing module in the display processor. The read request arbitrator 132 can be an arbitration circuit that implements polling arbitration, weighted polling arbitration, etc. The arbitration circuit can refer to the existing technology and will not be described here.

[0061] In one embodiment, the read data channel 110 further includes an address buffer 113. The address buffer 113 is connected to the buffer 112 and each command interface 120, and the address buffer 113 is configured to store the write address of read data in the buffer area and the read address of read data read from the buffer area.

[0062] In this embodiment, read data is stored in the buffer area of ​​buffer 112. However, the same buffer area may store multiple read data, so it is necessary to distinguish the read data in the buffer area to differentiate between read data that can be read and read data that can be overwritten. Therefore, an address buffer can be set up, which is connected to buffer 112 and each command interface 120 respectively. The address buffer records the write address of read data in the buffer area and the read address after the read data is read, so that the command interface 120 can determine whether there is still unread read data in buffer 112 by using the write address and read address. If there is unread read data, it can retrieve the read data from buffer 112.

[0063] Accordingly, after the selector 111 determines the corresponding buffer area through the identification information, it can obtain the read address corresponding to the buffer area and determine the storage space that can be overwritten in the buffer area.

[0064] In the above embodiments, the address buffer 113 can be implemented using existing buffers, which will not be elaborated here.

[0065] In some embodiments, the read data channel 110 may further include a base address memory group 114, which includes multiple base address memories, and the address buffer 113 is connected to each command interface 120 through each base address memory.

[0066] Command interface 120 may not have the function of determining read address and write address. In this embodiment, a base address memory can be set up to obtain the write address that can be read from the corresponding buffer of address cache 113 through the base address memory and provide it to the corresponding command interface 120.

[0067] The base address memory can be an existing memory with storage function. For example, the base address memory can be a FIFO (First Input First Output) memory, a register, etc.

[0068] In one embodiment, the read data channel 110 may further include a buffered read arbitrator 115. The buffered read arbitrator 115 is connected to the buffer 112 and each command interface 120, respectively. The buffered read arbitrator 115 is configured to instruct each command interface 120 to obtain read data from the buffer 112.

[0069] The principle of the simultaneous read request arbitrator 132 is similar. When the command interface 120 reads the buffer 112, only one command interface 120 is usually allowed to read the buffer 112 at the same time. Accordingly, in this embodiment, if multiple command interfaces 120 need to read the buffer 112 at the same time, the buffer read arbitrator 115 can instruct each command interface 120 to read in sequence to reduce the possibility of data loss and read errors.

[0070] Next, the command interface 120 currently allowed to receive read data can be configured to prioritize acquiring read data, and the read request arbitrator 132 will preferentially instruct the command interface with the higher priority to acquire read data. For example, see [link to relevant documentation]. Figure 4 When the buffer read arbitration determines the command interface for obtaining read data, it will feed back the command interface and the write address of the read data to the buffer, so that the command interface can obtain read data from the buffer area of ​​the buffer according to the write address.

[0071] In the embodiments of this application, the format of the read data is adapted to the bandwidth of the transmission bus, which may not be directly connected by the image processing module. The command interface 120 needs to convert it into a data format that the image processing module can use, and the conversion process takes time. At this time, the command interface 120 may not be able to receive or allow receiving read data. Accordingly, in this embodiment, the command interface 120 that is allowed to receive read data can be given priority in obtaining read data.

[0072] In some embodiments, the preset read priority rules can also be configured according to the real-time requirements of the read data by the image processing module corresponding to each command interface 120, or in other ways. The buffer read arbitrator 115 can refer to the existing arbitration circuit, which will not be elaborated here.

[0073] In one embodiment, each command interface 120 may include a command buffer 121 and a command parser. The command buffer 121 is connected to the buffer 112, and the command parser is connected to the image processing module.

[0074] Since the bandwidth of the transmission bus may not match the interface bandwidth of the display processor, the command interface 120 needs to convert the bandwidth of the read data so that the configuration commands in the read data can be used to configure the image processing module in the display processor.

[0075] In this embodiment, the command buffer 121 is used to store the read data obtained from the buffer 112. The command parser is used to output the read data to the image processing module according to a preset format for configuring the image processing module. The preset format can be the data size, for example, 4 bytes, 32 bytes, etc., and the data size corresponding to the preset format is the same as the interface bandwidth of the image processing module.

[0076] The command buffer 121 allows for temporary storage of read data. This serves two purposes: firstly, it allows for the storage of multiple read data entries, reducing the storage pressure on the buffer 112; secondly, the size of data corresponding to the preset format is typically smaller than the size of a single read data entry, making it impossible for the command parser to convert the read data all at once. Temporarily storing the read data in the command buffer 121 reduces the possibility of data loss. Therefore, through the command buffer 121 and the command parser, read data can be transmitted without adhering to the display processor's interface bandwidth before being output to the display processor. Since the transmission bandwidth is typically greater than the display processor's interface bandwidth, this improves the utilization rate of the transmission bandwidth during read data transmission.

[0077] In one embodiment, the command parser includes a first parser 122 or a second parser 123.

[0078] In the display processor, configuration commands include ordinary commands and coefficient commands. A first parser 122 converts ordinary commands into a preset format, and a second parser 123 converts coefficient commands. The image processing modules configured based on ordinary commands typically have the same interface bandwidth. Therefore, the output bandwidth of each first parser 122 is the same and equal to the bandwidth of the display processor module.

[0079] The coefficient command is used to configure the image processing module, which includes 3D LUTs, in the display processor. The interface width of such display processor modules may be different. For example, some display processor modules have a width of 36 bits, while others have a width of 48 bits. If the output bandwidth of the command parser is uniform and is 32 bits, the command parser needs to send the same configuration command twice, which may make it impossible to make full use of the bandwidth in the second transmission.

[0080] The second parser 123 is configured to output read data to the image processing module according to the output bandwidth of the second parser 123; the output bandwidth of the second parser 123 in each command interface 120 is matched with the bandwidth of each image processing module in the display processor that has a three-dimensional lookup table.

[0081] In embodiments of this application, for different image processing modules including 3D LUTs, the command interface 120 in its corresponding command interface 120 can be configured as a second parser 123, and the output bandwidth of the second parser 123 can be configured to match the bandwidth of the image processing module. Therefore, for such image processing modules including 3D LUTs, it is unnecessary to transmit a configuration command multiple times, effectively utilizing the interface bandwidth and improving the efficiency of cooperation with the image processing module.

[0082] The command configuration unit 100 can convert the bit width of the read data into the bit width that the image processing module's interface can receive. When transmitting read data and read requests, transmission can be based on the bandwidth of the transmission bus, which is greater than the bit width of the image processing module's interface. This improves the utilization of transmission bandwidth and thus enhances the configuration efficiency of the display processor. Furthermore, the command configuration unit 100 allows multiple configuration command requests or parsing to be performed concurrently, further improving the display processor's configuration efficiency.

[0083] For ease of understanding, an example is provided here; this example should not be construed as limiting this application. Please refer to [link / reference]. Figure 5 and Figure 6 , Figure 5 This is a schematic diagram illustrating the operation of a read request channel according to an embodiment of this application. Figure 6 This is a schematic diagram illustrating the data reception and parsing process according to an embodiment of this application.

[0084] In this example, the number of command interfaces 120 is configured to be 20, the corresponding number of read request generators 131 is 20, and the number of buffer areas is 20. The read request arbitrator 132 adopts the corresponding circuit of weighted round-robin arbitration. The buffer area can store 256 bytes of data. The interface width between the command interface 120 and the image processing module is 4 bytes, and the transmission bus between the memory and the command configuration unit 100 is 32 bytes.

[0085] First, such as Figure 5 As shown, each read request generator 131 generates a read request corresponding to each image processing module according to the control of the display processor controller. The read request may include the identifier and / or address of the storage area of ​​the read data in the memory, and is sent to the memory after passing through the read request arbitrator 132.

[0086] Next, as Figure 6 As shown, selector 111 determines the corresponding buffer region and allocates a write address based on the identification information of the read data obtained from the memory, and then stores the read data into the corresponding buffer region. For example, each buffer region is 256 bytes in size, and the read / write unit is 64 bytes.

[0087] Then, the write address and read address are provided to the base address memory, which determines the write address from which the read data can be read and provides this write address to the corresponding command interface 120. The read / write unit is 64 bytes, meaning 64 bytes of read data can be written each time.

[0088] The buffer read arbitrator 115 controls each command interface 120 to retrieve read data from the buffer area of ​​the buffer 112 according to a preset read priority rule. In addition, if read data is read from the buffer area, the address register 113 records the corresponding read address.

[0089] The read data acquired by each command interface 120 is stored in the command buffer 121 and awaits command parsing to convert the read data according to a preset format before outputting it to the image processing module for configuration. The command buffer 121 can read from the buffer 112 with a bandwidth of 64 bytes, and each command interface can output the converted read data in 4-byte increments. Specifically, the command interface with a second parser can parse read data including coefficient commands, while the command interface with a first parser can parse read data including ordinary commands.

[0090] Based on the same inventive concept, this application also provides a command configuration method. The command configuration method includes a command configuration unit 100 that can be applied to the foregoing embodiments.

[0091] Please see Figure 7 , Figure 7 A flowchart illustrating a command configuration method provided in an embodiment of this application. The command configuration method includes:

[0092] S210 receives read data through the selector.

[0093] S220: The selector stores the read data into the corresponding buffer area according to the identification information of the received read data.

[0094] S230 retrieves read data from the buffer area corresponding to the command interface through the command interface.

[0095] S240 configures the display processor based on configuration commands in the read data via the command interface.

[0096] In one embodiment, before receiving read data via the selector, read requests can also be sent to the memory via each read request generator 131, so that the memory responds to the read request and sends read data to the buffer.

[0097] In one embodiment, after each read request generator 131 sends a read request to the memory, the output order of each read request can be controlled by a read request arbitrator 132. The read request arbitrator 132 is configured to control the output order of each read request based on a preset output priority rule.

[0098] In one embodiment, after storing the read data into the corresponding buffer area through the selector according to the identification information of the received read data, the write address of the read data in the buffer area and the read address of the read data read from the buffer area can also be stored through the address buffer 113. Correspondingly, S230 includes obtaining the read data from the buffer area corresponding to the command interface through the command interface and the write address.

[0099] In one embodiment, after storing the write address of the read data in the buffer area and the read address of the read data read from the buffer area through the address buffer 113, the write address can also be provided to the command interface connected to the base address memory through the base address memory.

[0100] In one embodiment, obtaining read data from the buffer area corresponding to the command interface through the command interface may further include: obtaining read data from the buffer through the preset read priority rules in the buffer read arbitrator 115.

[0101] In one embodiment, the display processor is configured based on configuration commands in the read data via a command interface, including: storing the read data obtained from the buffer based on the command buffer 121; and outputting the read data to the image processing module in a preset format based on the command parser to configure the image processing module.

[0102] In one embodiment, outputting read data to the image processing module according to a preset format based on a command parser includes: parsing a configuration command including a coefficient command based on a second parser 123. The coefficient command is used to configure the image processing module with a three-dimensional lookup table. The second parser 123 is configured to output read data to the image processing module according to the output bandwidth of the second parser 123; the output bandwidth of the second parser 123 in each command interface is matched with the bandwidth of each image processing module with a three-dimensional lookup table in the display processor.

[0103] Based on the same inventive concept, embodiments of this application also provide a display processor. Please refer to... Figure 8 , Figure 8 This is a schematic diagram of a display processor provided in an embodiment of the present application. The display processor includes a command configuration unit 100 and a plurality of image processing modules 210.

[0104] Multiple image processing modules 210 are respectively connected to the command interface of the command configuration unit of the command configuration unit 100. The command configuration unit 100 provided in any of the foregoing embodiments can be referenced, and the image processing modules 210 can refer to the image processing modules in existing display processors, which will not be elaborated upon here.

[0105] Based on the same inventive concept, embodiments of this application also provide an electronic device. Please refer to... Figure 9 , Figure 9 This is a schematic diagram of an electronic device 300 provided in an embodiment of this application. The electronic device 300 includes a display processor 200, a controller 310, and a memory 320.

[0106] The display processor 200 can be the display processor 200 provided in the foregoing embodiments. For details, please refer to the previous text, which will not be elaborated here.

[0107] The controller and memory can use existing devices; for example, the controller 310 can be a CPU, and the memory 320 can be DRAM. The controller, memory, and display processor 200 are connected via a bus.

[0108] In embodiments of this application, controller 310 is configured to generate read data and store the read data in memory; memory 320 is used to output read data to display processor 200 in response to a read request from display processor. The functions of controller 310 and memory 320 in electronic devices can be found in the prior art and will not be described further here.

[0109] In one embodiment, the memory 320 is configured with multiple storage areas, each corresponding to a different command interface; each storage area is configured to store read data corresponding to each command interface.

[0110] By partitioning the memory 320, read data can be retrieved from the corresponding storage area based on the identifier information corresponding to the command interface in the read request, in order to configure the display processor.

[0111] Based on the same inventive concept, embodiments of this application also provide an image display system. Please refer to... Figure 10 , Figure 10 This is a schematic diagram of an image display system provided in one embodiment of this application. The image display system 400 includes an electronic device 300 and a display device 410. The electronic device 300 can be any of the electronic devices provided in the foregoing embodiments.

[0112] Display device 410 is communicatively connected to electronic device 300 and is used to receive image data output by display processor in electronic device 300 and display it.

[0113] In some embodiments, the display device may be disposed within the electronic device as part of the electronic device structure.

[0114] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0115] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A command configuration unit, characterized in that, include: A read data channel includes a buffer and a selector, the buffer being connected to the selector and the buffer being configured with multiple buffer areas; the selector is used to connect to a memory that outputs read data, the read data including configuration commands and identification information, the configuration commands including parameters for configuring each image processing module in the display processor, and the identification information characterizing the buffer area corresponding to the read data; Multiple command interfaces are provided, each of which is connected to the buffer and is configured to correspond to a different buffer region. Each of the command interfaces is used to connect to the image processing module; The selector is configured to receive the read data and store the read data into the corresponding buffer area according to the identification information. Each of the command interfaces is configured to obtain the read data from the corresponding buffer area and configure the image processing module based on the configuration command in the read data; The command configuration unit further includes a read request channel, which includes multiple read request generators, each of which corresponds to a different command interface. Each of the read request generators is used to send a read request to the memory; the memory is configured to send the read data to the buffer in response to the read request.

2. The command configuration unit according to claim 1, characterized in that, The read request channel further includes a read request arbitrator; the read request arbitrator is connected to each of the read request generators and is used to connect to the memory; The read request arbitrator is configured to control the output order of each read request based on a preset output priority rule.

3. The command configuration unit according to claim 1, characterized in that, The read data channel further includes an address buffer, which is connected to the buffer and each of the command interfaces respectively. The address buffer is configured to store the write address of the read data in the buffer area and the read address of the read data read out of the buffer area. The command interface is configured to read the read data from the buffer area according to the write address; The selector is configured to store the read data into the corresponding buffer area according to the read address and the identification information.

4. The command configuration unit according to claim 3, characterized in that, The read data channel further includes a base address memory group, which includes multiple base address memories. The address buffer is connected to each of the command interfaces through each of the base address memories. The base address memory is used to provide the write address to the command interface connected to the base address memory after the read data is stored in the buffer area.

5. The command configuration unit according to claim 3, characterized in that, The read data channel also includes a buffered read arbitrator; the buffered read arbitrator is connected to the buffer and each of the command interfaces respectively; The buffer read arbitrator is configured to instruct each of the command interfaces to retrieve the read data from the buffer.

6. The command configuration unit according to claim 1, characterized in that, Each of the command interfaces shares the storage space of the buffer, and the storage space of each buffer is allocated according to the amount of data read by each command interface in the buffer.

7. The command configuration unit according to any one of claims 1-6, characterized in that, Each of the command interfaces includes a command buffer and a command parser, the command buffer being connected to the buffer and the command parser being connected to the command parser; the command parser is used to connect to the image processing module; The command buffer is used to store the read data obtained from the buffer; The command parser is used to output the read data to the image processing module in a preset format in order to configure the image processing module.

8. The command configuration unit according to claim 7, characterized in that, The command parser includes a first parser or a second parser; The configuration commands include coefficient commands, which are used to configure the image processing module with a three-dimensional lookup table; The second parser is configured to output the read data to the image processing module according to the output bandwidth of the second parser; The output bandwidth of the second parser in each of the command interfaces is matched with the bandwidth of each of the image processing modules in the display processor that have the three-dimensional lookup table.

9. A display processor, characterized in that, include: The command configuration unit as described in any one of claims 1-8; Multiple image processing modules are connected to the command configuration unit.

10. An electronic device, characterized in that, include: The display processor as described in claim 9; A controller and a memory, wherein the memory is connected to the controller and the display processor, respectively; The controller is configured to generate the read data and store the read data into the memory; The memory is used to output the read data to the display processor in response to a read request from the display processor.

11. A command configuration method, characterized in that, An application is provided in a command configuration unit, the command configuration unit comprising: a read data channel, the read data channel including a buffer and a selector, the buffer being connected to the selector, the buffer being configured with multiple buffer areas; the selector being used to connect to a memory that outputs read data, the read data including configuration commands and identification information, the configuration commands including parameters for configuring a display processor, the identification information representing the buffer area corresponding to the read data; and multiple command interfaces, each of the command interfaces being connected to the buffer and configured to correspond to a different buffer area; each command interface being used to connect to the display processor. The command configuration unit further includes: a read request channel, which includes multiple read request generators, each corresponding to a different command interface; each read request generator is used to send a read request to the memory; the memory is configured to send the read data to the buffer in response to the read request. The command configuration method includes: The read data is received through the selector; The selector stores the read data into the corresponding buffer area according to the identification information of the received read data; The read data is obtained from the buffer area corresponding to the command interface through the command interface; The display processor is configured using the command interface based on the configuration commands in the read data.

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