Joint correction method for electron beam proximity effect and etching load effect and mask

Abstract

The present disclosure provides a method and a mask for jointly correcting electron beam proximity effect and etching load effect, which relates to the technical field of semiconductor manufacturing. The method for jointly correcting electron beam proximity effect and etching load effect includes: correcting a layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout, where the first corrected layout is the layout obtained by compensating the first contour shift caused by the electron beam proximity effect for the layout to be corrected; correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, where the second corrected layout is the layout obtained by compensating the second contour shift caused by the etching load effect for the layout to be corrected; performing an intersection operation on the first corrected layout and the second corrected layout to obtain a jointly corrected layout; preparing a mask based on the jointly corrected layout, and the size of each graphic element in the mask pattern of the mask is within a preset size range.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and more specifically, to a method and a mask for jointly correcting electron beam proximity effect and etching load effect. Background Art

[0002] The progress of integrated circuit technology has promoted the development of technologies such as 5G, Internet of Things, and artificial intelligence, making electronic devices faster, smarter, and more efficient, and having a revolutionary impact on economic development and social progress. In the past more than 50 years, the progress of lithography technology has been crucial for maintaining Moore's Law. However, since the minimum feature size of integrated circuits has been reduced to far below the light wavelength used in the lithography process, the semiconductor industry is facing manufacturing process challenges to continue increasing transistor density. In particular, with the reduction of transistor size and the increase of density, it is easy to generate electron beam proximity effect (abbreviated as PE) and etching load effect (abbreviated as LE) during the mask manufacturing process. The electron beam proximity effect appears during the electron beam lithography (EBL) process. Due to the forward scattering and backscattering of electrons, different area and different density patterns receive inconsistent doses under the same exposure dose, resulting in defects such as line end contraction, pattern corner becoming arc-shaped, and line width increase after the mask is finally etched. The etching load effect appears during the plasma etching process. Due to the different pattern areas and pattern densities in different regions of the layout, the etching rates are inconsistent during the etching process, and there is a deviation between the pattern size of the mask after final etching and the target layout. Therefore, how to optimize the defects caused by the electron beam proximity effect and the etching load effect during the mask manufacturing process has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, the present disclosure provides a method and a mask for jointly correcting electron beam proximity effect and etching load effect, which are used to at least partially solve the above technical problems.

[0004] The first aspect of the present disclosure provides a method for jointly correcting electron beam proximity effect and etching load effect, including: correcting the layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout, where the first corrected layout is the layout obtained by compensating the first contour offset caused by the electron beam proximity effect for the layout to be corrected; correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, where the second corrected layout is the layout obtained by compensating the second contour offset caused by the etching load effect for the layout to be corrected; performing an intersection process on the first corrected layout and the second corrected layout to obtain a jointly corrected layout; preparing a mask based on the jointly corrected layout, and the size of each graphic element in the mask pattern of the mask is within a preset size range.

[0005] According to an embodiment of the present disclosure, the method further includes: when the size of each graphic element in the mask pattern of the reticle is outside the preset size range, performing supplementary correction on the combined corrected layout based on the etching load effect, and performing an intersection process on the combined corrected layout after the supplementary correction and the first corrected layout to generate a new combined corrected layout; iterating in this way until the size of each graphic element in the mask pattern of the reticle prepared based on the new combined corrected layout is within the preset size range.

[0006] According to an embodiment of the present disclosure, correcting the layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout includes: performing equal grid processing on the layout to be corrected, determining the point spread function of the energy distribution in the electron beam resist and the initial electron beam exposure dose of each grid when performing unit-dose electron beam direct writing exposure on the electron beam resist; determining a first offset pixel block in the non-graphical area of the layout to be corrected based on the point spread function and the initial electron beam exposure dose of each grid, so as to compensate for the first contour offset caused by the electron beam proximity effect; generating a first corrected layout according to the layout to be corrected and the first offset pixel block.

[0007] According to an embodiment of the present disclosure, correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout includes: sequentially forming a light-shielding layer and an electron beam resist on the surface of the mask substrate; performing electron beam direct writing exposure and development on the electron beam resist based on the layout to be corrected, and performing etching treatment on the light-shielding layer to obtain an initial reticle; obtaining a second offset pixel block between the etching profile of each graphic element in the mask pattern of the initial reticle and the profile of each corresponding graphic element in the layout to be corrected, so as to compensate for the second contour offset caused by the etching load effect; generating a second corrected layout according to the layout to be corrected and the second offset pixel block.

[0008] According to an embodiment of the present disclosure, obtaining the second offset pixel block between the etching profile of each graphic element in the mask pattern of the initial reticle and the profile of each corresponding graphic element in the layout to be corrected includes: respectively determining the coordinates of the first pixel points of each first graphic element according to the profile of each first graphic element in the layout to be corrected; respectively determining the coordinates of the second pixel points of each second graphic element according to the etching profile of each second graphic element in the mask pattern of the initial reticle; where, one first graphic element corresponds to one second graphic element; for each first graphic element, determining the second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point.

[0009] According to an embodiment of the present disclosure, for each first graphic element, determining a second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point includes: for each first pixel point on the boundary of each first graphic element in the same layout to be corrected, determining a first offset in the first direction of the etching profile of the second graphic element according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; determining a second offset in the first direction of the etching profile of the second graphic element according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point; calculating the size in the first direction corresponding to the second offset pixel block according to the first offset, the second offset, and a preset gradient value; taking the first pixel point as the starting pixel point, determining the number of first pixel points that are the same in size and continuous in the first direction, and determining the size in the second direction corresponding to the second offset pixel block based on the number; the first direction intersects with the second direction, and the second direction is parallel to the tangent direction of the boundary; determining the area of the second offset pixel block corresponding to the first pixel point based on the coordinates of the first pixel point, the size in the first direction corresponding to the second offset pixel block, and the size in the second direction; repeating the operation of determining a first offset in the first direction of the etching profile of the second graphic element according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; determining a second offset in the first direction of the etching profile of the second graphic element according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point until determining the area of the second offset pixel block corresponding to the first pixel point based on the coordinates of the first pixel point, the size in the first direction corresponding to the second offset pixel block, and the size in the second direction, to determine all the second offset pixel blocks on the boundary, where the second offset pixel blocks are adjacent to each other.

[0010] According to an embodiment of the present disclosure, calculating the size in the first direction corresponding to the second offset pixel block according to the first offset, the second offset, and a preset gradient value includes: when the difference between the first offset and the second offset is less than or equal to the preset gradient value, determining the first offset as the size in the first direction corresponding to the second offset pixel block; when the difference between the first offset and the second offset is greater than the preset gradient value, determining the difference between the first offset and the preset gradient value as the size in the first direction corresponding to the second offset pixel block.

[0011] According to an embodiment of the present disclosure, generating a second corrected layout according to the layout to be corrected and the second offset pixel block includes: performing an inversion operation on the second offset pixel block with the boundary line in the layout to be corrected adjacent to the second offset pixel block as the axis of symmetry to obtain a mirrored second offset pixel block; the difference between the layout to be corrected and the mirrored second offset pixel block of each graphic element is the second corrected layout.

[0012] The second aspect of the present disclosure provides a method for jointly correcting large-scale electron beam proximity effect and etch loading effect, including: correcting initial layout diagrams with different density distributions based on the electron beam proximity effect respectively to obtain a plurality of first corrected layout diagrams, where the first corrected layout diagram is the layout diagram after compensating the first contour shift caused by the electron beam proximity effect for the initial layout diagram; correcting initial layout diagrams with different density distributions based on the etch loading effect respectively to obtain a plurality of second corrected layout diagrams, where the second corrected layout diagram is the layout diagram after compensating the second contour shift caused by the etch loading effect for the initial layout diagram; respectively performing an intersection process on the first corrected layout diagram and the second corrected layout diagram corresponding to the initial layout diagram with the same density distribution to obtain a plurality of jointly corrected layout diagrams; inputting the initial layout diagrams with different density distributions and the plurality of jointly corrected layout diagrams into a generative adversarial network for multiple iterative trainings until the convergence condition is satisfied to obtain a trained generative adversarial network; and inputting the layout diagram to be corrected into the trained generative adversarial network to output a target jointly corrected layout diagram.

[0013] The third aspect of the present disclosure provides a mask, which is prepared based on the jointly corrected layout diagram. Among them, the size of each graphic element in the mask pattern of the mask is within a preset size range, and the jointly corrected layout diagram is obtained by using the above-mentioned joint correction method.

[0014] The method for jointly correcting the electron beam proximity effect and the etch loading effect provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0015] This method can accurately predict and compensate the contour shift caused by the electron beam proximity effect by calculating the energy distribution of each grid of the layout diagram to be corrected based on the point spread function. At the same time, by analyzing the difference between the actual etch contour and the designed contour, the contour shift caused by the etch loading effect is determined and compensated. This method takes into account the influence of both the electron beam proximity effect and the etch loading effect, compensates and optimizes the mask pattern of the mask, can accurately compensate the errors caused by the two effects, and thus improves the quality of the mask. Compared with the traditional single-effect correction method, this method not only solves the error accumulation caused by ignoring the potential problems brought by the other effect, but also ensures that the finally prepared mask is as close as possible to the design specifications.

[0016] This method uses the jointly corrected layout diagrams with different density distributions as a sample set to perform iterative training on the generative adversarial network to obtain a trained generative adversarial network model. This model can automatically learn complex patterns and relationships in a large dataset, intelligently fuse the correction results of the electron beam proximity effect and the etch loading effect, and generate an optimal layout diagram that comprehensively considers the influence of the two effects. In this way, not only can large-scale layout data be processed quickly and accurately, improving work efficiency, but also it can adapt to different design requirements and process condition changes. Description of the Drawings

[0017] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0018] Figure 1 Schematically shows a flowchart of a method for jointly correcting electron beam proximity effect and etching load effect according to an embodiment of the present disclosure;

[0019] Figure 2 Schematically shows a flowchart of a method for jointly correcting electron beam proximity effect and etching load effect according to another embodiment of the present disclosure;

[0020] Figure 3 Schematically shows a flowchart of a method for generating a first corrected layout according to an embodiment of the present disclosure;

[0021] Figure 4 Schematically shows a flowchart of a method for generating a second corrected layout according to an embodiment of the present disclosure;

[0022] Figure 5 Schematically shows a flowchart of a method for generating a second offset pixel according to an embodiment of the present disclosure;

[0023] Figure 6 Schematically shows a schematic diagram of a local area of a layout to be corrected and a corresponding etching area according to an embodiment of the present disclosure;

[0024] Figure 7 Schematically shows a schematic diagram of an etching deviation of a graphic element according to an embodiment of the present disclosure;

[0025] Figure 8 Schematically shows a schematic diagram of an etching deviation inversion operation of a graphic element according to an embodiment of the present disclosure;

[0026] Figure 9 Schematically shows a schematic diagram of a graphic element correction according to an embodiment of the present disclosure;

[0027] Figure 10 Schematically shows a schematic diagram of a jointly corrected layout according to an embodiment of the present disclosure;

[0028] Figure 11 Schematically shows a comparison diagram of a mask pattern etched based on an original layout and a jointly corrected layout according to an embodiment of the present disclosure;

[0029] Figure 12 Schematically shows a schematic diagram of a method for jointly correcting a large-scale layout according to an embodiment of the present disclosure;

[0030] Figure 13Schematically shows a structure diagram of a generative adversarial network according to an embodiment of the present disclosure. Detailed implementation manners

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, numerous specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can be implemented without these specific details. In addition, in the following description, descriptions of well-known systems and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0033] By Figures 1 to 13 A joint correction method of embodiments of the present disclosure will be described in detail.

[0034] Figure 1 Schematically shows a flowchart of a joint correction method for electron beam proximity effect and etch loading effect according to an embodiment of the present disclosure.

[0035] As Figure 1 shown, the joint correction method of this embodiment includes steps S110 to S140.

[0036] Step S110: Correct the layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout, where the first corrected layout is the layout obtained by compensating the first contour offset caused by the electron beam proximity effect for the layout to be corrected.

[0037] Step S120: Correct the layout to be corrected based on the etch loading effect to obtain a second corrected layout, where the second corrected layout is the layout obtained by compensating the second contour offset caused by the etch loading effect for the layout to be corrected.

[0038] Step S130: Perform an intersection operation on the first corrected layout and the second corrected layout to obtain a jointly corrected layout.

[0039] Step S140: Prepare a mask based on the jointly corrected layout, and the size of each graphic element in the mask pattern of the mask is within a preset size range.

[0040] In an embodiment of the present disclosure, the electron beam proximity effect refers to the phenomenon that when electron beam direct writing technology is used for lithography, due to electron scattering, the resist around the designed pattern is also affected by exposure. This effect causes a deviation between the actual pattern and the designed pattern. The etch loading effect refers to the pattern distortion phenomenon during the etching process due to the difference in etching rates in different density regions. For example, in high-density regions, it is difficult for the etchant or gas to reach, which may lead to under-etching; while in low-density regions, over-etching may occur.

[0041] Currently, the commonly used methods for the above-mentioned electron beam proximity effect are to compensate for the influence of the electron beam proximity effect by adjusting the exposure dose or to compensate for the electron beam proximity effect by changing the pattern shape. The commonly used methods for the above-mentioned etch loading effect are to change the etching process parameters or deposit a barrier layer to weaken the influence of the loading effect. However, these methods do not comprehensively consider the pattern distortion problem caused by the simultaneous action of the electron beam proximity effect and the etch loading effect. In fact, these two effects often coexist in the mask preparation process, and dealing with only one of the effects cannot completely eliminate the distortion defects of the finally prepared mask.

[0042] Based on this, in order to effectively solve the mask pattern distortion problem caused by the electron beam proximity effect and the etch loading effect, the present disclosure proposes a joint correction method. This method first corrects the layout to be corrected based on the electron beam proximity effect to generate a first corrected layout. Then, it corrects the layout to be corrected again based on the etch loading effect to obtain a second corrected layout. Next, by taking the intersection of the first corrected layout and the second corrected layout, a joint corrected layout that comprehensively considers the influence of the two effects is generated. And a mask is fabricated according to this joint corrected layout to ensure that the size of each graphic element in the mask pattern is within the preset size range, completing the optimization of the layout to be corrected.

[0043] Among them, contour offset refers to the positional deviation between the designed pattern and the actually formed pattern during the actual manufacturing process due to the influence of the electron beam proximity effect or the etch loading effect. Specifically, the first contour offset caused by the electron beam proximity effect is due to the change in the exposure amount of the resist around the designed pattern caused by electron scattering, which makes the position of the actual pattern shift relative to the designed pattern. The second contour offset caused by the etch loading effect is due to the difference in etching rates in different regions, such as the difference between high-density regions and low-density regions, resulting in changes in the size or shape of the actual pattern.

[0044] According to an embodiment of the present disclosure, this combined correction method can achieve efficient correction of the electron beam proximity effect and the etching load effect without changing the electron beam exposure dose and the plasma etching process conditions used for the same mask, and effectively solves the limitations caused by the failure to comprehensively consider multiple effects in the traditional method.

[0045] Figure 2 The flowchart of the combined correction method for the electron beam proximity effect and the etching load effect according to another embodiment of the present disclosure is schematically shown.

[0046] As Figure 2 shown, the combined correction method of this embodiment further includes steps S150 to S160.

[0047] Step S150: When the size of each graphic element in the mask pattern of the mask is outside the preset size range, perform supplementary correction on the combined correction layout based on the etching load effect, and perform an intersection operation on the supplementary corrected combined correction layout and the first correction layout to generate a new combined correction layout.

[0048] Step S160: Iterate in this way until the size of each graphic element in the mask pattern of the mask prepared based on the new combined correction layout is within the preset size range.

[0049] In an embodiment of the present disclosure, if it is checked that the sizes of all graphic elements on the mask generated based on the current combined correction layout do not meet the requirements of the preset size range, then correct the current combined correction layout based on the etching load effect to generate a new second correction layout. And perform an intersection operation on the new second correction layout and the first correction layout to generate a new combined correction layout. During this period, step S150 is continuously repeated until the size of each graphic element in the mask pattern of the mask generated based on the new combined correction layout is within the preset size range.

[0050] In some possible embodiments, the size deviation between each graphic element in the mask pattern of the mask generated based on the new combined correction layout and each graphic element designed in the layout to be corrected is ±5%.

[0051] According to an embodiment of the present disclosure, through continuous evaluation and optimization, this method effectively solves the limitations that may be caused by single-effect correction, providing strong support for modern semiconductor manufacturing.

[0052] Figure 3 The flowchart of the method for generating the first correction layout according to an embodiment of the present disclosure is schematically shown.

[0053] As Figure 3 shown, the method of this embodiment includes steps S210 to S230.

[0054] Based on the electron beam proximity effect, the layout to be corrected is corrected to obtain a first corrected layout, including:

[0055] Step S210: Perform equal-grid processing on the layout to be corrected, and determine the point spread function of the energy distribution in the electron beam resist and the initial electron beam exposure dose of each grid when performing single-dose electron beam direct writing exposure on the electron beam resist.

[0056] Step S220: Determine the first offset pixel block of the non-patterned area based on the point spread function and the initial electron beam exposure dose of each grid, so as to compensate for the first contour offset caused by the electron beam proximity effect.

[0057] Step S230: Generate a first corrected layout according to the layout to be corrected and the first offset pixel block.

[0058] In the embodiments of the present disclosure, the layout to be corrected is segmented according to a preset rule to form a series of grids of equal size. Set the acceleration voltage, beam spot diameter, number of simulated electrons, material thickness and material properties of the electron beam resist and the substrate of the electron beam direct writing exposure, and perform electron beam Monte Carlo simulation according to the above parameters to obtain the forward scattering range α (nm) and the backscattering range β (nm) of the electron beam, as well as the energy ratio η of the forward scattering to the backscattering.

[0059] Based on the double Gaussian function, calculate the point spread function F(r) of the energy distribution in the electron beam resist during single-dose electron beam direct writing exposure, which can be used to represent the relationship between the energy generated by a single electron beam exposure point in the electron beam resist and the attenuation with distance. Its expression is as follows:

[0060]

[0061] Through the point spread function, the energy contribution of each grid to other surrounding grids can be calculated, so as to evaluate the energy superposition situation caused by the electron beam proximity effect in the entire pattern area. Based on the above energy analysis, using the point spread function and the initial exposure dose information of each grid, predict and quantify the impact of the electron beam proximity effect on the non-patterned area, and then determine the displacement amount caused by the electron beam scattering in these areas, that is, the first offset pixel block.

[0062] For each first offset pixel block identified as being affected by the electron beam proximity effect, correspondingly adjust the size, shape or relative position of the surrounding graphic elements to ensure that the finally formed pattern is as close as possible to the design specifications in the ideal state.

[0063] According to an embodiment of the present disclosure, by systematically analyzing and correcting the layout to be corrected, this method effectively solves the common proximity effect problem in electron beam lithography technology, and improves the accuracy and reliability of the micro-nano manufacturing process.

[0064] Further, calculate the total effective exposure dose E of any grid p according to the point spread function and the initial exposure dose of each grid of the electron beam. p , and its expression is as follows:

[0065]

[0066] Where, is the energy distribution point spread function at a distance r from grid p, is the initial exposure dose at a distance r from grid p, N is the number of grids in the x direction of the layout, M is the number of grids in the y direction of the layout, and the initial exposure dose of each grid is the same and is the minimum exposure dose that can ensure that all patterns in the layout can reach the development threshold. [[ID=1,7]]

[0067] By calculating the total effective exposure dose E of any grid p p the energy distribution of the entire layout to be corrected can be obtained.

[0068] Further, determine the position of the non-graphic area in the layout to be corrected , and its expression is as follows:

[0069]

[0070] Based on the position of the non-graphic area and the total effective exposure dose E of any grid p p calculate the energy distribution E of the non-graphic area q , and its expression is as follows:

[0071]

[0072] According to the development threshold E th , determine the area that needs to be corrected for the proximity effect , and its expression is as follows:

[0073]

[0074] Take the grids as the offset pixel blocks for the electron beam proximity effect, perform an inversion operation on the offset pixel blocks with the boundary line of the adjacent original layout as the axis of symmetry, and subtract the offset pixel blocks from the original layout to obtain the initial layout corrected for the electron beam proximity effect .

[0075] Figure 4 Schematically shows a flowchart of a method for generating a second corrected layout according to an embodiment of the present disclosure.

[0076] As shown Figure 4 in the figure, the method for generating the second corrected layout in this embodiment includes steps S310 to S330.

[0077] Correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, including:

[0078] Step S310: Sequentially form a light-shielding layer and an electron beam resist on the surface of the mask substrate.

[0079] Step S320: Perform electron beam direct writing exposure and development on the electron beam resist based on the layout to be corrected, and etch the light-shielding layer to obtain an initial mask template.

[0080] Step S330: Obtain a second offset pixel block between the etching profile of each graphic element in the mask pattern of the initial mask template and the profile of the corresponding graphic element in the layout to be corrected, so as to compensate for the second profile offset caused by the etching load effect.

[0081] Step S340: Generate a second corrected layout according to the layout to be corrected and the second offset pixel block.

[0082] In the embodiment of the present disclosure, an initial mask template is obtained by using electron beam direct writing exposure and plasma etching technology on quartz glass deposited with a light-shielding material based on the layout to be corrected. The etching profile of each graphic element in the initial mask template is extracted by the contour extraction method, and the extracted etching profile is compared with the profile of the corresponding graphic element in the layout to be corrected to determine the etching deviation, that is, the second offset pixel block. Finally, combining the original layout to be corrected, an accurate second corrected layout is generated, which can effectively compensate for the contour deviation caused by the etching load effect.

[0083] Furthermore, a scanning electron microscope image of each graphic element in the initial mask template is collected, and the collected image is subjected to equal grid processing to facilitate quantification of the etching deviation. Among them, the offset pixel block refers to the offset amount of a single graphic element after etching from the corresponding graphic element in the layout to be corrected, and is composed of multiple grids.

[0084] Furthermore, the light-shielding material may include chromium, molybdenum, tantalum, or molybdenum silicide.

[0085] According to the embodiment of the present disclosure, by introducing the second offset pixel block and adjusting the corrected layout accordingly, the influence of the etching load effect on the final product can be significantly reduced, thereby improving the accuracy of pattern transfer.

[0086] Figure 5 Schematically shows a flowchart of the method for generating the second offset pixel according to the embodiment of the present disclosure.

[0087] As shown Figure 5 in the figure, the method for generating the second offset pixel in this embodiment includes steps S410 to S430.

[0088] Obtaining the second offset pixels between the etching profile of each graphic element in the mask pattern of the initial mask and the corresponding graphic element profile in the layout to be corrected includes:

[0089] Step S410: Determine the coordinates of the first pixel points of each first graphic element in the layout to be corrected according to the profile of each first graphic element respectively.

[0090] Step S420: Determine the coordinates of the second pixel points of each second graphic element in the mask pattern of the initial mask according to the etching profile of each second graphic element respectively; wherein, one first graphic element corresponds to one second graphic element.

[0091] Step S430: For each first graphic element, determine the second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point.

[0092] In the embodiments of the present disclosure, a pixel point refers to a contour composition point of a single image element.

[0093] On the basis of determining the coordinates of the second pixel points of the etching profile of each second graphic element in the initial mask, based on each second graphic element, place the profile of the corresponding first graphic element in the layout to be corrected in the same coordinate system as the etching profile. Calculate the offset amount of the etching profile of each second graphic element relative to the design expectation, that is, the second offset pixel block.

[0094] According to the embodiments of the present disclosure, based on each first graphic element, by comparing the difference between the etching profile and the design target, the offset amount is accurately quantified, improving the accuracy of correction.

[0095] Further, step S430: For each first graphic element, determining the second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point includes:

[0096] For the first pixel points on the boundary of each first graphic element in the layout to be corrected, determine the first offset amount of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point.

[0097] Determine the second offset of the etching profile of the second graphic element in the first direction based on the coordinates of the first pixel points adjacent to the first pixel point and the coordinates of the second pixel points corresponding to the first pixel points adjacent to the first pixel point.

[0098] Calculate the size of the second offset pixel block in the first direction according to the first offset, the second offset and the preset gradient value.

[0099] Further, when the difference between the first offset and the second offset is less than or equal to the preset gradient value, determine the first offset as the size of the second offset pixel block in the first direction.

[0100] When the difference between the first offset and the second offset is greater than the preset gradient value, determine the difference between the first offset and the preset gradient value as the size of the second offset pixel block in the first direction.

[0101] Taking the first pixel point as the starting pixel point, determine the number of first pixel points with the same size and continuous in the first direction, and determine the size of the second offset pixel block in the second direction based on the number; the first direction intersects the second direction, and the second direction is parallel to the tangent direction of the boundary.

[0102] Based on the coordinates of the first pixel point, the size of the second offset pixel block in the first direction and the size of the second direction, determine the area of the second offset pixel block corresponding to the first pixel point.

[0103] Repeat the operation of determining the first offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point. Determine the second offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel points adjacent to the first pixel point and the coordinates of the second pixel points corresponding to the first pixel points adjacent to the first pixel point until the area of the second offset pixel block corresponding to the first pixel point is determined based on the coordinates of the first pixel point, the size of the second offset pixel block in the first direction and the size of the second direction, to determine all the second offset pixel blocks on the boundary, where each of the second offset pixel blocks is adjacent to each other.

[0104] In an embodiment of the present disclosure, based on each first graphic element in the layout to be corrected, the second graphic element in the mask pattern of the initial mask after etching is compared with the first graphic element in the layout to be corrected, where each first graphic element corresponds to each second graphic element one by one. An algorithm is used to search for the maximum offset point in the first direction at the same position in the etching profile and the layout to be corrected, that is, the second pixel point, and the first offset h1 is calculated. At this time, the first offset is the maximum offset in the graphic elements at the same position. And according to the first offset point, a second offset point adjacent to the grid corresponding to the first offset point is determined, that is, the second pixel point adjacent to the second pixel point, and the offset between the second offset point and the profile at the same position in the layout to be corrected is calculated, that is, the second offset h2. The preset gradient value is set to t, and the gradient value can be in nanometers, then the size D of the second offset pixel block in the first direction v The expression is as follows:

[0105]

[0106] The size D of the second offset pixel block in the second direction h The expression is as follows:

[0107]

[0108] Where x i is the grid size, and N is the number of horizontal grids included in the size D in the first direction v And so on until all offset pixel blocks in the same direction are calculated.

[0109] For example, when calculating a second offset pixel block adjacent to a second offset pixel block on the above boundary, the first pixel point at the last in the second direction of a second offset pixel block above is used as the starting pixel point. Based on this starting pixel point, the size of the second offset pixel block adjacent in the first direction and the size in the second direction are recalculated, and then the area of the second offset pixel block adjacent is determined.

[0110] According to the embodiment of the present disclosure, it can be ensured that even in the case of large local deviations, the influence of these deviations can be reduced through an appropriate compensation mechanism, thereby improving the accuracy and consistency of the final product. At the same time, it can also more accurately capture significant deviations in a small range that occur in the actual manufacturing process and make targeted corrections. And by setting the preset gradient value t, the correction intensity can be controlled to a certain extent to avoid new problems caused by overcorrection.

[0111] Based on the above embodiment, generating a second corrected layout according to the layout to be corrected and the second offset pixel block includes:

[0112] Using the boundary line in the layout to be corrected adjacent to the second offset pixel block as the axis of symmetry, perform an inversion operation on the second offset pixel block to obtain a mirrored second offset pixel block.

[0113] The difference between the layout to be corrected and the mirrored second offset pixel block of each graphic element is the second corrected layout.

[0114] In an embodiment of the present disclosure, the boundary lines of each graphic element in the layout to be corrected are identified, and these boundary lines will serve as the axes of symmetry in the inversion operation. For each determined second offset pixel block, perform a mirror transformation with its corresponding boundary line as the axis. This means that if a graphic element has a design error in a certain direction, the inversion operation will generate a corresponding compensation amount in the opposite direction to offset this deviation. Finally, calculate the difference between the layout to be corrected and the mirrored second offset pixel block of each graphic element. This difference actually represents the adjustment amount required to compensate for the etching load effect. In this way, a new layout, namely the second corrected layout, can be obtained.

[0115] According to the embodiments of the present disclosure, by accurately calculating and applying the inversion operation, the dimensional deviation caused by the etching load effect can be effectively compensated. By adopting the above correction method, potential manufacturing errors can be considered in the design stage, thereby reducing the need for later adjustments.

[0116] Figure 6 Schematically shows a schematic diagram of a local area of the layout to be corrected and the corresponding etching area according to an embodiment of the present disclosure. Among them, Figure 6 a is a schematic diagram of a sparse area in the layout to be corrected, Figure 6 b is Figure 6 a schematic diagram of the corresponding etching area. Figure 6 c is a schematic diagram of a dense area in the layout to be corrected, Figure 6 d is Figure 6 a schematic diagram of the corresponding etching area of c.

[0117] In some possible embodiments, the layout to be corrected is subjected to equal grid processing, and the size of each grid can be set according to the process node and optimization accuracy requirements, such as it can be set to 1nm - 10nm, where the size of the layout to be corrected is 3.5mm × 3.5mm.

[0118] As Figure 6 shown in a, 1 is a rectangular element with a size of 130nm × 50nm. 2 is a non-graphic dividing area. 3 is a square hole element with a size of 50nm × 50nm. As Figure 6 shown in c, 4 is a square element with a period of 130nm and a size of 50nm × 50nm.

[0119] The initial exposure dose for each grid can be set to 380 μC / cm 2 , which can ensure that all graphic elements in the layout to be corrected can reach the development threshold. Among them, the development threshold is affected by photoresist materials, exposure parameters, development conditions, film characteristics, etc., and can be obtained through experiments.

[0120] Calculate the energy distribution of the non-graphic area in the layout to be corrected according to the above parameters. According to the energy development threshold of the electron beam resist, determine the area where the energy distribution in the non-graphic area reaches the development threshold, and perform pixel optimization on the adjacent layout elements in this graphic area to generate the first corrected layout .

[0121] Based on the layout to be corrected, a 38-nm chromium layer can be deposited on a 6.35-mm-thick quartz substrate with chromium as the light-shielding material. After subsequent spin coating, electron beam direct writing, development, and plasma etching processes, the final pattern is formed on the quartz substrate to obtain the initial mask. Among them, the minimum etching time is to ensure that the graphic elements with the slowest etching rate in the mask layout are etched to the corresponding size of the target layout. As Figure 6 shown in b and d of Figure 6 , where b is the image of a in Figure 6 after etching, and d is the image of c in

[0122] Figure 7 after etching. Due to the influence of the etching load effect, there are phenomena of line width increase and corner rounding in the rectangular elements and dense hole elements after etching.

[0123] As Figure 7 shown, taking the rectangular element 1 in b of Figure 6 as an example. By designing a contour extraction algorithm, extract the edge contour after graphic etching and assign contour pixel point coordinates, and then place the graphics at the corresponding positions in the original layout in the same coordinate system for comparison. Among them, 1-1 is the corresponding graphic in the original layout, 1-2 is the pixel points of the graphic etching edge contour, and 1-3 is the second offset pixel block.

[0124] Specifically, compare the graphic element contour in the etched initial mask with the graphic element at the same position in the original layout. As Figure 7 shown, taking the horizontal edge as an example, calculate the innermost pixel point of the contour, use the algorithm to search for the maximum offset point x1 of the contour and the layout at the same position, and calculate the first offset h1 according to the x1 point of the etching contour and the corresponding x2 point on the layout to be corrected. And calculate the second offset h2 according to the adjacent next corresponding grid x3 and the corresponding x4, and set the minimum optimization gradient to t, then the size D of the second offset pixel block in the first direction v , that is, the size D in the longitudinal directionv As follows:

[0125]

[0126] The size of the second offset pixel block in the second direction, i.e., the horizontal size D h is , where x i is the grid size, and N is the number of grids in the second direction included under the same longitudinal size D v The number of grids in the second direction.

[0127] And so on until all offset pixel blocks in the same direction are calculated (as shown by 1-34, 1-33, 1-32, 1-31 in Figure 7 ).

[0128] Figure 8 Schematically shows a schematic diagram of the etching deviation inversion operation of graphic elements according to an embodiment of the present disclosure.

[0129] As Figure 8 shown, an inversion operation is performed on the offset pixel block with the boundary line of the adjacent layout to be corrected as the axis of symmetry. The pixel block after symmetric inversion is as shown in Figure 8 , where 1-4 is the second mirror offset pixel block. And so on, for the longitudinal edges of rectangular elements and the horizontal and longitudinal edges of dense hole elements, referring to the above steps, all offset pixel blocks of the horizontal and longitudinal edges of each element can be calculated.

[0130] Figure 9 Schematically shows a schematic diagram of the correction of graphic elements according to an embodiment of the present disclosure.

[0131] As Figure 9 shown, the original graphic element 1-1 in the layout to be corrected is subtracted from the corresponding second mirror offset pixel block 1-4 to obtain the corrected graphic element 1-6. Among them, after the original second mirror offset pixel block 1-4 is corrected, it is converted into a non-graphic area 1-5 in the generated corrected layout. And so on, for each graphic element, the layout to be corrected is subtracted from the offset pixel block to obtain the second corrected layout with the etching load effect corrected .

[0132] Figure 10 Schematically shows a schematic diagram of the combined corrected layout according to an embodiment of the present disclosure.

[0133] Perform an intersection operation on the first corrected layout and the second corrected layout to obtain the first combined corrected layout. As shown in Figure 10 , Figure 10 a in Figure 6 is the layout of the rectangular element 1 in a after combined correction.Figure 10 b in Figure 6 Figure 4(c) shows the layout after combined correction of the square holes 4 in c. Among them, the edges of the rectangular and square elements in the layout to be corrected show a stepped morphology after combined correction of the electron beam proximity effect and the etch loading effect.

[0134] Based on the layout of the first optimization, a mask after the first optimization is prepared by plasma etching. It is judged whether the etch size of each graphic element in the mask pattern of the mask reaches the design size of the graphic element in the layout to be corrected. If the design size has been reached, the optimization is completed. If the design size is not reached, the second corrected layout is updated, and a new combined corrected layout is generated based on the updated second corrected layout and the first corrected layout. This process continues until the error between the size of the graphic element in the mask prepared based on the new combined corrected layout and the size of the design graphic is less than the deviation tolerance limit of ±5%.

[0135] Figure 11 Schematically shows a comparison diagram of mask patterns etched based on the original layout and the combined corrected layout according to an embodiment of the present disclosure. Among them, Figure 11 a is the mask pattern etched in the sparse region based on the original layout Figure 1 the mask pattern etched in the sparse region based on the original layout, Figure 11 b is the mask pattern etched in the same sparse region based on the combined corrected layout. Figure 11 c is the mask pattern etched in the dense region based on the original layout Figure 1 the mask pattern etched in the dense region based on the original layout, Figure 11 d is the mask pattern etched in the same dense region based on the combined corrected layout. Figure 11 e is the mask pattern etched in the sparse square hole region based on the original layout Figure 1 the mask pattern etched in the sparse square hole region based on the original layout, Figure 11 f is the mask pattern etched in the same sparse square hole region based on the combined corrected layout.

[0136] As Figure 11 shown, after combined correction and optimization of the electron beam proximity effect and the etch loading effect, the mask has significant improvements in terms of graphic line width, edge flatness, and line end corner rounding after plasma etching compared to before optimization. This enables the sizes of graphics with different densities and areas in the same mask to reach the target layout design size after etching under the same electron beam exposure dose and plasma etching conditions.

[0137] Among them, for comparison, only the long edges of the rectangular elements are optimized while the short edges and the hole elements are not optimized. As Figure 11 shown in a and b in Figure 5, after optimization, the line width and edge flatness in the corresponding direction of the long sides of the rectangular elements are significantly improved, while the short edges and the edges of the hole elements still show a circular arc shape. After optimizing both the long edges and the short edges of the rectangular elements, the circular arc shape at the line ends and the line width size are both significantly improved, as Figure 11As shown in the embedded dashed-line diagram of b in the figure.

[0138] As Figure 11 Shown in c and d in the figure, the four edges of the dense square holes are optimized. Before optimization, the etched holes show a round hole morphology and are relatively large in size, while after optimization, they show a square hole morphology, and the rounding of the corners is significantly improved, and the size of the holes reaches the target layout design value.

[0139] As Figure 11 Shown in e and f in the figure, the four edges of the sparse square holes are optimized. After optimization, the edge morphology, flatness, rounding of the corners, and the size of the holes are all significantly improved.

[0140] Figure 12 Schematically shows a schematic diagram of the method for large-scale layout joint correction according to an embodiment of the present disclosure.

[0141] As Figure 12 Shown in the figure, the method for large-scale layout joint correction in this embodiment includes steps S510 to S540.

[0142] Step S510: Based on the electron beam proximity effect, correct the initial layouts with different density distributions respectively to obtain a plurality of first corrected layouts. The first corrected layout is the layout after compensating the first contour offset caused by the electron beam proximity effect for the initial layout. The principle of this step is the same as that of step S110, and will not be elaborated here.

[0143] Step S520: Based on the etching load effect, correct the initial layouts with different density distributions respectively to obtain a plurality of second corrected layouts. The second corrected layout is the layout after compensating the second contour offset caused by the etching load effect for the initial layout. The principle of this step is the same as that of step S120, and will not be elaborated here.

[0144] Step S530: Respectively perform an intersection process on the first corrected layout and the second corrected layout corresponding to the initial layout with the same density distribution to obtain a plurality of joint corrected layouts. The principle of this step is the same as that of step S110, and will not be elaborated here.

[0145] Step S540: Input the initial layouts with different density distributions and the plurality of joint corrected layouts into the generative adversarial network for multiple iterative trainings until the convergence condition is satisfied, and obtain the trained generative adversarial network.

[0146] Step S550: Input the layout to be corrected into the trained generative adversarial network, and output the target joint corrected layout.

[0147] In an embodiment of the present disclosure, in a large-scale mask layout, there are graphic elements with different area sizes and different density distributions. At the same electron beam exposure dose, if the optimal exposure dose is ensured for the smallest area or sparsely distributed graphics, the exposure dose obtained by the large-area or densely distributed graphic elements will be excessive, ultimately resulting in an increase in the graphic line width. In addition, during the plasma etching process, due to the inconsistent etching rates of graphic elements with different area sizes and different density distributions during the etching process, under the same etching conditions, if the etching of the smallest area or sparsely distributed graphics reaches the target layout design size, there will be a deviation between the etched large-area or densely distributed graphic elements and the target layout design size.

[0148] Based on this, by inputting the initial layout with different density distributions and multiple jointly corrected layouts generated based on the initial layout with different density distributions into the generative adversarial network for multiple iterative trainings, a trained generative adversarial network is obtained. Finally, according to the specified input method, the generative adversarial network can generate a jointly corrected layout of the electron beam proximity effect and the etching load effect for any large-scale mask layout.

[0149] Figure 13 Schematically shows a structural diagram of a generative adversarial network according to an embodiment of the present disclosure.

[0150] Specifically, as Figure 13As shown, the generative adversarial network includes a generator and a discriminator. Among them, the generator uses convolutional layers and transposed convolutional layers to construct an encoder-decoder structure, designs a U-Net skip connection structure, fuses the feature maps of the encoder and the decoder through skip connections to retain more detailed information; adds residual blocks in the encoder and decoder to improve the network's expressive ability; uses LeakyReLU or ReLU as the activation function, and the output layer uses the Sigmoid or Tanh function. The discriminator uses multiple convolutional layers to extract features, gradually reduces the size of the feature maps, uses global average pooling instead of a fully connected layer in the last layer to reduce the number of parameters; uses LeakyReLU as the activation function, and the output layer uses the Sigmoid function. Input the initial layout diagrams with different density distributions into the generator, encode the graphic elements in the layout through a series of convolutional layers and activation functions, then decode the graphic elements through a series of transposed convolutional layers and activation functions, map the latent space vectors to the data space to obtain a generated layout, and input it into the discriminator. At the same time, the jointly corrected layout corresponding to the initial layout is rotated, flipped and other enhanced operations are performed and then input into the discriminator as an optimized sample set. Through a series of convolutional layers and activation functions, the features of the input samples are extracted for comparison, and binary cross-entropy loss is used to distinguish the layout generated by the generator and the real optimized layout. The discriminator judges the difference between the layout generated by the generator network and the optimized sample set, calculates the loss function and updates the parameters, and feeds back to the generator network. The generator adjusts its own parameters according to the feedback of the discriminator, and finally achieves the effect that the layout generated by the generator is indistinguishable from the real sample set, and obtains a trained generative adversarial network.

[0151] The present disclosure also provides a mask, which is prepared based on the jointly corrected layout. Among them, the size of each graphic element in the mask pattern of the mask is within a preset size range, and the jointly corrected layout is obtained by using the above-mentioned joint correction method. The principle of the joint correction method is the same as the above expression and will not be elaborated here.

[0152] The embodiments of the present disclosure have been described above. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A combined correction method for electron beam proximity effect and etching load effect, characterized in that Including: Performing grid processing on the layout to be corrected, etc., and determining the point spread function of the energy distribution in the electron beam resist and the initial electron beam exposure dose of each grid when performing electron beam direct writing exposure with a unit dose on the electron beam resist; Determining a first offset pixel block of the non-patterned area of the layout to be corrected based on the point spread function and the initial electron beam exposure dose of each grid, so as to compensate for the first contour offset caused by the electron beam proximity effect; generating a first corrected layout according to the layout to be corrected and the first offset pixel block; Successively forming a light-shielding layer and an electron beam resist on the surface of the mask substrate; Performing electron beam direct writing exposure and development on the electron beam resist based on the layout to be corrected, and performing etching treatment on the light-shielding layer to obtain an initial mask; Obtaining a second offset pixel block between the etching contour of each graphic element in the mask pattern of the initial mask and the contour of the corresponding graphic element in the layout to be corrected, so as to compensate for the second contour offset caused by the etching load effect; generating a second corrected layout according to the layout to be corrected and the second offset pixel block; Performing an intersection operation on the first corrected layout and the second corrected layout to obtain a combined corrected layout; Preparing a mask based on the combined corrected layout, and the size of each graphic element in the mask pattern of the mask is within a preset size range.

2. The method according to claim 1, characterized in that, Also including: In the case where the size of each graphic element in the mask pattern of the mask is outside the preset size range, performing supplementary correction on the combined corrected layout based on the etching load effect, and performing an intersection operation on the supplemented combined corrected layout and the first corrected layout to generate a new combined corrected layout; Iterating in this way until the size of each graphic element in the mask pattern of the mask prepared based on the new combined corrected layout is within the preset size range.

3. The method according to claim 1, characterized in that The obtaining of the second offset pixel block between the etching contour of each graphic element in the mask pattern of the initial mask and the contour of the corresponding graphic element in the layout to be corrected includes: Respectively determining the coordinates of the first pixel points of each first graphic element according to the contour of each first graphic element in the layout to be corrected; Respectively determining the coordinates of the second pixel points of each second graphic element according to the etching contour of each second graphic element in the mask pattern of the initial mask; wherein, one first graphic element corresponds to one second graphic element; For each first graphic element, determining the second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point.

4. The method according to claim 3, wherein The for each first graphic element, determining the second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point includes: For each first pixel point on the boundary of each first graphic element in the layout to be corrected, determine a first offset of the etching profile of the second graphic element in a first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; determine a second offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point; Calculate a size of the second offset pixel block in the first direction according to the first offset, the second offset, and a preset gradient value; Taking the first pixel point as a starting pixel point, determine the number of consecutive first pixel points with the same size in the first direction, and determine a size of the second offset pixel block in a second direction based on the number; the first direction intersects the second direction, and the second direction is parallel to the tangent direction of the boundary; Based on the coordinates of the first pixel point, the size of the second offset pixel block in the first direction, and the size of the second direction, determine the area of the second offset pixel block corresponding to the first pixel point; Repeat the operation of determining a first offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; determining a second offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point to determining the area of the second offset pixel block corresponding to the first pixel point based on the coordinates of the first pixel point, the size of the second offset pixel block in the first direction, and the size of the second direction, to determine all the second offset pixel blocks on the boundary, where each of the second offset pixel blocks is adjacent to each other.

5. The method according to claim 4, wherein The calculating a size of the second offset pixel block in the first direction according to the first offset, the second offset, and a preset gradient value includes: When the difference between the first offset and the second offset is less than or equal to the preset gradient value, determine the first offset as the size of the second offset pixel block in the first direction; When the difference between the first offset and the second offset is greater than the preset gradient value, determine the difference between the first offset and the preset gradient value as the size of the second offset pixel block in the first direction.

6. The method according to claim 1, characterized in that, The generating a second corrected layout according to the layout to be corrected and the second offset pixel block includes: Perform an inversion operation on the second offset pixel block with the boundary line in the layout to be corrected adjacent to the second offset pixel block as a symmetry axis to obtain a mirrored second offset pixel block; The difference between the layout to be corrected and each mirrored second offset pixel block of each graphic element is the second corrected layout.

7. A combined correction method for large-scale electron beam proximity effect and etching load effect, characterized in that, including: For each initial layout in the initial layouts with different density distributions, perform the following operations: perform equal grid processing on the initial layout, and determine the point spread function of the energy distribution in the electron beam resist and the initial exposure dose of the electron beam for each grid when performing direct writing exposure of the electron beam resist with a unit dose; Determine a first offset pixel block in the non-patterned area of the initial layout based on the point spread function and the initial exposure dose of the electron beam for each grid, so as to compensate for the first contour offset caused by the electron beam proximity effect; generate a first corrected layout according to the initial layout and the first offset pixel block; For each initial layout in the initial layouts with different density distributions, perform the following operations: sequentially form a light-shielding layer and an electron beam resist on the surface of the mask substrate; perform direct writing exposure and development on the electron beam resist based on the initial layout, and perform etching treatment on the light-shielding layer to obtain an initial mask; Obtain a second offset pixel block between the etching profile of each graphic element in the mask pattern of the initial mask and the profile of the corresponding graphic element in the initial layout, so as to compensate for the second contour offset caused by the etching load effect; generate a second corrected layout according to the initial layout and the second offset pixel block; Perform an intersection process on the first corrected layout and the second corrected layout corresponding to the initial layout with the same density distribution respectively to obtain a plurality of combined corrected layouts; Input the initial layouts with different density distributions and the plurality of combined corrected layouts into the generative adversarial network for multiple iterative trainings until the convergence condition is satisfied to obtain a trained generative adversarial network; Input the layout to be corrected into the trained generative adversarial network and output the target combined corrected layout.

8. A mask, characterized in that, The mask is prepared based on the combined corrected layout, wherein the size of each graphic element in the mask pattern of the mask is within a preset size range, and the combined corrected layout is obtained by using the method according to any one of claims 1-7.

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