Low-power-consumption, small-area and high-PSR full-MOS voltage reference circuit and device

Abstract

The invention relates to a low-power-consumption, small-area and high-PSR full-MOS voltage reference circuit and equipment, a reference current generating circuit and a core reference circuit are designed by adopting a depletion-mode MOS transistor and an enhancement-mode transistor in a circuit process, so that tiny reference current can be generated under a relatively small circuit area; according to the full-MOS voltage reference circuit, the structure design of a full-MOS transistor is adopted on a core circuit structure, the area overhead of the circuit is greatly saved, a power supply voltage preprocessing circuit is designed to provide power supply voltage preprocessing so as to effectively improve the PSR of the full-MOS voltage reference circuit, and the full-MOS voltage reference circuit has the advantages of being low in power consumption, small in area and high in PSR. And finally, the aim of designing the voltage reference circuit with low power consumption, small area and high PSR is fulfilled.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuit design, and relates to a full MOS voltage reference circuit and equipment with low power consumption, small area and high PSR. Background Art

[0002] A voltage reference source is a voltage reference source with a low temperature coefficient obtained by linearly superimposing different temperature characteristics between devices. The reference voltage it generates can remain as stable and accurate as possible in the presence of influencing factors such as process deviations, operating temperature and operating voltage fluctuations, thereby ensuring the circuit reliability and accuracy of the electronic equipment to which it is applied.

[0003] The circuits of many electronic devices need to be compared with a fixed reference voltage. At present, most voltage reference sources use a bandgap reference structure to achieve this function. Although the circuit stability of traditional bandgap voltage reference sources is generally good and can output reference voltages that are less affected by process, power supply voltage and temperature changes, in order to achieve low-power design, very large resistors are often required, which undoubtedly increases the circuit area and cost, and is not conducive to integration. In addition, the PSR (Power Supply Rejection Ratio) of traditional bandgap voltage reference sources is not high and is easily affected by power supply voltage fluctuations. Therefore, how to achieve a voltage reference circuit design with low power consumption, small area and high PSR has become a technical problem to be solved. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a low-power, small-area, high-PSR full-MOS voltage reference circuit and an electronic device, which can realize the design of a low-power, small-area, high-PSR voltage reference circuit.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a low-power, small-area, high-PSR full-MOS voltage reference circuit and device are provided, including an inverter, a reference current generating circuit, a current biasing circuit, a power supply voltage preprocessing circuit, a core reference circuit, a power switch circuit, and a filtering circuit; The enable control terminals of the reference current generating circuit, the power switch circuit, the power voltage preprocessing circuit and the core reference circuit are all used to access the enable signal, the input terminal of the inverter is used to access the enable signal, the output terminal of the inverter is respectively connected to the auxiliary enable control terminals of the reference current generating circuit and the power switch circuit, the reference current generating circuit is connected to the current bias circuit, the current bias circuit is respectively connected to the core reference circuit and the power voltage preprocessing circuit, the power voltage preprocessing circuit is respectively connected to the power switch circuit and the core reference circuit, and the core reference circuit is connected to the filter circuit; The reference current generating circuit and the core reference circuit are both circuits composed of depletion transistors and enhancement transistors, the current bias circuit, the power supply voltage preprocessing circuit and the power switch circuit are all circuits composed of enhancement transistors, the reference current generating circuit is used to generate a reference current, the current bias circuit is used to copy the reference current to the core reference circuit and the power supply voltage preprocessing circuit respectively, the power supply voltage preprocessing circuit is used to perform power supply voltage preprocessing to increase the PSR of the full MOS voltage reference circuit, the power switch circuit is used to transmit the preprocessed power supply voltage to the core reference circuit, the core reference circuit is used to generate a reference voltage, and the filtering circuit is used to filter the reference voltage and output it.

[0006] On the other hand, an electronic device is also provided, which is equipped with the above-mentioned low-power, small-area, high-PSR full MOS voltage reference circuit.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned low-power, small-area, high-PSR full-MOS voltage reference circuit and equipment adopts depletion-mode MOS transistors and enhancement-mode transistors in circuit technology to design the reference current generating circuit and the core reference circuit, so that it can generate a tiny reference current in a smaller circuit area. The core circuit structure adopts a full-MOS transistor structure design, which greatly saves the circuit area overhead, and designs a power supply voltage preprocessing circuit to provide power supply voltage preprocessing to effectively improve the PSR of the full-MOS voltage reference circuit, so that it has the characteristics of low power consumption, small area and high PSR, and finally achieves the purpose of designing a voltage reference circuit with low power consumption, small area and high PSR. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 The circuit structure diagram of the traditional bandgap voltage reference source; Figure 2 A schematic diagram of a module structure of a full MOS voltage reference circuit with low power consumption, small area and high PSR in one embodiment; Figure 3 A schematic diagram of a module structure of a full MOS voltage reference circuit with low power consumption, small area and high PSR in another embodiment; Figure 4 The figure is a schematic diagram of a specific circuit structure of a full MOS voltage reference circuit with low power consumption, small area and high PSR in one embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] The circuit of the traditional bandgap voltage reference source is as follows Figure 1 As shown, it mainly includes operational amplifier OP1, transistor Q1, transistor Q2, transistor Q3, resistor R01, resistor R02, transistor M01, transistor M02 and transistor M03. The reference voltage output by the bandgap voltage reference source is VREF. Among them, transistor Q1, transistor Q2 and transistor Q3 are key components in the circuit. They usually work at different current densities and use the relationship between the base-emitter voltage (VBE) and temperature of the transistor to generate a bandgap reference voltage. Among them, transistor Q1 and transistor Q2 form a basic current mirror structure for generating a positive temperature coefficient voltage. The positive temperature coefficient voltage generates a positive temperature coefficient current on the resistor R01. The positive temperature coefficient current is copied to the output stage through the above transistor M02, thereby generating a positive temperature voltage on the resistor R02 and a negative temperature voltage on the transistor Q3. By reasonably selecting the resistance values ​​of resistors R01 and R02, the size and temperature coefficient of the output reference voltage can be adjusted.

[0014] The operational amplifier OP1 plays a clamping role in the circuit through feedback control, making the positive and negative input voltages approximately equal. Its input terminal is connected to the emitter of transistor Q1 and one end of resistor R01, and its output terminal is connected to the gates of transistors M01, M02 and M03. Through the negative feedback mechanism, the operational amplifier OP1 ensures that the base voltages of transistors Q1 and Q2 are equal, thereby stabilizing the current and voltage relationship in the circuit and improving the accuracy and stability of the reference voltage. Transistor M01, transistor M02 and transistor M03 form a current mirror structure for copying and mirroring the current in the circuit. The currents of transistors M01 and M02 are equal, and the current of transistor M03 is in a certain proportional relationship with the currents of transistors M01 and M02. Through this current mirror structure, the voltage signal output by the operational amplifier OP1 can be converted into a stable current signal, thereby generating a stable voltage drop on the resistor to achieve the output of the reference voltage. VREF is the output end of the entire circuit and outputs a reference voltage. This reference voltage has a relatively stable characteristic and is not greatly affected by factors such as power supply voltage and temperature. It can be used as a reference voltage for other circuit modules. For example, in circuits such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), it provides an accurate voltage reference to ensure the normal operation and performance of the circuit.

[0015] PSR is used to measure the voltage reference source's ability to resist interference from power supply voltage changes. It is defined as the ratio of the change in input voltage to the change in output reference voltage, expressed in decibels (dB). The higher the PSR, the less the voltage reference source is affected by power supply voltage fluctuations, and the more stable the output voltage is. Conversely, the lower the PSR, the easier it is for power supply voltage changes to be transmitted to the output, resulting in greater fluctuations in the output reference voltage. However, the above-mentioned traditional bandgap voltage reference source circuit is still difficult to achieve low power consumption, small area, and high PSR. Therefore, a new circuit design is proposed in this manual to achieve this goal.

[0016] In one embodiment, Figure 2As shown, a full MOS voltage reference circuit with low power consumption, small area and high PSR is provided, including an inverter INV, a reference current generating circuit 12, a current bias circuit 14, a power supply voltage preprocessing circuit 16, a core reference circuit 18, a power switch circuit 20 and a filter circuit 22. The enable control terminals of the reference current generating circuit 12, the power switch circuit 20, the power supply voltage preprocessing circuit 16 and the core reference circuit 18 are all used to access the enable signal. The input terminal of the inverter INV is used to access the enable signal, and the output terminal of the inverter INV is respectively connected to the sub-enable control terminals of the reference current generating circuit 12 and the power switch circuit 20. The reference current generating circuit 12 is connected to the current bias circuit 14, the current bias circuit 14 is respectively connected to the core reference circuit 18 and the power supply voltage preprocessing circuit 16, the power supply voltage preprocessing circuit 16 is respectively connected to the power switch circuit 20 and the core reference circuit 18, and the core reference circuit 18 is connected to the filter circuit 22.

[0017] The reference current generating circuit 12 and the core reference circuit 18 are both circuits composed of depletion transistors and enhancement transistors, the current bias circuit 14, the power supply voltage preprocessing circuit 16 and the power switch circuit 20 are all circuits composed of enhancement transistors, the reference current generating circuit 12 is used to generate a reference current, the current bias circuit 14 is used to copy the reference current to the core reference circuit 18 and the power supply voltage preprocessing circuit 16 respectively, the power supply voltage preprocessing circuit 16 is used to perform power supply voltage preprocessing to increase the PSR of the full MOS voltage reference circuit, the power switch circuit 20 is used to transmit the preprocessed power supply voltage to the core reference circuit 18, the core reference circuit 18 is used to generate a reference voltage, and the filter circuit 22 is used to filter the reference voltage and output it.

[0018] It can be understood that the enable signal, namely EN, is one of the input signals of the above-mentioned full MOS voltage reference circuit, and is used to realize the enable control of the circuit. The secondary enable control terminal of the power switch circuit 20 is another enable control terminal relative to the enable control terminal of the power switch circuit 20 (i.e., the terminal connected to the enable signal EN), which is controlled by the enable signal ENB output by the inverter INV, and jointly realizes the on-off control of the power switch circuit 20. The circuit states of the reference current generating circuit 12, the power switch circuit 20 and the power supply voltage preprocessing circuit 16 are controlled by the enable signal EN and the enable signal ENB output by the inverter INV, respectively, to control whether the above-mentioned full MOS voltage reference circuit is working.

[0019] After a tiny reference current is generated by the reference current generating circuit 12, the reference current is copied and transmitted to the core reference circuit 18 and the power supply voltage preprocessing circuit 16 through the current bias circuit 14. The power supply voltage (VDD) is preprocessed in the power supply voltage preprocessing circuit 16. For example, after the power supply voltage is divided by the power supply voltage preprocessing circuit 16, the power supply voltage is subjected to voltage division adjustment in the process of being converted to the core reference circuit to adjust the ratio of the change in the power supply voltage to the change in the output reference voltage, thereby improving the PSR of the full MOS voltage reference circuit. The preprocessed power supply voltage is then transferred to the core reference circuit 18, which generates a reference voltage based on the input reference current and the preprocessed power supply voltage. The reference voltage is finally filtered by the filter circuit 22 to output an accurate and stable reference voltage.

[0020] It should be noted that those skilled in the art can use depletion-mode transistors and enhancement-mode transistors according to the functions of the above-mentioned module circuits, combined with inverter INV, resistors and capacitor devices according to the circuit layout design rules of this field, and adopt a variety of different specific circuit structure designs for specific implementation, as long as the functions of the above-mentioned module circuits can be realized based on the above-mentioned design concepts.

[0021] The above-mentioned low-power, small-area, high-PSR full MOS voltage reference circuit uses depletion-mode MOS transistors and enhancement-mode transistors in circuit technology to design the reference current generating circuit 12 and the core reference circuit 18, so that it can generate a tiny reference current in a smaller circuit area. The core circuit structure adopts a full MOS transistor structure design, which greatly saves the circuit area overhead, and designs a power supply voltage preprocessing circuit 16 to provide power supply voltage preprocessing to effectively improve the PSR of the full MOS voltage reference circuit, so that it has the characteristics of low power consumption, small area and high PSR, and finally achieves the purpose of designing a voltage reference circuit with low power consumption, small area and high PSR.

[0022] In one embodiment, Figure 3 As shown, the reference current generating circuit 12 includes a mirror unit, a switch unit and a proportional unit. The input end of the mirror unit is used to access the power supply voltage, the output end of the mirror unit is connected to the input end of the proportional unit through the switch unit, and the output end of the proportional unit is grounded. The mirror unit is used to generate a reference current, the switch unit is used to control the on-off between the mirror unit and the proportional unit, and the proportional unit is used for current proportional control.

[0023] It can be understood that the mirror unit is a main circuit unit designed with enhancement transistors and used to generate a reference current, the proportional unit is a circuit unit designed with depletion transistors and used to cooperate with the mirror unit to generate a small reference current of the required size, and the switch unit is a circuit unit used to control whether the reference current generating circuit 12 works under the control of an enable signal, and can be designed using a pair of enhancement PMOS transistors and enhancement NMOS transistors. The mirror unit and the proportional unit can adopt various types of existing mirror circuit structures in the art, wherein the proportional unit can accurately control the size and bias conditions of the depletion transistors so that the current in its series structure is in a certain proportional relationship with the current of other branches to meet the generation needs of the required size of the reference current. Therefore, the specific number of depletion transistors connected in series with the proportional unit can be selected according to the generation needs of the reference current.

[0024] Through the structural design of the mirror unit, the switch unit and the proportional unit, the reference current required in a specific application scenario can be accurately controlled in a smaller circuit area.

[0025] In one embodiment, Figure 4 As shown, the proportional unit includes transistors M1, M2, M3, M4, M5, M6, M7 and M8, all of which have their gates grounded and are connected in series in sequence, and the sources of transistors M1 to M8 are grounded respectively. The switch unit includes transistors M9 and M10, the drain of transistor M9 and the source of transistor M10 are both connected to the drain of transistor M8, the source of transistor M10 is grounded, the gate of transistor M9 is used to access an enable signal, the source of transistor M9 is used to access a power supply voltage, and the gate of transistor M10 is connected to the output end of the inverter INV.

[0026] The mirror unit includes a transistor M11, a transistor M12 and a resistor R1. One end of the resistor R1 is respectively connected to the source of the transistor M9, the drain of the transistor M10 and the gate of the transistor M11, the source of the transistor M11 is used to access the power supply voltage, the drain of the transistor M11 is respectively connected to the gate of the transistor M12 and the other end of the resistor R1, the gate of the transistor M11 and the gate of the transistor M12 are respectively connected to the current bias circuit 14, the drain of the transistor M12 is connected to the source of the transistor M11, and the source of the transistor M12 is used to access the power supply voltage. The transistors M1 to M8 are all depletion-type NMOS transistors, the transistors M9, M11 and M12 are all enhancement-type PMOS transistors, and the transistor M10 is all enhancement-type NMOS transistors.

[0027] It can be understood that in this embodiment, the following is provided: Figure 4A specific reference current generating circuit 12 structure is shown in the figure, in which a depletion-type MOS tube and a full MOS tube design are used, and a large resistor is no longer required to generate the required tiny reference current with low power consumption.

[0028] Among them, in the switch unit, for example, when the enable signal EN is at a high level and the enable signal ENB is at a low level, the transistor M9 is turned on, the transistor M10 is turned off, and the power supply voltage VDD is effectively connected to realize the power on; conversely, when the enable signal EN is at a low level and the enable signal ENB is at a high level, the transistor M9 is turned off, the transistor M10 is turned on, and the power supply voltage VDD is disconnected to realize the power off. By controlling the on and off of the power supply through this circuit, the power supply of the circuit module can be turned off when it does not need to work, so as to reduce the overall power consumption of the system.

[0029] In one embodiment, Figure 4 As shown, the current bias circuit 14 includes a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22 and a resistor R2. The sources of the transistors M13, M19 and M21 are all used to access the power supply voltage, the gates of the transistors M13, M19 and M21 are all connected to the reference current generating circuit 12, the gates of the transistors M14, M20 and M22 are all connected to the reference current generating circuit 12, the source of the transistor M14 is connected to the drain of the transistor M13 and is used to access the power supply voltage, the source of the transistor M20 is connected to the drain of the transistor M19 and is used to access the power supply voltage, the drain of the transistor M20 is connected to the core reference circuit 18, the source of the transistor M22 is connected to the drain of the transistor M21 and is used to access the power supply voltage, and the drain of the transistor M22 is connected to the power supply voltage preprocessing circuit 16.

[0030] One end of the resistor R2 is respectively connected to the drain of the transistor M14, the gate of the transistor M15 and the gate of the transistor M17, the other end of the resistor R2 is respectively connected to the drain of the transistor M15, the gate of the transistor M16 and the gate of the transistor M18, the source of the transistor M15 is connected to the drain of the transistor M16 and grounded, the source of the transistor M17 is connected to the drain of the transistor M18 and grounded, the source of the transistor M16 and the source of the transistor M18 are both grounded, and the drain of the transistor M17 is connected to the core reference circuit 18. The transistors M13 to M14 and the transistors M19 to M22 are all enhancement type PMOS transistors, and the transistors M15 to M18 are all enhancement type NMOS transistors.

[0031] It can be understood that in this embodiment, the following is provided: Figure 4A specific current bias circuit 14 structure is shown in the figure, which adopts a design using all MOS tubes, and no longer requires large resistors to achieve accurate replication and transmission of low-power reference current, and greatly reduces the circuit area occupied.

[0032] In one embodiment, Figure 4 As shown, the power supply voltage preprocessing circuit 16 includes a transistor M23, a transistor M24, a transistor M25, a transistor M26 and a transistor M27. The transistor M23 and the transistor M24 are enhanced PMOS transistors, and the transistors M25 to M27 are enhanced NMOS transistors. The source of the transistor M23 is respectively connected to the gate of the transistor M27 and the drain of the transistor M22, the source of the transistor M23 is used to access the power supply voltage, the source of the transistor M24 is connected to the drain of the transistor M23 and is used to access the power supply voltage, the gate of the transistor M23 is connected to the drain of the transistor M26, the source of the transistor M26 is grounded, and the gate of the transistor M26 is used to access the enable signal. The drain of transistor M24 is grounded, the gate of transistor M24 is respectively connected to the drain of transistor M25 and the core reference circuit 18, the source of transistor M25 is grounded, the gate of transistor M25 is used to access the enable signal, the drain of transistor M27 is connected to the power switch circuit 20, and the source of transistor M27 is connected to the core reference circuit 18 and grounded.

[0033] It can be understood that in this embodiment, the following is provided: Figure 4 A specific power supply voltage preprocessing circuit 16 structure shown in the figure adopts a design using all MOS transistors, which can efficiently provide the required power supply voltage preprocessing and greatly reduce the circuit area occupied by it. The power supply voltage is divided by transistors M21, M22, M23 and M24, and is output from the source level of transistor M23 through the gate of transistor M27 minus the gate-source voltage Vgs of transistor M27, and is output from the source level of transistor M27 to supply power to transistor M31. The power supply is divided during the process of being converted to the core reference circuit 18, thereby adjusting the ratio of the change of the power supply voltage to the change of the output reference voltage, thereby improving the PSR of the full MOS voltage reference circuit.

[0034] In one embodiment, Figure 4 As shown, the power switch circuit 20 includes an enhancement type PMOS transistor M28 and an enhancement type NMOS transistor M29. The source of the transistor M28 is used to access the power supply voltage, the gate of the transistor M28 is used to access the enable signal, the drain of the transistor M28 is connected to the drain of the transistor M27, the drain of the transistor M29 is used to access the power supply voltage, the gate of the transistor M29 is connected to the output end of the inverter INV, and the source of the transistor M29 is connected to the drain of the transistor M27 and grounded.

[0035] It can be understood that in this embodiment, the specific circuit structure of the power switch circuit 20 can adopt the same circuit structure as the switch unit, so as to effectively realize the on-off control between the core reference circuit 18 and the power supply voltage. At the same time, the circuit design complexity can be reduced by reusing the circuit structure, and the circuit area occupied by the full MOS tube design can be reduced.

[0036] In one embodiment, Figure 4 As shown, the core reference circuit 18 includes a transistor M30, a transistor M31, and a transistor M32, all of which are enhancement type NMOS transistors. The gate of the transistor M30 is respectively connected to the gate of the transistor M31, the drain of the transistor M32, and the drain of the transistor M30, the drain of the transistor M30 is connected to the drain of the transistor M20, and the source of the transistor M30 is grounded. The drain of the transistor M31 is connected to the source of the transistor M27, the source of the transistor M31 is respectively connected to the gate of the transistor M24, the filter circuit 22, and the drain of the transistor M17 and is grounded, the gate of the transistor M32 is used to access the enable signal, and the source of the transistor M32 is grounded.

[0037] It can be understood that in this embodiment, the following is provided: Figure 4 A specific core reference circuit 18 structure is shown in the figure, which adopts a design using all MOS tubes, which can accurately output the reference voltage before filtering while greatly reducing the circuit area it occupies, supporting low power consumption operation.

[0038] In one embodiment, Figure 4 As shown, the filter circuit 22 includes a resistor R3 and a capacitor C1. One end of the resistor R3 is used to output a filtered reference voltage (VREF), the other end of the resistor R3 is respectively connected to one end of the capacitor C1 and the source of the transistor M31, and the other end of the capacitor C1 is grounded.

[0039] It can be understood that in this embodiment, the following is provided: Figure 4 A specific filter circuit 22 structure is shown in , which adopts the simplest filter design, can accurately filter out the clutter in the reference voltage and achieve stable and accurate reference voltage output.

[0040] In one embodiment, an electronic device is also provided, equipped with the above-mentioned low-power, small-area, high-PSR full MOS voltage reference circuit.

[0041] It can be understood that the electronic devices in this embodiment can be, but are not limited to, automotive sensors such as (sensors for measuring parameters such as vehicle speed, tire pressure, and oil temperature), vehicle-mounted electronic devices (such as navigation systems, vehicle-mounted entertainment systems, and other equipment), smart phones, smart wearable devices (such as smart watches, bracelets, etc.), smart meters (such as smart electric meters, water meters, and gas meters, etc.), and portable medical instruments (such as portable blood glucose meters, blood pressure meters, etc.). In these electronic devices, the above-mentioned low-power, small-area, high-PSR full-MOS voltage reference circuit can be used to improve the accurate and stable reference voltage source to ensure the stable operation, precise measurement and control of the equipment. In these electronic devices, it is only necessary to replace the original reference circuit module with a relatively large circuit area with the above-mentioned low-power, small-area, high-PSR full-MOS voltage reference circuit to obtain a higher-performance reference voltage source.

[0042] The above-mentioned electronic device, by applying the above-mentioned low-power, small-area, high-PSR full MOS voltage reference circuit, can effectively save the circuit board area of ​​the device while reducing the power consumption of the device and improving the reference voltage stability of the device.

[0043] It can be understood that the explanation of the low-power, small-area, high-PSR full MOS voltage reference circuit in the above-mentioned electronic device can be understood by referring to the corresponding explanations of the various embodiments of the above-mentioned low-power, small-area, high-PSR full MOS voltage reference circuit, and will not be repeated here.

[0044] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A low power consumption, small area, high PSR full MOS voltage reference circuit, characterized in that: It includes an inverter, a reference current generating circuit, a current biasing circuit, a power supply voltage preprocessing circuit, a core reference circuit, a power supply switching circuit and a filtering circuit; The enable control terminals of the reference current generating circuit, the power switch circuit, the power voltage preprocessing circuit and the core reference circuit are all used to access the enable signal, the input terminal of the inverter is used to access the enable signal, the output terminal of the inverter is respectively connected to the reference current generating circuit and the secondary enable control terminal of the power switch circuit, the reference current generating circuit is connected to the current bias circuit, the current bias circuit is respectively connected to the core reference circuit and the power voltage preprocessing circuit, the power voltage preprocessing circuit is respectively connected to the power switch circuit and the core reference circuit, and the core reference circuit is connected to the filter circuit; The reference current generating circuit and the core reference circuit are both circuits composed of depletion transistors and enhancement transistors, the current bias circuit, the power supply voltage preprocessing circuit and the power switch circuit are all circuits composed of enhancement transistors, the reference current generating circuit is used to generate a reference current, the current bias circuit is used to copy the reference current to the core reference circuit and the power supply voltage preprocessing circuit respectively, the power supply voltage preprocessing circuit is used to perform power supply voltage preprocessing to increase the PSR of the full MOS voltage reference circuit, the power switch circuit is used to transmit the preprocessed power supply voltage to the core reference circuit, the core reference circuit is used to generate a reference voltage, and the filtering circuit is used to filter the reference voltage and output it.

2. The low-power, small-area, high-PSR full-MOS voltage reference circuit according to claim 1, characterized in that: The reference current generating circuit comprises a mirror unit, a switch unit and a proportional unit, wherein the input end of the mirror unit is used to access the power supply voltage, the output end of the mirror unit is connected to the input end of the proportional unit through the switch unit, and the output end of the proportional unit is grounded; The mirror unit is used to generate a reference current, the switch unit is used to control the on-off between the mirror unit and the proportional unit, and the proportional unit is used for current proportional control.

3. The low-power, small-area, high-PSR full-MOS voltage reference circuit according to claim 2, characterized in that: The proportional unit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7 and a transistor M8, the gates of which are all grounded and connected in series in sequence, and the sources of the transistors M1 to M8 are grounded respectively; The switch unit includes a transistor M9 and a transistor M10, the drain of the transistor M9 and the source of the transistor M10 are both connected to the drain of the transistor M8, the source of the transistor M10 is grounded, the gate of the transistor M9 is used to access the enable signal, the source of the transistor M9 is used to access the power supply voltage, and the gate of the transistor M10 is connected to the output end of the inverter; The mirror unit includes a transistor M11, a transistor M12 and a resistor R1, one end of the resistor R1 is respectively connected to the source of the transistor M9, the drain of the transistor M10 and the gate of the transistor M11, the source of the transistor M11 is used to access the power supply voltage, the drain of the transistor M11 is respectively connected to the gate of the transistor M12 and the other end of the resistor R1, the gate of the transistor M11 and the gate of the transistor M12 are respectively connected to the current bias circuit, the drain of the transistor M12 is connected to the source of the transistor M11, and the source of the transistor M12 is used to access the power supply voltage; The transistors M1 to M8 are all depletion-type NMOS transistors, the transistors M9, M11 and M12 are all enhancement-type PMOS transistors, and the transistor M10 is an enhancement-type NMOS transistor.

4. The low-power, small-area, high-PSR full MOS voltage reference circuit according to any one of claims 1 to 3, characterized in that: The current bias circuit includes a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22 and a resistor R2; The sources of the transistor M13, the transistor M19 and the transistor M21 are all used to access the power supply voltage, the gates of the transistor M13, the transistor M19 and the transistor M21 are all connected to the reference current generating circuit, the gates of the transistor M14, the transistor M20 and the transistor M22 are all connected to the reference current generating circuit, the source of the transistor M14 is connected to the drain of the transistor M13 and is used to access the power supply voltage, the source of the transistor M20 is connected to the drain of the transistor M19 and is used to access the power supply voltage, the drain of the transistor M20 is connected to the core reference circuit, the source of the transistor M22 is connected to the drain of the transistor M21 and is used to access the power supply voltage, and the drain of the transistor M22 is connected to the power supply voltage preprocessing circuit; One end of the resistor R2 is respectively connected to the drain of the transistor M14, the gate of the transistor M15 and the gate of the transistor M17, the other end of the resistor R2 is respectively connected to the drain of the transistor M15, the gate of the transistor M16 and the gate of the transistor M18, the source of the transistor M15 is connected to the drain of the transistor M16 and is grounded, the source of the transistor M17 is connected to the drain of the transistor M18 and is grounded, the source of the transistor M16 and the source of the transistor M18 are both grounded, and the drain of the transistor M17 is connected to the core reference circuit; The transistors M13 to M14 and the transistors M19 to M22 are all enhancement-type PMOS transistors, and the transistors M15 to M18 are all enhancement-type NMOS transistors.

5. The low-power, small-area, high-PSR full-MOS voltage reference circuit according to claim 4, characterized in that: The power supply voltage preprocessing circuit includes a transistor M23, a transistor M24, a transistor M25, a transistor M26 and a transistor M27, wherein the transistor M23 and the transistor M24 are enhanced PMOS transistors, and the transistors M25 to M27 are enhanced NMOS transistors; The source of the transistor M23 is respectively connected to the gate of the transistor M27 and the drain of the transistor M22, the source of the transistor M23 is used to access the power supply voltage, the source of the transistor M24 is connected to the drain of the transistor M23 and is used to access the power supply voltage, the gate of the transistor M23 is connected to the drain of the transistor M26, the source of the transistor M26 is grounded, and the gate of the transistor M26 is used to access the enable signal; The drain of the transistor M24 is grounded, the gate of the transistor M24 is respectively connected to the drain of the transistor M25 and the core reference circuit, the source of the transistor M25 is grounded, the gate of the transistor M25 is used to access the enable signal, the drain of the transistor M27 is connected to the power switch circuit, and the source of the transistor M27 is connected to the core reference circuit and grounded.

6. The low-power, small-area, high-PSR full MOS voltage reference circuit according to claim 5, characterized in that: The power switch circuit includes an enhancement type PMOS transistor M28 and an enhancement type NMOS transistor M29, the source of the transistor M28 is used to access the power supply voltage, the gate of the transistor M28 is used to access the enable signal, the drain of the transistor M28 is connected to the drain of the transistor M27, the drain of the transistor M29 is used to access the power supply voltage, the gate of the transistor M29 is connected to the output end of the inverter, and the source of the transistor M29 is connected to the drain of the transistor M27 and grounded.

7. The low-power, small-area, high-PSR full-MOS voltage reference circuit according to claim 5, characterized in that: The core reference circuit includes a transistor M30, a transistor M31 and a transistor M32, all of which are enhancement-type NMOS transistors, the gate of the transistor M30 is respectively connected to the gate of the transistor M31, the drain of the transistor M32 and the drain of the transistor M30, the drain of the transistor M30 is connected to the drain of the transistor M20, and the source of the transistor M30 is grounded; The drain of the transistor M31 is connected to the source of the transistor M27, the source of the transistor M31 is respectively connected to the gate of the transistor M24, the filter circuit, the drain of the transistor M17 and grounded, the gate of the transistor M32 is used to access the enable signal, and the source of the transistor M32 is grounded.

8. The low-power, small-area, high-PSR full-MOS voltage reference circuit according to claim 7, characterized in that: The filter circuit includes a resistor R3 and a capacitor C1, one end of the resistor R3 is used to output the filtered reference voltage, the other end of the resistor R3 is respectively connected to one end of the capacitor C1 and the source of the transistor M31, and the other end of the capacitor C1 is grounded.

9. An electronic device, characterized in that: A full MOS voltage reference circuit with low power consumption, small area and high PSR is provided, comprising: a circuit ...

Images