Band-gap reference circuit

Abstract

The invention provides a band-gap reference circuit, which comprises a bias voltage generating unit, a reference current generating unit and a reference current generating unit, the reference voltage generating unit comprises a first branch circuit and a second branch circuit which have different starting voltages, and the first branch circuit receives the first voltage; the current mirror unit enables currents on the first branch circuit and the second branch circuit to be equal in magnitude; the reference voltage generating unit generates band-gap reference voltage on the second branch according to the first voltage and the difference between the turn-on voltages of the first branch and the second branch. According to the scheme, the circuit of the N-type PMOS device is used for replacing a circuit which needs to use a plurality of BJT devices, so that the circuit area is greatly reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a bandgap reference circuit. Background Art

[0002] A bandgap voltage reference, also known as a bandgap reference circuit, is a voltage reference circuit widely used in integrated circuits. It generates a fixed voltage that is independent of power supply changes, temperature changes, and circuit loads. The so-called bandgap, also known as the energy gap, refers to the energy difference between the lowest point of the conduction band and the highest point of the valence band of a semiconductor or insulator. Bandgap reference circuits play a vital role in the design of integrated circuits such as lithium battery protection chips, LED driver chips, linear regulators (LDOs), power management chips, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), dynamic memory (DRAM), and Flash memory.

[0003] The traditional bandgap reference circuit requires at least two BJTs (bipolar transistors), which are located in two branches. In the standard CMOS process, since BJTs occupy a large area, the area of ​​the bandgap reference circuit based on BJTs is usually large, for example, it can reach several thousand to tens of thousands of square microns, which is not conducive to the miniaturization trend of chip circuits. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a bandgap reference circuit, which aims to simplify the structure of the bandgap reference circuit to greatly reduce the circuit area.

[0005] According to a first aspect of the present application, a bandgap reference circuit is provided, comprising:

[0006] A bias voltage generating unit generates a bias voltage according to a reference current;

[0007] A reference voltage generating unit, comprising a first branch and a second branch, wherein the first branch and the second branch respectively generate a first branch current and a second branch current according to the bias voltage when the first branch and the second branch are turned on;

[0008] a current mirror unit, connected to the first branch and the second branch respectively, to balance the first branch current and the second branch current so that the first branch current and the second branch current are equal in magnitude;

[0009] The first branch and the second branch have different turn-on voltages, the first branch receives a first voltage, and the reference voltage generating unit generates a bandgap reference voltage on the second branch according to the first voltage and a difference between the turn-on voltages of the first branch and the second branch.

[0010] Optionally, the reference voltage generating unit includes:

[0011] A first field effect transistor located on the first branch and a second field effect transistor located on the second branch;

[0012] The threshold voltage of the first field effect transistor is the turn-on voltage of the first branch;

[0013] The threshold voltage of the second field effect transistor is a turn-on voltage of the second branch.

[0014] Optionally, the gate of the first field effect transistor receives the first voltage, the gate of the second field effect transistor is connected to the second transmission electrode of the second field effect transistor, and the reference voltage generating unit generates the bandgap reference voltage at the gate of the second field effect transistor.

[0015] Optionally, the first field effect transistor and the second field effect transistor operate in a saturation region.

[0016] Optionally, a threshold voltage of the first field effect transistor is lower than a threshold voltage of the second field effect transistor.

[0017] Optionally, the first field effect transistor and the second field effect transistor have the same size.

[0018] Optionally, the first field effect transistor and the second field effect transistor are both enhancement mode PMOS transistors;

[0019] The gate of the first field effect transistor includes N-type polysilicon formed by using N-type ion implantation.

[0020] Optionally, the bias voltage generating unit includes:

[0021] a third field effect transistor and a fourth field effect transistor, wherein the gate of the third field effect transistor is connected to the second transmission electrode of the third field effect transistor and the gate of the fourth field effect transistor to form a current mirror structure;

[0022] The substrate and the first transmission electrode of the third field effect transistor are connected to the power supply terminal, and the second transmission electrode of the third field effect transistor receives the reference current;

[0023] The substrate and the first transmission electrode of the fourth field effect transistor are connected to the power supply terminal, and the second transmission electrode of the fourth field effect transistor outputs the reference voltage.

[0024] Optionally, the third field effect transistor and the fourth field effect transistor are P-type field effect transistors.

[0025] Optionally, the current mirror unit includes:

[0026] a fifth field effect transistor and a sixth field effect transistor, wherein a gate of the fifth field effect transistor is connected to a first transmission electrode of the fifth field effect transistor and a gate of the sixth field effect transistor to form a current mirror structure;

[0027] a seventh field effect transistor and an eighth field effect transistor, wherein a gate of the seventh field effect transistor is connected to a second transmission electrode of the seventh field effect transistor and a gate of the eighth field effect transistor to form a current mirror structure;

[0028] The fifth field effect transistor and the seventh field effect transistor are connected in series on the first branch, and the sixth field effect transistor and the eighth field effect transistor are connected in series on the second branch;

[0029] Substrates of the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, and the eighth field effect transistor are all connected to a reference ground.

[0030] Optionally, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are N-type field effect transistors.

[0031] The beneficial effects of this application include at least:

[0032] The embodiment of the present application utilizes a structure including a bias voltage generating unit, a reference voltage generating unit and a current mirror unit to construct a bandgap reference circuit. Compared with the existing scheme, the bandgap reference circuit disclosed in the present application mainly provides a bias voltage to the reference voltage generating unit through the bias voltage generating unit to power the reference voltage generating unit, and provides two equal currents to the two branches of the reference voltage generating unit through the current mirror unit, so that the reference voltage generating unit generates a bandgap reference voltage according to the difference between the start-up voltages of its two branches. The circuit has a simple structure and occupies a smaller area.

[0033] In a further preferred embodiment, the present application scheme adopts field effect transistor devices to construct a reference voltage generating unit. Compared with the existing scheme using BJT (bipolar junction transistor) devices, the field effect transistor devices have a smaller area and can greatly reduce the circuit area.

[0034] In a further preferred embodiment, the present application scheme further adopts an enhancement PMOS transistor device to construct a reference voltage generating unit, and sets the gate of one of the enhancement PMOS transistor devices to be N-type polysilicon formed by N-type ion implantation, so that the two field effect transistors in the reference voltage generating unit can have the same device size while having different threshold voltages, which is conducive to further reducing the circuit area.

[0035] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of an implementation of a bandgap reference circuit provided according to an embodiment of the present application is shown;

[0037] Figure 2 Show Figure 1 Schematic diagram of the device structure of a field effect transistor in the reference voltage generating unit. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0039] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0040] In the description of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. Herein, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the differences.

[0041] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0042] Figure 1 FIG. 1 shows a schematic diagram of an implementation of a bandgap reference circuit provided in an embodiment of the present application, referring to FIG. Figure 1 In this embodiment, the bandgap reference circuit includes: a bias voltage generating unit 110, a reference voltage generating unit 120 and a current mirror unit 130. The bias voltage generating unit 110 is connected to the reference voltage generating unit 120, and the current mirror unit 130 is connected to the reference voltage generating unit 120.

[0043] The bias voltage generating unit 110 is used to generate a bias voltage according to a reference current (referred to as Iin); the reference voltage generating unit 120 includes a first branch and a second branch, and the reference voltage generating unit 120 is used to generate a first branch current (referred to as I1) and a second branch current (referred to as I2) respectively according to the bias voltage provided by the bias voltage generating unit 110 when the first branch and the second branch are turned on; the current mirror unit 130 is respectively connected to the first branch and the second branch of the reference voltage generating unit 120, and is used to balance the first branch current I1 and the second branch current I2, so that the first branch current I1 and the second branch current I1 are equal (or approximately equal) in magnitude. Among them, the first branch and the second branch of the reference voltage generating unit 120 have different turn-on voltages, the first branch receives a first voltage (referred to as V1), and the reference voltage generating unit 120 generates a bandgap reference voltage (referred to as Vref) on the second branch according to the first voltage V1 and the difference between the turn-on voltages of the first branch and the second branch. In the embodiment of the present application, the bandgap reference circuit constructed by using the aforementioned bias voltage generating unit 110, the reference voltage generating unit 120 and the current mirror unit 130 has a relatively simple circuit structure and occupies a smaller area.

[0044] It should be noted that in the present application, the first branch current I1 and the second branch current I2 only need to be equal in a broad sense, that is, as long as the difference between the first branch current I1 and the second branch current I2 is within the allowable error range, it is also deemed that the first branch current I1 and the second branch current I2 are equal in magnitude, and this situation is also within the protection scope of the present application.

[0045] During specific implementation, in some embodiments, the bias voltage generating unit 110 generates a bias voltage corresponding to the reference current Iin by replicating the reference current Iin, thereby supplying power to the reference voltage generating unit 120 .

[0046] exist Figure 1 In the illustrated embodiment, the bias voltage generating unit 110 includes: a field effect transistor PM1 and a field effect transistor PM2, wherein the gate of the field effect transistor PM1 is connected to the second transmission electrode (such as the drain electrode) of the field effect transistor PM1 and the gate of the field effect transistor PM2, and the field effect transistor PM1 and the field effect transistor PM2 form a current mirror structure. Further, the substrate and the first transmission electrode (such as the source electrode) of the field effect transistor PM1 are both connected to the power supply terminal VDD, the second transmission electrode of the field effect transistor PM1 receives the reference current Iin, the substrate and the first transmission electrode (such as the source electrode) of the field effect transistor PM2 are both connected to the power supply terminal VDD, and the second transmission electrode (such as the drain electrode) of the field effect transistor PM2 outputs the reference voltage.

[0047] Optionally, in some embodiments, the field effect transistor PM1 and the field effect transistor PM2 are P-type field effect transistors.

[0048] The reference voltage generating unit 120 includes: a field effect transistor PM3 and a field effect transistor PM4, wherein the field effect transistor PM3 is located on the first branch, and the field effect transistor PM4 is located on the second branch. That is to say, the reference voltage generating unit 120 uses the threshold voltage of the field effect transistor PM3 as the turn-on voltage of its first branch, and uses the threshold voltage of the field effect transistor PM4 as the turn-on voltage of its second branch. Furthermore, the reference voltage generating unit 120 uses the difference in the threshold voltages of the field effect transistor PM3 and the field effect transistor PM4 to characterize the different turn-on voltages of the first branch and the second branch.

[0049] Specifically, Figure 1 As shown, the gate of the field effect transistor PM3 receives the first voltage V1, the gate of the field effect transistor PM4 is connected to the second transmission electrode (such as the drain) of the field effect transistor PM4, and the reference voltage generating unit 120 generates a bandgap reference voltage Vref at the gate of the field effect transistor PM4.

[0050] exist Figure 1In the illustrated embodiment, the gate of the field effect transistor PM3 is connected to the reference ground, and at this time, the aforementioned first voltage V1 is equal to the reference ground voltage, such as 0 V. Of course, in some other embodiments, the gate of the field effect transistor PM3 may also be connected to other nodes of the circuit to receive the first voltage V1 having other voltage values.

[0051] In addition, Figure 1 In the illustrated embodiment, the substrate and the first transmission electrode (such as the source) of the field effect transistor PM3, and the substrate and the first transmission electrode (such as the source) of the field effect transistor PM4 are connected to the output end of the bias voltage generating unit 110 (i.e., the second transmission electrode of the field effect transistor PM2) to receive the bias voltage.

[0052] Optionally, in some embodiments, the field effect transistor PM3 and the field effect transistor PM4 are P-type field effect transistors.

[0053] In this embodiment, the threshold voltage of the field effect transistor PM3 is less than the threshold voltage of the field effect transistor PM4, and at this time, the reference voltage generating unit 120 generates a bandgap reference voltage Vref with a positive voltage. Of course, in some other embodiments, the threshold voltage of the field effect transistor PM3 can also be set to be greater than the threshold voltage of the field effect transistor PM4, and accordingly, the reference voltage generating unit 120 will generate a bandgap reference voltage Vref with a negative voltage.

[0054] Optionally, the difference in threshold voltages of the field effect transistor PM3 and the field effect transistor PM4 in the reference voltage generating unit 120 can be achieved by selecting two field effect transistors of different materials, or two field effect transistors with different doping concentrations, or two field effect transistors with different gate structures. It can be understood that, according to the different implementation methods of the difference in threshold voltages of the field effect transistor PM3 and the field effect transistor PM4, the field effect transistor PM3 and the field effect transistor PM4 in the reference voltage generating unit 120 can have different device sizes or the same device size. In some preferred embodiments, it is preferred that the field effect transistor PM3 and the field effect transistor PM4 have the same size so as to further reduce the circuit area.

[0055] For example, both the field effect transistor PM3 and the field effect transistor PM4 are enhancement type PMOS transistors. When the threshold voltage of the field effect transistor PM3 is required to be less than the threshold voltage of the field effect transistor PM4, the field effect transistor PM4 can be set as a normal enhancement type PMOS transistor, and the field effect transistor PM3 is a device formed by performing N-type ion implantation on the gate of the enhancement type PMOS transistor. At this time, the device structure of the field effect transistor PM3 is as follows: Figure 2As shown, it includes: an N-well (NWELL) 210 located between two shallow trench isolation regions (STI) 260 and 270, a first P+ injection region 220 and a second P+ injection region 230 located in the N-well (NWELL) 210, and a gate structure 240 located on the surface of the N-well (NWELL) 210, wherein the gate structure 240 of the field effect transistor PM3 includes an N-type polysilicon 250 formed by using N-type ion implantation. It can be understood that after N-type ion implantation is performed on the gate of a normal enhancement PMOS transistor, the field effect transistor PM3 has a characteristic that its threshold voltage value is about Eg / q smaller than that of an enhancement PMOS transistor of the same size, wherein Eg represents the bandgap width of silicon, and q represents the amount of electron charge, that is, about 1.12V at room temperature.

[0056] Similarly, when the threshold voltage of the field effect transistor PM3 is required to be greater than the threshold voltage of the field effect transistor PM4, the field effect transistor PM3 can be set to be a normal enhancement type PMOS transistor, and the field effect transistor PM4 is a device formed by performing N-type ion implantation on the gate of the enhancement type PMOS transistor. At this time, the device structure of the field effect transistor PM4 is as follows: Figure 2 shown.

[0057] Continue to refer Figure 1 In this embodiment, the current mirror unit 130 includes: a field effect transistor NM1, a field effect transistor NM2, a field effect transistor NM3 and a field effect transistor NM4, wherein the gate of the field effect transistor NM1 is connected to the first transmission electrode of the field effect transistor NM1 and the gate of the field effect transistor NM2, and the field effect transistor NM1 and the field effect transistor NM2 form a current mirror structure; the gate of the field effect transistor NM3 is connected to the second transmission electrode of the field effect transistor NM3 and the gate of the field effect transistor NM4, and the field effect transistor NM3 and the field effect transistor NM4 form a current mirror structure; the field effect transistor NM1 and the field effect transistor NM3 are connected in series on the first branch, and the field effect transistor NM2 and the field effect transistor NM4 are connected in series on the second branch; the substrates of the field effect transistor NM1, the field effect transistor NM2, the field effect transistor NM3 and the field effect transistor NM4 are all connected to the reference ground.

[0058] Optionally, in some embodiments, the field effect transistor NM1 , the field effect transistor NM2 , the field effect transistor NM3 , and the field effect transistor NM4 are all N-type field effect transistors.

[0059] Combine the following Figure 1 , the working principle of the bandgap reference circuit in this application is explained.

[0060] After providing the bandgap reference circuit with power supply voltage VDD and reference current Iin, the current mirror structure composed of field effect transistor PM1 and field effect transistor PM2 in the bias voltage generating unit 110 starts to work, mirrors the reference current Iin to generate a corresponding bias voltage, and supplies power to the reference voltage generating unit 120.

[0061] The field effect transistors in the reference voltage generating unit 120 and the current mirror unit 130 start to work based on the bias voltage provided by the bias voltage generating unit 110. The field effect transistors NM1, NM2, NM3 and NM4 in the current mirror unit 130 form a CASCODE structure current mirror, which can accurately copy the first branch current I1 on the branch where the field effect transistor PM3 is located to the field effect transistor PM4, so that the currents flowing through the field effect transistors PM3 and PM4 are equal.

[0062] Under a reasonable power supply voltage VDD, field effect transistor PM3 and field effect transistor PM4 operate in the saturation region. From the saturation region current formula, it can be seen that the bandgap reference voltage Vref generated by the reference voltage generating unit 120 is the difference between the threshold voltages of field effect transistor PM4 and field effect transistor PM3, for example, about 1.12V at room temperature.

[0063] In summary, the present application proposes a small-area bandgap reference circuit, which generates a bandgap reference voltage through the cooperation between the bias voltage generating unit 110, the reference voltage generating unit 120 and the current mirror unit 130. The structure is simple and the occupied area is small.

[0064] In a further preferred embodiment, the present application uses two field effect transistor devices to construct the reference voltage generating unit 120, and utilizes the difference in electrical characteristics between a normal enhancement-type PMOS transistor and an N-type PMOS device (i.e., a device formed by using N-type ion implantation at the gate of the enhancement-type PMOS transistor device) to obtain a bandgap reference voltage. The bandgap reference voltage can be generated using a simple circuit structure on the basis of omitting the BJT device, thereby greatly reducing the circuit area.

[0065] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A bandgap reference circuit, comprising: A bias voltage generating unit generates a bias voltage according to a reference current; A reference voltage generating unit, comprising a first branch and a second branch, wherein the first branch and the second branch respectively generate a first branch current and a second branch current according to the bias voltage when the first branch and the second branch are turned on; a current mirror unit, connected to the first branch and the second branch respectively, to balance the first branch current and the second branch current so that the first branch current and the second branch current are equal in magnitude; The first branch and the second branch have different turn-on voltages, the first branch receives a first voltage, and the reference voltage generating unit generates a bandgap reference voltage on the second branch according to the first voltage and a difference between the turn-on voltages of the first branch and the second branch.

2. The bandgap reference circuit according to claim 1, wherein: The reference voltage generating unit comprises: A first field effect transistor located on the first branch and a second field effect transistor located on the second branch; The threshold voltage of the first field effect transistor is the turn-on voltage of the first branch; The threshold voltage of the second field effect transistor is a turn-on voltage of the second branch.

3. The bandgap reference circuit according to claim 2, wherein: The gate of the first field effect transistor receives the first voltage, the gate of the second field effect transistor is connected to the second transmission electrode of the second field effect transistor, and the reference voltage generating unit generates the bandgap reference voltage at the gate of the second field effect transistor.

4. The bandgap reference circuit according to claim 3, wherein: The first field effect transistor and the second field effect transistor operate in a saturation region.

5. The bandgap reference circuit according to claim 2, wherein: A threshold voltage of the first field effect transistor is lower than a threshold voltage of the second field effect transistor.

6. The bandgap reference circuit according to claim 5, wherein: The first field effect transistor and the second field effect transistor have the same size.

7. The bandgap reference circuit according to claim 6, wherein: The first field effect transistor and the second field effect transistor are both enhancement type PMOS transistors; The gate of the first field effect transistor includes N-type polysilicon formed by using N-type ion implantation.

8. The bandgap reference circuit according to claim 1, wherein: The bias voltage generating unit comprises: a third field effect transistor and a fourth field effect transistor, wherein the gate of the third field effect transistor is connected to the second transmission electrode of the third field effect transistor and the gate of the fourth field effect transistor to form a current mirror structure; The substrate and the first transmission electrode of the third field effect transistor are connected to the power supply terminal, and the second transmission electrode of the third field effect transistor receives the reference current; The substrate and the first transmission electrode of the fourth field effect transistor are connected to the power supply terminal, and the second transmission electrode of the fourth field effect transistor outputs the reference voltage.

9. The bandgap reference circuit according to claim 8, wherein: The third field effect transistor and the fourth field effect transistor are P-type field effect transistors.

10. The bandgap reference circuit according to claim 1, wherein: The current mirror unit comprises: a fifth field effect transistor and a sixth field effect transistor, wherein a gate of the fifth field effect transistor is connected to a first transmission electrode of the fifth field effect transistor and a gate of the sixth field effect transistor to form a current mirror structure; a seventh field effect transistor and an eighth field effect transistor, wherein a gate of the seventh field effect transistor is connected to a second transmission electrode of the seventh field effect transistor and a gate of the eighth field effect transistor to form a current mirror structure; The fifth field effect transistor and the seventh field effect transistor are connected in series on the first branch, and the sixth field effect transistor and the eighth field effect transistor are connected in series on the second branch; Substrates of the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, and the eighth field effect transistor are all connected to a reference ground.

11. The bandgap reference circuit according to claim 10, wherein: The fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are N-type field effect transistors.

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