Parallel communication data processing method and device

Abstract

The application provides a parallel communication data processing method and device. The method comprises the following steps: a user stores effective data to be sent in a sending data storage unit; the sending data storage unit transmits the effective data to an internal DMA control unit according to a user configuration; the internal DMA control unit generates a first time sequence of a read operation of the sending data storage unit; the effective data is carried from the sending data storage unit to the internal DMA control unit through a DMA channel based on the first time sequence; the effective data is carried to a channel cache FIFO unit; the channel cache FIFO unit obtains I-channel data and Q-channel data through I and Q channels for the effective data, and performs data interleaving processing on the I-channel data and the Q-channel data, so as to transmit the effective data to a sending control unit; the sending control unit determines a target sending protocol mode according to a sending protocol mode, and transmits the effective data to an external device based on the target sending protocol mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a parallel communication data processing method and device. BACKGROUND

[0002] Microcomputer system, or microcomputer system, is an important part of modern computing technology. With the production and development of microprocessors and microcomputers, microcomputer system has gradually become an important tool in the field of information technology. From the original 4-bit microprocessor to the current 64-bit or even higher performance processor, microcomputer system has experienced rapid development. In the microcomputer system, data exchange and processing are often involved.

[0003] At present, there is a general programmable parallel I / O interface which is widely used in almost all series of microcomputer systems. The programmable parallel I / O interface has three data ports with latches or buffers, which can exchange data with peripherals in parallel. Among them, the data bus buffer and read-write control logic realize the write-in of sending data and the read-out of receiving data control.

[0004] However, the existing technology needs three 8-bit data ports, PA port, PB port and PC port, to communicate with peripherals. PA port, PB port and PC port can only transmit their own data respectively, which greatly wastes I / O resources and the utilization rate of transmission channel is also low. Moreover, the CPU needs to write sending data frequently during each data transmission, which causes large CPU overhead and low data transmission efficiency. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a parallel communication data processing method and device. Through the parallel data processing of the data storage unit, internal DMA control unit, channel cache FIFO unit and transceiver control unit, the data of two channels can be transmitted through one channel by the data interleaving processing of I / O channel, and only one set of signals is mapped to external I / O, which saves I / O resources and improves the utilization rate of transmission channel. At the same time, the internal DMA control unit can greatly reduce the CPU overhead during high-speed data transmission, thereby improving the data transmission efficiency.

[0006] In a first aspect, the embodiments of the present application provide a parallel communication data processing method applied to a parallel communication data processing device. The parallel communication data processing device includes a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiver control unit. The data storage unit includes a sending data storage unit and a receiving data storage unit. The transceiver control unit includes a sending control unit and a receiving control unit. The parallel communication data processing device has a data receiving mode and a data sending mode. The method comprises:

[0007] In the data sending mode, a user stores valid data to be sent in the sending data storage unit, and the sending data storage unit transmits the valid data to the internal DMA control unit according to a preset user configuration; the user configuration includes a DMA configuration;

[0008] The internal DMA control unit generates a first timing for reading the sending data storage unit, and based on the first timing, the internal DMA control unit carries the valid data from the sending data storage unit to the internal DMA control unit through a DMA channel of the internal DMA control unit, and carries the valid data to the channel cache FIFO unit; wherein the channel cache FIFO unit includes an I channel and a Q channel;

[0009] The channel cache FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit;

[0010] The sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits the valid data to an external device based on the target sending protocol mode; wherein the sending protocol mode includes a single edge mode and a double edge mode.

[0011] In a possible implementation, the method further includes:

[0012] In the data receiving mode, the receiving control unit determines a corresponding target sending protocol mode according to the sending protocol mode, and transmits the received valid data to the channel cache FIFO unit based on the target sending protocol mode;

[0013] The channel cache FIFO unit performs de-interleaving processing on the valid data, transmits the processed valid data to corresponding I channel and Q channel respectively, and transmits the valid data to the internal DMA control unit through I / Q channel;

[0014] The internal DMA control unit receives the data of the I channel and the Q channel, and generates a second timing required for writing operation of the receiving data storage unit, and based on the second timing, carries the data of the I channel and the Q channel to the receiving data storage unit;

[0015] The receiving data storage unit receives the data of the I channel and the Q channel of the internal DMA control unit, and stores the data to a corresponding address space.

[0016] In a possible implementation, the sending data storage unit and the receiving data storage unit are dual-port RAMs, wherein a left port supports an access protocol of an AHB bus and supports 32-bit mode access; and a right port supports a three-bus protocol of an access RAM interface and supports 8-bit mode access.

[0017] The method further includes:

[0018] The valid data to be sent is written into the sending data storage unit based on a preset write address through the AHB bus; and the write address is 32-bit boundary alignment, that is, the valid data is stored in the form of 0x0, 0x4, 0x8, 0xC addresses.

[0019] In a possible implementation, the internal DMA control unit is obtained by the following steps:

[0020] A target programming model is obtained, and the internal DMA control unit is obtained based on the target programming model; wherein the target programming model represents a simplified programming model.

[0021] Parameter information is configured for each DMA channel of the internal DMA control unit; wherein the parameter information includes a window address, a byte number, a row number and a row offset address.

[0022] In a possible implementation, the window address is a position of the valid data in the data storage unit, the window address is aligned according to a 32-bit boundary, and when the window address is not aligned, the window address is aligned based on a preset alignment standard; the alignment standard is that the lower 2 bits are automatically filled with 0, and the address is aligned downward;

[0023] The byte number is a byte number in each row; the byte number is an even number; the byte number is configured as 2 or 4; and when the byte number is configured as 0, the internal DMA control unit does not transfer data.

[0024] The row number is a row number of each window; and when the product of the row number and the byte number is 0, the transmission of data is not started.

[0025] The row offset address is an offset address between the first byte of a row and the first byte of a next row in consecutive rows; and the row offset address is aligned with a 32-bit boundary in the memory.

[0026] In a possible implementation, the method further includes:

[0027] When the parallel communication data processing device operates in the receiving mode, the internal DMA control unit receives the valid data from the I / Q channel and writes the valid data into the receiving data storage unit.

[0028] When the parallel communication data processing device operates in the transmitting mode, the internal DMA control unit reads the valid data from the address of the data storage unit and transfers the valid data to the I / Q channel of the internal DMA control unit.

[0029] In a possible implementation, the DMA channel of the internal DMA control unit has a transmission queue, and the transmission queue has a descriptor; the method further includes:

[0030] The internal DMA control unit sequentially performs transmission through the descriptors in the transmission queue of the DMA channel, acquires a new descriptor during the transmission, and adds the new descriptor to the transmission queue for queuing; each DMA channel has at most one active transmission and one queued transmission; the active transmission is the transmission currently being performed, and the queued transmission is the transmission that has been configured but not started;

[0031] When the active transmission is completed, the internal DMA control unit takes the next descriptor from the transmission queue and performs new transmission based on the descriptor.

[0032] In a possible implementation, the I channel data and the Q channel data are obtained through the I channel and the Q channel, and the I channel data and the Q channel data are subjected to data interleaving processing, including:

[0033] The valid data is distributed to the I channel and the Q channel of the channel buffer FIFO unit to obtain the I channel data and the Q channel data;

[0034] The I channel data and the Q channel data are combined into one channel based on the transmitting mode to perform data interleaving.

[0035] In a possible implementation, a queuing state machine corresponds to the transmission of the DMA channel of the internal DMA control unit; the method further includes:

[0036] When an abnormal state occurs during the transmission, the queuing state machine is reset to the initial state based on preset software, and the descriptor is reconfigured to start the transmission again;

[0037] When the I channel and the Q channel are initialized and idle, the internal DMA control unit transmits the valid data through the DMA channel.

[0038] In a second aspect, the embodiments of the present application further provide a parallel communication data processing apparatus, which comprises a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiving control unit; the data storage unit comprises a sending data storage unit and a receiving data storage unit; the transceiving control unit comprises a sending control unit and a receiving control unit; the parallel communication data processing apparatus has a data receiving mode and a data sending mode.

[0039] The parallel communication data processing apparatus is used to execute the parallel communication data processing method provided by the first aspect.

[0040] The parallel communication data processing method and apparatus provided by the embodiments of the present application store the effective data to be sent by a user in the sending data storage unit, and the sending data storage unit transmits the effective data to the internal DMA control unit according to the preset user configuration; the internal DMA control unit generates a first time sequence of the read operation of the sending data storage unit, carries the effective data from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit based on the first time sequence, and carries the effective data to the channel cache FIFO unit; the channel cache FIFO unit obtains the I-channel data and the Q-channel data through the I-channel and the Q-channel for the effective data, and performs data interleaving processing on the I-channel data and the Q-channel data to transmit the effective data to the sending control unit; the sending control unit determines the corresponding target sending protocol mode according to the preset sending protocol mode, and transmits the effective data to the external device based on the target sending protocol mode. The present application performs parallel data processing through the four units of the data storage unit, the internal DMA control unit, the channel cache FIFO unit and the transceiving control unit, and performs data interleaving processing through the I / O channel, so that the data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, thereby saving the I / O resource and improving the utilization rate of the transmission channel; meanwhile, the internal DMA control unit can greatly reduce the CPU overhead in the process of high-speed data transmission, thereby improving the data transmission efficiency.

[0041] In order to make the above objectives, characteristics and advantages of the present application more apparent, the following will describe the preferred embodiments in detail, and the accompanying drawings will be described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0043] Figure 1 is a flow chart of a parallel communication data processing method according to an embodiment of the present application;

[0044] Figure 2 is a schematic diagram of a parallel communication data processing flow;

[0045] Figure 3 is a model block diagram of an internal DMA control unit;

[0046] Figure 4 is a schematic diagram of data interaction before and after an internal DMA control unit in a data sending mode;

[0047] Figure 5 is a schematic diagram of address alignment of an internal DMA control unit in a data sending mode;

[0048] Figure 6 is a schematic diagram of data interleaving of I and Q channels;

[0049] Figure 7 is a schematic diagram of a DMA transmission queuing state machine in a data sending mode;

[0050] Figure 8 is a schematic diagram of a DMA transmission queuing state machine in a data receiving mode. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flow charts used in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow charts can not be implemented in sequence, and the steps without logical contextual relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flow charts or one or more operations can be removed from the flow charts under the guidance of the content of the present application by those skilled in the art.

[0052] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0053] It should be noted that the term "comprising" will be used in the embodiments of the present application to specify the presence of stated features, but does not exclude the presence of other features.

[0054] It should be noted that the term "comprising" will be used in the embodiments of the present application to specify the presence of stated features, but does not exclude the presence of other features.

[0055] At present, there is a general programmable parallel I / O interface which is widely used in almost all series of microcomputer systems. The programmable parallel I / O interface has three data ports with latches or buffers, and can perform data exchange with peripherals in parallel. Among them, the data bus buffer and read-write control logic realize the write of sent data and the read of received data control.

[0056] However, the prior art needs three 8-bit data ports, PA port, PB port and PC port, for communication with peripherals. The PA port, PB port and PC port can only transmit their own data respectively, which greatly wastes I / O resources and the utilization rate of transmission channels is also low. Moreover, the CPU needs to write sent data frequently during each data transmission, which causes large CPU overhead and low data transmission efficiency.

[0057] To solve the problem, the present application provides a parallel communication data processing method and device. The four units of data storage unit, internal DMA control unit, channel cache FIFO unit and transceiver control unit are used for parallel data processing. Through the data interleaving processing of I / O channels, the data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, which saves I / O resources and improves the utilization rate of transmission channels. At the same time, the internal DMA control unit can greatly reduce the CPU overhead during high-speed data transmission, thereby improving the data transmission efficiency.

[0058] Figure 1 It is a flowchart of the parallel communication data processing method provided by the embodiments of the present application. The parallel communication data processing method of the embodiments of the present application is applied to the parallel communication data processing device.

[0059] Wherein, the parallel communication data processing device comprises a data storage unit, an internal DMA (Direct Memory Access) control unit, a channel cache FIFO (First In First Out) unit and a transceiving control unit; the data storage unit comprises a sending data storage unit and a receiving data storage unit; the transceiving control unit comprises a sending control unit and a receiving control unit. The parallel communication data processing device has a data receiving mode and a data sending mode. The data storage unit and the channel cache FIFO unit are respectively in communication connection with the internal DMA control unit, and the channel cache FIFO unit is in communication connection with the transceiving control unit.

[0060] For example, as shown in Figure 2 , TX_RAM represents the sending data storage unit, RX_RAM represents the receiving data storage unit, TX_CTRL represents the sending control unit, RX_CTRL represents the receiving control unit, Internal DMA represents the internal DMA control unit, and Channel FIFO represents the channel cache FIFO unit. In addition, it can be seen from Figure 2 that the transmission direction from TX_RAM to the right represents the data sending mode, that is, data is sent from TX_RAM, and the transmission direction from RX_RAM to the left represents the data receiving mode, that is, data is received from RX_CTRL.

[0061] It should be noted that the present application uses TX_RAM, RX_RAM, TX_CTRL and RX_CTRL to represent the respective corresponding units.

[0062] As shown in Figure 1 , the parallel communication data processing method of the embodiment of the present application can specifically comprise:

[0063] S101, in the data sending mode, a user stores to-be-sent valid data in the sending data storage unit, and the sending data storage unit transmits the valid data to the internal DMA control unit according to a preset user configuration.

[0064] S102, the internal DMA control unit generates a first time sequence of reading operation of the sending data storage unit, and based on the first time sequence, the internal DMA control unit carries the valid data from the sending data storage unit to the internal DMA control unit through a DMA channel of the internal DMA control unit, and carries the valid data to the channel cache FIFO unit.

[0065] S103, the channel cache FIFO unit obtains I-channel data and Q-channel data through I-channel and Q-channel for the valid data, and performs data interleaving processing on the I-channel data and the Q-channel data to transmit the valid data to the sending control unit.

[0066] S104, the sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits the valid data to an external device based on the target sending protocol mode.

[0067] In the parallel communication data processing method, the four units of the data storage unit, the internal DMA control unit, the channel cache FIFO unit and the transceiving control unit are used for parallel data processing. Through the data interleaving processing of the I / O channel, the data of two channels can be transmitted through one channel, and only one set of signals is mapped to the external I / O, thereby saving the I / O resources and improving the utilization rate of the transmission channel. Meanwhile, the internal DMA control unit can greatly reduce the CPU overhead in the high-speed data transmission process, thereby improving the data transmission efficiency.

[0068] The above exemplary steps of the embodiment of the present application will be described below in combination with specific examples.

[0069] S101, in the sending mode, the user stores the valid data to be sent in the sending data storage unit, and the sending data storage unit transmits the valid data to the internal DMA control unit according to the preset user configuration.

[0070] It should be noted that before the parallel communication data processing is performed by the data storage unit, the internal DMA control unit, the channel cache FIFO unit and the transceiving control unit, the four units need to be configured.

[0071] In the embodiment of the present application, the valid data is the data to be sent, i.e., the UPP (Universal Parallel Port) data, and the user configuration includes the DMA configuration, i.e., the configuration of the internal DMA control unit, such as the size of the data to be transmitted, the bandwidth, etc. In the sending mode, i.e., when the data is sent, the user stores the valid data to be sent in the sending data storage unit, i.e., the TX_RAM unit, and the TX_RAM unit transmits the valid data to the internal DMA control unit according to the user configuration. For example, as shown in Figure 2 .

[0072] It should be noted that the internal DMA control unit is obtained through the following steps: obtaining a target programming model, obtaining the internal DMA control unit based on the target programming model, and configuring parameter information for each DMA channel of the internal DMA control unit. The target programming model represents a simplified programming model, and the parameter information includes a window address (Window Address), a byte count (Byte Count), a line count (Line Count) and a line offset address (Line Offset Address). In short, the internal DMA controller uses a simplified programming model, and each DMA channel can be configured with corresponding parameter information, for example, as shown inFigure 3 Window Address

[0073] Window Address is the location of valid data in the data storage unit (TX_RAM / RX_RAM unit), i.e. the location of the upp data in the TX_RAM / RX_RAM storage unit, and is aligned according to a 32-bit boundary, and is aligned according to a preset alignment standard when the window address is not aligned; the alignment standard is to automatically fill 0 in the low 2 bits, and the address is aligned downward; Byte Count is the number of bytes in each row; the number of bytes is even; the number of bytes is configured as 2 or 4; when the number of bytes is configured as 0, the internal DMA control unit does not transport data; Line Count is the number of lines of each window; when the product of Line Count and Byte Count is 0, the transmission of data is not started; Line Offset Address is the offset address between the first byte between rows in consecutive rows; the line offset address is aligned with the 32-bit boundary in the memory.

[0074] Specifically, Window Address must be aligned according to a 32-bit boundary, and a window address that is not aligned will be automatically adjusted to a correctly aligned value, with 0 automatically filled in the low 2 bits, and the address is aligned downward. The address is addressed according to 0x0, 0x4, 0x8, 0xC. Byte Count, the number of bytes in each row, must be even to ensure data alignment, and when Byte Count is configured as 0, the DMA does not transport data; since the data requires 32-bit alignment, Byte Count can be configured as 2 or 4. Line Count, the number of lines of each window, the total number of bytes of transmission is equal to B (Byte Count) x L (Line Count), where B is the number of bytes per row and L is the number of rows, and when the total number of bytes is 0, the transmission of data is not started.

[0075] Continuing, Line Offset Address, the offset address between the first byte between rows in consecutive rows, must be aligned with the 32-bit boundary in the memory and cannot exceed 0xFFFC, and its configuration value is 0x4, 0x8, 0xC, etc. Some values of the line offset address have the following special effects on the structure of the data buffer: if the line offset address = byte count, the data buffer is a continuous block in the memory, and its size is equal to (line count) x (byte count); if the line offset address = 0, the data buffer is composed of a row (specifically the first row), and the total size is equal to the byte count, if the I / O channel is configured in transmission mode, the line (number of rows) will be continuously transmitted before the DMA transmission is completed, and if the I / O channel is configured in reception mode, the buffer will be repeatedly written and overwritten by the incoming data.

[0076] It should be noted that the sending data storage unit and the receiving data storage unit are dual-port RAMs, wherein the left port supports an AHB (Advanced High-performance Bus) bus access protocol and supports 32-bit mode access; and the right port supports a three-bus protocol for accessing the RAM interface and supports 8-bit mode access.

[0077] Optionally, when storing the valid data to be sent in the sending data storage unit, the valid data to be sent is written in the sending data storage unit based on a preset write address through the AHB bus. The write address is 32-bit boundary alignment, that is, stored in the form of 0x0, 0x4, 0x8, 0xC addresses.

[0078] For example, in the sending mode, the following description is made as shown in FIG. 6. Figure 4 The TX_RAM is a dual-port RAM, the left port supports a standard AHB bus protocol and supports 32-bit mode access, and the right port supports a three-bus protocol for accessing the RAM interface and supports 8-bit mode access. The user writes the data to be sent in the TX_RAM through the AHB bus, and the write address is 32-bit boundary alignment, that is, stored in the form of 0x0, 0x4, 0x8, 0xC addresses as shown in FIG. 6. Figure 5

[0079] It should be noted that since the internal DMA control unit of the present application supports an 8-bit access mode, the DMA will certainly encounter a case where the window address is not 32-bit aligned when moving the data. Therefore, the low 2-bit address is discarded and rounded down by aligning the window address of the internal DMA control unit, that is, when the window address is configured as 0x06, the internal processing address is 0x04, and the DMA starts moving the data from the 0x04 position of the TX_RAM unit, so that the data stored in the TX_RAM unit can be completely taken out.

[0080] S102, the internal DMA control unit generates a first time sequence of reading operation of the sending data storage unit, and based on the first time sequence, the valid data is moved from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and the valid data is moved to the channel cache FIFO unit.

[0081] ​In the embodiment of the present application, the channel cache FIFO unit includes an I channel and a Q channel, the first timing is the timing information for the read operation of the sending data storage unit, and the internal DMA control unit generates the first timing of the read operation of the sending data storage unit after receiving the valid data sent by the sending data storage unit. Based on the first timing, the internal DMA control unit carries the valid data from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and carries the valid data to the channel cache FIFO unit. For example, as shown in Figure 2 .

[0082] In S103, the channel cache FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit.

[0083] In the embodiment of the present application, after the channel cache FIFO unit receives the valid data sent by the internal DMA control unit, the channel cache FIFO unit obtains I channel data and Q channel data corresponding to the valid data through the I channel and the Q channel of the channel cache FIFO unit, and performs data interleaving processing on the I channel data and the Q channel data to interleave and transmit the valid data to the sending control unit. For example, as shown in Figure 2 .

[0084] It should be noted that the I channel data and the Q channel data are processed by data interleaving according to the channel configuration information. The channel configuration information is the mode of the I channel and the Q channel of the channel cache FIFO unit.

[0085] Optionally, when the I channel data and the Q channel data are obtained through the I channel and the Q channel and the I channel data and the Q channel data are processed by data interleaving, the valid data is distributed to the I channel and the Q channel of the channel cache FIFO unit to obtain the I channel data and the Q channel data, and the I channel data and the Q channel data are merged into one channel based on the sending mode to perform data interleaving. For example, as shown in Figure 6 , wherein Demux represents the data interleaving processing of the present application, and Non-Demux represents non-interleaving. The figure only embodies the difference between interleaving and non-interleaving, and does not represent that the two can be performed at the same time.

[0086] Continue as Figure 6As shown, according to the configuration information, single channel I or two channels I and Q can be selected for data transmission, and the data is stored in channel I (I_D7, I_D6, I_D5, I_D4, I_D3, I_D2, I_D1, I_D0) and channel Q (Q_D7, Q_D6, Q_D5, Q_D4, Q_D3, Q_D2, Q_D1, Q_D0) respectively. Through interleaving processing, multiple data streams are combined into one physical channel for interleaving transmission, and the output data is (I_D7, Q_D7, I_D6, Q_D6, …, I_D0, Q_D0), which improves the utilization rate of channel resources.

[0087] Thus, through interleaving (multiplexing) of channel I and channel Q, multiple data streams are combined into one physical channel for transmission, allowing other data streams to be transmitted when the channel is idle, rather than simply waiting for one data stream to complete transmission, which improves the utilization rate of channel resources and transmission efficiency. Such interleaving processing belongs to block interleaving technology, which is simple in structure and easy to implement, and is suitable for a large amount of storage space.

[0088] S104, the sending control unit determines the corresponding target sending protocol mode according to the preset sending protocol mode, and transmits the valid data to the external device based on the target sending protocol mode.

[0089] In the embodiment of the application, the sending protocol mode includes single edge mode and double edge mode, and the sending control unit determines the corresponding target sending protocol mode according to the sending protocol mode when receiving the valid data represented by the I channel data and the Q channel data sent by the channel buffer FIFO unit, and transmits the valid data to the external device based on the target sending protocol mode, that is, when the sending protocol mode is selected, the valid data is transmitted to the external device through the sending protocol mode. For example, as shown. Figure 2 Thus, the design of the internal DMA control unit improves the data transmission efficiency and stability, and the internal DMA control unit can maximize the CPU overhead during high-speed data transmission, thereby improving the data transmission efficiency. The interleaving (multiplexing) processing technology of the channel buffer FIFO unit realizes interleaving processing of data, thereby improving the utilization rate of the transmission channel.

[0090] The parallel communication data processing method provided by the embodiment of the application is as follows: a user stores to-be-sent valid data in a sending data storage unit, the sending data storage unit transmits the valid data to an internal DMA control unit according to a preset user configuration, the internal DMA control unit generates a first time sequence of a read operation of the sending data storage unit, and based on the first time sequence, the internal DMA control unit carries the valid data from the sending data storage unit to the internal DMA control unit through a DMA channel of the internal DMA control unit, and carries the valid data to a channel cache FIFO unit; the channel cache FIFO unit obtains I-channel data and Q-channel data through I and Q channels for the valid data, and performs data interleaving processing on the I-channel data and the Q-channel data, so as to transmit the valid data to a sending control unit; the sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits the valid data to an external device based on the target sending protocol mode. The parallel communication data processing method provided by the application performs parallel data processing through four units, namely, a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiving control unit, and through data interleaving processing of I / O channels, data of two channels can be transmitted through one channel, and only one group of signals is mapped to an external I / O, thereby saving I / O resources and improving utilization of transmission channels; meanwhile, the internal DMA control unit can greatly reduce CPU overhead in a high-speed data transmission process, thereby improving data transmission efficiency.

[0091] Further, in a data receiving mode, a receiving control unit determines a corresponding target sending protocol mode according to a sending protocol mode, and transmits received valid data to a channel cache FIFO unit based on the target sending protocol mode; the channel cache FIFO unit performs de-interleaving processing on the valid data, transmits the processed valid data to corresponding I and Q channels respectively, and transmits the valid data to an internal DMA control unit through I / Q channels; the internal DMA control unit receives data of the I and Q channels, generates a second time sequence required for a write operation of a receiving data storage unit, and carries the data of the I and Q channels to the receiving data storage unit based on the second time sequence; the receiving data storage unit receives the data of the I and Q channels of the internal DMA control unit, and stores the data to corresponding address spaces.

[0092] For example, as shown in FIG. 1, a sending data storage unit 101, an internal DMA control unit 102, a channel cache FIFO unit 103 and a sending control unit 104 are provided in a sending device 100. Figure 2As shown, RX_CTRL receives data in single-edge mode and double-edge mode according to configuration information, and transmits the received valid data to a channel buffer FIFO unit. The channel buffer FIFO unit deinterleaves the valid data, and then transmits the valid data to corresponding I and Q channels respectively, and transmits the data to an internal DMA control unit through the I / Q channels. The internal DMA control unit receives the data of the I and Q channels, generates second timing information required for write operation of the RX_RAM unit according to user configuration, and carries the I / Q channel data to the RX_RAM unit according to the configuration requirement. The RX_RAM unit receives the data of the internal DMA control unit and stores the data in the corresponding address space, and the user can read the data at any time.

[0093] It should be noted that the flow in the data receiving mode is similar to the flow in the data sending mode described above, and will not be described in detail here. Please refer to the description of the data sending mode above.

[0094] Further, when the parallel communication data processing device operates in the receiving mode, the internal DMA control unit receives valid data from the I / Q channels and writes the valid data into the receiving data storage unit. When the parallel communication data processing device operates in the sending mode, the internal DMA control unit reads valid data from the address of the data storage unit and transmits the valid data to the I / Q channels of the internal DMA control unit.

[0095] Specifically, when the UPP data operates in the receiving mode, the DMA receives incoming data from the I / O channels and writes the data into the address of the RX_RAM unit. When the UPP data operates in the sending mode, the DMA reads data from the address of the TX_RAM unit and transmits the data to the I / O channels.

[0096] Further, the DMA channel of the internal DMA control unit has a transmission queue, and the transmission queue has descriptors. The internal DMA control unit sequentially performs transmission through the descriptors in the transmission queue of the DMA channel, obtains new descriptors during the transmission process, and adds the new descriptors to the transmission queue for queuing. When the active transmission is completed, the internal DMA control unit takes the next descriptor from the transmission queue and performs new transmission based on the descriptor. Each DMA channel has at most one active transmission (active DMA transmission) and queued transmission (queued DMA transmission). The active transmission is the transmission currently being performed, and the queued transmission is the transmission that has been configured but has not yet started.

[0097] It should be noted that the DMA allows new descriptors to be queued during the transmission process, and each DMA channel has at most one active transmission and queued transmission. After the active transmission is completed, the DMA automatically takes the next descriptor from the queued transmission and starts a new transmission. The DMA performs the transmission in the order of the descriptor queue. During the active transmission, new descriptors can be added to the queue to wait for the active transmission to complete and then start execution.

[0098] Thus, the operation of the DMA queue improves the transmission efficiency of data.

[0099] Further, the internal DMA control unit corresponds to the queue state machine during the transmission process of the DMA channel. When an abnormal state occurs during the transmission process, the software is reset based on the preset software to reset the queue state machine to the initial state and reconfigure the descriptor to start the transmission again. When the I channel and the Q channel are initialized and idle (i.e., the I / O channel is initialized and idle), the internal DMA control unit transmits valid data through the DMA channel. Optionally, the software can be a reset software controlled by the CPU, and the reset button can be defined on the software.

[0100] Specifically, when an abnormal state (such as a transmission error, an overflow error, etc.) occurs during the DMA transfer process, the software is reset to reset the DMA queue state machine to the initial state. At this time, the descriptor is reconfigured to start the DMA transmission again, i.e., to restart the transmission. In addition, the internal DMA controller always transfers data in byte addressing mode. If the related I / O channel is initialized and idle, the DMA transmission starts immediately. If no abnormal working condition occurs during the transmission process, the transmission will continue until the configured number of bytes is transmitted.

[0101] Thus, the soft reset processing of the internal DMA control unit increases the stability of the transmission.

[0102] As can be understood by those skilled in the art, the descriptor is used to describe the data block transmission information, which includes key parameters such as source address, target address, transmission length, control information, etc. When the descriptor is reconfigured, i.e., these parameters are reset.

[0103] The queue state machine in the DMA transmission of the present application is described in detail below.

[0104] In the data sending mode, the DMA transmission queue state machine is as follows Figure 7TCH_IDLE, indicating that the DMA is in a non-transmission state, after detecting the DMA transmission valid signal r_dmatx_valid (used to indicate the validity of DMA transmission or the validity of data), the dmatxburst_sts state machine jumps to TCH_TRANS, otherwise it is always in the TCH_IDLE state. TCH_TRANS, indicating that if a new descriptor enable signal i_chi_en is detected during the r_dmatx_valid valid period, the dmatxburst_sts state machine jumps to TCH_WAIT (queuing of descriptors), if r_dmatx_valid is detected to be invalid (indicating off, such as reset), the dmatxburst_sts state machine jumps to TCH_END, otherwise it is always in the TCH_TRANS state.

[0105] Continuing to say, TCH_WAIT, indicating that no new descriptor is responded in this state until r_dmatx_valid is detected to be invalid, the dmatxburst_sts state machine jumps to TCH_JUMP, and r_txchi_en_tmp or r_txchq_en_tmp is set (reset, off or invalid). TCH_JUMP, indicating that the dmatxburst_sts state machine jumps to TCH_END. TCH_END, indicating that the dmatxburst_sts state machine jumps to TCH_IDLE.

[0106] In the data receiving mode, the DMA transmission queuing state machine is as follows Figure 8 The state machine description is similar to the above-mentioned data sending mode, which will not be described in detail.

[0107] Thus, the DMA allows new descriptors to be queued during transmission, and each DMA channel has at most one active transmission and queued transmission, and the operation of DMA queuing improves the transmission efficiency of data.

[0108] The embodiment of the application also provides a parallel communication data processing device, which comprises a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiver control unit; the data storage unit comprises a sending data storage unit and a receiving data storage unit; the transceiver control unit comprises a sending control unit and a receiving control unit; the parallel communication data processing device has a data receiving mode and a data sending mode. The above-mentioned parallel communication data processing device is used to execute the above-mentioned parallel communication data processing method.

[0109] The parallel communication data processing device provided by the embodiment of the present application stores the effective data to be sent by a user in a sending data storage unit, and the sending data storage unit transmits the effective data to an internal DMA control unit according to a preset user configuration. The internal DMA control unit generates a first timing sequence of reading the sending data storage unit, and carries the effective data from the sending data storage unit to the internal DMA control unit through a DMA channel of the internal DMA control unit based on the first timing sequence, and carries the effective data to a channel cache FIFO unit. The channel cache FIFO unit obtains I-channel data and Q-channel data through I and Q channels for the effective data, and performs data interleaving processing on the I-channel data and the Q-channel data to transmit the effective data to a sending control unit. The sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits the effective data to an external device based on the target sending protocol mode. The parallel communication data processing device of the present application performs parallel data processing through four units of the data storage unit, the internal DMA control unit, the channel cache FIFO unit and the transceiving control unit, and through data interleaving processing of the I / O channel, the data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, thereby saving I / O resources and improving the utilization rate of the transmission channel. Meanwhile, the internal DMA control unit can greatly reduce the CPU overhead in the process of high-speed data transmission, thereby improving the data transmission efficiency.

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be described herein. In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be indirect coupling or communication connection through some communication interface, device or module, which can be electrical, mechanical or other forms.

[0111] The modules described as separate components can or can not be physically separated, and the components displayed as modules can or can not be physical units, that is, they can be located in one place, or can be distributed to a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0112] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0113] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the deployment method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, and various media that can store program codes.

[0114] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A parallel communication data processing method, characterized in that, This invention relates to a parallel communication data processing device, which includes a data storage unit, an internal DMA control unit, a channel buffer FIFO unit, and a transceiver control unit; the data storage unit includes a transmitting data storage unit and a receiving data storage unit. The transceiver control unit includes a transmitting control unit and a receiving control unit; The parallel communication data processing device has a data receiving mode and a data sending mode; the method includes: In the data transmission mode, the user stores the valid data to be transmitted in the transmission data storage unit, and the transmission data storage unit transmits the valid data to the internal DMA control unit according to the preset user configuration; the user configuration includes DMA configuration. The internal DMA control unit generates a first timing sequence for reading the transmit data storage unit, and based on the first timing sequence, moves the valid data from the transmit data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and moves the valid data to the channel buffer FIFO unit; wherein, the channel buffer FIFO unit includes an I channel and a Q channel; The channel buffer FIFO unit obtains I-channel data and Q-channel data through the I-channel and Q-channel for the valid data, and performs data interleaving processing on the I-channel data and Q-channel data to transmit the valid data to the transmission control unit; wherein, The transmission control unit determines the corresponding target transmission protocol mode according to the preset transmission protocol mode, and transmits the valid data to the external device based on the target transmission protocol mode; wherein, the transmission protocol mode includes single-edge mode and double-edge mode.

2. The parallel communication data processing method according to claim 1, characterized in that, The method further includes: In the data receiving mode, the receiving control unit determines the corresponding target transmission protocol mode according to the transmission protocol mode, and transmits the received valid data to the channel buffer FIFO unit based on the target transmission protocol mode; The channel buffer FIFO unit performs deinterleaving processing on the valid data, transmits the processed valid data to the corresponding I channel and Q channel respectively, and transmits the valid data to the internal DMA control unit through the I / Q channel; The internal DMA control unit receives data from the I channel and the Q channel, generates a second timing sequence required for the write operation of the receive data storage unit, and moves the data from the I channel and the Q channel to the receive data storage unit based on the second timing sequence; The receiving data storage unit receives the data from the I channel and the Q channel of the internal DMA control unit and stores it in the corresponding address space.

3. The parallel communication data processing method according to claim 2, characterized in that, The transmitting data storage unit and the receiving data storage unit are dual-port RAMs. The left port supports the AHB bus access protocol and supports 32-bit mode access; the right port supports the three-bus protocol for accessing the RAM interface and supports 8-bit mode access. The step of storing the valid data to be sent in the transmission data storage unit includes: The valid data to be sent is written to the transmission data storage unit via the AHB bus based on a preset write address; wherein the write address is 32-bit boundary aligned, that is, stored in the form of 0x0, 0x4, 0x8, 0xC address.

4. The parallel communication data processing method according to claim 3, characterized in that, The internal DMA control unit is obtained through the following steps: Obtain a target programming model, and obtain the internal DMA control unit based on the target programming model; wherein, the target programming model represents a simplified programming model; Configure parameter information for each DMA channel of the internal DMA control unit; wherein the parameter information includes window address, number of bytes, number of rows, and row offset address.

5. The parallel communication data processing method according to claim 4, characterized in that, The window address is the position of the valid data in the data storage unit. The window address is aligned according to a 32-bit boundary and is aligned based on a preset alignment standard when the window address is not aligned. The alignment standard is that the lower 2 bits are automatically filled with 0 and the address is aligned downwards. The number of bytes is the number of bytes in each line; the number of bytes is an even number; the number of bytes is configured to be 2 or 4; when the number of bytes is configured to be 0, the internal DMA control unit does not move data; The number of rows is the number of rows in each window; when the product of the number of rows and the number of bytes is 0, data transmission is not initiated. The row offset address is the offset address between the first byte of each consecutive row; the row offset address is aligned with the 32-bit boundary in memory.

6. The parallel communication data processing method according to claim 5, characterized in that, The method further includes: When the parallel communication data processing device operates in the receiving mode, the internal DMA control unit receives the valid data from the I / Q channel and writes the valid data to the receiving data storage unit. When the parallel communication data processing device operates in the transmission mode, the internal DMA control unit reads the valid data from the address of the data storage unit and transmits the valid data to the I / Q channel of the internal DMA control unit.

7. The parallel communication data processing method according to claim 6, characterized in that, The DMA channel of the internal DMA control unit has a transfer queue, and the transfer queue has a descriptor; the method further includes: The internal DMA control unit sequentially transmits data using descriptors in the DMA channel's transmission queue, acquires new descriptors during transmission, and adds these new descriptors to the transmission queue for queuing. Each DMA channel has at most one active transmission and one queued transmission. The active transmission is the transmission currently in progress, and the queued transmission is a transmission that has been configured but not yet started. When the active transfer is completed, the internal DMA control unit retrieves the next descriptor from the transfer queue and performs a new transfer based on the descriptor.

8. The parallel communication data processing method according to claim 7, characterized in that, The process of obtaining I-channel data and Q-channel data through the I-channel and Q-channel, and then performing data interleaving processing on the I-channel data and Q-channel data, includes: The valid data is distributed to the I channel and Q channel of the channel buffer FIFO unit to obtain the I channel data and the Q channel data; Based on the transmission mode, the I-channel data and the Q-channel data are merged into one channel for data interleaving.

9. The parallel communication data processing method according to claim 8, characterized in that, The corresponding queuing state machine is used during the transmission process of the DMA channel in the internal DMA control unit; The method further includes: If an abnormal state occurs during transmission, a reset is performed based on preset software to reset the queuing state machine to its initial state and reconfigure the descriptor to restart transmission. When the I channel and the Q channel are initialized and idle, the internal DMA control unit transmits the valid data through the DMA channel.

10. A parallel communication data processing device, characterized in that, The parallel communication data processing device includes a data storage unit, an internal DMA control unit, a channel buffer FIFO unit, and a transceiver control unit; the data storage unit includes a transmitting data storage unit and a receiving data storage unit; the transceiver control unit includes a transmitting control unit and a receiving control unit; the parallel communication data processing device has a data receiving mode and a data transmitting mode. The parallel communication data processing device is used to execute the parallel communication data processing method as described in any one of claims 1-9.

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