Semiconductor device interconnection metal design method, electronic equipment and program product

Abstract

The invention discloses a semiconductor device interconnection metal design method. The method comprises the following steps: A1, setting an expected working time length of a semiconductor device; a2, according to the expected working duration, calculating a leakage current variation caused by the aging effect stress of the semiconductor device; a3, calculating Joule heat under the breakdown effect stress of the semiconductor device according to the working duration; a4, calculating the service life of the interconnection metal of the semiconductor device according to the parameters of the interconnection metal material of the semiconductor device, the Joule heat, the self-heating of the device and the variation of the leakage current; and A5, if the service life of the interconnection metal of the semiconductor device does not meet the design target, optimizing the design parameters of the interconnection metal of the semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device design, and in particular relates to a semiconductor device interconnection metal design method, electronic equipment and program product. Background Art

[0002] As integrated circuits gradually enter nanometer nodes, the size of MOS devices continues to shrink. Figure 1 As shown. At the same time, the introduction of new device structures with low heat dissipation capabilities (such as FinFET, GAAFET, etc.) has continuously enhanced the electric field on the gate oxide layer, and the local operating temperature of the device has gradually increased. These changes have made the aging problems of devices and circuits (such as bias temperature instability (BTI), hot carrier degradation (HCD), etc.) more prominent, becoming a key challenge that needs to be urgently solved in the current integrated circuit field.

[0003] In addition to the miniaturization of device size, the distance between the back-end metal layers (such as M0 pitch, Mx pitch, etc.) is also constantly decreasing. With the reduction of metal size and the reduction of the spacing between interconnected metals, not only will the maximum current carrying capacity of the metal decrease, but the heat dissipation capacity of the interconnection lines will also be significantly weakened. This makes the reliability of the device working under high current and high temperature even more worrying, greatly increasing the risk of breakdown. Therefore, at advanced process nodes, device aging and breakdown problems are still one of the core bottlenecks restricting the further development of integrated circuits. It is urgent to solve these challenges through technological innovation and optimized design to ensure the long-term stable operation of integrated circuits. Figure 1 The English terms in are explained as follows:

[0004] Dimension scaling

[0005] M0 pitch (nm)——the first layer metal line spacing (nanometer);

[0006] Gate pitch (nm)——gate spacing (nanometer);

[0007] Lg: Gate Length-HP (nm)——Gate length-high performance (nanometer);

[0008] Device lateral pitch (nm)——Device lateral pitch (nanometer);

[0009] Mx pitch (nm)——metal line pitch of the xth layer (nanometers).

[0010] Figure 1Represents the scaling trend of key dimensional parameters of semiconductor devices from 2018 to 2034. These parameters are critical to evaluating the performance and density of integrated circuits (ICs). Among them, M0 pitch (nm) is the first-layer metal line pitch, which indicates the distance between the first-layer metal lines. Over time, M0 pitch decreases from 36nm in 2018 to 16nm in 2034;

[0011] Gate pitch (nm) is the distance between gates. The gate pitch is reduced from 54nm in 2018 to 40nm in 2034.

[0012] Lg: Gate Length-HP (nm) is the high-performance gate length, which indicates the gate length of high-performance devices. The gate length is reduced from 20nm in 2018 to 12nm in 2034.

[0013] Device lateral pitch (nm) refers to the device lateral spacing, which indicates the device spacing in the lateral direction. The device lateral pitch is reduced from 32nm in 2018 to 12nm in 2034.

[0014] Mx pitch (nm) is the x-th metal line pitch, which indicates the distance between the x-th metal lines. The Mx pitch is reduced from 40nm in 2018 to 16nm in 2034.

[0015] Therefore, over time, the key dimensional parameters of semiconductor devices are shrinking. This scaling trend is a manifestation of Moore's Law, which states that the number of transistors that can be accommodated on an integrated circuit doubles approximately every two years, driving the performance of electronic devices and reducing costs. Dimensional scaling is critical to improving the performance and density of integrated circuits. Smaller gate pitch and gate length can increase the switching speed of devices and reduce power consumption. Smaller metal line pitch and device lateral spacing can increase the integration of circuits, thereby achieving higher performance and lower cost. However, dimensional scaling also brings some challenges, such as increased process complexity, rising manufacturing costs, and reduced device reliability. Therefore, while pursuing dimensional scaling, it is also necessary to continuously improve manufacturing processes and design methods to meet these challenges. Summary of the invention

[0016] One of the embodiments of the present disclosure is a method for designing interconnect metals based on the coupling of aging effects and breakdown effects of semiconductor devices, which is used for semiconductor device and standard unit circuit design and integrated circuit back-end design.

[0017] A method for designing interconnect metal of a semiconductor device, the method comprising the following steps:

[0018] A1, assuming the expected working time of the semiconductor device;

[0019] A2, calculating the leakage current change caused by the aging effect stress of the semiconductor device according to the expected working time;

[0020] A3, calculating the Joule heat of the semiconductor device under breakdown effect stress according to the working time;

[0021] A4, calculating the metal interconnection life of the semiconductor device according to the metal interconnection material parameters, Joule heat, device self-heating and leakage current change of the semiconductor device;

[0022] A5, if the lifetime of the semiconductor device interconnection metal does not meet the design target, optimizing the design parameters of the semiconductor device interconnection metal.

[0023] The disclosed embodiments propose a novel interconnect metal design method based on the coupling of device aging effect and device breakdown effect, which integrates the coupling characteristics of aging effect and breakdown effect and provides an efficient and reliable solution for interconnect metal design at advanced process nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0025] Figure 1 Schematic diagram of the scaling trend of key dimensional parameters of existing semiconductor devices.

[0026] Figure 2 Schematic diagram of the effect of HCD on device breakdown according to one embodiment of the present invention.

[0027] Figure 3 Schematic diagram of the effect of HCD and EiB on the life of a CMOS circuit according to one embodiment of the present invention.

[0028] Figure 4 A flow chart of a method for designing interconnect metal of a semiconductor device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0029] In existing methods, device aging and device breakdown are usually characterized and modeled independently, and their corresponding lifespans are evaluated separately. However, with the advent of advanced technology nodes, the density of transistors and interconnect metals continues to increase, and the introduction of new materials and new structures has made device aging and breakdown problems more serious. At the same time, the coupling effect between the two has also begun to emerge and become non-negligible. In this context, the traditional method of still using separate characterizations of device aging and breakdown is bound to lead to overly optimistic estimates of device lifespan. Therefore, the development of a new design method based on the coupling of device aging effects and breakdown effects is of great significance for the reliability design of integrated circuits at advanced process nodes.

[0030] Further investigation of existing design methods shows that the industry usually adopts accelerated life test methods for life evaluation and optimized design of device aging or device breakdown, which accelerates the aging or breakdown process of the device by applying stress conditions such as higher voltage or temperature, and then fits the experimental data to extract parameters in combination with physical models (such as Power-Law model, Arrhenius model and TAT model, etc.), so as to predict the life of the device under actual working conditions. At the same time, it is supplemented by methods such as TCAD simulation, and on this basis, the device design is iteratively optimized to meet performance and reliability requirements.

[0031] At mature process nodes, the coupling effect between device aging and breakdown is relatively weak. Therefore, in existing methods, device aging and breakdown are usually characterized separately, modeled independently, and their reliability is evaluated separately. However, as process technology gradually moves towards advanced nodes, it has been observed that the hot carrier degradation effect (HCD) of the device has a significant impact on the device breakdown behavior (such as Figure 2 Specifically, compared with devices that have not undergone HCD aging, the breakdown life of the interconnect metal of NMOS devices that have undergone HCD degradation is significantly shortened (as shown in Figure 2 In contrast, for PMOS devices, HCD degradation can lead to a significant increase in the breakdown lifetime of the interconnect metal (as shown in Figure 2 This phenomenon indicates that the interaction between device aging effect and breakdown effect becomes non-negligible at advanced nodes. Figure 2 The English terms in are explained as follows:

[0032] nFinFETs – n-type fin field effect transistors;

[0033] pFinFETs – p-type fin field effect transistors;

[0034] TDDB (Time-Dependent Dielectric Breakdown)——Time-dependent dielectric breakdown;

[0035] HCD (Hot Carrier Degradation)——Hot carrier degradation effect;

[0036] Vg (Gate Voltage)——gate voltage;

[0037] Vd (Drain Voltage)——Drain voltage;

[0038] Vs (Source Voltage)——Source voltage;

[0039] Vb (Bulk Voltage)——substrate voltage;

[0040] Ig (Gate Current)——gate current;

[0041] Tstr (Stress Time)——stress time;

[0042] Temp (Temperature)——Temperature.

[0043] Figure 2 (a) shows the change of Ig (gate current) under TDDB stress (Vg = 2.2V, Vd = Vs = Vb = 0V) for nFinFETs that have undergone HCD degradation and nFiNFETs that have not undergone degradation. The solid line shows the change of Ig under TDDB stress for nFinFETs that have undergone HCD degradation, and the dotted line shows the change of Ig under TDDB stress for nFiNFETs that have not undergone degradation. It can be seen that the breakdown time of nFinFETs that have undergone HCD degradation is significantly lower than that of nFiNFETs that have not undergone degradation, indicating that HCD has a significant impact on TDDB.

[0044] Figure 2 (b) shows the change of Ig (gate current) under TDDB stress (Vg = -3.12V, Vd = Vs = Vb = 0V) for pFinFETs that have undergone HCD degradation and pFinFETs that have not undergone degradation. Similar to Figure (a), the breakdown time of pFinFETs that have undergone HCD degradation is higher than that of pFiNFETs that have not undergone degradation.

[0045] Figure 2(c) Comparison of the Weibull distribution of the breakdown time of nFinFETs that have undergone HCD degradation (HCD conditions: Vg = Vd = 1.3V, temperature = 300K, Tstr = 1ks) and nFiNFETs that have not undergone degradation. The figure shows the breakdown lifetime (tbd) of each device in the statistical test, where T63% represents the mean time for the device to breakdown. For nFiNFETs that have not undergone degradation, no device breakdown was measured within the test window (5000s), while for nFinFETs that have undergone HCD degradation, it can be seen that the device breakdown time is significantly reduced.

[0046] Figure 2 (d) Comparison of the Weibull distribution of the breakdown time of pFinFETs that have undergone HCD degradation (HCD conditions: Vg = Vd = -1.1V, temperature = 300K, Tstr = 100s / 1ks) and pFiNFETs that have not undergone degradation. The figure shows the breakdown lifetime (tbd) of each device in the statistical test, where T63% represents the mean time when 63% of the devices break down. It can be seen that as the device degradation (ΔVth) increases, the breakdown time of the device gradually increases.

[0047] The above experimental results show that the coupling effect of HCD and EiB is very significant under advanced process nodes. In addition, with the continuous development of integrated circuit technology, the core frequency of processors continues to increase, and the alternating frequency of HCD stress and electric field induced breakdown (EiB) stress that devices are subjected to during operation has increased significantly (e.g. Figure 3 As shown). This not only increases the complexity of device aging and breakdown effects, but also enhances the coupling effect between the two, posing a higher challenge to existing independent characterization methods. Therefore, the present disclosure proposes a new design method based on the coupling of device aging and breakdown effects, the purpose of which is to achieve a more accurate life prediction of the device, while providing more reliable guidance for the design of devices and circuits, helping to cope with the more stringent requirements of advanced process nodes on performance and reliability, and laying a solid foundation for the future development of integrated circuits. Figure 3 The English term explanations include:

[0048] Vin——input voltage;

[0049] Vout——output voltage;

[0050] Vdd——power supply voltage;

[0051] Gnd——ground;

[0052] NMOS – N-type metal oxide semiconductor;

[0053] PMOS – P-type metal oxide semiconductor;

[0054] HCD (Hot Carrier Degradation)——Hot carrier degradation effect;

[0055] EiB (Electric Induced Breakdown)——Electric field induced breakdown.

[0056] Figure 3 A typical CMOS (Complementary Metal Oxide Semiconductor) inverter circuit and its operating waveforms are included. A CMOS inverter consists of an NMOS and a PMOS transistor, which are turned on alternately to achieve a logic inversion function.

[0057] In the HCD stage, the NMOS or PMOS transistor is in the on state, and the output voltage Vout is pulled down or pulled up to achieve logic inversion. In the EiB stage, the NMOS or PMOS transistor is in the off state, and the output voltage Vout remains stable to avoid unnecessary power consumption.

[0058] The working principle of the CMOS inverter is based on the complementary characteristics of NMOS and PMOS transistors. When the input voltage Vin is at a low level, the PMOS transistor is turned on, the NMOS transistor is turned off, and the output voltage Vout is pulled up to close to Vdd; when the input voltage Vin is at a high level, the NMOS transistor is turned on, the PMOS transistor is turned off, and the output voltage Vout is pulled down to close to Gnd. In the HCD stage, the transistor is in the on state, and current flows through the transistor, causing the output voltage Vout to change. In the EiB stage, the transistor is in the off state, no current flows, and the output voltage Vout remains stable. This alternating on and off working mode gives the CMOS inverter the advantages of low power consumption and high noise tolerance. In the HCD stage, although the power consumption is high, it can respond quickly to changes in the input signal; in the EiB stage, the power consumption is low, which can reduce unnecessary energy consumption.

[0059] At advanced process nodes, the electric induced breakdown (EiB) life of NMOS devices is significantly shortened after experiencing hot carrier degradation (HCD) stress. The physical root of this phenomenon is that HCD stress causes a significant increase in the leakage current of the NMOS gate dielectric layer. The increase in leakage current further triggers higher Joule heat accumulation, and the combined effect of high current and high heat significantly accelerates the breakdown failure of the back-end interconnect metal. (For detailed physical mechanisms, please refer to the literature: Y.Xue et al., "On the Interaction between Hot Carrier Degradation (HCD) and Electrical-induced Breakdown (EiB) in Advanced FinFET Nodes" in IEEE Trans. Electron Devices, 2025, (under review))

[0060] Through the above analysis and research on the defects of the prior art, the solution proposed in the present disclosure is to propose a new interconnect metal design method based on the coupling of device aging effect and breakdown effect. This method can ensure the realization of high-reliability interconnect metal design under the condition that the coupling of aging effect and breakdown effect is significantly enhanced, thereby effectively ensuring that the overall life of the device meets the design specifications and actual application requirements.

[0061] According to one or more embodiments, the present invention discloses a novel interconnect metal design method based on the coupling of device aging effect and device breakdown effect, taking the optimization of the back-end interconnect metal of NMOS in the inverter as an example (such as Figure 3 The specific operation process is as follows:

[0062] 1) Determine basic parameters: Assume that the expected working time of the inverter is T 0 (For example, 1us, 1ms, 1s, 1ks, etc.), the duty cycle is DF, then the cumulative duration of NMOS under electric field induced breakdown (EiB) stress is DF*T 0 At the same time, assuming that the proportion of HCD (hot carrier degradation effect) stress in the periodic signal is λ, the cumulative duration of NMOS under HCD stress is t hcd =λ*T 0 ;

[0063] 2) Calculate the leakage current caused by HCD: According to the influence of HCD stress on device performance, calculate the change in leakage current caused by HCD during the working time: ΔIg =f(V g ,V d ,t hcd ). Among them, V g and V d are the gate voltage and drain voltage of NMOS respectively;

[0064] 3) Calculate the Joule heat under EiB stress: Based on the material properties (such as electrical conductivity, thermal conductivity) and geometric parameters (such as thickness, width, etc.) of the back-end interconnect metal, combined with the leakage current, calculate the Joule heat generated by the metal under EiB stress: T joule =g(ΔI g ,V g ,Metal);

[0065] 4) Evaluate metal life: metal material parameters, Joule heat T joule 、Device self-heating T SHE and leakage current change ΔI g Substitute into the EM simulation platform to calculate the lifespan of the back-end metal. The role of the EM (Electromigration) simulation platform is to simulate and analyze potential reliability issues caused by electromigration in semiconductor devices or integrated circuits, so as to help evaluate and optimize the width, length and material selection of metal wiring in the chip design stage to reduce the risk of electromigration.

[0066] 5) Life verification and optimization: Compare the calculated metal life with the design target:

[0067] a) If Lifetime>T crit (T crit It can be customized or defined by inverter working conditions, such as T crit =DF*T 0 ), indicating that the metal will not fail due to electromigration (EM) during EiB stress, and the interconnect metal meets the design requirements;

[0068] b) If Lifetime≤T crit , it is necessary to optimize the interconnect metal design, such as replacing the metal material, adjusting the geometric dimensions or optimizing the structure, until the life test passes.

[0069] In the life verification and optimization of semiconductor devices, T crit is a critical time threshold used to evaluate the reliability of interconnect metal under electromigration (EM) stress. crit It can be used as a design target time to determine whether metal interconnects will fail during electromigration stress.

[0070] Through the above method, the present disclosure realizes the precise optimization design of interconnect metal when the coupling effect between device aging and breakdown is significant, ensuring that its reliability meets the actual application requirements.

[0071] Figure 4 Explanations of Chinese and English terms include:

[0072] HCD simulation——hot carrier degradation effect simulation;

[0073] Operation time——operation time;

[0074] Leakage current——leakage current;

[0075] Joule heat——Joule heat;

[0076] EM simulation——electromigration simulation;

[0077] Lifetime——Lifespan;

[0078] T crit - critical time;

[0079] PASS——passed;

[0080] Interconnect metal (Metal)——interconnect metal;

[0081] Modify the width of Metal,or replace the material,etc——Modify the width of metal or replace the material, etc.

[0082] like Figure 4 As shown, a MOS device interconnect metal design method based on the coupling of aging effect and device breakdown effect comprises the following steps:

[0083] S101, assuming that the expected working time of the MOS tube is T 0 , the duty cycle is DF,

[0084] The cumulative duration of the MOS tube EiB stress is DF*T 0 ,

[0085] The MOS tube HCD stress is within the expected working time T 0 The proportion of is λ, then the cumulative duration of HCD stress of the MOS tube is t hcd =λ*T 0 ;

[0086] S102, calculating the leakage current variation ΔI caused by the HCD stress of the MOS tube g =f(V g ,V d ,t hcd ), V g is the MOS gate voltage, V d is the MOS drain voltage, t hcd is the accumulated duration of HCD stress,

[0087] S103, calculating the Joule heat of the MOS tube EiB stress,

[0088] T joule =g(ΔI g ,V g ,Metal),

[0089] ΔI g is the leakage current, V g is the gate voltage, Metal is the metal material parameter;

[0090] S104, based on metal material parameters, Joule heat T joule 、Device self-heating T SHE and leakage current change ΔI g , calculate the back-end interconnect metal lifetime;

[0091] S105, if the downstream metal life is greater than T crit , then the interconnect metal meets the design requirements;

[0092] If the back-end interconnect metal is less than or equal to T crit , then optimize the back-end interconnect metal design.

[0093] Figure 4 A process method is used to evaluate and optimize the reliability of semiconductor devices under high current conditions. By simulating leakage current, Joule heating and electromigration effects, the device life can be predicted and the design can be optimized based on the prediction results.

[0094] The optimization design precautions in the embodiments of the present invention are not limited to inverter circuits, but are also applicable to other types of circuits or devices; the aging simulation is not limited to hot carrier degradation effects (HCD), but is also applicable to other aging effects (such as temperature bias instability, Bias Temperature Instability, BTI), etc.

[0095] Therefore, the embodiments of the present disclosure consider optimizing the back-end interconnect metal design after combining the device aging and device breakdown coupling effects. The design process includes a complete logical chain of aging simulation, Joule heat calculation, life prediction, and interconnect metal optimization, which is applicable to different circuit types (such as digital circuits, analog circuits, etc.), different devices (such as FinFET, GAAFET, etc.), and different process nodes. At the same time, it can also be expanded to consider other aging and breakdown effects (such as BTI, TDDB, etc.). TDDB (Time Dependent Dielectric Breakdown) is both an aging effect and a breakdown effect, which mainly affects the gate oxide layer of MOSFET.

[0096] The design of the disclosed embodiment has been verified by aging effect and breakdown effect modeling and simulation, and the optimization measures for interconnect metal include specific optimization design solutions for metal material selection (such as high thermal conductivity metal), structural size adjustment (such as line width optimization), and heat dissipation enhancement (such as thermal interface material).

[0097] In summary, the technical effects of the present disclosure include:

[0098] 1) The coupling effect of device aging and breakdown is comprehensively considered.

[0099] This disclosure breaks the traditional design method of independently characterizing device aging effects and breakdown effects, and for the first time incorporates the coupling effect of the two into the core consideration of interconnect metal design, which is more in line with the complexity of actual device working conditions at advanced process nodes.

[0100] 2) Improve the reliability of interconnect metal.

[0101] By combining the dynamic changes of aging stress and breakdown stress, this technical solution can optimize metal materials, structural dimensions and heat dissipation capabilities, effectively improve the anti-aging and anti-breakdown capabilities of interconnect metals, and thus significantly extend the life of the device.

[0102] 3) Support high-precision life prediction.

[0103] Due to the combination of multi-physics models (such as leakage current model, Joule heat calculation model, etc.) and simulation platform, this method can accurately predict the lifetime of devices under complex coupling effects, avoiding the misjudgment of lifetime caused by traditional design methods due to ignoring coupling effects.

[0104] 4) Adapt to the requirements of advanced process nodes.

[0105] In response to the reliability challenges brought about by device miniaturization, high frequency operation, and high power density in advanced nodes, this disclosure provides feasible design guidance to ensure a balance between device performance and reliability requirements.

[0106] 5) Strong scalability.

[0107] The design method of the present disclosure is not only applicable to current NMOS devices, but also can be extended to other types of devices (such as PMOS) and interconnect metal structures, providing a general solution for the reliability design of multiple process nodes.

[0108] The solution of the present disclosure integrates the coupling characteristics of the aging effect and the breakdown effect, providing an efficient and reliable solution for the interconnect metal design under advanced process nodes, and having significant technical advantages and practical values.

[0109] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0110] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0111] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0112] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for designing interconnect metal of a semiconductor device, characterized in that: The method comprises the following steps: A1, assuming the expected working time of the semiconductor device; A2, calculating the leakage current change caused by the aging effect stress of the semiconductor device according to the expected working time; A3, calculating the Joule heat of the semiconductor device under breakdown effect stress according to the working time; A4, calculating the metal interconnection life of the semiconductor device according to the metal interconnection material parameters, Joule heat, device self-heating and leakage current change of the semiconductor device; A5, if the lifetime of the semiconductor device interconnection metal does not meet the design target, optimizing the design parameters of the semiconductor device interconnection metal.

2. The method according to claim 1, characterized in that The aging effects include HCD, BTI, and / or TDDB.

3. The method according to claim 2, characterized in that The breakdown effects include EiB, and / or TDDB.

4. The method according to claim 3, characterized in that The semiconductor device is a MOS tube, including an NMOS or PMOS circuit.

5. The method according to claim 3, characterized in that: The method comprises the following steps: S101, assuming that the expected working time of the MOS tube is T0, and the duty cycle is DF, The cumulative stress duration of the MOS tube EiB is DF*T0. The proportion of the MOS tube HCD stress in the expected working time T0 is λ, and the cumulative time of the MOS tube HCD stress is t hcd =λ*T0; S102, calculating the leakage current variation ΔI caused by the HCD stress of the MOS tube g =f(V g ,V d ,t hcd ), V g is the MOS gate voltage, V d is the MOS drain voltage, t hcd is the HCD stress accumulation time, S103, calculating the Joule heat of the MOS tube EiB stress, T joule =g(ΔI g ,V g ,Metal), ΔI g is the leakage current, V g is the gate voltage, Metal is the metal material parameter; S104, based on metal material parameters, Joule heat T joule 、Device self-heating T SHE and leakage current change ΔI g , calculate the back-end interconnect metal lifetime; S105, if the downstream metal life is greater than T crit , then the interconnect metal meets the design requirements; If the back-end interconnect metal is less than or equal to T crit , then optimize the back-end interconnect metal design.

6. The method according to claim 5, characterized in that The optimized back-end interconnect metal design includes replacing metal materials, adjusting geometric dimensions or optimizing structures.

7. The method according to claim 1, characterized in that The semiconductor device includes FinFET and GAAFET.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor runs the computer program to implement the method according to any one of claims 1 to 7.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. A computer program product, comprising a computer program, characterized in that The computer program is executed by a processor to implement the method according to any one of claims 1 to 7.

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