Chip verification system, method and device, verification equipment, medium and program

Abstract

The embodiment of the invention provides a chip verification system, method and device, verification equipment, medium and program, the chip verification system comprises a plurality of test platforms corresponding to a plurality of chips, one test platform is used for providing a simulation environment for the corresponding chip; the test platform comprises a verification object of the chip; the mapping module is connected with the verification objects in the plurality of test platforms to form a joint simulation environment of the plurality of chips, and the joint simulation environment is used for combining simulation tasks of the plurality of chips; and, in the joint simulation environment, transmitting simulation communication data between the verification objects through cross-process communication. According to the chip verification system provided by the embodiment of the invention, joint simulation verification of a plurality of chips can be supported, and the comprehensiveness of chip verification is improved.

Claims

1. A chip verification system, characterized in that: include: A plurality of test platforms corresponding to a plurality of chips, wherein one test platform is used to provide a simulation environment for a corresponding chip; the test platform includes a verification object of the chip; A mapping module connects the verification objects in the multiple test platforms to form a joint simulation environment for the multiple chips, wherein the joint simulation environment is used to combine the simulation tasks of the multiple chips; and, in the joint simulation environment, transmits simulation communication data between the verification objects through cross-process communication.

2. The chip verification system according to claim 1, characterized in that: The verification object includes a DUT module; the mapping module includes: a DUT mapping module.

3. The chip verification system according to claim 2, characterized in that: The verification object further includes: an environmental verification module; wherein an environmental verification module in a test platform is connected to a DUT module in the test platform to provide stimulus for the DUT module; The mapping module also includes: a test platform mapping module.

4. The chip verification system according to any one of claims 1 to 3, characterized in that: Also includes: The simulator is used to load the connection relationship of the mapping module to connect the verification objects and establish virtual connections between the verification objects in the multiple test platforms.

5. A chip verification method, characterized in that: The test platform applied to the chip includes: Determine simulation communication data, the simulation communication data is generated by the verification object of the chip in the test platform, and sent to the opposite verification object of the opposite test platform, the opposite verification object is the verification object of the chip in the opposite test platform; wherein the test platform and the verification object in the opposite test platform are connected through a mapping module to at least form a joint simulation environment between the chips; Performing format conversion on the simulated communication data to obtain simulated communication data with format conversion; The format-converted simulation communication data is provided to the simulator so that the simulator transmits the simulation communication data to the peer verification object of the chip in the peer test platform through the connection relationship of the verification object connected by the mapping module.

6. The chip verification method according to claim 5, characterized in that: The verification object includes a DUT module; and the determination of simulation communication data includes: The DUT communication data generated by the DUT module is determined, and the DUT communication data is sent to the opposite-end DUT module of the opposite-end test platform.

7. The chip verification method according to claim 6, characterized in that: The verification object further includes an environment verification module, wherein an environment verification module in a test platform is connected to a DUT module in the test platform to provide stimulus for the DUT module; and the determination of the simulation communication data further includes: The environmental communication data generated by the environmental verification module is determined, and the environmental communication data is sent to the peer environmental verification module of the peer test platform.

8. The chip verification method according to claim 5, characterized in that: The format conversion of the simulated communication data to obtain the simulated communication data after the format conversion comprises: The simulation communication data is serialized to convert the simulation communication data into a bit stream.

9. A chip verification device, characterized in that: The test platform applied to the chip includes: A simulation communication data determination module, used to determine simulation communication data, the simulation communication data is generated by the verification object of the chip in the test platform, and sent to the opposite verification object of the opposite test platform, the opposite verification object is the verification object of the chip in the opposite test platform; wherein the test platform and the verification object in the opposite test platform are connected through a mapping module to at least form a joint simulation environment between the chips; A data format conversion module, used for performing format conversion on the simulated communication data to obtain simulated communication data with format conversion; The data sending module is used to provide the simulated communication data with format conversion to the simulator, so that the simulator can transmit the simulated communication data to the opposite verification object of the chip in the opposite test platform through the connection relationship of the verification object connected by the mapping module.

10. A chip verification method, characterized in that: The test platform applied to the chip includes: Monitoring whether the simulation communication data sent by the peer test platform is received, the simulation communication data is generated by the peer verification object in the peer test platform, and the peer verification object is the verification object of the chip in the peer test platform; wherein the test platform and the verification object in the peer test platform are connected through a mapping module to at least form a joint simulation environment between the chips; If the simulated communication data is received from the peer test platform, the format of the simulated communication data is restored to obtain the simulated communication data with restored format, and the simulated communication data with restored format is used for the simulation task of the verification object of the chip in the test platform.

11. The chip verification method according to claim 10, characterized in that: The monitoring of whether the simulated communication data sent by the opposite test platform is received includes: By utilizing the connection relationship of the verification object loaded by the simulator, it is monitored whether the opposite-end test platform that has a connection relationship with the verification object of the test platform has sent simulation communication data.

12. The chip verification method according to claim 11, characterized in that: The verification object includes a DUT module; the monitoring of whether the opposite test platform connected to the verification object of the test platform sends the simulation communication data includes: Monitor whether the opposite test platform connected to the DUT module of the test platform sends DUT communication data.

13. The chip verification method according to claim 12, characterized in that: The verification object further includes an environment verification module, wherein the environment verification module in a test platform is connected to a DUT module in the test platform to provide stimulation for the DUT module; the monitoring of whether the opposite test platform connected to the verification object of the test platform sends simulation communication data also includes: Monitor whether the opposite-end test platform connected to the environment verification module of the test platform has sent environment communication data.

14. A chip verification device, characterized in that: The test platform applied to the chip includes: A simulation communication data monitoring module, used to monitor whether the simulation communication data sent by the peer test platform is received, wherein the simulation communication data is generated by the peer verification object in the peer test platform, and the peer verification object is the verification object of the chip in the peer test platform; wherein the test platform and the verification object in the peer test platform are connected through a mapping module to at least form a joint simulation environment between the chips; The data receiving and processing module is used to restore the format of the simulated communication data sent by the opposite test platform if it is received, so as to obtain the simulated communication data with restored format. The simulated communication data with restored format is used for the simulation task of the verification object of the chip in the test platform.

15. A verification device, characterized in that: It includes at least one memory and at least one processor, the memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the chip verification method as described in any one of claims 5 to 8, or executes the chip verification method as described in any one of claims 10 to 13.

16. A storage medium, characterized in that: The storage medium stores one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the chip verification method as described in any one of claims 5 to 8 is implemented, or the chip verification method as described in any one of claims 10 to 13 is implemented.

17. A computer program product, characterized in that It comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, it implements the chip verification method as described in any one of claims 5 to 8, or implements the chip verification method as described in any one of claims 10 to 13.

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