Method and system for improving integrated circuit layout

Abstract

The invention provides a method and a system for improving an integrated circuit layout. The method comprises the following steps: acquiring a netlist of integrated circuit (IC) design; performing an automatic placement and routing (APR) process on the netlist to generate a final layout map; in each operation of the APR process, the transport network in the generated layout map is improved at each operation of the APR process using a machine learning model.

Description

Technical Field

[0001] Embodiments of the present application relate to methods and systems for improving integrated circuit layouts. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. In semiconductor integrated circuit design, the standard cell approach is often used for the design of semiconductor devices on a chip. The standard cell approach uses standard cells as an abstract representation of certain functions to integrate millions of devices on a single chip. As integrated circuits continue to shrink, more and more devices are integrated into a single chip. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method is provided, including: obtaining a netlist of an integrated circuit (IC) design; and performing multiple operations of an automatic placement and routing (APR) process; generating a layout diagram having a power delivery network after each operation of the APR process is completed; and adjusting a portion of the power delivery network of the layout diagram using the machine learning model by inputting multiple features of the layout diagram generated in each operation of the APR process into the machine learning model.

[0004] According to another aspect of an embodiment of the present application, a method is provided, comprising: obtaining a netlist of an integrated circuit (IC) design; performing an automatic placement and routing (APR) process on the netlist to generate a final layout diagram; and during each operation in the APR process: dividing the layout diagram generated by each operation in the APR process into a plurality of grids of a fixed size; and adaptively updating a power delivery network of the layout diagram based on the grid using the machine learning model by inputting a plurality of features of each grid within the layout diagram into a machine learning model.

[0005] According to another aspect of an embodiment of the present application, a system is provided, comprising a non-transitory computer-readable medium storing program instructions; and a processor operably coupled to the non-transitory computer-readable medium, wherein the program instructions, when executed by the processor, cause the processor to perform the following operations: obtain a netlist of an integrated circuit (IC) design; and based on multiple features of the IC design, use a machine learning model to determine whether a power delivery network within a layout diagram corresponding to the IC design generated by an automatic placement and routing (APR) process is of the first type or the second type; and manufacture the integrated circuit using the layout diagram generated by the APR process. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of an IC design system 100 according to some embodiments.

[0008] Figure 2 is a functional flow diagram of at least a portion of an IC design flow 200 according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of a training process for a machine learning model for generating an adaptive power delivery network in an integrated circuit according to some embodiments of the present disclosure.

[0010] FIG. 4A to FIG. 4J is a diagram of different PDN (Power Delivery Network) structures according to some embodiments of the present disclosure.

[0011] Figure 5 is a diagram illustrating different layers on the front side and back side of a semiconductor substrate according to some embodiments of the present disclosure.

[0012] Fig. 6A is a flowchart of the inference process of a machine learning model according to some embodiments of the present disclosure.

[0013] Figure 6B It is shown Fig. 6A Diagram of the inference process of a machine learning model in .

[0014] Figure 7 is a flow chart of a process for constructing an adaptive frontside PDN within an IC layout during various operations in an APR process according to some embodiments of the present disclosure.

[0015] FIG. 8A to FIG. 8D yes Figure 7 Different perspective views of a layout diagram during different operations in process 700.

[0016] Fig. 9 is a flow chart of a process for constructing an adaptive backside PDN within an IC layout during various operations in an APR process according to some embodiments of the present disclosure.

[0017] Figure 10A to Figure 10D-3 yes Fig. 9 Different perspective views of a layout diagram during different operations in process 900.

[0018] Fig.11is a flow chart of a process for constructing an adaptive dual-sided PDN within an IC layout during various operations in an APR process according to some embodiments of the present disclosure.

[0019] Figures 12A-1 to 12D-3 yes Fig.11 Different perspectives of a layout diagram during different operations in process 1100.

[0020] Fig.13 is a flow chart of a process for constructing an optimal frontside PDN within an IC layout during an APR process according to some embodiments of the present disclosure.

[0021] FIG. 14A to FIG. 14D yes Fig.13 Different perspective views of a layout diagram during different operations in process 1300 of .

[0022] Fig.15 is a cross-section of a semiconductor structure according to some embodiments of the present disclosure.

[0023] Fig.16 is a block diagram of an IC manufacturing system and its associated IC manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0026] Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present.

[0027] The embodiments or examples shown in the drawings are disclosed as follows using specific language. However, it should be understood that the embodiments and examples are not intended to be limiting. Any changes or modifications in the disclosed embodiments, as well as any further applications of the principles disclosed herein, are generally contemplated by those of ordinary skill in the relevant art.

[0028] Furthermore, it will be appreciated that several processing steps and / or features of the device are only briefly described. Furthermore, additional processing steps and / or features may be added, and certain of the following processing steps and / or features may be deleted or altered while still implementing the present disclosure. Therefore, it will be appreciated that the following description represents examples only and does not imply that one or more steps or features are required.

[0029] In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0030] In integrated circuit (IC) design, various functions are integrated into a single chip, usually using an application specific integrated circuit (ASIC) or system on chip (SOC) cell based design. In this approach, a library of known functions is provided, and after specifying the functional design of the device by selecting and connecting these standard functions, and verifying the correct operation of the resulting circuit using electronic design automation (EDA) tools, the library elements are mapped onto predefined layout cells containing preconfigured components such as transistors. The cells are selected keeping in mind the specific semiconductor process node and parameters, and a process parameterized physical representation of the design is created. The design flow continues from the point where the local and global connections required to form the complete design layout are placed and routed using standard cells.

[0031] After the layout is completed, various analysis procedures are performed to verify whether the layout violates various constraints or rules. For example, design rule checking (DRC), layout and schematic (LVS) and electrical rule checking (ERC) are performed. DRC is the process of checking whether the layout successfully completes the physical measurement space according to the design rules, and LVS is the process of checking whether the layout conforms to the corresponding circuit diagram. In addition, ERC is the process of checking whether the device and the wiring / network are electrically connected well. After design rule checking, design rule verification, timing analysis, critical path analysis, static and dynamic power analysis, and final modifications to the design, the offline process is performed to generate photomask generation data. Then, the photomask generation (PG) data is used to create a photomask, which is used to manufacture semiconductor devices in the lithography process at the wafer fabrication facility (FAB). In the offline process, the database file of the IC is used to make various mask layers for integrated circuit manufacturing. In some embodiments, the database file is a graphic database system (GDS) file (e.g., a GDS file or a GDSII file). In addition, the GDS file is an industry standard format for transmitting IC layout data between design tools of different suppliers.

[0032] Figure 1 is a block diagram of an IC design system 100 according to some embodiments. According to one or more embodiments, the method for designing an IC layout and adaptively generating a power delivery network described herein can be implemented, for example, using the IC design system 100 according to some embodiments. In some embodiments, the IC design system 100 is an APR (automatic placement and routing) system, includes an APR system, or is part of an APR system, and can be used to perform an APR method.

[0033] In some embodiments, IC design system 100 is a general-purpose computing device including hardware processor 102 and memory 104. Memory 104 is a non-transitory computer-readable storage medium. Among other things, memory 104 encodes (i.e., stores) computer program code 1041 (i.e., a set of executable instructions). The execution of computer program code 1041 by hardware processor 102 represents (at least in part) an EDA tool that implements part or all of a method (e.g., processes 200, 300, 700, 900, 1100, and 1300 described later) (hereinafter referred to as the process and / or method).

[0034] The processor 102 is electrically coupled to the memory 104 via the bus 108. The processor 102 is also electrically coupled to the I / O interface 110 via the bus 108. The network interface 112 is also electrically connected to the processor 102 via the bus 108. The network interface 112 is connected to the network 114 so that the processor 102 and the memory 104 can be connected to external elements via the network 114. The processor 102 is configured to execute the computer program code 1041 encoded in the memory 104 so that the IC design system 100 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit, but the present disclosure is not limited thereto.

[0035] In one or more embodiments, the memory 104 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system (or device or apparatus). For example, the memory 104 may be or include a non-volatile memory such as a semiconductor or solid-state memory, a hard disk drive (HDD), a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a rigid disk, an optical disk, an SD memory card, a memory stick, a ferroelectric random access memory (FeRAM), a resistive random access memory (RRAM), etc., but the present disclosure is not limited thereto. In one or more embodiments using optical disks, the memory 104 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W) and / or a digital video disk (DVD).

[0036] In one or more embodiments, the memory 104 stores computer program code 1041 configured to enable the IC design system 100 (where such execution represents (at least in part) an EDA tool) to perform part or all of the described processes and / or methods. In one or more embodiments, the memory 104 also stores information that facilitates the performance of part or all of the described processes and / or methods. In one or more embodiments, the memory 104 includes an IC design memory 1042 that is configured to store one or more IC layout drawings, such as those later described with respect to FIG. FIG. 8A to FIG. 8D , Figure 10A to Figure 10D-3 , Figures 12A-1 to 12D-3 and FIG. 14A to FIG. 14D Discussed IC layouts 702-708, 902-908, 1102-1108, 1400A-1400D.

[0037] IC design system 100 includes an I / O interface 110. I / O interface 110 is coupled to external circuits. In one or more embodiments, I / O interface 110 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to processor 102.

[0038] In some embodiments, the IC design system 100 also includes a network interface 112 coupled to the processor 102. The network interface 112 allows the IC design system 100 to communicate with a network 114 to which one or more other computer systems are connected. In some embodiments, the network interface 112 includes a wireless network interface and / or a wired network interface. The wireless network interface may include Wi-Fi (802.11), Global System for Mobile Communications (GSM), Enhanced Data Rate GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Fourth Generation (4G), Fifth Generation (5G), Sixth Generation (6G), Ultra Wideband (UWB), Infrared (IR) Protocol, Near Field Communication (NFC) Protocol, Wibree, Bluetooth Protocol, Wireless Universal Serial Bus (USB) Protocol, etc. The wired network interface may include Ethernet, Universal Serial Bus (USB), Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), etc., but the present disclosure is not limited thereto. In one or more embodiments, part or all of the process and / or method is implemented in two or more IC design systems 100.

[0039] In some embodiments, the IC design system 100 is configured to receive information through the I / O interface 110. The information received through the I / O interface 110 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters processed by the processor 102. The information is transmitted to the processor 102 through the bus 108. The IC design system 100 is configured to receive information related to a user interface through the I / O interface 110. The information is stored in the memory 104 as a user interface (UI) 1043.

[0040] In some embodiments, the cell library 1044 can be configured to store a plurality of standard cells and / or circuit elements that can be used in the APR process. In some embodiments, the machine learning model 1045 can be configured to generate an adaptive power delivery network on the front side, back side, or both sides (i.e., including the front side and the back side) of the semiconductor substrate based on the power grid. For example, the processor 102 can execute the machine learning model 1045 to adaptively modify the power delivery network on the layout diagram after each operation or stage in the APR process (which may include floorplanning, cell placement, clock tree synthesis, routing, post-routing optimization, etc.), which power delivery network may be a front-side, back-side, or double-side PDN. Reference will be made to the following embodiments. Figures 2 to 14D Describe further details.

[0041] In some embodiments, the machine learning model 1046 may be configured to generate an optimal front-side power delivery network on the front-side of the semiconductor substrate based on one or more design parameters of a given IC layout.

[0042] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an add-on software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by IC design system 100. In some embodiments, the IC design system 100 is implemented using a software application such as available from CADENCEDESIGN SYSTEMS, INC. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0043] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM, RAM, a memory card, etc.).

[0044] IC design flow with power delivery network improvement phase

[0045] Figure 2 1 is a functional flow chart of at least a portion of an IC design flow 200 according to some embodiments of the present disclosure. Design flow 200 utilizes one or more electronic design automation (EDA) tools (e.g., computer program code 1041) to generate, optimize, and / or verify the design of an IC before manufacturing the IC. In some embodiments, an EDA tool is a set of one or more sets of executable instructions for execution by a processor (e.g., processor 102) or a controller or a programmed computer to perform the indicated functions. In at least one embodiment, IC design flow 200 is a flow chart of at least a portion of an IC design flow 200 described herein. Fig.16 Discuss the IC manufacturing systems implemented by a design company.

[0046] At IC design operation 210, the design of the IC is provided by a circuit designer. In some embodiments, the design of the IC includes an IC schematic, i.e., a circuit diagram, of the IC. In some embodiments, the schematic is generated or provided in the form of a schematic netlist (such as a SPICE netlist). Other data formats for describing the design are available in some embodiments. In some embodiments, a pre-layout simulation is performed on the design to determine whether the design meets predetermined specifications. When the design does not meet predetermined specifications, the IC is redesigned. In at least one embodiment, the pre-layout simulation is omitted.

[0047] In some embodiments, processor 102 may execute one or more computer program codes (e.g., EDA tools or APR tools) to perform an APR process to construct a floorplan of the IC design. The APR process may include operations 221, 222, 223, 224, and 225, which are floorplanning, cell placement, clock tree synthesis, routing, and post-routing optimization, respectively.

[0048] In automatic placement and routing (APR) operation 220, a layout diagram of the IC is generated based on the IC schematic. The IC layout diagram includes the physical locations of various circuit elements of the IC and the physical locations of various networks that interconnect the circuit elements. For example, the IC layout diagram is generated in the form of a graphic design system (GDS) file. Other data formats for describing IC designs are within the scope of various embodiments. Figure 2 In the example configuration of , the IC layout diagram is generated by an EDA tool such as an APR tool. The APR tool (e.g., computer program code 1041) receives an IC design in the form of a netlist as described herein. Figure 2 In the example configuration of FIG. 2 , the APR tool performs floorplanning operations 221, cell placement operations 222, clock tree synthesis operations 223, routing operations 224, and post-routing optimization operations 225. In addition, the APR operation 220 is performed in conjunction with a PDN improvement phase 240, which includes a PDN planning operation 241 and PDN improvement operations 242 to 245. In some embodiments, the PDN improvement phase 240 may be performed by Figure 1 The illustrated machine learning model 1045 performs to improve the PDN within the layout graph generated by each operation 221 to 225 in the APR operation 220 to meet the IR requirements of the integrated circuit with better PPA (performance, power and area). Further details thereof will be described.

[0049] At floorplanning operation 221, the APR tool identifies circuit elements and / or standard cells that are to be electrically connected to each other and placed close to each other to reduce the area of ​​the IC and / or reduce time delays of signals propagating on interconnects or nets connecting the electrically connected circuit elements. In some embodiments, the APR tool performs partitioning to partition the design of the IC into multiple blocks or groups, such as clock groups and logic groups.

[0050] In the PDN planning operation 241, the APR tool or the machine learning model 1045 performs power planning based on the partitioning and / or floor plan of the semiconductor substrate of the IC design to generate an initial power delivery network (such as a grid structure) including several conductive layers (such as metal layers). Depending on the preset type of the machine learning model 1045 used, the initial power delivery network can be sparse or dense, and can be set on the front side, back side, or both sides (i.e., including the front side and the back side) of the semiconductor substrate.

[0051] At cell placement operation 222, the APR tool performs cell placement. For example, standard cells configured to provide predefined functions and having pre-designed layouts are stored in a cell library 1044. The APR tool accesses various standard cells from the cell library 1044 and places these standard cells in an adjacent manner to generate an IC layout corresponding to the IC schematic.

[0052] In some embodiments, the IC layout diagram (e.g., the first IC layout diagram) generated by the cell placement operation 222 includes a power grid structure and a plurality of standard cells (or simply "cells"), each of which includes one or more circuit elements and / or one or more networks. Circuit elements may be active elements or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc., FinFETs, planar MOS transistors with convex source / drains, etc. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. Examples of networks include, but are not limited to, vias, conductive pads, conductive traces, and conductive redistribution layers, etc. In some embodiments, each standard cell may be a macro including one or more logic gates. Examples of macros including a logic gate may be NAND (NAND), NOR (NOR), XOR (exclusive OR), XOR gates, etc. Examples of a macro including a plurality of logic gates or CMOS compound gates may be a 2-bit full adder, a D flip-flop, a latch, a buffer, and / or an AND-OR-Inverter (AOI), or an AND-Inverter (OAI), and the like.

[0053] The IC layout diagram generated by the cell placement operation 222 is improved by the PDN improvement operation 242. For example, at the PDN improvement operation 242, the processor 102 can execute the machine learning model 1045 to perform an inference process (e.g., a first inference process) using the IC layout diagram generated by the cell placement operation 222, so as to alternate the distribution of the conductive layer and the position of the standard cells in each grid of the power density network according to the characteristics of the standard cells within each grid of the layout diagram to generate an improved IC layout diagram with better PPA (e.g., an improved first IC layout diagram). For example, the characteristics of the standard cells within each grid of the layout diagram may include, but are not limited to, power density, cell drive, cell function, switching rate, routing congestion, pin density, timing critical path, etc., but the present disclosure is not limited thereto. The improved IC layout diagram generated by the PDN improvement operation 242 is sent to the APR tool for clock tree synthesis (CTS).

[0054] At clock tree synthesis operation 223, the APR tool performs clock tree synthesis to minimize clock skew and / or delay that may exist due to the placement of standard cells in the IC layout diagram generated by the PDN improvement operation 242. Clock tree synthesis may include an optimization process to ensure that signals are transmitted and / or arrive with proper timing. For example, during the optimization process within the clock tree synthesis, the APR tool may insert one or more vias into the IC layout diagram to add and / or eliminate slack (timing of signal arrival), and / or insert one or more clock buffers into the IC layout diagram to achieve the desired clock timing. Thus, another IC layout diagram (e.g., a second IC layout diagram) is generated by clock tree synthesis operation 223.

[0055] The IC layout generated by the clock tree synthesis operation 223 is improved by the PDN improvement operation 243. For example, at the PDN improvement operation 243, the processor 102 may execute the machine learning model 1045 to perform another inference process (e.g., a second inference process) using the IC layout generated by the clock tree synthesis operation 223, thereby alternating the distribution of the conductive layer in each grid of the power density network and the position of the standard cell according to the characteristics of the standard cell within each grid of the layout to generate an improved IC layout with better PPA (e.g., an improved second IC layout). The improved IC layout generated by the PDN improvement operation 243 is sent to the APR tool for routing.

[0056] At the routing operation 224, the APR tool performs routing to route various networks (e.g., wires) that interconnect the placed standard cells. Routing is performed to ensure that the interconnections or networks of the routing meet a set of constraints. For example, the routing operation 224 includes global routing, track allocation, and detailed routing. During the global routing process, routing resources for the interconnections or networks are allocated. For example, the routing area is divided into a plurality of sub-areas, the pins of the placed standard cells are mapped to the sub-areas, and the network is constructed as a collection of sub-areas in which the interconnections are physically routable. During the track allocation process, the APR tool assigns the interconnections or networks to the corresponding conductive layers of the IC layout diagram. During the detailed routing process, the APR tool routes the interconnections or networks within the specified conductive layers and global routing resources. For example, detailed physical interconnections are generated in the collection of corresponding sub-areas defined at the global routing and the conductive layers defined at the track allocation. After the routing operation 224, the APR tool outputs an IC layout diagram (e.g., a third IC layout diagram) including a power grid structure, placed standard cells, and a routing network. The described APR tool is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more operations described are omitted.

[0057] The IC layout generated by the routing operation 224 is further improved by the PDN improvement operation 244. For example, at the PDN improvement operation 244, the processor 102 can execute the machine learning model 1045 to perform another inference process (e.g., a third inference process) using the IC layout generated by the routing operation 224, thereby alternating the distribution of the conductive layer in each grid of the power density network and the position of the standard cell according to the characteristics of the standard cell within each grid of the layout diagram to generate an improved IC layout with better PPA (e.g., an improved third IC layout diagram). The improved IC layout generated by the PDN improvement operation 244 is sent to the APR tool for post-routing optimization.

[0058] In some embodiments, the post-routing optimization operation 225 can be considered a sign-off operation. At the post-routing optimization operation 225, one or more physical and / or timing verifications are performed. For example, the post-routing optimization operation 225 includes one or more of resistance and capacitance (RC) extraction, layout and schematic (LVS) checking, design rule checking (DRC), and timing sign-off checking (also known as post-layout simulation). Other verification processes can be used in other embodiments.

[0059] In some embodiments, the EDA tool performs RC extraction to determine parasitic parameters of components in the IC layout, such as parasitic resistance and parasitic capacitance, for timing simulation in subsequent operations.

[0060] In some embodiments, an LVS check tool (e.g., one of the EDA tools) can perform an LVS check to ensure that the generated IC layout diagram corresponds to the design of the IC. Specifically, the LVS check tool identifies electrical components and connections from the pattern of the generated IC layout diagram, and then generates a layout netlist representing the identified electrical components and connections. The LVS check tool compares the layout netlist generated by the IC layout diagram with the schematic netlist of the IC design. If the two netlists match within a certain tolerance, the LVS check is passed. Otherwise, the IC layout diagram and / or the design of the IC is corrected, and the process returns to the IC design operation 210 and / or the APR operation 220.

[0061] In some embodiments, a DRC tool (e.g., one of the EDA tools) can perform DRC to ensure that the IC layout diagram meets certain manufacturing design rules, thereby ensuring the manufacturability of the IC. If any design rules are violated, the IC layout diagram and / or the design of the IC are corrected, and the process returns to the IC design operation 210 and / or the APR operation 220. Examples of design rules include, but are not limited to, width rules that specify the minimum width of a pattern, spacing rules that specify the minimum spacing between adjacent patterns, area rules that specify the minimum area of ​​a pattern in the IC layout diagram, and the like. In some embodiments, at least one design rule is voltage-dependent. A DRC that is used to check whether an IC layout diagram complies with one or more voltage-dependent design rules is referred to as a VDRC.

[0062] In some embodiments, the EDA tool performs a timing sign-off check (post-layout simulation) using the extracted parasitic parameters to determine whether the IC layout diagram meets the predetermined specifications of one or more timing requirements. If the simulation shows that the IC layout diagram does not meet the predetermined specifications, such as the parasitic parameters causing unexpected delays, at least one of the IC layout diagram or the IC design is corrected by returning the process to the IC design operation 210 and / or the APR operation 220. Otherwise, the IC layout diagram is improved by the PDN improvement operation 245.

[0063] At the PDN improvement operation 245, the processor 102 may execute the machine learning model 1045 to perform another inference process (e.g., a fourth inference process) using the IC layout generated by the post-routing optimization operation 225, thereby alternating the distribution of the conductive layer in each grid of the power density network and the position of the standard cell according to the characteristics of the standard cell within each grid of the layout to generate an improved IC layout with improved PPA (e.g., an improved fourth IC layout). The improved IC layout can then be passed to a manufacturing process or an additional verification process.

[0064] In some other methods, power analysis is performed after the routing operation 224, such as during the post-routing optimization operation 225. If the power analysis results do not meet the design specifications, the power delivery network that supplies power to the standard cells in the IC layout will be redesigned or modified. This in turn may result in changes in cell placement and / or routing, which may result in longer turnaround times. These disadvantages can be avoided in some embodiments described herein.

[0065] In some embodiments, operations 241 to 245 within the power delivery network improvement phase 240 may improve the IC layout generated at each phase of the APR process 220 on a grid basis, thereby allowing the improved IC layout generated at each phase to meet IR (current-resistance) requirements (e.g., including power-consuming cells, IR hot spots, etc.) with better PPA. For example, the PDN improvement operation 242 may adaptively improve the IC layout generated at the cell placement operation 222, and the improved IC layout may include an adaptive PDN having a dense PDN for a grid with a high density of power-consuming cells and a sparse PDN for a grid with a low density of cells. In addition, the PDN improvement operation 243 may adaptively improve the IC layout generated at the clock tree synthesis operation 223, and the improved IC layout may include another adaptive PDN to address IR hot spots caused by a new clock buffer added by the clock tree synthesis operation 223.

[0066] The training process of machine learning models

[0067] Figure 3 is a flow chart of a training process for a machine learning model for generating an adaptive power delivery network in an integrated circuit according to some embodiments of the present disclosure. Figure 3 The method may include other operations not shown here, and various illustrated operations of the method may be performed in an order different from the order shown. Figure 3 The method may be executed by one or more processing devices within a computing device.

[0068] In some embodiments, Figure 3 The process 300 shown in FIG. Figure 2 2. The training process of the machine learning model 1045 of the APR operation 220 shown in FIG. In operation 310, a plurality of PnR (placement and routing) databases are obtained. For example, the PnR database may include a plurality of IC layout diagrams of one or more IC designs, as well as PDN factors and design factors. The PDN factors may include PDN type, PDN structure, and PDN density.

[0069] In some embodiments, the PDN type may refer to whether the PDN is located on the front side, back side, or both sides of the semiconductor substrate within each PnR database. The PDN structure may refer to the arrangement of the PDN and the wiring, such as FIG. 4A to FIG. 4J The PDN density may include dense PDN or sparse PDN. When the PDN is a dense PDN, it indicates a relatively large number of wires in a unit area. On the other hand, when the PDN is a sparse PDN, it indicates a relatively small number of wires in a unit area. In addition, a predetermined density threshold may be set to distinguish between dense PDN and sparse PDN.

[0070] In some embodiments, design factors may include operating frequency, design style, wiring congestion, pin density and utilization. For example, the operating frequency may refer to the frequency at which a functional circuit (e.g., a standard cell) formed on a semiconductor substrate operates, such as 100MHz, 5GHz, etc. The design style may be related to the functions of an IC layout diagram, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), a system on a chip (SoC), etc. Cell drive may refer to the cell drive capability of a standard cell in an IC layout diagram. Wiring congestion may refer to the wiring congestion level of an IC layout diagram, such as high, medium, or low. Pin density and utilization may be mutually influential. For example, a high pin density indicates a high utilization, while a low pin density indicates a low utilization. In some embodiments, the pin density and utilization of each IC layout diagram may be collectively referred to as a design factor. Alternatively, the pin density and utilization of each IC layout diagram may be considered as separate design factors.

[0071] In operation 320, each PnR database is decomposed into a plurality of grids. For example, the grids may have the same size and they may be Figure 2 The APR is shown fixed during operation 220 .

[0072] In operation 330, each grid is characterized using a corresponding combination of different features. For example, these features may include, but are not limited to, power density, cell drive, cell function, switching rate, routing congestion, pin density, and timing critical path. For example, most of the features (power density, cell drive, switching rate, congestion, pin density, and critical path) can be divided into three levels. For example, each of power density, switching rate, congestion, pin density, and critical path can be divided into three levels, such as high, medium, and low. In addition, cell drive can also be divided into three levels, such as strong, medium, and weak. Since each grid can include one or more standard cells, the cell function can refer to the type of logic gate within each grid, such as inverter, NAND, NOR, D flip-flop, etc.

[0073] In operation 340, the first feature of each PnR database and the second feature of each grid are classified. For example, the first feature may refer to the performance, power, and area, collectively referred to as PPA, of each PnR database. The second feature may refer to the cell (e.g., the type of logic gate), line delay, and line length in each grid.

[0074] In operation 350, the machine learning model 1045 is trained using the PnR database, the predetermined features of each grid, the first features of each PnR database, and the second features of each grid. For example, after the training process is completed, Figure 2 The APR operation 220 shown uses the trained machine learning model 1045 to adaptively adjust the PDN within the IC layout based on the grid. In some embodiments, the machine learning model 1045 can be a K-nearest neighbor (KNN) model or any other classification machine learning model, but the present disclosure is not limited thereto.

[0075] FIG. 4A to FIG. 4J is a diagram of different PDN structures according to some embodiments of the present disclosure.

[0076] In some embodiments, reference Figure 4A , the PDN structure within the grid 410A may be referred to as a "strip" or "strip" structure. For example, the grid 410A may include a first track 414 extending along a first direction (e.g., a horizontal direction) and a second track 415 extending along a second direction different from the first direction (e.g., a vertical direction). In addition, the first track 414 is parallel and evenly distributed along the second direction, while the second track 415 is parallel and evenly distributed along the first direction. The PDN within the grid 410A is formed by a plurality of strips 411, each of which extends from a first edge (e.g., an upper edge) of the grid 410A to a second edge (e.g., a lower edge), wherein the first edge is opposite to the second edge. The routing network within the grid 410A is formed by a plurality of strips 412, each of which extends from a third edge (e.g., a left edge) of the grid 410A to a fourth edge (e.g., a right edge) opposite to the third edge, wherein the third edge is opposite to the fourth edge. In addition, one or more through-holes 413 may be formed at the intersection between the PDN and the routing network.

[0077] In some embodiments, Figure 4B The grid 410B shown may be similar to Figure 4A The grid 410A shown is different in that Figure 4B The distance D2 between two adjacent bands 411 is greater than Figure 4A The distance D1 between two adjacent bands 411 in the grid 410A and the distance D2 between two adjacent bands 411 in the grid 410A and the distance D2 between two adjacent bands 411 in the grid 410B are D1 and D2, respectively.

[0078] In some embodiments, reference Figure 4C , the PDN structure within the grid 420A may be referred to as a “long column” structure. Figure 4C The tracks 424 and 425 shown may be similar to Figure 4A Tracks 414 and 415 shown. The PDN within the grid 420A is formed by multiple pairs of posts 421A and 421B, each pair of posts being located on a respective track 425. Each post 421A is slightly larger than each post 421B. In addition, the routing network within the grid 420A is formed by multiple short posts 422, each short post 422 having a length less than or equal to the interval between two adjacent tracks 425. The posts 421A and 421B can be arranged in a staggered manner and placed across several intervals between two adjacent first tracks 424. In addition, one or more through-holes 423 can be formed at the intersection between the PDN and the routing network. Since the long posts 421A and 421B are placed on the same track 425 and aligned, the PDN within the grid 420A can also be considered a "long aligned post" structure.

[0079] In some embodiments, Figure 4D The grid 420B shown may be similar to Figure 4C The grid 420A shown is different in that Figure 4D The distance D2 between two adjacent bands 421 is greater than Figure 4C The spacing D1 between two adjacent strips 421 is shown in FIG. Specifically, the PDN structures in the grids 420A and 420B can be referred to as a dense long column structure and a sparse long column structure, respectively.

[0080] In some embodiments, reference Figure 4E , the PDN structure within the grid 430A may be referred to as a “short pillar” structure. Figure 4E The tracks 434 and 435 shown in FIG. 4 can be similar to Figure 4A 430A. The PDN within the grid 430A is formed by a plurality of posts 431 arranged in a staggered manner, and the length of each post 431 is less than or equal to the interval between two adjacent tracks 434. For example, three posts 431 are arranged on the same track 435, and two posts 431 are arranged on another track 435. In addition, the routing network within the grid 430A is formed by a plurality of short posts 432, and the length of each short post 432 is less than or equal to the interval between two adjacent tracks 435. Since the short posts 431 are placed on the same track 435 and aligned, the PDN within the grid 430A can also be regarded as a "short aligned post" structure.

[0081] In some embodiments, Figure 4F The grid 430B shown may be similar to Figure 4E The grid 430A shown is different in that Figure 4FThe distance D2 between two adjacent columns 431 is greater than Figure 4E The distance D1 between two adjacent pillars 431 is shown in FIG. Specifically, the PDN structures in the grids 430A and 430B can be referred to as a dense short pillar structure and a sparse short pillar structure, respectively.

[0082] In some embodiments, reference Figure 4G , the PDN structure within the grid 440A may be referred to as a “long staggered column” structure. Figure 4G The tracks 444 and 445 shown in FIG. 4 can be similar to Figure 4A 41 and 415 shown in FIG. 4. The PDN within the grid 440A is formed by a plurality of posts 441 arranged in a staggered manner, each post 441 being placed across a number of intervals between two adjacent tracks 444. For example, the leftmost post 441 is disposed on the upper side of its corresponding track 445, while the next post 441 is disposed on the lower side of its corresponding track 445. In other words, the long posts 441 are placed on different tracks 445 in a staggered manner. In addition, the routing network within the grid 440A is formed by a plurality of short posts 442, each of which has a length less than or equal to the interval between two adjacent tracks 445.

[0083] In some embodiments, Figure 4H The grid 440B shown may be similar to Figure 4G The grid 440A shown is different in that Figure 4H The distance D2 between two adjacent columns 441 is greater than Figure 4G The distance D1 between two adjacent pillars 441 is shown in FIG. Specifically, the PDN structures in the grids 440A and 440B can be referred to as a dense long staggered pillar structure and a sparse long staggered pillar structure, respectively.

[0084] In some embodiments, reference Fig. 4I , the PDN structure within the grid 450A may be referred to as a “short staggered column” structure. Fig. 4I The tracks 454 and 455 shown in FIG. 4 may be similar to Figure 4A 414 and 415 are shown in FIG. The PDN within the grid 450A is formed by a plurality of posts 451 arranged in a staggered manner, and the length of each post 451 is less than or equal to the interval between two adjacent tracks 454. For example, the posts 441 are arranged on different tracks 455. In addition, the routing network within the grid 450A is formed by a plurality of short posts 452, and the length of each short post 452 is less than or equal to the interval between two adjacent tracks 445.

[0085] In some embodiments, Figure 4J The grid 450B shown may be similar to Fig. 4I The grid 450A shown is different in that Figure 4JThe distance D2 between two adjacent columns 451 is greater than Fig. 4I The spacing D1 between two adjacent pillars 451 is shown in FIG. Specifically, the PDN structures in the grids 450A and 450B can be referred to as a dense short pillar structure and a sparse short pillar structure, respectively.

[0086] Figure 5 is a diagram illustrating different layers on the front side and back side of a semiconductor substrate according to some embodiments of the present disclosure.

[0087] In some embodiments, the semiconductor substrate 510 may have a front side 510s1 and a back side 510s2. The IC layout generated in operations 223 to 225 may include multiple front side layers and / or multiple back side layers. The front side layer may include M0 (metal layer 0), VIA0 (via layer 0), M1 (metal layer 1), VIA1 (via layer 1), M2 (metal layer 2), etc. formed on the front side 510s1 of the semiconductor substrate 510. For the purpose of description, M15 (metal layer 15) is the topmost metal layer (e.g., Mtop). Similarly, the back side layer may include B_M0 (back side metal layer 0), B_VIA0 (back side via layer 0), B_M1 (back side metal layer 1), B_RV (back side redistribution via), B_RDL (back side redistribution layer), etc. formed on the back side 510s2 of the semiconductor substrate 510. For ease of description, B_M15 is the bottommost back side metal layer or the topmost back side metal.

[0088] In some embodiments, the standard cell may be disposed between layers M0 to M2 on the front side 510s1 of the semiconductor substrate 510 within the IC layout. When a front-side PDN is adopted on the front side 510s1 of the semiconductor substrate 510 within the IC layout, the conductive lines of the front-side PDN may be distributed within layers M0 to M15 (Mtop). When a back-side PDN is adopted on the back side 510s2 of the semiconductor substrate 510 within the IC layout, the conductive lines of the back-side PDN may be distributed within back-side layers B_M0 to B_M15 (BMtop). In addition, when a double-sided PDN is adopted in the IC layout, it means that both the front-side PDN and the back-side PDN are adopted. As a result, the conductive lines of the double-sided PDN may be distributed within layers M0 to M15 and B_M0 to B_M15.

[0089] More specifically, FIG. 4A to FIG. 4E The pillars of the PDN and the pillars of the routing network within the PDN structure shown are not necessarily within the same metal layer. The PDN and the routing network may be electrically connected by one or more vias formed at the intersections between them, depending on the arrangement of the EDA tool.

[0090] The inference process of machine learning models

[0091] Fig. 6Ais a flowchart of the inference process of a machine learning model according to some embodiments of the present disclosure. Figure 6B It is shown Fig. 6A Diagram of the inference process of a machine learning model in .

[0092] In some embodiments, Fig. 6A Flow 600 in FIG. 1 shows various operations in the inference process of the machine learning model 1045. In operation 602, a plurality of graphs 611 to 617 associated with various predetermined features of the IC layout graph are obtained. For example, the predetermined features may include power density, cell drive, cell function, switching rate, congestion, pin density, and timing critical path. Therefore, Figure 6B The diagrams 611 to 617 shown in the figure can be respectively called power density diagram, unit drive diagram, unit function diagram, switching rate diagram, congestion diagram, pin density diagram, and timing critical path diagram. It should be noted that the size of these diagrams 611 to 617 can be substantially the same as the size of the IC layout diagram.

[0093] In operation 604, the IC layout diagram and each diagram associated with a corresponding predetermined feature are divided into a plurality of grids. Figure 6B As shown in operation block 604 in FIG. 611 to 617, the diagrams 611 to 617 may be divided into grids 6111, 6121, 6131, 6141, 6151, 6161, and 6171, respectively. In addition, each grid of the IC layout diagram may have a fixed size, and the grid division within the IC layout diagram may be performed in a fixed size. Figure 2 The APR operation 220 period shown remains the same.

[0094] In operation 606, the features of each grid are extracted. For example, each grid in the figure can represent different features of each grid in the IC layout diagram. For example, the grid 6171 enlarged in operation block 606 may include multiple features, each feature representing the level of a corresponding predetermined feature (e.g., including power density, cell drive capability, cell switching rate, wiring congestion, pin density, timing critical path) or an actual standard cell (e.g., XOR, NAND, D flip-flop, etc.) used by the corresponding predetermined feature (e.g., for cell function). For example, the level of predetermined features (such as power density, cell drive capability, cell switching rate, wiring congestion, pin density, timing critical path) can be divided into high, medium or low (weak). For the purpose of description, features 621 to 627 within grid 6171 may refer to low power density, weak cell drive, NAND cell, high switching rate, high congestion, high pin density and low timing critical path, respectively.

[0095] In operation 608, based on the extracted features of each grid, the PDN structure of each grid in the IC layout is inferred using the machine learning model 1045 to generate an adaptive PDN. For example, using a PnR database (e.g., Figure 1 The machine learning model 1045 is trained based on the features of each grid in various layout drawings in the IC design storage 1042 in the IC design storage 1042, so that the inference process of the machine learning model 1045 can be performed on a grid basis. Therefore, the machine learning model 1045 can predict the most suitable PDN structure for each grid based on the extracted features of each grid to generate an adaptive PDN for the IC layout drawing.

[0096] For example, the combination of different features of each grid can be viewed as a vector, which can be mapped to corresponding coordinates in a multidimensional space. For simplicity, Figure 6B A two-dimensional plane is shown in operation block 608 in . The machine learning model 1045 can be a K nearest neighbor (KNN) model that identifies the K nearest neighbors of a given data point from a training set and assigns the label of the majority class in the neighbors to the data point. In addition, the KNN model can evaluate the input graph and segment features to determine the distance between the input point (e.g., point 6081) and the pre-trained classification point. Therefore, the trained machine learning model 1045 (e.g., the trained KNN model) is able to classify each grid based on the extracted features and generate a suitable PDN structure.

[0097] In some embodiments, for different types of PDNs, such as front-side PDN, back-side PDN, and double-side PDN, there may be three basic groups 631, 632, and 633. In addition, each of the basic groups 631 to 633 may include six subgroups, such as subgroups 6311 to 6316, 6321 to 6326, and 6331 to 6336, respectively. The subgroups 6311 to 6316, 6321 to 6326, and 6331 to 6336 may refer to dense strips, sparse strips, dense short columns, sparse short columns, dense long columns, and sparse long column structures, respectively. Figure 4A , Figure 4B , Figure 4E , Figure 4F , Figure 4C and Figure 4D In some embodiments, in addition to the above six PDN structures, more subgroups may be used in each basic group, for example Figure 4G to Figure 4JThe densely aligned long pillars, sparsely aligned long pillars, densely aligned short pillars, and sparsely aligned short pillar structures are shown. More specifically, the PDN structures can be classified by the length of the wires (e.g., dense strips, sparse strips, dense short pillars, sparse short pillars, dense long pillars, and sparse long pillar structures) or by the alignment of the wires (e.g., dense strips, sparse strips, densely aligned long pillars, sparsely aligned long pillars, densely aligned short pillars, and sparsely aligned short pillar structures).

[0098] In operation 610, the generated adaptive PDN is used to update the PDN within the IC layout diagram. For example, the inferred (or predicted) PDN structure of each grid can form an adaptive PDN, and the PDN of each grid in the IC layout diagram can be replaced with the inferred PDN structure of each grid. In other words, the machine learning model 1045 can adaptively update the power delivery network in the IC layout diagram using the inferred PDN structure of each grid.

[0099] Figure 7 is a flow chart of a process for constructing an adaptive front-side PDN within an IC layout during various operations in an APR process according to some embodiments of the present disclosure. FIG. 8A to FIG. 8D yes Figure 7 Different perspective views of a layout diagram during different operations in process 700.

[0100] In some embodiments, Figure 7 The process 700 shown in FIG. 7 can be similar to Figure 2 2, except that flow 700 is specifically used to construct an adaptive front side (FS) PDN within an IC layout. For example, each of operations 222 to 225 is followed by a corresponding PDN improvement operation for the front side PDN (eg, operations 242 to 245).

[0101] At floorplanning operation 221 , the APR tool may perform floorplanning on an input IC design (eg, an IC schematic) to generate a layout diagram 221L, such as Fig. 8A 810 shown in . At PDN planning operation 241, the APR tool or machine learning model 1045 performs power planning based on the partitioning and / or floorplanning of the layout diagram 221L to generate a layout diagram 702 having an initial front-side power delivery network (including metal lines 801). In some embodiments, according to predefined settings of the APR tool, a sparse type or a dense type of initial power delivery network can be set on the front side 810s1 of the semiconductor substrate 810. For simplicity, the initial power delivery network is a sparse PDN.

[0102] At the cell placement operation 222, the APR tool places one or more standard cells 820 on the front side 810s1 of the semiconductor substrate 810 to generate a layout diagram 222L. For example, standard cells 820 configured to provide predefined functions and having pre-designed layout diagrams are stored in a cell library 1044. The APR tool accesses various standard cells from the cell library 1044 and places these standard cells in an adjacent manner to generate an IC layout diagram corresponding to the IC schematic. At the PDN improvement operation 242, the processor 102 can execute the machine learning model 1045 to perform an inference process (e.g., a first inference process) using the layout diagram 222L to generate a layout diagram 704 with an adaptive front-side PDN, such as Figure 8B shown.

[0103] At clock tree synthesis operation 223, the APR tool performs clock tree synthesis on floorplan 704 to generate floorplan 223L. For example, during optimization within clock tree synthesis, the APR tool may insert one or more clock buffers 822 into floorplan 704 to achieve desired clock timing. At PDN improvement operation 243, processor 102 may execute machine learning model 1045 to perform an inference process (e.g., a second inference process) using floorplan 223L to generate floorplan 706 with an adaptive front-side PDN, such as Figure 8C It should be noted that the location and distribution of metal lines 801 in the front-side PDN of layout 706 are different from the location and distribution of metal lines 801 in the front-side PDN of layout 704. In addition, the number and location of standard cells 820 in layout 706 may be different from those in layout 704.

[0104] At routing operation 224, the APR tool performs routing to route various nets (e.g., metal lines 831) that interconnect the standard cells 820 and clock buffers 822 placed within the layout map 706, thereby generating a layout map 224L. For example, routing is performed to ensure that the routed interconnects or nets satisfy a set of constraints. At PDN improvement operation 244, the processor 102 may execute the machine learning model 1045 to perform an inference process (e.g., a third inference process) using the layout map 224L, thereby generating the layout map 708 with an adaptive front-side PDN, such as Fig.8D Routing operation 224 and PDN improvement operation 244 may alternate metal lines 801 (eg, front-side PDN) and metal lines 831 (eg, routing network) of layout diagram 708 to cause the locations and distribution of metal lines 801 and 831 in layout diagram 708 to be different from those in layout diagram 706 .

[0105] At the post-routing optimization operation 225, the APR tool performs one or more physical verifications and / or timing verifications on the layout diagram 708 to generate the layout diagram 225L. It should be noted that in order to resolve IR and timing issues of the layout diagram 225L, the APR tool may alternate the location and distribution of the standard cells 820, the clock buffers 822, the metal lines 801 and 831 within the layout diagram 706. As a result, the location and distribution of the standard cells 820, the clock buffers 822, the metal lines 801 and 831 within the layout diagram 225L may be different from those within the layout diagram 708. Similarly, the layout diagram 225L generated by the post-routing optimization operation 225 is further improved by the PDN improvement operation 245. At the PDN improvement operation 245, the processor 102 may execute the machine learning model 1045 to perform yet another inference process (e.g., a fourth inference process) using the layout diagram 225L to generate the layout diagram 710, which may be a signed-off layout diagram to be passed to manufacturing. For brevity, the layout diagram 710 is described in detail below. Fig.8D Layout diagram 710 similar to layout diagram 708 in FIG. 7 is not explicitly shown.

[0106] Fig. 9 is a flow chart of a process for constructing an adaptive backside PDN within an IC layout during various operations in an APR process according to some embodiments of the present disclosure. Figure 10A to Figure 10D-3 yes Fig. 9 Different perspective views of a layout diagram during different operations in process 900.

[0107] In some embodiments, Fig. 9 The process 900 shown in FIG. 1 may be similar to Figure 2 2, except that flow 900 is specifically used to construct an adaptive backside (BS) PDN within an IC layout. For example, each of operations 222 to 225 is followed by a corresponding PDN improvement operation for the backside PDN (eg, operations 242 to 245).

[0108] At floorplanning operation 221 , the APR tool may perform floorplanning on an input IC design (eg, an IC schematic) to generate a layout 902 , such as Fig. 10A . In some embodiments, the PDN planning operation 241 is omitted to indicate that the layout diagram 902 will be used for the cell placement operation 222. Alternatively, the PDN planning operation 241 is performed to indicate that the APR tool or machine learning model 1045 performs power planning based on the partitioning and / or floor plan of the layout diagram 221L to generate the layout diagram 902 with the initial backside power delivery network. For the purpose of description, Fig. 10A The layout diagram 904 shown in FIG. 9 is not equipped with any backside power delivery grid.

[0109] In the cell placement operation 222, the APR tool places one or more standard cells 1020 on the front side 1010s1 of the semiconductor substrate 1010 to generate a layout map 222L. In the PDN improvement operation 242, the processor 102 may execute the machine learning model 1045 to perform an inference process (e.g., a first inference process) using the layout map 222L to generate a layout map 904 with an adaptive backside PDN, such as Figure 10B-1 to Figure 10B-3 For example, refer to Figure 10B-1 , which is a top perspective view of the layout diagram 904, the standard cell 1020 is disposed on the front side 1010s1 of the semiconductor substrate 1010. Figure 10B-2 , which is a bottom perspective view of the layout diagram 904, the metal line 1001B of the backside PDN is disposed on the backside 1010s2 of the semiconductor substrate 1010. Figure 10B-3 , which is a side view of the layout diagram 904 , it can be seen that the standard cell 1020 and the metal line 1001B of the backside PDN are arranged on opposite sides of the semiconductor substrate 1010 (ie, the front side 1010s1 and the back side 1010s2 ).

[0110] At clock tree synthesis operation 223, the APR tool performs clock tree synthesis on floorplan 904 to generate floorplan 223L. For example, during optimization within clock tree synthesis, the APR tool may insert one or more clock buffers 1022 into floorplan 904 to achieve desired clock timing. At PDN improvement operation 243, processor 102 may execute machine learning model 1045 to perform an inference process (e.g., a second inference process) using floorplan 223L to generate floorplan 904 with an adaptive backside PDN, such as Figure 10C-1 to Figure 10C-3 For example, refer to Figure 10C-1 , which is a top perspective view of the layout diagram 904, the metal line 1031 of the front wiring network is arranged on the front side 1010s1 of the semiconductor substrate 1010. Figure 10C-2 , which is a bottom perspective view of the layout diagram 906, the metal line 1001B of the backside PDN is disposed on the backside 1010s2 of the semiconductor substrate 1010. In addition, Figure 10C-2 The location and distribution of the metal line 1001B of the backside PDN in the layout diagram 906 are similar to Figure 10B-2 The layout diagram 904 in FIG. Figure 10C-3 , which is a side view of the layout diagram 906, it can be seen that Figure 10C-2 The location and distribution of the metal line 1001B of the backside PDN in the layout diagram 906 are similar to Figure 10B-2 The difference within the layout diagram 904 in FIG.

[0111] At routing operation 224, the APR tool performs routing to route various nets (e.g., metal lines 831) that interconnect the standard cells 1020 and clock buffers 1022 placed within the layout diagram 906, thereby generating a layout diagram 224L. For example, routing is performed to ensure that the routed interconnects or nets satisfy a set of constraints. At PDN improvement operation 244, the processor 102 may execute the machine learning model 1045 to perform an inference process (e.g., a third inference process) using the layout diagram 224L, thereby generating the layout diagram 908 with an adaptive front-side PDN, such as Figure 10D-1 to Figure 10D-3 Routing operation 224 and PDN improvement operation 244 may alternately use metal line 1001B (eg, backside PDN) within layout diagram 906 to cause the location and distribution of metal lines 1001B and 1031 within layout diagram 908 to be different from that within the PDN of layout diagram 906 .

[0112] At post-routing optimization operation 225, the APR tool performs one or more physical verifications and / or timing verifications on the layout diagram 908 to generate a layout diagram 225L. It should be noted that in order to resolve the IR and timing issues of the layout diagram 225L, the APR tool may alternate the locations and distributions of the standard cells 1020, the clock buffers 1022, and the metal lines 1001B and 1031 within the layout diagram 908. Therefore, the locations and distributions of the standard cells 1020, the clock buffers 1022, and the metal lines 1001B and 1031 in the layout diagram 225L may be different from those in the layout diagram 908. Similarly, the backside PDN within the layout diagram 225L generated by the post-routing optimization operation 225 is further improved by the PDN improvement operation 245. At PDN improvement operation 245, processor 102 may execute machine learning model 1045 to perform yet another inference process (e.g., a fourth inference process) using layout map 225L to generate a layout map 910 with an adaptive backside PDN, which may be a signed-off layout map to be delivered to manufacturing. Figure 10D-1 to Figure 10D-3 Layout diagram 910 is similar to layout diagram 908 in FIG.

[0113] Fig.11 is a flow chart of a process for constructing an adaptive dual-sided PDN within an IC layout during various operations in an APR process according to some embodiments of the present disclosure. Figures 12A-1 to 12D-3 yes Fig.11 Different perspectives of a layout diagram during different operations in process 1100.

[0114] In some embodiments, Fig.11 The process 1100 shown in FIG. 1 may be similar to Figure 2200, except that the process 1100 is specifically used to construct an adaptive double-sided (DS) PDN in an IC layout diagram, which includes a front-side PDN and a back-side PDN. For example, each of operations 222 to 225 is followed by a corresponding PDN improvement operation for the double-sided PDN (e.g., operations 242 to 245).

[0115] At floorplanning operation 221 , the APR tool may perform floorplanning on an input IC design (eg, an IC schematic) to generate a floorplan 221L, such as Figure 12A-1 . At PDN planning operation 241, the APR tool or machine learning model 1045 performs power planning based on the partitioning and / or floorplanning of the layout diagram 221L to generate a layout diagram 1102 having an initial two-sided power delivery network (which includes metal lines 1201 and 1201B). In some embodiments, according to predefined settings of the APR tool, the initial two-sided power delivery network, which may be a sparse type or a dense type, may be disposed on the front side 1210s1 and the back side 1210s2 of the semiconductor substrate 1210. For simplicity, the initial two-sided power delivery network is a sparse PDN, such as Figures 12A-1 to 12A-3 For example, refer to Figure 12A-1 , which is a top perspective view of the layout diagram 1102, the metal line 1201 (ie, the front side PDN) is disposed on the front side 1210s1 of the semiconductor substrate 1210. Figure 12A-2 , which is a bottom perspective view of the layout diagram 1102, the metal line 1201B (ie, the backside PDN) is disposed on the backside 1210s2 of the semiconductor substrate 1210. Figure 12A-3 , which is a side view of the layout diagram 1102 , it can be seen that the metal lines 1201 and 1201B are respectively arranged on the front side 1210s1 and the back side 1210s2 of the semiconductor substrate 1210 .

[0116] In the cell placement operation 222, the APR tool places one or more standard cells 1220 on the front side 1210s1 of the semiconductor substrate 1210 to generate a layout map 222L. In the PDN improvement operation 242, the processor 102 may execute the machine learning model 1045 to perform an inference process (e.g., a first inference process) using the layout map 222L to generate a layout map 1104 with an adaptive two-sided PDN, such as Figure 12B-1 to Figure 12B-3 For example, refer to Figure 12B-1 , which is a top perspective view of the layout diagram 1104, the standard cell 1220 and the metal line 1201 are arranged on the front side 1210s1 of the semiconductor substrate 1210. Figure 12B-2, which is a bottom perspective view of the layout diagram 1104, the metal line 1201B of the backside PDN is disposed on the backside 1210s2 of the semiconductor substrate 1210. Figure 12B-3 , which is a side view of the layout diagram 1104, it can be seen that the metal line 1201 and the metal line 1201B are arranged on opposite sides of the semiconductor substrate 1210 (ie, the front side 1210s1 and the back side 1210s2). It should be noted that Figure 12B-1 and Figure 12B-2 The location and distribution of the front side PDN (e.g., metal line 1201) and the back side PDN (e.g., metal line 1201B) in FIG. Figure 12A-1 and Figure 12A-2 , because both the front-side PDN and the back-side PDN are improved by the PDN improvement operation 242 (eg, the front-side PDN and the back-side PDN are replaced with the inferred adaptive front-side PDN and the inferred adaptive back-side PDN, respectively).

[0117] At clock tree synthesis operation 223, the APR tool performs clock tree synthesis on floorplan 1104 to generate floorplan 223L. For example, during optimization within clock tree synthesis, the APR tool may insert one or more clock buffers 1022 into floorplan 1104 to achieve desired clock timing. At PDN improvement operation 243, processor 102 may execute machine learning model 1045 to perform an inference process (e.g., a second inference process) using floorplan 223L to generate floorplan 1106 with an adaptive two-sided PDN, such as Figure 12C-1 to Figure 12C-3 For example, refer to Figure 12C-1 , which is a top perspective view of the layout diagram 1106, the metal line 1231 of the front wiring network is arranged on the front side 1210s1 of the semiconductor substrate 1210 together with the standard cell 1220 and the metal line 1201. Figure 12C-2 , which is a bottom perspective view of the layout diagram 1106, the metal line 1201B of the backside PDN is disposed on the backside 1210s2 of the semiconductor substrate 1210. Figure 12C-3 , which is a side view of the layout diagram 1106, it can be seen that Figure 12C-1 to Figure 12C-3 The locations and distributions of metal lines 1201 (eg, front-side PDN) and metal lines 1201B (eg, back-side PDN) within layout diagram 1106 in FIG. Figure 12B-1 to Figure 12B-3 The difference within the layout diagram 1106 in FIG.

[0118] At routing operation 224, the APR tool performs routing to route various nets (e.g., metal lines 1231) that interconnect the standard cells 1220 and clock buffers 1222 placed within the layout map 1106 to generate a layout map 224L. For example, routing is performed to ensure that the routed interconnects or nets satisfy a set of constraints. At PDN improvement operation 244, the processor 102 may execute the machine learning model 1045 to perform an inference process (e.g., a third inference process) using the layout map 224L to generate the layout map 1108 with an adaptive two-sided PDN, such as Figure 12D-1 to Figure 12D-3 Routing operation 224 and PDN improvement operation 244 may alternate metal lines 1201 (eg, frontside PDN) and 1201B (eg, backside PDN) within layout diagram 1106 to result in different locations and distributions of metal lines 1201 and 1201B within layout diagram 1108 than in layout diagram 1106 .

[0119] At post-routing optimization operation 225, the APR tool performs one or more physical verifications and / or timing verifications on the layout diagram 1108 to generate a layout diagram 225L. It should be noted that in order to resolve the IR and timing issues of the layout diagram 225L, the APR tool may alternate the locations and distributions of the standard cells 1220, the clock buffers 1222, and the metal lines 1201, 1201B, and 1231 within the layout diagram 1108. Therefore, the locations and distributions of the standard cells 1220, the clock buffers 1222, and the metal lines 1201, 1201B, and 1231 in the layout diagram 225L may be different from those in the layout diagram 1108. Similarly, the double-sided PDN within the layout diagram 225L generated by the post-routing optimization operation 225 is further improved by the PDN improvement operation 245. At PDN improvement operation 245, processor 102 may execute machine learning model 1045 to perform another inference process (e.g., fourth inference process) using layout map 225L to generate a layout map 1110 with an adaptive two-sided PDN, which may be a signed-off layout map that is delivered to manufacturing. Figure 12D-1 to Figure 12D-3 Layout 1110 is similar to layout 1108 in FIG.

[0120] In some embodiments, Fig.15 The semiconductor structure 1500 shown may be used Figure 10B-1 to Figure 10D-3 and Figures 12A-1 to 12D-3A backside PDN (e.g., metal line 1001B) of a layout diagram of the semiconductor structure 1500 may be provided. A technique called “backside direct contact” may be applied to the semiconductor structure 1500. For example, the backside PDN may include a metal layer 1501B disposed on a backside 1510s2 of a semiconductor substrate 1510. The metal layer 1501B may be electrically connected to a source / drain region (e.g., S / D region) 1521 of a standard cell 1520 disposed on a front side 1510s1 of the semiconductor substrate 1510 through a backside contact 1511. Specifically, the backside contact 1511 may penetrate the semiconductor substrate 1510 from the backside 1510s2 of the semiconductor substrate 1510 and directly reach the S / D region 1521 of the standard cell 1520, thereby reducing a vertical distance from the backside PDN to the standard cell on the front side 1510s1. This allows power on the backside PDN (eg, metal line 1501B and via 1502B) to be delivered directly to the S / D region 1521 of the standard cell 1520, thereby reducing unnecessary power consumption caused by the power path.

[0121] Fig.13 is a flow chart of a process for constructing an optimal frontside PDN within an IC layout during an APR process according to some embodiments of the present disclosure. FIG. 14A to FIG. 14D yes Fig.13 Different perspective views of a layout diagram during different operations in process 1300 of .

[0122] In some embodiments, Fig.13 The process 1300 shown in FIG. 1 may be similar to Figure 2 1300 is similar to the flow 200 shown in , except that the flow 1300 is specifically used to construct an optimal front side (FS) PDN within an IC layout. For example, a machine learning model 1046 based on multiple design parameters of the IC layout can be used to create an optimal front side PDN.

[0123] At floorplanning operation 221, the APR tool may provide an input netlist (e.g., Fig.14A At operation 1302, the machine learning model 1046 can use the multiple design parameters of the input IC design netlist to create an optimal front-side power delivery network on the front side 1410s1 of the semiconductor substrate 1410 to generate a layout diagram 1400A, as shown in FIG. Fig.14A In some embodiments, based on the determination result of the machine learning model 1046, an optimal front side power delivery network that may be dense or sparse may be set on the front side 810s1 of the semiconductor substrate 810. For the purpose of description, Fig.14A The optimal front-side power delivery network including metal line 1401 shown in FIG. 1 is a sparse front-side PDN.

[0124] In some embodiments, the design parameters may include, but are not limited to, the cell composition of the input netlist, the operating frequency of the IC design, and the design style. For example, the cell composition may refer to the type of standard cells within the input netlist, which may include, but are not limited to, AOI22 (e.g., AND or inverting gate), OAI22 (example, OR and inverting gate), ND2 (e.g., NAND gate), NR2 (e.g., NOR), INV (e.g., inverter), BUFF (e.g., buffer), SDF (e.g., scan D flip-flop), etc. In some embodiments, a high usage rate of AOI22 or OAI22 cells within the input netlist may indicate that pin access and routing of the IC design corresponding to the input netlist may be challenging. In addition, a high usage rate of ND2, NR2, INV, and BUFF cells within the input netlist may indicate that pin access and routing of the IC design corresponding to the input netlist may be easier.

[0125] In some embodiments, the structure or type of the PDN of the IC layout diagram 1400A can be associated with the operating frequency of the IC design. For example, the higher the operating frequency used by the IC design, the higher the power consumption used by the unit. In other words, when the operating frequency of the IC design is very high, this indicates that the machine learning model 1046 is more likely to use a dense PDN structure. On the other hand, when the operating frequency of the IC design is low, this indicates that the machine learning model 1046 is more likely to use a sparse PDN structure.

[0126] In some embodiments, the structure or type of the PDN of the IC layout diagram 1400A can be associated with the design style of the IC design. For design styles with high data access rates, such as CPU, GPU, NPC, etc., the standard cells in the IC layout diagram may consume more power. Therefore, in this case, the machine learning model 1046 is more likely to use a dense PDN structure. For design styles with lighter data access rates, in this case, the machine learning model 1046 is more likely to use a sparse front-side PDN structure.

[0127] Specifically, the training data for the machine learning model 1046 may include multiple netlists of IC designs, as well as the operating frequencies and design styles of these IC designs. In addition, the PDN structures of the signed layouts of these IC designs may be used as labels for the training data. Thus, the trained machine learning model 1046 is able to predict or determine the most suitable PDN structure (e.g., sparse or dense) using the netlist of a given IC design. In some embodiments, different metal layers (e.g., Figure 5 The PDN structure of the front-side PDN in M0 to Mtop (shown in FIG. 1 ) may be different. The details of the PDN structure can be referred to FIG. 4A to FIG. 4J , so it will not be repeated here.

[0128] In some embodiments, the machine learning model 1046 may also be a K-nearest neighbor (KNN) model or any other classification machine learning model, but the present disclosure is not limited thereto.

[0129] At cell placement operation 222 , the APR tool places one or more standard cells 1420 on the front side 1410s1 of the semiconductor substrate 1410 to generate a layout 1400B. For example, standard cells 1420 configured to provide predefined functions and having pre-designed layouts are stored in the cell library 1044 .

[0130] At clock tree synthesis operation 223, the APR tool performs clock tree synthesis on floorplan 1400B to generate floorplan 1400C. For example, during optimization within clock tree synthesis, the APR tool may insert one or more clock buffers 1422 into floorplan 1400B to achieve desired clock timing.

[0131] At routing operation 224, the APR tool performs routing to route various nets (e.g., metal lines 1431) that interconnect the standard cells 1420 and clock buffers 1422 placed within layout 1400C to generate layout 1400D. For example, routing is performed to ensure that the routed interconnections or nets satisfy a set of constraints. It should be noted that during process 1400, the location and distribution of PDNs (e.g., metal lines 1401) within IC layouts 1400A, 1400B, 1400C, and 1400D remain unchanged.

[0132] At post-routing optimization operation 225, the APR tool performs one or more physical verifications and / or timing verifications on layout diagram 1400D to generate an output IC layout diagram. It should be noted that in order to resolve IR and timing issues of the output layout diagram, the APR tool may alternate the location and distribution of standard cells 1420, clock buffers 1422, metal lines 1401 and 1431 within layout diagram 1400D. Therefore, the location and distribution of standard cells 1420, clock buffers 1422, metal lines 1401 and 1431 in the output IC layout diagram may be different from that in layout diagram 1400D. For the sake of brevity, the layout diagrams that are not explicitly shown are not shown. Fig.14D In addition, the output IC layout generated by the APR process (eg, flow 1300) can be used to manufacture integrated circuits in a foundry.

[0133] Fig.161 is a block diagram of an IC manufacturing system 1600 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the IC layout diagram, the manufacturing system 1600 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0134] exist Fig.16 In the present invention, IC manufacturing system 1600 includes entities that interact in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 1660, such as design room 1620, mask room 1630 and IC manufacturing plant / manufacturer ("Fab") 1650. The entities in system 1600 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of design room 1620, mask room 1630 and IC manufacturing plant 1650 are owned by a single larger company. In some embodiments, two or more of design room 1620, mask room 1630 and IC manufacturing plant 1650 coexist in a common facility and use common resources.

[0135] The design office (or design team) 1620 generates an IC design layout 1622. The IC design layout 1622 includes various geometric patterns, such as the above-mentioned IC layout. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layer of the various components constituting the IC device 1660 to be manufactured. The layers are combined to form various IC components. For example, a portion of the IC design layout 1622 includes various IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines or through holes for interlayer interconnection, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 1620 implements an appropriate design process to form the IC design layout 1622. The design process includes one or more of a logical design, a physical design, or a location and a route. The IC design layout 1622 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout 1622 can be represented in a GDSII file format or a DFII file format.

[0136] The mask chamber 1630 includes data preparation 1632 and mask manufacturing 1644. The mask chamber 1630 uses the IC design layout drawing 1622 to manufacture one or more masks 1645 for manufacturing various layers of the IC device 1660 according to the IC design layout drawing 1622. The mask chamber 1630 performs mask data preparation 1632, wherein the IC design layout drawing 1622 is converted into a representative data file (RDF). The mask data preparation 1632 provides the RDF to the mask manufacturing 1644. The mask manufacturing 1644 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1645 or a semiconductor wafer 1653. The design layout drawing 1622 is manipulated by the mask data preparation 1632 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 1650. In Fig.16 , mask data preparation 1632 and mask manufacturing 1644 are shown as separate elements. In some embodiments, mask data preparation 1632 and mask manufacturing 1644 may be collectively referred to as mask data preparation.

[0137] In some embodiments, mask data preparation 1632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1622. In some embodiments, mask data preparation 1632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT), which treat OPC as an inverse imaging problem, are also used.

[0138] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that checks the IC design layout 1622 that has been processed in OPC using a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1622 to compensate for the constraints during mask fabrication 1644, which can undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0139] In some embodiments, mask data preparation 1632 includes a lithography process check (LPC), which simulates a process to be performed by IC fabrication plant 1650 to fabricate IC device 1660. LPC simulates the process based on IC design layout 1622 to create a simulated fabricated device, such as IC device 1660. Process parameters in the LPC simulation may include parameters related to various processes of the IC fabrication cycle, parameters related to tools used to fabricate the IC, and / or other aspects of the fabrication process. LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after LPC creates a simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 1622.

[0140] It should be understood that the above description of mask data preparation 1632 has been simplified for the sake of clarity. In some embodiments, data preparation 1632 includes additional features, such as modifying the logic operations (LOPs) of IC design layout 1622 according to manufacturing rules. In addition, the processes applied to IC design layout 1622 during data preparation 1632 can be performed in a variety of different orders.

[0141] After mask data preparation 1632 and during mask manufacturing 1644, a mask 1645 or a set of masks 1645 are manufactured based on the modified IC design layout 1622. In some embodiments, mask manufacturing 1644 includes performing one or more photolithography exposures based on the IC design layout 1622. In some embodiments, a pattern is formed on a mask (photomask or reticle) 1645 using an electron beam (e-beam) or a plurality of electron beams based on the modified IC design layout 1622. Mask 1645 can be formed using various techniques. In some embodiments, mask 1645 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) or EUV beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 1645 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque area of ​​the binary mask. In another example, a mask 1645 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1645, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 1644 is used for various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1653, the mask is used in an etching process to form various etched regions in the semiconductor wafer 1653, and / or used in other suitable processes.

[0142] IC manufacturing plant 1650 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturing plant 1650 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0143] IC fabrication facility 1650 includes wafer fabrication tools 1652 configured to perform various fabrication operations on semiconductor wafer 1653 to fabricate IC devices 1660 based on masks (e.g., mask 1645). In various embodiments, fabrication tools 1652 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes described herein.

[0144] IC manufacturing plant 1650 uses mask 1645 manufactured by mask chamber 1630 to manufacture IC device 1660. Therefore, IC manufacturing plant 1650 at least indirectly uses IC design layout 1622 to manufacture IC device 1660. In some embodiments, semiconductor wafer 1653 is manufactured by IC manufacturing plant 1650 using mask 1645 to form IC device 1660. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 1622 at least indirectly. Semiconductor wafer 1653 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 1653 also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0145] One aspect of the present disclosure provides a method comprising the steps of obtaining a netlist of an integrated circuit (IC) design; and performing multiple operations of an automatic place and route (APR) process; generating a layout diagram having a power delivery network after each operation of the APR process is completed; and adjusting a portion of the power delivery network of the layout diagram using a machine learning model by inputting multiple features of the layout diagram generated in each operation of the APR process into the machine learning model.

[0146] In some embodiments, adjusting the portion of the power delivery network of the layout diagram comprises adjusting an arrangement and / or density of the portion of the power delivery network in the layout diagram.

[0147] In some embodiments, the method further includes: generating a first layout diagram based on a netlist of the IC design in a floorplanning operation within the APR process; and arranging an initial power delivery network on the semiconductor substrate within the first layout diagram to generate an improved first layout diagram.

[0148] In some embodiments, the method further includes: placing a plurality of standard cells on a semiconductor substrate within an improved first layout diagram in a cell placement operation within an APR process to generate a second layout diagram; and improving an initial power delivery network within the second layout diagram using a machine learning model to generate an improved second layout diagram.

[0149] In some embodiments, an initial power delivery network and standard cells are disposed on a first side of a semiconductor substrate.

[0150] In some embodiments, the standard cell and the initial power delivery network are disposed on a first side and a second side opposite to the first side of the semiconductor substrate, respectively.

[0151] In some embodiments, the standard cell is disposed on a first side of the semiconductor substrate; and the initial power delivery network includes a first portion and a second portion, the first portion is disposed on the first side of the semiconductor substrate, and the second portion is disposed on a second side opposite to the first side of the semiconductor substrate.

[0152] In some embodiments, the method further includes: performing clock tree synthesis on the improved second layout diagram in a clock tree synthesis operation within the APR process to generate a third layout diagram; and improving a power delivery network within the third layout diagram using a machine learning model to generate an improved third layout diagram.

[0153] In some embodiments, during the clock tree synthesis operation, one or more clock buffers are disposed on the semiconductor substrate within the modified second layout.

[0154] In some embodiments, the method further includes: in a routing operation within the APR process, routing a plurality of wires interconnecting the placed standard cells to generate a fourth layout diagram; and improving a power delivery network within the fourth layout diagram using a machine learning model to generate an improved fourth layout diagram.

[0155] In some embodiments, the method further includes: performing an optimization process on the improved fourth layout diagram in a post-routing optimization operation within the APR process to generate a fifth layout diagram; and improving the power delivery network within the fourth layout diagram using a machine learning model to generate a final layout diagram.

[0156] In some embodiments, improving a power delivery network within a layout diagram generated at each operation within an APR process using a machine learning model includes: obtaining a plurality of diagrams associated with a plurality of predetermined features of the layout diagram; dividing the layout diagram generated at each operation in the APR process into a plurality of grids; extracting features of each grid in the layout diagram; inferring a power delivery network structure of each grid within the layout diagram using a machine learning model based on the extracted features of each grid to generate an adaptive power delivery network; and replacing the power delivery network within the layout diagram with the generated adaptive power delivery network.

[0157] In some embodiments, the predetermined characteristics include power density, cell drive, cell functionality, toggle rate, congestion, pin density, and timing critical paths.

[0158] In some embodiments, the features of each grid include respective levels of predetermined features.

[0159] Another aspect of the present disclosure provides a method comprising the steps of obtaining a netlist of an integrated circuit (IC) design; performing an automatic placement and routing (APR) process on the netlist to generate a final layout diagram; and during each operation of the APR process, dividing the layout diagram generated by each operation in the APR process into a plurality of fixed-size grids; and adaptively updating a power delivery network of the layout diagram based on the grid using the machine learning model by inputting a plurality of features of each grid within the layout diagram into a machine learning model.

[0160] In some embodiments, the characteristics of each grid include respective levels of a plurality of predetermined characteristics, and the predetermined characteristics include power density, cell drive, cell functionality, switching rate, congestion, pin density, and timing critical paths of each grid.

[0161] In some embodiments, the power delivery network of the layout is disposed on a first side of the semiconductor substrate within the layout, on a second side opposite to the first side, or on both the first side and the second side.

[0162] Another aspect of the present disclosure provides a system for improving an integrated circuit layout diagram, which includes a non-transitory computer-readable medium storing program instructions; and a processor operably coupled to the non-transitory computer-readable medium, wherein the program instructions, when executed by the processor, cause the processor to perform the following operations: obtain a netlist of an integrated circuit (IC) design; and determine, based on multiple features of the IC design, using a machine learning model whether a power delivery network within a layout diagram corresponding to the IC design generated by an automatic place and route (APR) process is a first type or a second type; and manufacture the integrated circuit using the layout diagram generated by the APR process.

[0163] In some embodiments, the density of wires in the first type of power delivery network is higher than the density of wires in the second type of power delivery network.

[0164] In some embodiments, the characteristics of the IC design include the cell composition of the netlist of the IC structure, and the operating frequency and design style of the IC design.

[0165] The methods and features of the present disclosure have been fully described in the examples and descriptions provided. It should be understood that any modification or change without departing from the spirit of the present disclosure is intended to be included in the scope of protection of the present disclosure.

[0166] In addition, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufactures, and compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will readily understand from this disclosure that, in accordance with this disclosure, processes, machines, manufactures, compositions of matter, means, methods, or steps currently existing or later developed that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized.

[0167] Therefore, the appended claims are intended to include within their scope the process, machine, manufacture, composition of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the present disclosure.

Claims

1. A method for improving an integrated circuit layout diagram, comprising: Obtain a netlist for an integrated circuit design; as well as Perform multiple operations of the automated placement and routing process; After each operation of the automatic placement and routing process is completed, generating a layout diagram having a power delivery network; as well as Portions of the power delivery network of the layout diagram are adjusted using the machine learning model by inputting a plurality of features of the layout diagram generated during various operations of the automated placement and routing process into the machine learning model.

2. The method according to claim 1, wherein: Adjusting the portion of the power delivery network of the layout diagram comprises adjusting an arrangement and / or density of the portion of the power delivery network in the layout diagram.

3. The method according to claim 1, further comprising: In a floorplanning operation within the automatic place and route process, generating a first layout diagram based on the netlist of the integrated circuit design; as well as An initial power delivery network is arranged on the semiconductor substrate within the first layout to generate an improved first layout.

4. The method according to claim 3, further comprising: In a cell placement operation within the automatic place and route process, a plurality of standard cells are placed on the semiconductor substrate within the improved first layout diagram to generate a second layout diagram; as well as The initial power delivery network within the second layout diagram is improved using the machine learning model to generate an improved second layout diagram.

5. The method according to claim 4, wherein: The initial power delivery network and the standard cell are disposed on a first side of the semiconductor substrate.

6. The method according to claim 4, wherein: The standard cell and the initial power delivery network are disposed on a first side of the semiconductor substrate and a second side opposite to the first side, respectively.

7. The method according to claim 4, wherein: The standard cell is disposed on a first side of the semiconductor substrate; and The initial power delivery network includes a first portion and a second portion, the first portion being disposed on a first side of the semiconductor substrate and the second portion being disposed on a second side opposite to the first side of the semiconductor substrate.

8. The method according to claim 1, wherein: Improving the power delivery network within the layout graph generated at each operation within the automatic place and route process using the machine learning model includes: obtaining a plurality of graphs associated with a plurality of predetermined features of the layout graph; Dividing the layout graph generated by each operation in the automatic placement and routing process into a plurality of grids; Extracting features of each grid in the layout diagram; Inferring a power delivery network structure of each grid within the layout diagram using the machine learning model based on the extracted features of each grid to generate an adaptive power delivery network; and The power delivery network within the layout diagram is replaced with the generated adaptive power delivery network.

9. A method for improving an integrated circuit layout diagram, comprising: Obtain a netlist for an integrated circuit design; performing an automatic placement and routing process on the netlist to generate a final layout diagram; as well as During each operation in the automatic placement and routing process described: Dividing the layout graph generated by each operation in the automatic placement and routing process into a plurality of grids of fixed size; and By inputting multiple features of each grid in the layout diagram into a machine learning model, the machine learning model is used to adaptively update the power transmission network of the layout diagram based on the grid.

10. A system for improving an integrated circuit layout, comprising a non-transitory computer-readable medium storing program instructions; and a processor operably coupled to the non-transitory computer-readable medium, wherein: The program instructions, when executed by the processor, cause the processor to perform the following operations: Obtain a netlist for an integrated circuit design; and determining, based on a plurality of features of the integrated circuit design, using a machine learning model, whether a power delivery network within a layout corresponding to the integrated circuit design generated by an automated place and route process is of a first type or a second type; and An integrated circuit is fabricated using the layout generated by the automated place and route process.

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