Level shifter and memory device including same

Abstract

The invention provides a level shifter and a memory device including the same. The level shifter includes: a first circuit that pulls down a first output node and a first intermediate node based on an input signal, and pulls down a second output node and a second intermediate node based on an inverted input signal of the input signal; and a second circuit that pulls up the second output node to a supply voltage based on the first intermediate node when the first circuit pulls down the first output node, and pull up the first output node to the supply voltage based on the second intermediate node when the first circuit pulls down the second output node.

Description

Technical Field

[0001] The present disclosure relates to a level shifter generating an output voltage having a level different from that of the input voltage based on an input voltage and a memory device including the level shifter. Background Art

[0002] An electronic device may include various components. These components may operate in the same voltage domain, or may operate in domains different from each other. Components belonging to the same voltage domain may operate using the same power supply voltage and the same ground voltage. Components belonging to different voltage domains may operate using different power supply voltages and different ground voltages.

[0003] The electronic device may include a level shifter for converting a signal belonging to a first voltage domain into a signal belonging to another second voltage domain. Summary of the invention

[0004] The present disclosure may provide a level shifter for receiving an input voltage to generate an output voltage having a level different from that of the input voltage, and a memory device including the level shifter.

[0005] In addition, the present disclosure may provide a level shifter for alleviating degradation of a transistor based on a bias voltage and reducing a voltage difference between a gate terminal and a source terminal and between the gate terminal and a drain terminal of the transistor, and a memory device including the level shifter.

[0006] Furthermore, the present disclosure may provide a level shifter having a path different from a path for pulling up a voltage level of an output voltage in response to an input signal, and a memory device including the level shifter.

[0007] In addition, the present disclosure may provide a level shifter for changing a voltage level of an output voltage by controlling transistors in the level shifter via a path different from a path for pulling up the voltage level of the output voltage in response to an input signal and a memory device including the level shifter.

[0008] A level shifter according to an exemplary embodiment includes a first circuit and a second circuit. The first circuit is configured to pull down a first output node and a first intermediate node based on an input signal, and pull down a second output node and a second intermediate node based on an inverted input signal of the input signal. The second circuit is configured to pull up the second output node to a power supply voltage based on the first intermediate node when the first circuit pulls down the first output node, and pull up the first output node to the power supply voltage based on the second intermediate node when the first circuit pulls down the second output node.

[0009] A level shifter according to an exemplary implementation includes first to fourth transistors. The first transistor is connected between a first line at a first voltage level and a first node and includes a gate connected to a second node. The second transistor is connected between the first line and the second node and includes a gate connected to the first node. The third transistor is connected in parallel with the first transistor between the first line and the first node and is configured to turn off the second transistor based on an input signal. The fourth transistor is connected in parallel with the second transistor between the first line and the second node and is configured to turn off the first transistor and the third transistor based on an inverted input signal of the input signal.

[0010] A memory device according to an exemplary embodiment includes: a row address decoder including a level shifter; and a memory cell array. The level shifter is configured to: upon receiving a first input signal, generate an output signal by pulling up a voltage level of a first node to a first voltage level different from the voltage level of the first input signal by a first current flowing through a first path; upon receiving a second input signal as an inverted signal of the first input signal, cut off the first current by a second current flowing through a second path different from the first path; and upon receiving the second input signal and cutting off the first current, pull down the voltage level of the first node to a second voltage level different from the first voltage level by a third current flowing through a third path. The memory cell array includes: a first word line configured to receive the output signal; and a plurality of memory cells connected to the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a circuit diagram illustrating a level shifter according to a first comparative example.

[0012] Figure 2 is a circuit diagram illustrating a level shifter according to a second comparative example.

[0013] Figure 3 is a circuit diagram for explaining current fighting of a level shifter according to a second comparative example.

[0014] Figure 4 It is used to illustrate Figure 3 The timing diagram of the operation of the level shifter.

[0015] Figure 5 is a block diagram of a level shifter according to an exemplary embodiment.

[0016] Fig. 6A is a circuit diagram of a level shifter according to an exemplary embodiment.

[0017] Figure 6B is a timing diagram for explaining the operation of a level shifter according to an exemplary embodiment.

[0018] Figure 7 is a circuit diagram of a level shifter according to an exemplary embodiment.

[0019] Figure 8 is a block diagram of a level shifter according to an exemplary embodiment.

[0020] Fig.9A is a circuit diagram of a level shifter according to an exemplary embodiment.

[0021] Fig. 9B is a circuit diagram of a level shifter according to an exemplary embodiment.

[0022] Fig.10 is a layout diagram of a level shifter according to an exemplary embodiment.

[0023] Fig.11 is a circuit diagram of a level shifter according to an exemplary embodiment.

[0024] Fig.12 is a circuit diagram of a level shifter according to an exemplary embodiment.

[0025] Fig.13 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0026] Fig.14 It is used to illustrate Fig.13 Schematic block diagram of a storage device in FIG.

[0027] Fig.15 It is used to illustrate Fig.14 Schematic block diagram of a level shifter in a voltage generator in FIG.

[0028] Fig.16 It is used to illustrate Fig.13 Schematic block diagram of a storage device in FIG.

[0029] Fig.17 It is used to illustrate Fig.16 Schematic block diagram of the level shifter in the row address decoder. DETAILED DESCRIPTION

[0030] In the following detailed description, only certain exemplary embodiments have been shown and described, simply by way of illustration. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0031] Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.Like reference numerals designate like elements throughout this specification.

[0032] In addition, unless clear expressions such as "a", "an" or "single" are used, expressions written in the singular can be understood as singular or plural. Expressions such as "first", "second", "middle", etc. used herein can refer to various different elements, regardless of their order and / or priority, and are only used to distinguish one element from another element, without limiting the element.

[0033] Figure 1 is a circuit diagram illustrating a level shifter according to a first comparative example.

[0034] The level shifter 100 may receive an input signal IN, a power supply voltage VDD, and a ground voltage VSS. The level shifter 100 may output a power supply voltage VDD and a ground voltage VSS having levels different from the level of the input signal IN based on the input signal IN. The input signal IN may swing between a first voltage level and a second voltage level. Here, the second voltage level may be higher than the first voltage level. The voltage level difference between the voltage level of the power supply voltage VDD and the voltage level of the ground voltage VSS may be greater than the voltage level difference between the first voltage level and the second voltage level. Here, the voltage levels of the first voltage level and the ground voltage VSS may be substantially the same. In the following description, it is assumed that the voltage level of the power supply voltage VDD is higher than the second voltage level and the voltage level of the ground voltage VSS is equal to the first voltage level; however, they are not limited thereto.

[0035] The level shifter 100 may include a pull-down circuit 110 and a pull-up circuit 120 .

[0036] The pull-down circuit 110 may pull down the voltage level of the first voltage V0 of the first node ND0 and the voltage level of the second voltage V1 of the second node ND1 to the ground voltage VSS in response to the input signal IN and the inverted input signal INB. The pull-down circuit 110 may include transistors T1 and T2. The transistors T1 and T2 may be N-type transistors. The first transistor T1 may be connected between the first node ND0 and the ground voltage (VSS) line. In an embodiment, the source and drain of the first transistor T1 may be connected to the ground voltage (VSS) line and the first node ND0, respectively. The first transistor T1 may receive the input signal IN through its gate. The first transistor T1 may be turned on according to the voltage level of the input signal IN, thereby discharging the voltage level of the first voltage V0 of the first node ND0 to the ground voltage VSS. The second transistor T2 may be connected between the second node ND1 and the ground voltage (VSS) line. In an embodiment, the source and drain of the second transistor T2 may be connected to the ground voltage (VSS) line and the second node ND1, respectively. The second transistor T2 may receive the inverted input signal INB through its gate. The second transistor T2 may be turned on according to the voltage level of the inverted input signal INB, thereby discharging the voltage level of the second voltage V1 of the second node ND1 to the ground voltage VSS.

[0037] The pull-up circuit 120 may pull up a voltage level of a first voltage V0 of the first node ND0 and a voltage level of a second voltage V1 of the second node ND1 to the power supply voltage VDD in response to an input signal IN and an inverted input signal INB. The pull-up circuit 120 may pull up a voltage level of the second node ND1 to the power supply voltage VDD in response to the voltage of the first node ND0 being pulled down to the ground voltage VSS by the input signal IN, and may pull up a voltage level of the first node ND0 to the power supply voltage VDD in response to the voltage of the second node ND1 being pulled down to the ground voltage VSS by the inverted input signal INB.

[0038] The pull-up circuit 120 may include transistors T3 and T4. The transistors T3 and T4 may be cross-connected and may be P-type transistors. The third transistor T3 may be connected between a power supply voltage (VDD) line and a first node ND0. The source, drain, and gate of the third transistor T3 may be connected to the power supply voltage (VDD) line, the first node ND0, and the second node ND1, respectively. The third transistor T3 may be turned on according to the voltage level of the second voltage V1 of the second node ND1, thereby pulling up the voltage level of the first voltage V0 of the first node ND0 to the power supply voltage VDD. The fourth transistor T4 may be connected between the power supply voltage (VDD) line and the second node ND1. The source, drain, and gate of the fourth transistor T4 may be connected to the power supply voltage (VDD) line, the second node ND1, and the first node ND0, respectively. The fourth transistor T4 may be turned on according to the voltage level of the first voltage V0 of the first node ND0, thereby pulling up the voltage level of the second voltage V1 of the second node ND1 to the power supply voltage VDD.

[0039] However, in the level shifter 100 according to the first comparative example, the power supply voltage VDD may cause a large voltage difference Vdiff between the gate and drain of the transistors T1, T2, T3, and T4 and between the gate and source of these transistors. For example, when the first node ND0 is pulled down to the ground voltage VSS and the second node ND1 is pulled up to the power supply voltage VDD, a voltage difference Vdiff between the power supply voltage VDD and the ground voltage VSS may be generated between the gate and drain of the third transistor T3 and between the gate and source of the fourth transistor T4. In addition, a voltage difference Vdiff between the power supply voltage VDD and the ground voltage VSS may be generated between the gate and drain of the second transistor T2. Therefore, when the power supply voltage VDD is applied for a long time, the transistors T1, T2, T3, and T4 may be degraded due to hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and bias temperature instability (BTI) phenomena, etc., which may cause reliability problems of the transistors T1, T2, T3, and T4.

[0040] Figure 2 is a circuit diagram illustrating a level shifter according to a second comparative example. Figure 1 Different from the level shifter 100 in FIG. 1 , the level shifter 200 may further include a bias circuit 230 .

[0041] The bias circuit 230 may be connected between the pull-down circuit 210 and the pull-up circuit 220. The bias circuit 230 may include transistors T5, T6, T7, and T8. The transistors T5, T6, T7, and T8 may be stacked between the pull-down circuit 210 and the pull-up circuit 220. The transistors T5 and T6 may be N-type transistors, and the transistors T7 and T8 may be P-type transistors.

[0042] The transistors T7 and T8 can adjust the lower limit of the voltage level of the first voltage V0 of the first node ND0 and the lower limit of the voltage level of the second voltage V1 of the second node ND1 to be equal to or higher than the voltage level of the first bias signal BIAS_P based on the first bias signal BIAS_P. The voltage level of the first bias signal BIAS_P may be a minimum voltage level (e.g., Vp) for turning on the transistors T7 and T8. Since the lower limit of the voltage level of the first voltage V0 of the first node ND0 and the lower limit of the voltage level of the second voltage V1 of the second node ND1 are higher than the ground voltage VSS due to the transistors T7 and T8, the voltage difference Vdiff1 between the gate and the drain of the transistors T3 and T4 connected to the first node ND0 and the second node ND1 and between the gate and the source of the transistors T3 and T4 connected to the first node ND0 and the second node ND1 may be smaller than the voltage difference Vdiff in the transistors T3 and T4 in the first comparative example. This can alleviate the degradation of the transistors T3 and T4.

[0043] The transistors T5 and T6 can adjust the upper limit of the voltage level of the third voltage V2 of the third node ND2 and the upper limit of the voltage level of the fourth voltage V3 of the fourth node ND3 to be equal to or lower than the voltage level of the second bias signal BIAS_N based on the second bias signal BIAS_N. The voltage level of the second bias signal BIAS_N can be a minimum voltage level (e.g., Vn) for turning on the transistors T5 and T6. Since the upper limit of the voltage level of the third voltage V2 of the third node ND2 and the upper limit of the voltage level of the fourth voltage V3 of the fourth node ND3 are lower than the power supply voltage VDD due to the transistors T5 and T6, the voltage difference Vdiff2 between the gate and the drain of the transistors T1 and T2 connected to the third node ND2 and the fourth node ND3 and the gate and the source of the transistors T1 and T2 connected to the third node ND2 and the fourth node ND3 can be less than the voltage difference Vdiff in the transistors T1 and T2 in the first comparative example. This can alleviate the degradation of the transistors T1 and T2.

[0044] However, in order for the level shifter 200 to output a power supply voltage VDD and a ground voltage VSS having a level different from that of the input signal IN, it is necessary to change the states of the cross-connected transistors T3 and T4 based on the input signal IN. For example, the transistors T3 and T4 can be turned on or off based on the voltage levels of the first node ND0 and the second node ND1, so that the level shifter 200 outputs an output signal having a voltage level different from that of the input signal. However, due to the transistors T7 and T8 added to ensure the reliability of the transistors T1, T2, T3, and T4, it may not be easy to change the states of the cross-connected transistors T3 and T4. Figure 3 and Figure 4 Describe this.

[0045] Figure 3 is a circuit diagram for explaining current confrontation of a level shifter according to a second comparative example, and Figure 4 It is used to illustrate Figure 3 The timing diagram of the operation of the level shifter.

[0046] refer to Figure 3 , when an input signal IN having a first voltage level (e.g., VSS) is input to the level shifter 300, the first transistor T1 may be turned off and the second transistor T2 may be turned on. When the second transistor T2 is turned on, a second voltage V1 (e.g., Vp) may be applied to the second node ND1 through the transistors T6 and T8. When the third transistor T3 is turned on by the second voltage V1 of the second node ND1, the driving current Id3 flowing through the third transistor T3 may pull up the voltage level of the first voltage V0 of the first node ND0 to the power supply voltage VDD.

[0047] Thereafter, when having a second voltage level (eg, Figure 4 When an input signal IN having a second voltage level VDD1) is input to the level shifter 300, in order to pull up the voltage level of the second voltage V1 of the second node ND1 of the level shifter 300 to the power supply voltage VDD, it is necessary to change the states of the cross-connected transistors T3 and T4. In an embodiment, when the level shifter 300 receives an input signal IN having a second voltage level VDD1, the first transistor T1 may be turned on and the second transistor T2 may be turned off. When the first transistor T1 is turned on by the input signal IN having the second voltage level VDD1, a driving current Id1 for discharging the third voltage V2 of the third node ND2 to the ground voltage VSS may flow through the first transistor T1. Similarly, a driving current Id2 weaker than the driving current Id1 may flow through the transistors T5 and T7 stacked on the first transistor T1. When the third voltage V2 of the third node ND2 is discharged to the ground voltage VSS by the driving current Id1 and the first voltage V0 of the first node ND0 is pulled down to a voltage (e.g., Vp) sufficient to turn on the fourth transistor T4 by the driving current Id2, the cross-connected fourth transistor T4 can be turned on and the second voltage V1 of the second node ND1 can be pulled up to the power supply voltage VDD.

[0048] However, the driving current Id3 (i.e., pull-up current) that has been flowing through the third transistor T3 due to the input signal IN having the first voltage level VSS before the input signal IN having the second voltage level VDD1 is input may cause a current confrontation 310 with the driving current Id2 (i.e., pull-down current) that flows through the seventh transistor T7 after the input signal IN having the second voltage level VDD1 is input. Figure 3 as well as Figure 4 In the timing diagram 400, when the input signal IN having the second voltage level VDD1 is input at the first time point t0, a current confrontation may occur between the driving current Id3 that has been flowing through the third transistor T3 and the driving current Id2 that flows through the seventh transistor T7. When the driving current Id2 that flows through the seventh transistor T7 is greater than the driving current Id3 that flows through the third transistor T3 (that is, when the driving current Id2 that flows through the seventh transistor T7 is sufficient to pull down the voltage level of the first voltage V0 of the first node ND0), the voltage level of the first voltage V0 of the first node ND0 may be pulled down. When the fourth transistor T4 is turned on as the voltage level of the first voltage V0 is pulled down, the voltage level of the second voltage V1 of the second node ND1 may be pulled up to the power supply voltage VDD. However, the current confrontation may cause a time delay Tdelay (see reference numeral "410") when the second voltage V1 of the second node ND1 is pulled up to the power supply voltage VDD.

[0049] However, when the driving current Id2 flowing through the seventh transistor T7 is less than the driving current Id3 that has been flowing through the third transistor T3 (i.e., when the driving current Id2 flowing through the seventh transistor T7 is insufficient to pull down the voltage level of the first voltage V0 of the first node ND0), the voltage level of the first voltage V0 of the first node ND0 cannot be sufficiently decreased to turn on the fourth transistor T4. Figure 3 and Figure 4 When the driving current Id2 flowing through the seventh transistor T7 is less than the driving current Id3 that has been flowing through the third transistor T3, the fourth transistor T4 cannot be turned on, and the voltage level of the second voltage V1 of the second node ND1 cannot be pulled up to the power supply voltage VDD (see reference numeral “420”).

[0050] Although the driving current Id2 flowing through the transistors T7 and T8 can reduce the reliability problem of the transistors, the driving capability of the driving current Id2 can be quickly reduced to below a certain voltage, so that the states of the cross-connected transistors T3 and T4 do not change. Therefore, an output voltage with a desired level cannot be generated in response to the input signal IN. Therefore, the characteristics of the level shifter become degraded.

[0051] Figure 5 is a block diagram of a level shifter according to an exemplary embodiment.

[0052] In an exemplary embodiment, the level shifter 500 may include a pull-up circuit 510, a pull-down circuit 530, a bias circuit 520, and auxiliary circuits 541 and 543. The auxiliary circuits 541 and 543 may be circuits for controlling the transistors in the pull-up circuit 510 in a special path separated for changing the state of the transistors in the pull-up circuit 510 and in a path where there is no current antagonism to ensure the characteristics of the level shifter 500. For example, the auxiliary circuits 541 and 543 may turn off the transistors in the pull-up circuit 510 that generate the pull-up current in response to the previous input signal IN. Since the transistors are turned off, the generation of the pull-up current is prevented. Therefore, the current antagonism can be minimized.

[0053] In an exemplary embodiment, the level shifter 500 may include a pull-down circuit 530, a bias circuit 520, and auxiliary circuits 541 and 543. In an exemplary embodiment, the level shifter 500 may not include the pull-up circuit 510. The auxiliary circuits 541 and 543 according to the exemplary embodiment may control the nodes ND0 and ND1 on their respective paths to be subsequently connected to the output circuit to ensure the characteristics of the level shifter 500. FIG. 6A to FIG. 7 A detailed configuration of the auxiliary circuits 541 and 543 is described. Configurations of the pull-up circuit 510, the pull-down circuit 530, and the bias circuit 520 are the same as or similar to those in the level shifter according to the comparative example, and therefore a detailed description thereof will not be provided.

[0054] Fig. 6A is a circuit diagram of a level shifter according to an exemplary embodiment, and Figure 6B is a timing diagram for explaining the operation of a level shifter according to an exemplary embodiment.

[0055] The level shifter 600 may receive an input signal IN, a power supply voltage VDD, and a ground voltage VSS. The level shifter 600 may output a power supply voltage VDD and a ground voltage VSS having a level different from that of the input signal IN based on the input signal IN. In an embodiment, the input signal IN may swing between a first voltage level and a second voltage level, and the second voltage level may be higher than the first voltage level. The voltage level difference between the voltage level of the power supply voltage VDD and the voltage level of the ground voltage VSS may be greater than the voltage level difference between the first voltage level and the second voltage level. Here, the voltage levels of the first voltage level and the ground voltage VSS may be substantially the same. In the following description, it is assumed that the voltage level of the power supply voltage VDD is higher than the second voltage level and the voltage level of the ground voltage VSS is equal to the first voltage level; however, embodiments of the present invention are not limited thereto. Similarly, in the following description, it is assumed that the level shifter 600 is a level shifter that receives a low voltage signal and outputs a high voltage signal; however, embodiments of the present invention are not limited thereto. The level shifter 600 may be a level shifter that receives a high voltage signal and outputs a low voltage signal. Alternatively, the level shifter 600 may be a level shifter that outputs an inverted signal of an input signal as an output signal.

[0056] In an exemplary embodiment, the level shifter 600 may include a pull-up circuit 610 , a bias circuit 620 , a pull-down circuit 630 , and auxiliary circuits 641 and 643 .

[0057] In an exemplary embodiment, the auxiliary circuit 641 may include transistors T9 and T11. The transistors T9 and T11 may be P-type transistors. In the following description, it is assumed that the transistors T9 and T11 are P-type transistors; however, they are not limited thereto.

[0058] In an exemplary embodiment, the ninth transistor T9 may be connected between a power supply voltage (VDD) line and a first node ND0. In an embodiment, the source and drain of the ninth transistor T9 may be connected to the power supply voltage (VDD) line and the first node ND0, respectively. In an exemplary embodiment, the ninth transistor T9 may be connected in parallel with the third transistor T3 of the pull-up circuit 610 between the power supply voltage (VDD) line and the first node ND0. In an exemplary embodiment, the ninth transistor T9 may control the first voltage V0 of the first node ND0. The first node ND0 is a node connected to the gate of the fourth transistor T4, and the state of the fourth transistor T4 may be controlled. The gate of the ninth transistor T9 may be connected to the eleventh transistor T11.

[0059] In an exemplary embodiment, the eleventh transistor T11 may be connected between the ninth transistor T9 and the sixth node ND5. In an embodiment, the source and drain of the eleventh transistor T11 may be connected to the gate of the ninth transistor T9 and the sixth node ND5, respectively. The sixth node ND5 may be a node between the sixth transistor T6 and the eighth transistor T8 in the bias circuit 620. In an exemplary embodiment, the eleventh transistor T11 may reduce the voltage difference between the gate and the drain of the ninth transistor T9 and between the gate and the source of the ninth transistor T9. The eleventh transistor T11 may alleviate the degradation of the ninth transistor T9.

[0060] In an exemplary embodiment, the auxiliary circuit 643 may include transistors T10 and T12. The transistors T10 and T12 may be P-type transistors. In the following description, it is assumed that the transistors T10 and T12 are P-type transistors; however, they are not limited thereto.

[0061] In an exemplary embodiment, the tenth transistor T10 may be connected between a power supply voltage (VDD) line and a second node ND1. In an embodiment, the source and drain of the tenth transistor T10 may be connected to the power supply voltage (VDD) line and the second node ND1, respectively. In an exemplary embodiment, the tenth transistor T10 may be connected in parallel with the fourth transistor T4 of the pull-up circuit 610 between the power supply voltage (VDD) line and the second node ND1. In an exemplary embodiment, the tenth transistor T10 may control the second voltage V1 of the second node ND1. The second node ND1 is a node connected to the gate of the third transistor T3, and the state of the third transistor T3 may be controlled. The gate of the tenth transistor T10 may be connected to the twelfth transistor T12.

[0062] In an exemplary embodiment, the twelfth transistor T12 may be connected between the tenth transistor T10 and the fifth node ND4. In an embodiment, the source and drain of the twelfth transistor T12 may be connected to the gate of the tenth transistor T10 and the fifth node ND4, respectively. The fifth node ND4 may be a node between the fifth transistor T5 and the seventh transistor T7 in the bias circuit 620. In an exemplary embodiment, the twelfth transistor T12 may reduce the voltage difference between the gate and the drain of the tenth transistor T10 and between the gate and the source of the tenth transistor T10. The twelfth transistor T12 may alleviate the degradation of the tenth transistor T10.

[0063] Hereinafter, a process will be described in which the input signal IN has a second voltage level (eg, VDD1) before the time point t0 and drops to a first voltage level (eg, VSS) at the time point t0. Figure 6B The timing diagram of describes the operation of each transistor in the level shifter 600. For ease of explanation, Figure 6B The nodes shown in the timing diagram 6000 are shown in a particular order, but not necessarily in the order shown in the timing diagram 6000. Figure 6B The operations are performed in the order shown.

[0064] In an exemplary embodiment, when an input signal having a second voltage level VDD1 is received before time point t0, the first transistor T1 may be turned on, whereby the voltage level of the third node ND2 may be pulled down to the ground voltage VSS. Therefore, the fifth transistor T5 may pull down the voltage level of the fifth node ND4 to the ground voltage VSS. Since the seventh transistor T7 and the twelfth transistor T12 are connected to the fifth node ND4, the voltage levels of the first node ND0 and the eighth node ND7 may be pulled down to the gate voltage (e.g., Vp) of the seventh transistor T7 and the twelfth transistor T12. According to the voltage levels of the first node ND0 and the eighth node ND7, the fourth transistor T4 and the tenth transistor T10 may be turned on, and thus the driving current 656 flowing through the fourth transistor T4 and the tenth transistor T10 may pull up the voltage level of the second node ND1 to the power supply voltage VDD.

[0065] In an exemplary embodiment, the input signal IN may drop from the second voltage level (e.g., VDD1) to the first voltage level (e.g., VSS) at time point t0. As the input signal IN drops, the inverted input signal INB rises. Therefore, the first transistor T1 may be turned off and the second transistor T2 may be turned on. Fig. 6A and Figure 6B As the input signal IN drops from the second voltage level VDD1 to the first voltage level VSS, the inverted input signal INB may rise from the first voltage level VSS to the second voltage level VDD1. As the inverted input signal INB rises, the second transistor T2 may pull down the voltage level of the fourth node ND3 to the ground voltage VSS, and the sixth transistor T6 may pull down the voltage level of the sixth node ND5 to the ground voltage VSS.

[0066] In an exemplary embodiment, since the driving current 651 flows toward the sixth node ND5 through the eleventh transistor T11, the voltage level of the seventh node ND6 may be pulled down to the gate voltage Vp of the eleventh transistor T11, and the ninth transistor T9 may be turned on. Fig. 6A and Figure 6B , as the sixth node ND5 is pulled down to the ground voltage (VSS) level, the voltage level of the seventh node ND6 may be pulled down to the voltage level Vp of the first bias signal BIAS_P.

[0067] In an exemplary embodiment, when the ninth transistor T9 is turned on as the voltage level of the seventh node ND6 is pulled down, a driving current 653 for pulling up the first node ND0 to the power supply voltage (VDD) level may flow, and the voltage level of the first node ND0 may be pulled up to the power supply voltage (VDD) level. Similarly, the voltage level of the fifth node ND4 may be pulled up to the power supply voltage (VDD) level through the seventh transistor T7. In an exemplary embodiment, when the voltage level of the fifth node ND4 is pulled up to the power supply voltage (VDD) level, a driving current 655 flowing through the twelfth transistor T12 may pull up the voltage level of the eighth node ND7 to the power supply voltage (VDD) level. Fig. 6A and Figure 6B As the voltage level of the seventh node ND6 is pulled down, the voltage levels of the first node ND0 and the fifth node ND4 may be pulled up to the power supply voltage (VDD) level. Similarly, the voltage level of the eighth node ND7 may be pulled up to the power supply voltage (VDD) level.

[0068] In an exemplary embodiment, the fourth transistor T4 may be turned off by the voltage level of the first node ND0, and the tenth transistor T10 may be turned off by the voltage level of the eighth node ND7. Therefore, the driving current 656 that has been flowing to the second node ND1 through the fourth transistor T4 and the tenth transistor T10 may be cut off. In an exemplary embodiment, as the driving current 656 that has been flowing through the fourth transistor T4 and the tenth transistor T10 to pull up the voltage level of the second node ND1 is cut off and the voltage level of the sixth node ND5 is pulled down, the driving current 654 for pulling down the voltage level of the second node ND1 may flow through the eighth transistor T8, so that the voltage level of the second node ND1 is pulled down (see Figure 6B ” in the figure). Therefore, the third transistor T3 may be turned off.

[0069] As described above, in order to change the voltage level of the output signal in response to the voltage level of the input signal, it is necessary to change the state of the cross-connected transistors T3 and T4 in the pull-up circuit 610. However, due to the current confrontation between the pull-up current and the pull-down current, the state of the cross-connected transistors T3 and T4 may not change. The level shifter 600 according to the exemplary embodiment can use the drive current 651 flowing through a path different from the path through which the existing pull-up current 656 flows to generate the drive current 653 and 655 for controlling the transistors T4 and T10 through which the existing pull-up current 656 has been flowing. The level shifter 600 according to the exemplary embodiment cuts off the existing pull-up current 656 by turning off the transistors T4 and T10 based on the drive currents 653 and 655, thereby making it easier to control the state of the cross-connected transistors T3 and T4. For example, as the input signal IN drops, in order to change the state of the third transistor T3, the level shifter 600 according to the exemplary embodiment can control the state of the transistors T4 and T10 through the paths in the auxiliary circuits 641 and 643. As the transistors T4 and T10 are turned off, the voltage level of the second node ND1 is pulled down without current opposition by the driving current 654. Therefore, the state of the third transistor T3 can also be changed more easily.

[0070] Figure 7 7 is a circuit diagram of a level shifter according to an exemplary embodiment. The level shifter 700 may include a bias circuit 720 , a pull-down circuit 730 , and auxiliary circuits 741 and 743 .

[0071] In the operation of the level shifter 700, when the input signal IN having the second voltage level VDD1 is received, the first transistor T1 may be turned on, and the voltage level of the third node ND2 may be pulled down to the ground voltage VSS. Therefore, the fifth transistor T5 may pull down the voltage level of the fifth node ND4 to the ground voltage VSS, and the voltage level of the first node ND0 may be pulled down to the gate voltage (e.g., Vp) of the seventh transistor T7. In addition, since the voltage level of the eighth node ND7 is pulled down to the gate voltage (e.g., Vp) of the twelfth transistor T12 as the voltage level of the fifth node ND4 is pulled down to the ground voltage VSS, the tenth transistor T10 may be turned on. Therefore, the voltage level of the second node ND1 may be pulled up to the power supply voltage VDD.

[0072] In an exemplary embodiment, the input signal IN can drop from the second voltage level VDD1 to the first voltage level VSS. Since the inverting input signal INB rises as the input signal IN drops, the first transistor T1 can be turned off and the second transistor T2 can be turned on. Similarly, the voltage level of the fourth node ND3 can be pulled down to the ground voltage VSS. Therefore, the sixth transistor T6 can pull the voltage level of the sixth node ND5 down to the ground voltage VSS. In an exemplary embodiment, since the driving current 751 flows to the sixth node ND5 through the eleventh transistor T11, the voltage level of the seventh node ND6 can be pulled down to the gate voltage Vp of the eleventh transistor T11, and the ninth transistor T9 can be turned on. Therefore, the voltage level of the first node ND0 can be pulled up to the power supply voltage (VDD) level, and the voltage level of the fifth node ND4 can also be pulled up to the power supply voltage (VDD) level through the seventh transistor T7.

[0073] In an exemplary embodiment, when the voltage level of the fifth node ND4 is pulled up to the power supply voltage (VDD) level, the driving current 755 flowing through the twelfth transistor T12 can pull up the voltage level of the eighth node ND7 to the power supply voltage (VDD) level. Therefore, the tenth transistor T10 can be turned off, and the voltage level of the second node ND1 can be pulled down to the gate voltage Vp of the eighth transistor T8 by the driving current 754 flowing through the eighth transistor T8.

[0074] The auxiliary circuits 741 and 743 according to the exemplary embodiment can control the voltage levels of the first node ND0 and the second node ND1 on their respective paths to be subsequently connected to the output circuit. The auxiliary circuits 741 and 743 according to the exemplary embodiment can control the states of the ninth transistor T9 and the tenth transistor T10 on their respective paths to ensure the characteristics of the level shifter 700.

[0075] Hereinafter, the level shifter will be described as including a pull-up circuit; however, the level shifter is not limited thereto as the pull-up circuit may be omitted in other embodiments.

[0076] Figure 8 8 is a block diagram of a level shifter according to an exemplary embodiment. In an embodiment, the level shifter 800 may further include an output circuit 810 for outputting an output signal OUT. Fig.9A and Fig. 9B The configuration of the output circuit 810 is described in detail.

[0077] Fig.9A is a circuit diagram of a level shifter according to an exemplary embodiment.

[0078] The level shifter 900 may receive an input signal IN, a power supply voltage VDD, and a ground voltage VSS. The level shifter 900 may output the power supply voltage VDD and the ground voltage VSS having levels different from those of the input signal IN based on the input signal IN.

[0079] In an exemplary embodiment, the level shifter 900 may include an output circuit 910 for outputting a power supply voltage VDD and a ground voltage VSS having different levels from the input signal IN as an output signal OUT. In an embodiment, the output signal OUT may swing between a power supply voltage (VDD) level and a ground voltage (VSS) level.

[0080] In an exemplary embodiment, the output circuit 910 may include transistors T13 and T16. The thirteenth transistor T13 may be a P-type transistor, and the sixteenth transistor T16 may be an N-type transistor; however, they are not limited thereto.

[0081] In an exemplary embodiment, the thirteenth transistor T13 may be connected between a power supply voltage (VDD) line and a ninth node ND8. A source and a drain of the thirteenth transistor T13 may be connected to the power supply voltage (VDD) line and the ninth node ND8, respectively. In an exemplary embodiment, a gate of the thirteenth transistor T13 may be connected to the first node ND0. In an exemplary embodiment, the thirteenth transistor T13 may be turned on according to a voltage level of a first voltage V0 of the first node ND0, and pulls up a voltage level of the ninth node ND8 to a power supply voltage (VDD) level.

[0082] In an exemplary embodiment, the sixteenth transistor T16 may be connected between a ground voltage (VSS) line and a tenth node ND9. The source and drain of the sixteenth transistor T16 may be connected to the ground voltage (VSS) line and the tenth node ND9, respectively. In an exemplary embodiment, the gate of the sixteenth transistor T16 may be connected to a node receiving an inverted input signal INB. In an exemplary embodiment, the sixteenth transistor T16 may be turned on according to the inverted input signal INB, and the voltage level of the tenth node ND9 may be pulled down to the ground voltage (VSS) level. The level shifter 900 may include an inverter for inverting the input signal IN to generate the inverted input signal INB.

[0083] In an exemplary embodiment, the output circuit 910 may further include transistors T14 and T15. In an exemplary embodiment, the fourteenth transistor T14 may be connected between the ninth node ND8 and the output signal (OUT) line. The source and drain of the fourteenth transistor T14 may be connected to the ninth node ND8 and the output signal (OUT) line, respectively. The gate of the fourteenth transistor T14 may be connected to a node receiving a first bias signal BIAS_P. In an exemplary embodiment, the fourteenth transistor T14 may output the voltage level of the ninth node ND8 as the output signal OUT based on the first bias signal BIAS_P.

[0084] In an exemplary embodiment, the fifteenth transistor T15 may be connected between the tenth node ND9 and the output signal (OUT) line. The source and drain of the fifteenth transistor T15 may be connected to the tenth node ND9 and the output signal (OUT) line, respectively. The gate of the fifteenth transistor T15 may be connected to the second bias signal BIAS_N. In an exemplary embodiment, the fifteenth transistor T15 may output the voltage level of the tenth node ND9 as the output signal OUT based on the second bias signal BIAS_N. In an exemplary embodiment, the fourteenth transistor T14 may be a P-type transistor and the fifteenth transistor T15 may be an N-type transistor; however, they are not limited thereto.

[0085] In an exemplary embodiment, the fourteenth transistor T14 can adjust the lower limit of the voltage level of the ninth node ND8 to be equal to or higher than the voltage level (e.g., Vp) of the first bias signal BIAS_P based on the first bias signal BIAS_P. The fourteenth transistor T14 can reduce the voltage difference between the gate and the drain of the thirteenth transistor T13 and between the gate and the source of the thirteenth transistor T13. This can alleviate the degradation of the thirteenth transistor T13.

[0086] In an exemplary embodiment, the fifteenth transistor T15 can adjust the upper limit of the voltage level of the tenth node ND9 to be equal to or lower than the voltage level (e.g., Vn) of the second bias signal BIAS_N based on the second bias signal BIAS_N. The fifteenth transistor T15 can reduce the voltage difference between the gate and the drain of the sixteenth transistor T16 and between the gate and the source of the sixteenth transistor T16. This can alleviate the degradation of the sixteenth transistor T16.

[0087] In an exemplary embodiment, the output circuit 910 of the level shifter 900 may also output a first output signal OUT1 and / or a second output signal OUT2. In an exemplary embodiment, the first output signal OUT1 may be a voltage level of a ninth node ND8, and the second output signal OUT2 may be a voltage level of a tenth node ND9. In an exemplary embodiment, the first output signal OUT1 may swing between a voltage level Vp of a first bias signal BIAS_P and a power supply voltage (VDD) level. In an exemplary embodiment, the second output signal OUT2 may swing between a voltage level Vn of a second bias signal BIAS_N and a ground voltage (VSS) level.

[0088] Fig. 9B 9000 is a circuit diagram of a level shifter according to an exemplary embodiment. The level shifter 9000 according to the exemplary embodiment may output a power supply voltage VDD and a ground voltage VSS having a level different from that of the input signal IN based on the input signal IN. Fig. 9B The components in the output circuit 910 are Fig.9A The components in the output circuit 910 are the same or similar, so a description thereof will not be provided here.

[0089] In an exemplary embodiment, a gate of the thirteenth transistor T13 of the output circuit 910 is connected to the second node ND1. In an exemplary embodiment, the thirteenth transistor T13 may be turned on according to the voltage level of the second voltage V1 of the second node ND1 and pull up the voltage level of the ninth node ND8 to the power supply voltage (VDD) level.

[0090] In an exemplary embodiment, a gate of the sixteenth transistor T16 in the output circuit 910 may be connected to a node receiving an input signal IN. In an exemplary embodiment, the sixteenth transistor T16 may be turned on according to the input signal IN and pull down a voltage level of the tenth node ND9 to the ground voltage VSS.

[0091] The level shifter 9000 according to an exemplary embodiment may output an inverted signal of the input signal IN as an output signal OUT based on the input signal IN. In an embodiment, the output signal OUT may swing between a power supply voltage (VDD) level and a ground voltage (VSS) level.

[0092] The level shifter 9000 according to the exemplary embodiment may also output a first output signal OUT1 and a second output signal OUT2. The first output signal OUT1 and the second output signal OUT2 may be inverted signals of the input signal IN. In an embodiment, the first output signal OUT1 may swing between the voltage level Vp of the first bias signal BIAS_P and the power supply voltage (VDD) level, and the second output signal OUT2 may swing between the voltage level Vn of the second bias signal BIAS_N and the ground voltage (VSS) level.

[0093] Fig.10 is a layout diagram of a level shifter according to an exemplary embodiment.

[0094] In an exemplary embodiment, the level shifter 1000 may include a pull-up circuit 1010, a bias circuit 1020, a pull-down circuit 1030, auxiliary circuits 1041 and 1042, and an output circuit 1050. The level shifter 1000 may receive an input signal and an inverted input signal from an input circuit 1060, and may output an output signal OUT through the output circuit 1050.

[0095] In an exemplary embodiment, the level shifter 1000 may include a power supply voltage (VDD) line, a first bias voltage (VP) line, a second bias voltage (VN) line, and a ground voltage (VSS) line of a first metal layer M1 extending in a first direction. The power supply voltage (VDD) line, the first bias voltage (VP) line, the second bias voltage (VN) line, and the ground voltage (VSS) line may be spaced apart from each other in a second direction perpendicular to the first direction. Each transistor T1 to T16 in the level shifter 1000 may include a gate terminal and a source / drain terminal. The gate terminal is shown as a multi-contact (PC) layer, and the source / drain terminal is shown as the first metal layer M1; however, they are not limited thereto.

[0096] In an exemplary embodiment, transistors T11 and T12 in the auxiliary circuits 1041 and 1042 are connected to nodes J1 and J2 in the bias circuit 1020, and transistors T9 and T10 connected to transistors T11 and T12 can control transistors T3 and T4 in the pull-up circuit 1010. For example, the first terminal of the eleventh transistor T11 can be connected to the first terminal of the eighth transistor T8 and the first terminal of the sixth transistor T6 through the second metal layer M2, the third metal layer M3, and the fourth metal layer M4. The gate terminal of the eleventh transistor T11 can be connected to the first bias voltage (VP) line, and the second terminal of the eleventh transistor T11 can be connected to the gate terminal of the ninth transistor T9 through the first metal layer M1 and the second metal layer M2. The first terminal of the ninth transistor T9 can be connected to the gate terminal of the fourth transistor T4 through the second metal layer M2, the third metal layer M3, and the fourth metal layer M4. In an embodiment, as the voltage level of the first node J1 is discharged, the eleventh transistor T11 can pull down the voltage level of the gate terminal of the ninth transistor T9, thereby turning on the ninth transistor T9. When the ninth transistor T9 is turned on, the voltage level of the gate terminal of the fourth transistor T4 is pulled up to the power supply voltage (VDD) level through the first terminal of the ninth transistor T9, and thus the fourth transistor T4 may be turned off.

[0097] The level shifter 1000 according to an exemplary embodiment may use the nodes J1 and J2 in the bias circuit 1020 as a current path for changing the states of the transistors T3 and T4 in the pull-up circuit 1010. This may minimize the area occupied by the auxiliary circuits 1041 and 1042 in the level shifter 1000.

[0098] As described above, the transistors T1 to T16 may be connected to each other through the first metal layer M1 to the fourth metal layer M4; however, they are not limited thereto and may be connected to each other through more or less metal layers. Likewise, although not shown in the drawings, the metal layers may be connected through metal paths.

[0099] Fig.11 11 is a circuit diagram of a level shifter according to an exemplary embodiment. The level shifter 1100 according to an exemplary embodiment may further include a first voltage level control circuit 1120 connected to the output circuit 1110 .

[0100] In an exemplary embodiment, the first voltage level control circuit 1120 may include a seventeenth transistor T17. The seventeenth transistor T17 may be connected to a line through which the output circuit 1110 outputs the output signal OUT. In an exemplary embodiment, the seventeenth transistor T17 may change the voltage level of the output signal OUT to be output by the output circuit 1110. The seventeenth transistor T17 may be a P-type transistor.

[0101] In an exemplary embodiment, the seventeenth transistor T17 can adjust the lower limit of the voltage level of the output signal OUT to be equal to or higher than the voltage level of the first bias signal BIAS_P based on the first bias signal BIAS_P to generate an adjusted signal, and output the adjusted signal as the first output signal OUTA. In an embodiment, the voltage level of the first bias signal BIAS_P can be a minimum level (e.g., Vp) for turning on the seventeenth transistor T17. Therefore, the first output signal OUTA output by the seventeenth transistor T17 can be a value swinging between the voltage level Vp of the first bias signal and the power supply voltage (VDD) level.

[0102] Fig.12 12 is a circuit diagram of a level shifter according to an exemplary embodiment. The level shifter 1200 according to an exemplary embodiment may further include a second voltage level control circuit 1220 connected to the output circuit 1210 .

[0103] In an exemplary embodiment, the second voltage level control circuit 1220 may include an eighteenth transistor T18. The eighteenth transistor T18 may be connected to a line through which the output circuit 1210 outputs the output signal OUT. In an exemplary embodiment, the eighteenth transistor T18 changes the voltage level of the output signal OUT to be output by the output circuit 1210. The eighteenth transistor T18 may be an N-type transistor.

[0104] In an exemplary embodiment, the eighteenth transistor T18 can adjust the upper limit of the voltage level of the output signal OUT to be equal to or lower than the voltage level of the second bias signal BIAS_N based on the second bias signal BIAS_N to generate an adjusted signal, and output the adjusted signal as the second output signal OUTA. In an embodiment, the voltage level of the second bias signal BIAS_N can be a minimum level (e.g., Vn) for turning on the eighteenth transistor T18. Therefore, the first output signal OUTA output by the eighteenth transistor T18 can be a value swinging between the voltage level Vn of the second bias signal and the ground voltage (VSS) level.

[0105] The level shifter 1200 according to an exemplary embodiment may include Fig.11 The first voltage level control circuit in Fig.11 Both or one of the reference numeral “1120” in the figure and the second voltage level control circuit 1220 adjusts the voltage level of the output signal OUT to be output in response to the input signal IN.

[0106] Fig.13 is a block diagram illustrating a storage system according to an exemplary embodiment. Fig.13 , the memory system 1300 may include a memory controller 1310 (eg, a controller circuit) and a memory device 1320. The memory device 1320 may include a level shifter 1330 according to example embodiments.

[0107] In an exemplary embodiment, the storage system 1300 can be installed in the form of a system on chip (SOC) in an electronic device such as a computer, a laptop, a cellular phone, a smart phone, an MP3 player, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital TV, a digital camera, a portable game console, a modem, etc.

[0108] The memory controller 1310 may read data DATA from the memory device 1320 and write data DATA to the memory device 1320 in response to a read / write request of an external host HOST (not shown). The memory controller 1310 may output a control signal CTRL, a command CMD, an address ADDR, and data DATA to the memory device 1320, and receive data DATA from the memory device in response to the read / write request.

[0109] The memory device 1320 is a device for storing data and may include a volatile memory such as a dynamic random access memory (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), or the like, or a non-volatile memory such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or the like.

[0110] The memory device 1320 may include a level shifter 1330 according to an exemplary embodiment of the present invention. The memory device 1320 may generate an output signal having a voltage higher or lower than a voltage applied from the outside through the level shifter 1330. The level shifter 1330 may be implemented by any of the previously described level shifters. Figures 14 to 17 The memory device 1320 and an operation method of the level shifter 1330 in the memory device 1320 are described.

[0111] Fig.14 It is used to illustrate Fig.13 Schematic block diagram of a storage device in FIG.

[0112] The memory device 1400 may include a memory cell array 1414, a voltage generator 1412, a row address decoder 1413, and a control circuit 1411. However, the memory device 1400 may further include other constituent elements such as a page buffer. Fig.13 The memory device 1320 may be implemented by the memory device 1400 .

[0113] The control circuit 1411 may provide various control signals related to memory operation to the voltage generator 1412 and the row address decoder 1413. The control circuit 1411 may control the overall operation of the memory device 1400. The control circuit 1411 may use a control signal based on a slave memory controller (see Fig.13 The memory device 1400 is controlled by an internal control signal of at least one of an address ADDR, a command CMD, and a control signal CTRL received by the memory device 1400 (reference numeral "1310" in FIG. 1 ). For example, the control circuit 1411 may generate a control signal CTRL for controlling a voltage generator 1412, or generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 1411 may output the row address R_ADDR to a row address decoder 1413.

[0114] The voltage generator 1412 may generate various voltages for performing a program operation and a read operation on the memory cell array 1414. The voltage generator 1412 may generate various word line voltages to be supplied to the word lines WL in the memory cell array 1414 based on the control signal CTRL of the control circuit 1411. The voltage generator 1412 may include a level shifter 1420 according to an exemplary embodiment. The level shifter 1420 may be implemented by any of the previously described level shifters. Fig.15 The operating method of the level shifter 1420 is described in detail.

[0115] The row address decoder 1413 may be connected to the memory cell array 1414 through a word line WL. The row address decoder 1413 may select the word line WL by decoding the row address R_ADDR. The row address decoder 1413 may provide the voltage signal Vg supplied from the voltage generator 1412 to the word line WL. The row address decoder 1413 may receive a read voltage or a program voltage from the voltage generator 1412 and provide them to a selected word line WL connected to a plurality of memory cells.

[0116] Fig.15 It is used to illustrate Fig.14 Schematic diagram of a level shifter in a voltage generator in FIG. Fig.15 14 is a diagram for explaining an operation method of a level shifter in the voltage generator 1412 of the memory device 1400 .

[0117] In an exemplary embodiment, the voltage generator 1412 may generate a voltage to be supplied to the memory cell array (see Fig.14 The voltage generator 1412 may include a read voltage generator 1431 for generating a read voltage Vread to be transmitted to the word line WL, a program voltage generator 1433 for generating a program voltage Vpgm, and a reference voltage generator 1435 for generating a reference voltage Vref for additional operations.

[0118] In an exemplary embodiment, the read voltage generator 1431, the program voltage generator 1433, and the reference voltage generator 1435 in the voltage generator 1412 may use a voltage having a different level from the external voltage. For example, the read voltage generator 1431, the program voltage generator 1433, and the reference voltage generator 1435 may operate by receiving a voltage having a higher level than the external voltage as an input voltage. Therefore, the level shifters 1421, 1423, and 1425 may supply voltages having different levels to be provided to the read voltage generator 1431, the program voltage generator 1433, and the reference voltage generator 1435 based on the external voltage. The level shifters 1421, 1423, and 1425 may be implemented by any of the previously described level shifters.

[0119] In an exemplary embodiment, the level shifters 1421, 1423, and 1425 include an auxiliary circuit for providing a path different from a path for pulling up the voltage level of the output voltage in response to an input signal. In an exemplary embodiment, the level shifters 1421, 1423, and 1425 can more easily change the voltage level of the output voltage by controlling transistors in the level shifters 1421, 1423, and 1425 through a path different from a path for pulling up the voltage level of the output voltage in response to an input signal.

[0120] Fig.16 It is used to illustrate Fig.13 15. The memory device 1500 may include a memory cell array 1514, a voltage generator 1512, a row address decoder 1513, and a control circuit 1511. However, the memory device 1500 may also include other constituent elements such as a column address decoder.

[0121] Regarding the memory device 1500, no further information will be provided herein. Fig.14 Description of duplicate description.

[0122] In an exemplary embodiment, the row address decoder 1513 may be connected to the memory cell array 1514 through the word line WL. The row address decoder 1513 may select a row to be activated from a plurality of rows of the memory cell array 1514 based on the row address R_ADDR. The row address decoder 1513 may receive a word line voltage Vg to be supplied to the word line WL from the voltage generator 1512, and apply the corresponding word line voltage to the word line WL corresponding to the row to be activated. In an exemplary embodiment, the row address decoder 1513 may include a level shifter 1520 according to an exemplary embodiment. This will be described below with reference to FIG. Fig.17 A level shifter 1520 is described. The level shifter 1520 may be implemented by any of the previously described level shifters.

[0123] Fig.17 It is used to illustrate Fig.16 Schematic block diagram of a level shifter in a row address decoder in FIG. Fig.17 This is a diagram for explaining the operation method of the level shifter in the row address decoder 1513 of the memory device 1500.

[0124] In an exemplary embodiment, the memory device 1500 may include a row address decoder 1513 and a memory cell array 1514. The memory cell array 1514 may include a plurality of memory cells MC. The memory cell array 1514 may include a plurality of rows and a plurality of columns. The plurality of memory cells MC may be arranged at the intersections of the plurality of rows and the plurality of rows. In an exemplary embodiment, the plurality of rows may be defined by a plurality of word lines WL, and the plurality of columns may be defined by a plurality of bit lines BL.

[0125] In an exemplary embodiment, the memory cell array 1514 may include a word line driver 1530. The word line driver 1530 may be connected to each of a plurality of word lines WL connected to memory cells MC disposed in the memory cell array 1514. In other words, the word line WL is driven by the word line driver 1530, and when the bit line BL is selected, one memory cell corresponding to the bit line can be accessed among the memory cells MC. In an exemplary embodiment, the access operation mode of the memory device 1500 includes a read operation and a program operation.

[0126] In an exemplary embodiment, a plurality of memory cells MC connected to all or some of the word lines WL in the memory cell array 1514 may use a voltage having a level different from the external voltage. The row address decoder 1513 may use a level shifter 1520 to provide a voltage having a level different from the external voltage to the word line driver 1530. The output voltage generated by the level shifter 1520 may be provided to the word line WL through the word line driver 1530.

[0127] In an exemplary embodiment, the level shifter 1520 may include an auxiliary circuit for providing a path different from a path for pulling up the voltage level of the output voltage in response to an input signal. In an exemplary embodiment, the level shifter 1520 may more easily change the voltage level of the output voltage by controlling transistors in the level shifter 1520 via a path different from a path for pulling up the voltage level of the output voltage in response to an input signal.

[0128] Although the inventive concept has been described with respect to what is currently considered to be an exemplary embodiment of the inventive concept, it should be understood that the inventive concept is not limited to the disclosed embodiments. On the contrary, the inventive concept is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A level shifter, comprising: a first circuit configured to pull down a first output node and a first intermediate node based on an input signal, and to pull down a second output node and a second intermediate node based on an inverted input signal of the input signal; as well as a second circuit configured to pull up the second output node to a power supply voltage based on the first intermediate node when the first circuit pulls down the first output node, and to pull up the first output node to the power supply voltage based on the second intermediate node when the first circuit pulls down the second output node.

2. The level shifter according to claim 1, wherein: The second circuit comprises: a first transistor connected between the first node and the second intermediate node and including a gate configured to receive a first bias signal; a second transistor connected between a line configured to apply the power supply voltage and the first output node and including a gate connected to the first node; a third transistor connected between the second node and the first intermediate node and including a gate configured to receive the first bias signal; and A fourth transistor is connected between a line to which the power supply voltage is applied and the second output node, and includes a gate connected to the second node.

3. The level shifter according to claim 1, wherein: The first circuit comprises: a first transistor connected between a line to which a ground voltage is applied and a first node and including a gate configured to receive the input signal; and A second transistor is connected between a line to which the ground voltage is applied and a second node and includes a gate configured to receive the inverted input signal.

4. The level shifter according to claim 3, further comprising: a third circuit configured to adjust an upper limit of a voltage level of the first intermediate node and the second intermediate node to be equal to or lower than a first bias voltage, and to adjust a lower limit of a voltage level of the first output node and the second output node to be equal to or higher than a second bias voltage different from the first bias voltage.

5. The level shifter according to claim 4, wherein: The first bias voltage is lower than the power supply voltage, and the second bias voltage is higher than the ground voltage.

6. The level shifter according to claim 4, wherein: The third circuit comprises: a third transistor connected between the first intermediate node and the first node and including a gate configured to receive the first bias voltage; a fourth transistor connected between the second intermediate node and the second node and including a gate configured to receive the first bias voltage; a fifth transistor connected between the first output node and the first intermediate node and including a gate configured to receive the second bias voltage; and A sixth transistor is connected between the second output node and the second intermediate node and includes a gate configured to receive the second bias voltage.

7. The level shifter according to claim 1, further comprising: A third circuit is configured to pull up an output node configured to output an output signal to the power supply voltage based on a voltage level of the first output node, and pull down the output node based on the inverted input signal.

8. The level shifter according to claim 7, wherein: The third circuit comprises: a first transistor connected between a line to which the power supply voltage is applied and a first node and including a gate connected to the first output node; and A second transistor is connected between a line to which the ground voltage is applied and a second node and includes a gate configured to receive the inverted input signal.

9. The level shifter according to claim 8, wherein: The third circuit further includes: a third transistor connected between the first node and the output node and including a gate configured to receive a first bias signal; and A fourth transistor is connected between the output node and the second node and includes a gate configured to receive a second bias signal different from the first bias signal.

10. The level shifter according to claim 9, further comprising: A fifth transistor including a gate configured to receive the first bias signal is connected to the output node and configured to adjust a lower limit of a voltage level of the output node to be equal to or higher than a voltage level of the first bias signal.

11. The level shifter according to claim 9, further comprising: A fifth transistor including a gate configured to receive the second bias signal is connected to the output node and configured to adjust an upper limit of a voltage level of the output node to be equal to or lower than a voltage level of the second bias signal.

12. The level shifter according to claim 1, further comprising: A third circuit is configured to pull up an output node configured to output an output signal to the power supply voltage based on a voltage level of the second output node, and pull down the output node based on the input signal.

13. The level shifter according to claim 1, further comprising: A third circuit is configured to pull up the second output node to the power supply voltage based on the voltage level of the first output node, and to pull up the first output node to the power supply voltage based on the voltage level of the second output node.

14. A level shifter, comprising: a first transistor connected between a first line at a first voltage level and a first node and including a gate connected to a second node; a second transistor connected between the first line and the second node and including a gate connected to the first node; a third transistor connected in parallel with the first transistor between the first line and the first node and configured to turn off the second transistor based on an input signal; as well as A fourth transistor is connected in parallel with the second transistor between the first line and the second node and is configured to turn off the first transistor and the third transistor based on an inverted input signal of the input signal.

15. The level shifter according to claim 14, further comprising: a fifth transistor connected between the first node and a third node and including a gate configured to receive a first bias voltage; a sixth transistor connected between the second node and a fourth node and including a gate configured to receive the first bias voltage; a seventh transistor connected between the third node and the fifth node and including a gate configured to receive a second bias voltage different from the first bias voltage; as well as An eighth transistor is connected between the fourth node and the sixth node and includes a gate configured to receive the second bias voltage.

16. The level shifter according to claim 15, further comprising: a ninth transistor connected between the second line at the second voltage level and the fifth node and including a gate configured to receive the input signal; as well as A tenth transistor is connected between the second line and the sixth node and includes a gate configured to receive the inverted input signal.

17. The level shifter according to claim 15, further comprising: a ninth transistor connected between the gate of the third transistor and the fourth node and including a gate configured to receive the first bias voltage; as well as A tenth transistor is connected between the gate of the fourth transistor and the third node and includes a gate configured to receive the first bias voltage.

18. A memory device, comprising a row address decoder and a memory cell array, wherein the row address decoder comprises a level shifter, wherein the level shifter is configured to: upon receiving a first input signal, generating an output signal by pulling up a voltage level of a first node to a first voltage level different from a voltage level of the first input signal by a first current flowing through a first path; upon receiving a second input signal that is an inverted signal of the first input signal, cutting off the first current by causing a second current to flow through a second path different from the first path; as well as When the second input signal is received and the first current is cut off, the voltage level of the first node is pulled down to a second voltage level different from the first voltage level by a third current flowing through a third path, The memory cell array includes a word line configured to receive the output signal and a plurality of memory cells connected to the word line.

19. The memory device according to claim 18, wherein: The level shifter is configured to pull up the voltage level of the first node to the first voltage level by a fourth current flowing through a fourth path when the first input signal is received.

20. The memory device according to claim 19, wherein: The second current is further configured to cut off the fourth current.

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