Data gate switching by controller

Abstract

The invention relates to data strobe switching by a controller. A method includes providing a first plurality of data signals and a first plurality of clock signals to a flip-flop circuit to generate a first plurality of outputs corresponding to the first plurality of data signals and the first plurality of clock signals; providing the first plurality of outputs to a first-in first-out (FIFO) device; providing a second plurality of data signals to the flip-flop circuit; providing a second plurality of clock signals generated by a controller to the flip-flop circuit; and providing a second plurality of outputs corresponding to the second plurality of data signals and the second plurality of clock signals to move the first plurality of outputs through the FIFO device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to data strobe (DQS) switching by a controller. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One aspect of the present disclosure relates to a method for data gating switching, comprising: providing a first plurality of data signals and a first plurality of clock signals to a flip-flop circuit to generate a first plurality of outputs corresponding to the first plurality of data signals and the first plurality of clock signals; providing the first plurality of outputs to a first-in-first-out (FIFO) device; providing a second plurality of data signals to the flip-flop circuit; providing a second plurality of clock signals generated by a controller to the flip-flop circuit; and providing a second plurality of outputs corresponding to the second plurality of data signals and the second plurality of clock signals to move the first plurality of outputs through the FIFO device.

[0004] Another aspect of the present disclosure relates to an apparatus for data strobe switching, comprising: a memory device interface, comprising: a first flip-flop circuit, which is used to receive a data signal from a data processing circuit; a second flip-flop circuit, which is used to receive a clock signal from a clock processing circuit; a first first-in-first-out (FIFO) device, which is used to receive first output data from the first flip-flop circuit; and a second FIFO device, which is used to receive second output data from the second flip-flop circuit; and a controller, which is configured to: receive the first output data from the first FIFO device; receive the second output data from the second FIFO device; generate an additional clock signal to be provided to the second flip-flop to generate additional output data; and notify a memory resource associated with the memory device to ignore the additional output data.

[0005] Yet another aspect of the present disclosure relates to a system for data strobe switching, comprising: a memory subsystem including a nonvolatile memory device; and a processing device coupled to the memory subsystem, wherein the processing device is configured to: generate a plurality of clock signals corresponding to a plurality of data signals received from the nonvolatile memory device; identify output values ​​within a first-in-first-out (FIFO) device based on the plurality of data signals and the plurality of clock signals; generate an additional clock signal when the nonvolatile memory device has completed sending the plurality of data signals; send the additional clock signal to the FIFO device; and instruct the nonvolatile memory device to provide an additional data signal to the FIFO device based on the additional clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 A system for DQS switching by a controller according to some embodiments of the present disclosure is described.

[0009] Figure 3 is a flow chart corresponding to a method for DQS switching according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to data strobe (DQS) switching performed by a controller, and in particular, to a memory subsystem including a switching component. The memory subsystem may be a memory system, a memory device, a memory module, or a combination thereof. An example of a memory subsystem is a memory system such as a solid state drive (SSD). Figure 1 Examples of storage devices and memory modules are described in , etc. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0012] The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a NAND (Negative AND) memory device (also known as flash technology). As used herein, a NAND memory device can include a set of flash memory dies or a combination of flash memory dies and a non-volatile memory (NVM) controller. The NVM controller can include circuitry for performing read / write operations as described herein. Other examples of non-volatile memory devices are described below in conjunction with Figure 1 A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. A block in the following text refers to a unit of a memory device used to store data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. For some memory devices, a block (also referred to as a "memory block" in the following text) is the smallest erasable area. A page cannot be erased individually, and only an entire block can be erased.

[0013] Each of the memory devices can include one or more arrays of memory cells. Depending on the cell type, the cells can be written to store one or more binary information bits and have various logical states related to the number of bits stored. The logical states can be represented by binary values (e.g., "0" and "1") or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one information bit and has two logical states.

[0014] Some NAND memory devices employ a floating-gate architecture, in which memory access is controlled based on the relative voltage change between the bit line and the word line. Other examples of NAND memory devices can employ a replacement-gate architecture, which can include using a word line layout that can allow charge corresponding to a data value to be trapped within a memory cell based on the properties of the material used to construct the word line.

[0015] In some previous methods, a first-in-first-out (FIFO) device may be utilized to buffer communications between a memory device and a controller during a read operation and / or a write operation. A FIFO device may be utilized to buffer communication signals between devices that operate at different speeds or utilize independent clock signals. A FIFO device may be utilized to increase bandwidth and prevent data loss during high-speed communications. In some embodiments, a FIFO device may release data from a buffer in the order in which the data arrives. That is, a signal may be provided to the input of the FIFO device and released at the output of the FIFO device in the order in which the signal is received at the input of the FIFO device.

[0016] In such methods, the input of the FIFO device may be coupled to a trigger circuit. In general, a trigger circuit or a latch circuit is a circuit having two stable states and can be used to store state information. The trigger circuit can be changed in state by a signal applied to one or more control inputs, and will have one or two outputs. In this way, whenever a signal is received at the input of the trigger circuit, the trigger circuit can change state information. In some embodiments, the FIFO device may include a plurality of stages or storage locations for storing a signal received from the output of the trigger circuit at the input of the FIFO device. A plurality of stages may each be used to store a corresponding state based on a received signal. When the FIFO device receives an additional signal, the previous signal is moved to the next stage until the signal is moved to the output of the FIFO device. In this way, when an additional signal is received from the trigger circuit at the input of the FIFO device, the signal received at the input of the FIFO device can be "pushed" through each of the plurality of stages until the signal is directed to the output of the FIFO device.

[0017] In previous methods, the FIFO device is positioned within the physical layer (PHY) of the memory device. In these methods, a data signal (DQ signal) may be provided by a memory device such as a NAND device. In addition, a strobe signal (DQS signal) may be provided by a controller device. A DQS signal may be generated for each DQ signal provided by the memory device. In this way, output data may be generated at a trigger circuit based on a received DQ signal and a DQS signal at the trigger circuit. The output data may be provided to the FIFO device so as to be provided to the controller in the order in which the output data is received at the FIFO device. In some embodiments, when the memory device and / or the controller stops providing a signal to the input of the trigger circuit, the output data, the DQ signal, and / or the DQS signal may be captured within the trigger circuit and / or the FIFO device. In this way, a delay may occur when processing a DQ signal from a memory device.

[0018] Aspects of the present disclosure address the above and other deficiencies by using DQS switching by a controller. For example, the present disclosure may utilize multiple trigger circuits within a PHY that are coupled to pipeline stages of a FIFO device placed outside the PHY or within an ASIC voltage domain. Compared to other configurations (such as those employed in previous methods), this configuration may allow the substrate area of ​​the FIFO device to be increased. As used herein, substrate area refers to the physical area used to locate components on a memory device. In these embodiments, the controller may generate additional DQS signals that are used to push data through the trigger circuits and pipeline stages of the FIFO device. The controller may then send instructions to the NAND device to generate additional DQ signals corresponding to the additional DQS signals. In this way, data corresponding to the DQ signals retained in the FIFO device may be pushed through the FIFO device for processing. In these embodiments, the additional DQ signals and DQS signals may be marked as being ignored as "discarded item data" when being processed because the DQ signals do not correspond to data stored on the NAND device.

[0019] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0023] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 130, 140 may include one or more arrays of memory cells. One type of memory cell (e.g., a single level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells (e.g., SLC, MLC, TLC, QLC, PLC, or any combination thereof). In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0028] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] As described above, the memory component may be a memory die or a memory package that forms at least a portion of the memory device 130. In some embodiments, a block of memory cells may form one or more "super blocks". As used herein, a "super block" generally refers to a group of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of several interleaved NAND blocks may be deployed across multiple memory dies having multiple planes and / or pages associated therewith. Given the context of the present disclosure, the terms "super block", "block", "memory cell block" and / or "interleaved NAND block" and variations thereof may be used interchangeably.

[0030] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130 and / or the memory device 140, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.). The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0034] In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140. For example, in some embodiments, memory device 140 may be a DRAM and / or SRAM configured to operate as a cache for memory device 130. In such examples, memory device 130 may be NAND.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory subsystem 110 may also include additional circuitry or components not illustrated.

[0036] The memory subsystem 110 may include a switching component 113, which may be referred to herein as a "controller." Figure 1 113 to facilitate aspects of media management, as described in detail herein. In some embodiments, switching component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow switching component 113 to coordinate and / or perform the operations described herein.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the switching component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the switching component 113 is part of the memory subsystem 110, an application, or an operating system.

[0038] In a non-limiting example, a device (e.g., computing system 100) may include switching component 113. Switching component 113 may reside on memory subsystem 110. As used herein, the term "residing on" refers to something that is physically located on a particular component. For example, switching component 113 "residing on memory subsystem 110" refers to a condition in which the hardware circuitry in which switching component 113 is included is physically located on memory subsystem 110. The term "residing on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0039] As referenced in this article Figure 2Further describing, the memory subsystem 110 may include a first flip-flop circuit for receiving a data signal from a data processing circuit. In these embodiments, the memory subsystem 110 may include a second flip-flop circuit for receiving a clock signal from a clock processing circuit. In some embodiments, the memory subsystem 110 may include a first first-in-first-out (FIFO) device for receiving first output data from the first flip-flop circuit and a second FIFO device for receiving second output data from the second flip-flop circuit. In this manner, the input of the first flip-flop circuit may be coupled to the DQ processing circuit and the output of the first flip-flop circuit may be coupled to the input of the first FIFO device. Additionally, the input of the second flip-flop circuit may be coupled to the DQS processing circuit and the output of the second flip-flop circuit may be coupled to the second FIFO device.

[0040] The switching component 113 may be configured to receive first output data from the first FIFO device. The first output data from the first FIFO device may be output data that is pushed through the first flip-flop circuit and through the first FIFO device to the output of the first FIFO device. In these examples, the first output data from the first FIFO device may be based on a signal received from the DQ processing circuit. As described herein, when a signal (e.g., a clock signal) is received at the input of the first flip-flop circuit, the first flip-flop circuit may change the state of the data value (e.g., a data value of logic "1" or logic "0"). In this manner, for each signal provided by the DQ processing circuit to the input of the flip-flop circuit, the DQ processing circuit may cause the state of the data value stored by the first flip-flop circuit to be altered (e.g., "flipped" or "inverted").

[0041] As described herein, in order to transfer the state of the first flip-flop circuit (e.g., a logic value of "1" or "0") to the input of the first FIFO device, the first flip-flop circuit needs to receive a subsequent signal. In this manner, if the DQ processing circuit does not provide an additional signal to the input of the first flip-flop circuit, the state within the first flip-flop circuit may not be transferred to the first FIFO device. As described herein, this may cause delays in some methods when attempting to process signals from the DQ processing circuit.

[0042] The switching component 113 may be configured to receive the second output data from the second FIFO device. The second output data from the second FIFO device may be output data that is pushed through the second flip-flop circuit and through the second FIFO device. In some embodiments, the DQS processing circuit may provide a signal to the input of the second flip-flop circuit and the output signal of the second flip-flop circuit may be provided to the input of the second FIFO device.

[0043] As described herein, in order to transfer the state of the second flip-flop circuit to the input of the second FIFO device, the second flip-flop circuit needs to receive a subsequent signal. In this manner, if the DQS processing circuit does not provide an additional signal to the input of the second flip-flop circuit, the state within the second flip-flop circuit may not be transferred to the second FIFO device. As described herein, this causes delays in previous approaches when attempting to process signals from the DQS processing circuit.

[0044] The switching component 113 may be configured to generate an additional clock signal to be provided to the second flip-flop circuit to generate additional output data. The additional clock signal provided to the second flip-flop circuit may be a signal generated by the switching component 113. In some embodiments, the additional clock signal may be generated so that the additional clock signal does not correspond to data to be read or written by the memory device 130 / 140. That is, the data generated from the additional clock signal may be referred to as discarded item data. As used herein, "discarded item data" refers to data or signals that are marked as being disregarded or ignored by a device, such as (several) memory devices 130 / 140.

[0045] In some embodiments, the additional clock signal may emulate a signal generated by the DQS processing circuit. In this manner, the additional clock signal may be provided to the input of the second flip-flop circuit to move the signal stored in the second flip-flop circuit to the input of the second FIFO device and push the data through the second FIFO device. In this manner, the DQS signal from the DQS processing circuit to be used to process the data held in the second flip-flop circuit and / or FIFO device may be pushed through the memory device 130 / 140 to avoid lags in processing the data.

[0046] In some embodiments, the switching component 113 can be configured to instruct the memory device 130 / 140 (e.g., NAND, etc.) to generate and provide an additional signal to the input of the first flip-flop circuit to correspond to the additional clock signal provided to the second flip-flop circuit by the switching component 113. In this way, output data that is pending within the first flip-flop circuit and / or the second flip-flop circuit can be processed. In these embodiments, the additional signal provided to the first flip-flop circuit and the second flip-flop circuit can be marked as ignored or disregarded.

[0047] The switching component 113 may be configured to notify a storage resource associated with the memory device 130 to ignore the additional output data. In some embodiments, the switching component may generate a notification to be provided to a memory resource associated with the memory device 130. For example, the notification may indicate a particular flag or mark used to mark obsolete data to be ignored. As described herein, the additional output data generated by the additional signal may be marked or labeled to indicate that the additional output data is obsolete data or data not utilized by the memory subsystem 110. That is, data from the additional clock signal provided to the first flip-flop circuit and / or the second flip-flop circuit may be discarded or ignored instead of being processed.

[0048] Figure 2 A system 221 for DQS switching by a controller 222 according to some embodiments of the present disclosure is illustrated. In some embodiments, the system 221 may include Figure 1 Components or elements similar to the memory system 110 of the present invention. In some embodiments, the controller 222 may be Figure 1 At least a portion of the switching component 113.

[0049] The system 221 may include a PHY voltage domain 224 and an application specific integrated circuit (ASIC) core voltage domain 223. As described herein, the PHY voltage domain 224 may be a physical layer of the circuitry of the system 221. In these embodiments, the ASIC core voltage domain 223 may include an integrated circuit customized for a specific purpose. In these embodiments, the system 221 may include a first FIFO device 233 and a second FIFO device 234 located (e.g., deployed) within the ASIC core voltage domain 223. In these embodiments, the system 221 includes a first flip-flop circuit 231 and a second flip-flop circuit 232 located on the PHY voltage domain 224. As described herein, previous methods may locate the first FIFO device 233 and the second FIFO device 234 within the PHY voltage domain. In this manner, the present disclosure moves the first FIFO device 233 and the second FIFO device 234 from the PHY voltage domain 224 to the ASIC core voltage domain 223.

[0050] The system 221 may include a DQ processing circuit 225 to provide a DQ signal from a NAND or other type of memory device. The DQ processing circuit 225 may include various hardware circuit systems that may be configured to provide the DQ signal to the delay line 227. The delay line 227 may be an arbiter or similar circuit system to ensure that the signals are not provided to the devices simultaneously or substantially simultaneously. The DQ signal may be provided to the first flip-flop circuit 231 and / or the second flip-flop circuit 232. In some embodiments, the first flip-flop circuit 231 may store a first value corresponding to the first DQ signal received from the delay line 227. In these embodiments, the first flip-flop circuit 231 may provide the first value to the first FIFO device 233 upon receiving the second DQ signal received from the delay line 227. In this embodiment, the first flip-flop circuit 231 may store a second value corresponding to the second DQ signal, and store the second value until a subsequent DQ signal is received by the first flip-flop circuit 231.

[0051] In a similar manner, the system 221 may include a DQS processing circuit 226 to provide a DQS signal from the controller 222. The DQS processing circuit 226 may include various hardware circuit systems that may be configured to provide the DQS signal to the delay line 228. The delay line 228 may be an arbiter or similar circuit system to ensure that the signals are not provided to the devices simultaneously or substantially simultaneously. In some embodiments, the DQS signal from the delay line 228 is provided to a NAND gate 229, which may receive the DQS signal from the DQS processing circuit 226 and / or the controller 222. In some embodiments, the controller 222 may be configured to generate a plurality of clock signals corresponding to a plurality of data signals received from the memory device. That is, the controller 222 may generate a clock signal for each data signal generated by the memory device (e.g., NAND device, etc.).

[0052] The DQS signal may be provided to the second flip-flop circuit 232 and / or the first flip-flop circuit 231. In some embodiments, the second flip-flop circuit 232 may store a first value of the first DQS signal received from the NAND gate 229. In these embodiments, upon receiving the second DQS signal received from the NAND gate 229, the second flip-flop circuit 232 may provide the first value to the second FIFO device 234. In this embodiment, the second flip-flop circuit 232 may store a second value corresponding to the second DQS signal, and store the second value until a subsequent DQS signal is received by the second flip-flop circuit 232.

[0053] In some embodiments, the first FIFO device 233 and the second FIFO device 234 may include several stages so that the data received at the input is transmitted through each of the stages before being transmitted from the corresponding FIFO device to the controller 222. For example, the first FIFO device 233 may include four stages. Although four stages are described, any number of stages may be utilized in a similar manner. In this example, the first FIFO device 233 may receive a first value (e.g., state) or a first DQ signal from the first flip-flop circuit 231. The first value may be stored at the first stage of the first FIFO device 233. In this example, the first FIFO device may receive a second value (e.g., state) or a second DQ signal from the first flip-flop circuit 231. The first FIFO device 233 may push the first value to the second stage and store the second value at the first stage. For each value received at the first FIFO device 233, the received value may be stored at the first stage and other values ​​may be pushed to the next stage until the value is pushed out of the fourth stage and pushed to the controller 222. When receiving the DQS signal from the NAND gate 229 , the second FIFO device 234 may operate in a similar manner to the first FIFO device 233 .

[0054] In some embodiments, the controller 222 may be configured to identify an output value based on a plurality of data signals and a plurality of clock signals applied to the FIFO device. In some embodiments, the output value may be a value that is set aside or captured within the FIFO device. The controller 222 may be able to identify a captured output value within the FIFO device based on the number of data signals and clock signals provided to the DQ processing circuit 225 and the DQS processing circuit 226, respectively. For example, the data signal and / or the clock signal may be a number that will cause the output data to be captured at a particular stage of the system 221. In some embodiments, the controller 222 may be configured to calculate the number of additional clock signals based on the number of bits to be provided to the memory device and the number of bits used by the first FIFO device 233 and the second FIFO device 234.

[0055] In another example, the controller 222 may be able to identify the captured output value when the NAND stops providing the data signal to the DQ processing circuit 225. For example, the controller 222 may be configured to identify the last clock signal from the memory device and determine the number of additional clock signals to be generated based on the number of bits within the FIFO device and the size of the FIFO device. As described herein, the size of the FIFO device may correspond to the maximum number of storage locations of the FIFO device and / or the number of stages associated with the FIFO device. In this manner, the controller 222 can determine the number of additional clock signals and data signals required to push the captured data within the FIFO device out of the FIFO device.

[0056] In some embodiments, the controller 222 may be configured to generate an additional clock signal when the memory device has completed sending a plurality of data signals. In these embodiments, the controller 222 may send the additional clock signal to the FIFO device (e.g., the second FIFO device 234) through the second flip-flop circuit 232. As further described herein, the controller 222 may be configured to instruct the memory device to provide additional data signals to the FIFO device (e.g., the first FIFO device 233) through the first flip-flop circuit 231 based on the additional clock signal.

[0057] As described herein, the process of pushing the DQ signal through the first flip-flop circuit 231 and the first FIFO device 233 to the controller 222 and pushing the DQS signal through the second flip-flop circuit 232 and the second FIFO device 234 to the controller 222 may traditionally result in data being held in one or more of the first flip-flop circuit 231, the first FIFO device 233, the second flip-flop circuit, and / or the second FIFO device 234. For this reason, the present disclosure may utilize the controller 222 to provide an additional DQS signal to the NAND gate 229 through the connection 235. In these embodiments, the additional DQS signal from the controller 222 to the NAND gate 229 may correspond to data to be ignored or identified as obsolete item data. The additional DQS signal from the controller 222 through the connection 235 may be used to push the held data through the second flip-flop circuit 232 and / or the second FIFO device 234.

[0058] In some embodiments, the controller 222 may determine the number of additional DQS signals to provide based on the amount of data that is pending within the second flip-flop circuit 232 and / or the second FIFO device 234. That is, the controller 222 may determine the number of additional DQS signals required to push the last received DQS signal from the DQS processing circuit 226 through the second flip-flop circuit 232 and / or the second FIFO device 234. In some embodiments, the additional DQS signals may be marked or flagged by the controller 222 as unusable signals or signals to be ignored.

[0059] In some embodiments, the controller 222 may send a signal or communication that provides the DQ signals to the DQ processing circuitry to the NAND or memory device. In these embodiments, the controller 222 may send a communication signal to the NAND to generate additional DQ signals to the DQ processing circuitry 225. In some embodiments, the number of additional DQ signals generated by the NAND or memory device may be the same as or similar to the number of additional DQS signals generated by the controller 222 and provided to the NAND gate 229. In a manner similar to the additional DQS signals, the additional DQ signals may be utilized to push the stored data within the first flip-flop circuit 231 and / or the first FIFO device 233. Additionally, the additional DQ signals may be marked or annotated as signals to be ignored or prevented from being processed.

[0060] Figure 3 is a flowchart corresponding to method 341 for DQS switching according to some embodiments of the present disclosure. Method 341 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 341 is performed by Figure 1 the switching component 113. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated process may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 342, method 341 may be executed to provide a first plurality of data signals and a first plurality of clock signals to a flip-flop circuit to generate a first plurality of outputs corresponding to the first plurality of data signals and the first plurality of clock signals. As used herein, a data signal may refer to a DQ signal provided by a NAND device or other type of memory storage device. As described herein, the DQ signal may be provided to Figure 2 the DQ processing circuitry 225 of Figure 2 and provided to the first flip-flop circuit 231 of Figure 2 As used herein, a clock signal may refer to a DQS signal provided by the controller. As described herein, the DQS signal may be provided to Figure 2 the DQS processing circuitry 226 of

[0062] In some embodiments, the data signal is compared to the clock signal to determine the output based on the comparison result. In these embodiments, the data signal and the clock signal may be provided to the input of the flip-flop circuit to generate a specific state or output within the flip-flop circuit based on the value of the data signal and the clock signal. As described herein, when a subsequent data signal and / or clock signal is received at the input of the flip-flop circuit, the state or output of the flip-flop circuit may be transmitted to the FIFO device. In some embodiments, the first plurality of outputs includes data outputs to be utilized by the controller. For example, the first plurality of outputs may include data to be read from a NAND device, the data including a data signal from the NAND device. In this way, the data signal corresponds to data stored in the NAND device.

[0063] At operation 343, method 341 may be performed to provide a first plurality of outputs to a first-in, first-out (FIFO) device. As described herein, a first plurality of outputs corresponding to data stored in a NAND device may be provided to a first FIFO device. The FIFO device may receive the first plurality of outputs and provide the outputs to a controller based on the order in which the first plurality of outputs are received. As described herein, a portion of the first plurality of outputs may be captured within the flip-flop circuit and / or the first FIFO device when there are no additional data signals or clock signals to push the output data through the flip-flop circuit and / or the FIFO device. In these embodiments, additional clock signals and / or data signals may be generated to push the captured data through the flip-flop circuit and / or the FIFO device.

[0064] At operation 344, method 341 may be performed to provide a second plurality of data signals to the flip-flop circuit. In some embodiments, the second plurality of data signals may be signals that do not correspond to data stored within the NAND device. In some embodiments, the controller may instruct the NAND device to send the second plurality of data signals in response to determining that output data from the first plurality of data signals is captured within the flip-flop circuit and / or the FIFO device. For example, the controller may determine the number of data signals required to push the remaining output data from the first plurality of data signals through the flip-flop circuit and / or the FIFO device. In this example, the controller may instruct the NAND device to generate the second plurality of data signals to include the determined number.

[0065] At operation 345, method 341 may be performed to provide a second plurality of clock signals generated by the controller to the flip-flop circuit. In some embodiments, the second plurality of clock signals may be generated by the controller and provided to the DQS processing circuit and / or provided directly to the NAND switch device such that the second plurality of clock signals are used to push the remaining output data from the first plurality of data signals through the flip-flop circuit and / or the FIFO device. As described herein, the second plurality of clock signals may not correspond to data to be read from the NAND device. For this reason, the second plurality of clock signals may be marked or identified as being ignored. In this manner, the output data generated from the second plurality of data signals and the second plurality of clock signals may be identified as discarded item data or data to be ignored.

[0066] At operation 346, method 341 may be performed to provide a second plurality of outputs corresponding to the second plurality of data signals and the second plurality of clock signals to move the first plurality of outputs through the FIFO device. As described herein, the second plurality of outputs corresponding to the second plurality of data signals and the second plurality of clock signals may be referred to as discarded data because the second plurality of outputs do not correspond to data stored within the NAND device. The second plurality of outputs may push captured output data from the first plurality of outputs through the flip-flop circuit and the FIFO device such that discarded outputs from the second plurality of outputs are captured within the flip-flop circuit and the FIFO device.

[0067] In this manner, data gaps may be created using additional clock signals and / or additional data signals. For example, discarded items output do not correspond to data within the NAND device and thus may be referred to as gaps in the data from the NAND. Data gaps may be used to push data from the NAND device through the flip-flop circuits and FIFO devices to allow the data to be processed when there is a delay in the additional data signals provided to the DQ processing circuits corresponding to the actual NAND device data.

[0068] As described herein, the second plurality of outputs can be marked as obsolete data so that the second plurality of outputs are ignored by the controller. In this way, when non-obsolete data or data from the NAND pushes the portion of the second plurality of outputs captured within the flip-flop circuits and FIFO devices through the flip-flop circuits and FIFO devices, the portion of the second plurality of outputs can be ignored. Thus, data to be read from the NAND can be pushed through the flip-flop circuits and FIFO devices and delays avoided, while obsolete data from the second plurality of outputs can be captured within the flip-flop circuits and FIFO devices.

[0069] Figure 4 is a block diagram of an example computer system 400 in which embodiments of the present disclosure may operate. For example, Figure 4An example machine illustrating a computer system 400 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0070] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0071] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0072] The processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 402 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 may further include a network interface device 408 for communicating over a network 420.

[0073] The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 426 or software embodying any one or more of the methodologies or functionality described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and / or within the processing device 402 during execution by the computer system 400, with the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0074] In one embodiment, the instructions 426 include instructions for implementing a command corresponding to a switching component (eg, Figure 1 The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0075] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common usage reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0076] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0077] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0078] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0079] The present disclosure may be provided as a computer program product or software including a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer).

[0080] In some embodiments, machine-readable (e.g., computer-readable) media include machine (e.g., computer) readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc. In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method (341) for data strobe switching, comprising: providing a first plurality of data signals and a first plurality of clock signals to a flip-flop circuit (231, 232) to generate a first plurality of outputs corresponding to the first plurality of data signals and the first plurality of clock signals; providing the first plurality of outputs to a first-in-first-out FIFO device (233, 234); providing a second plurality of data signals to the flip-flop circuits (231, 232); providing a second plurality of clock signals generated by the controller to the flip-flop circuits (231, 232); and A second plurality of outputs corresponding to the second plurality of data signals and the second plurality of clock signals are provided to move the first plurality of outputs through the FIFO device (233, 234).

2. The method according to claim 1, further comprising: calculating a number of the second plurality of clock signals based on a number of storage locations of the FIFO device; A number of the second plurality of clock signals and notification of ignoring the second plurality of outputs are provided by the controller to a memory resource associated with the memory device.

3. The method of claim 1, wherein the first plurality of outputs are provided to a memory resource when output from the FIFO device. 4 . The method of claim 1 , wherein the second plurality of clock signals are provided to a switch that receives the first plurality of clock signals from a DQS processing circuit. The method of claim 1 , wherein the second plurality of data signals is not based on data stored by a memory resource.

6. A device for data strobe switching, comprising: A memory device interface comprising: A first flip-flop circuit (231) for receiving a data signal from a data processing circuit (225); A second flip-flop circuit (232) for receiving a clock signal from a clock processing circuit (226); a first FIFO device (233) for receiving first output data from the first flip-flop circuit (231); and a second FIFO device (234) for receiving second output data from the second flip-flop circuit (232); and A controller (222) configured to: receiving the first output data from the first FIFO device (233); receiving the second output data from the second FIFO device (234); generating an additional clock signal to be provided to the second flip-flop circuit (232) to generate additional output data; and Memory resources associated with the memory device (130, 140) are notified to ignore the additional output data.

7. The apparatus of claim 6, wherein the controller is further configured to calculate the number of additional clock signals based on a number of bits to be provided to the memory resource and a number of bits utilized by the first and second FIFO devices.

8. The apparatus of claim 6, wherein the memory resource switches the data signal to the data processing circuit and the controller switches the clock signal to the clock processing circuit.

9. The apparatus of claim 6, wherein the controller is further configured to notify the memory resource associated with the memory device that the additional clock signal is provided to the second flip-flop circuit.

10. The apparatus of claim 6, wherein the first and second flip-flop circuits are located on a physical layer of the apparatus, and the first and second FIFO devices are located outside of the physical layer of the apparatus.

11. The apparatus of claim 6, wherein the first flip-flop circuit is coupled to the first FIFO device through a first plurality of pipeline stages, and the second flip-flop circuit is coupled to the second FIFO device through a second plurality of pipeline stages.

12. The apparatus of claim 6, wherein the controller is configured to send the additional clock signal to the memory resource and mark data associated with the additional clock signal to the clock processing circuit as obsolete data.

13. A system (221) for data strobe switching, comprising: a memory subsystem (110) comprising non-volatile memory devices (130, 140); and A processing device (117, 222) coupled to the memory subsystem (110), wherein the processing device (117, 222) is configured to: generating a plurality of clock signals corresponding to a plurality of data signals received from the nonvolatile memory device (130, 140); identifying an output value in a first-in-first-out (FIFO) device (233, 234) based on the plurality of data signals and the plurality of clock signals; generating an additional clock signal when the non-volatile memory device (130, 140) has completed sending the plurality of data signals; sending the additional clock signal to the FIFO device (233, 234); and The non-volatile memory device (130, 140) is instructed to provide an additional data signal to the FIFO device (233, 234) based on the additional clock signal.

14. The system of claim 13, wherein the processing device is further configured to utilize the additional clock signal to generate data gaps, wherein the additional clock signal pushes the output value out of the FIFO device.

15. The system of claim 13, wherein the processing device is further configured to: identifying a last clock signal from the non-volatile memory device; and The number of additional clock signals to be generated is determined based on the number of bits within the FIFO device and the size of the FIFO device.

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