Command signal clock switching by controller

Abstract

The invention relates to command signal clock switching by a controller. A method includes providing, by a controller, a plurality of control signals and a first plurality of clock signals to a memory device. In some embodiments, the first plurality of clock signals is greater than the plurality of control signals. The method may also include receiving, at the controller from the memory device, a first plurality of data signals corresponding to the plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals, and receiving, at the controller, a second plurality of data signals and a third plurality of clock signals corresponding to a second portion of the first plurality of clock signals from the memory device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to command signal clock switching by a controller. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure relates to a method for command signal clock switching, comprising: providing, by a controller, a plurality of control signals and a first plurality of clock signals to a memory device, wherein the first plurality of clock signals is greater than the plurality of control signals; receiving, at the controller, from the memory device a first plurality of data signals corresponding to the plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals; and receiving, at the controller, from the memory device a second plurality of data signals corresponding to a second portion of the first plurality of clock signals and a third plurality of clock signals.

[0004] In another aspect, the present disclosure relates to an apparatus for command signal clock switching, comprising: a memory device interface, comprising: a first trigger circuit, which is used to receive command data from a command data processing circuit of the memory device; a second trigger circuit, which is used to receive a clock signal from a clock processing circuit of the memory device; a first first-in-first-out (FIFO) device, which is used to receive output command data from the first trigger circuit; and a second FIFO device, which is used to receive output clock data from the second trigger circuit; and a controller, which is configured to: generate a plurality of command signals, which are to be provided to the memory device to generate command data in response to the plurality of command signals; generate a first plurality of clock signals, which correspond to the plurality of command signals to be provided to the memory device; and generate a second plurality of clock signals, which exceed the number of the plurality of command signals to be provided to the memory device, wherein the memory device will generate clock signals in response to the first plurality of clock signals and the second plurality of clock signals to be provided to the second trigger circuit.

[0005] In another aspect, the present disclosure relates to a system for command signal clock switching, comprising: a memory subsystem comprising a nonvolatile memory device; and a processing device coupled to the memory subsystem, wherein the processing device is configured to: generate a first plurality of clock signals corresponding to a first plurality of command signals and a second plurality of clock signals; provide the first plurality of clock signals, the second plurality of clock signals, and the plurality of command signals to the nonvolatile memory device; receive a second plurality of command signals corresponding to the first plurality of command signals and a third plurality of clock signals corresponding to the first plurality of clock signals at a first-in-first-out (FIFO) device; receive a third plurality of command signals and a fourth plurality of clock signals corresponding to the second plurality of clock signals at the FIFO device; identify a first group of output values ​​based on the second plurality of command signals and the third plurality of clock signals received within the FIFO device; and ignore a second group of output values ​​based on the third plurality of command signals and the fourth plurality of clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 A system for command signal clock switching by a controller is shown according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart corresponding to a method for command signal clock switching according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Various aspects of the present disclosure relate to command signal clock switching by a controller, and more particularly to a memory subsystem including a switching component. The memory subsystem may be a storage system, a storage device, a memory module, or a combination of these. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1 Examples of storage devices and memory modules are described in , etc. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0012] The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a NAND memory device (also known as flash technology). As used herein, a NAND memory device may include a set of flash memory dies or a combination of a flash memory die and a non-volatile memory (NVM) controller. The NVM controller may include circuitry for performing read / write operations as described herein. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a cell of a memory device for storing data, and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. For some memory devices, a block (also referred to as a "memory block" hereinafter) is the smallest erasable area. Pages cannot be erased individually, and only entire blocks can be erased.

[0013] Each of the memory devices may include one or more memory cell arrays. Depending on the cell type, the cell may be written to store one or more bits of binary information and have various logic states associated with the number of bits stored. The logic state may be represented by binary values ​​such as "0" and "1" or a combination of such values. There are various types of cells such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC may store one bit of information and have two logic states.

[0014] Some NAND memory devices employ a floating gate architecture in which memory access is controlled based on relative voltage changes between a bit line and a word line. Other examples of NAND memory devices may employ a replacement gate architecture that may include the use of a word line layout that may allow a charge corresponding to a data value to be trapped within a memory cell based on the properties of the material used to construct the word line.

[0015] In some previous methods, a first-in-first-out (FIFO) device may be used to buffer communications between a memory device and a controller during a read operation and / or a write operation. A FIFO device may be used to buffer communication signals between devices that operate at different speeds or utilize independent clock signals. A FIFO device may be used to increase bandwidth and prevent data loss during high-speed communications. In some embodiments, a FIFO device may release data from a buffer in the order in which the data arrives. That is, a signal may be provided to the input of the FIFO device and released at the output of the FIFO device in the order in which the signal is received at the input of the FIFO device.

[0016] In such methods, the input of the FIFO device may be coupled to a trigger circuit. In general, a trigger circuit or a latch circuit is a circuit having two stable states and can be used to store state information. The trigger circuit can change state by a signal applied to one or more control inputs, and will have one or two outputs. In this way, whenever a signal is received at the input of the trigger circuit, the trigger circuit can change state information. In some embodiments, the FIFO device may include multiple stages or storage locations to store signals received from the output of the trigger circuit at the input of the FIFO device. Multiple stages can each be used to store corresponding states based on the received signal. When the FIFO device receives an additional signal, the previous signal moves to the next stage until the additional signal moves to the output of the FIFO device. In this way, when an additional signal is received from the trigger circuit at the input of the FIFO device, the signal received at the input of the FIFO device can be "pushed" through each of the multiple stages until the signal is directed to the output of the FIFO device.

[0017] In previous methods, the FIFO device is positioned within the physical layer (PHY) of the memory device. In these methods, data signals (DQ signals, command data signals, etc.) may be provided by memory devices such as NAND devices. In addition, a strobe signal (DQS signal, clock signal, etc.) may be provided by a controller device to the memory device. In response, a DQS signal may be generated for each DQ signal provided to the controller by the memory device. In this way, in response to a command data request signal from the controller, output data may be generated at the trigger circuit based on the command data signal and clock signal received at the trigger circuit. The output data may be provided to the FIFO device to be provided to the controller in the order in which the output data is received at the FIFO device. In some embodiments, when the memory device and / or the controller stops providing a signal to the input of the trigger circuit, the output data, the DQ signal and / or the DQS signal may be captured in the trigger circuit and / or the FIFO device. In this way, a delay may occur when processing the command data signal from the memory device.

[0018] Aspects of the present disclosure solve the above and other defects by adopting command signal clock switching performed by a controller. For example, the present disclosure may utilize multiple trigger circuits inside the PHY, which are coupled to the pipeline stages of the FIFO device placed outside the PHY or in the ASIC voltage domain. Compared with other configurations, such as those adopted in the previous method, this configuration may allow the FIFO device to be occupied. As used herein, "occupied area" refers to the physical area used to locate components on the memory device. In these embodiments, the controller may generate an additional clock signal, which is used to push data through the trigger circuit and the pipeline stage of the FIFO device. The additional clock signal provided to the NAND device allows the NAND device to generate an additional command data clock signal corresponding to the additional command data signal. In this way, the command data corresponding to the command data signal retained in the FIFO device can be pushed through the FIFO device for processing. In these embodiments, the additional command data signal and the clock signal can be marked as being ignored as "junk data" when processing because the command data signal does not correspond to the data stored on the NAND device.

[0019] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercially available device), or such a computing device that includes a memory and a processing device.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0023] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components such as the memory device 130. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in combination with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 130, 140 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0028] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] As described above, the memory component may be a memory die or a memory package that forms at least a portion of the memory device 130. In some embodiments, a block of memory cells may form one or more "super blocks". As used herein, a "super block" generally refers to a group of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of several interleaved NAND blocks may be deployed across multiple memory dies having multiple planes and / or pages associated therewith. In the context of the present disclosure, the terms "super block", "block", "memory cell block" and / or "interleaved NAND block" and variations thereof may be used interchangeably.

[0030] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may be a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), name spaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0034] In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140. For example, in some embodiments, memory device 140 may be a DRAM and / or SRAM configured to operate as a cache for memory device 130. In such cases, memory device 130 may be NAND.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) that performs media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory subsystem 110 may also include additional circuitry or components not shown.

[0036] The memory subsystem 110 may include a switching component 113, which may alternatively be referred to herein as a "controller." Although Figure 1 Although not shown in order not to obscure the diagram, the switching component 113 may include various circuit systems to facilitate various aspects of media management, as described in detail herein. In some embodiments, the switching component 113 may include dedicated circuit systems in the form of ASICs, FPGAs, state machines, and / or other logic circuit systems that may allow the switching component 113 to arrange and / or perform the operations described herein.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the switching component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the switching component 113 is part of the memory subsystem 110, an application, or an operating system.

[0038] In a non-limiting example, a device (e.g., computing system 100) may include switching component 113. Switching component 113 may reside on memory subsystem 110. As used herein, the term "resides on" refers to something being physically located on a particular component. For example, switching component 113 "resides on memory subsystem 110" refers to the condition that the hardware circuitry including switching component 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0039] As referenced in this article Figure 2As further described, the memory subsystem 110 may include a first flip-flop circuit for receiving a data signal from a command data processing circuit. In these embodiments, the memory subsystem 110 may include a second flip-flop circuit for receiving a clock signal from a clock processing circuit. In some embodiments, the memory subsystem 110 may include a first first-in-first-out (FIFO) device for receiving first output data from the first flip-flop circuit, and a second FIFO device for receiving second output data from the second flip-flop circuit. In this manner, an input of the first flip-flop circuit may be coupled to the command data processing circuit, and an output of the first flip-flop circuit may be coupled to an input of the first FIFO device. Additionally, an input of the second flip-flop circuit may be coupled to the clock processing circuit, and an output of the second flip-flop circuit may be coupled to the second FIFO device.

[0040] The switching component 113 can be configured to generate a plurality of command signals to be provided to a memory device (e.g., memory device 130, etc.) to generate command data in response to the plurality of command signals. The command signals can be signals communicated in a state command / address (SCA) mode. For example, a controller can send command signals to a memory device via a command / address (CA) pin to read a state or determine other characteristics of the memory device. In this example, the controller or host system 120 can send command data signals and command clock signals to the memory device.

[0041] In this example, the memory device may respond with a command data signal and a corresponding command clock signal. In some embodiments, the command data signal and the corresponding command clock signal may be read by the controller to determine the state or other characteristics of the memory device during SCA mode. In some embodiments, the command data signal and the corresponding command clock signal from the memory device are sent to the host system and sampled by the controller.

[0042] The switching component 113 can be configured to generate a first plurality of clock signals corresponding to a plurality of command signals to be provided to the memory device. As described herein, the first plurality of command signals can be generated together with the first plurality of clock signals. In these embodiments, the first plurality of command signals and the corresponding first plurality of clock signals can be sent to the memory device during the SCA mode. In this way, for each command signal in the plurality of command signals, a corresponding clock signal in the first plurality of clock signals can be included.

[0043] The switching component 113 may be configured to generate a second plurality of clock signals that exceeds the number of the plurality of command signals to be provided to the memory device. In some embodiments, the protocol associated with SCA communication does not specify that the number of clock signals needs to be the same as the number of command signals. In this way, the number of clock signals that the switching component 113 may generate is greater than the number of command signals to be sent to the memory device. For example, the number of command signals may be less than the combined number of the first plurality of clock signals and the second plurality of clock signals. In a specific example, the plurality of command signals may be equal to the first plurality of clock signals, and the second plurality of clock signals may be excess clock signals that do not have corresponding command signals.

[0044] In these embodiments, the memory device may generate a clock signal in response to a first plurality of clock signals and a second plurality of clock signals to be provided to the flip-flop circuit. In some embodiments, the memory device may generate a clock signal in response to the first plurality of clock signals and the second plurality of clock signals according to the SCA protocol. In some embodiments, the memory device may generate a command data signal based on data stored at the memory device in response to a plurality of command signals generated by the switching component 113. In this way, the memory device may respond to a plurality of command signals with a plurality of command data signals that may be sampled by a controller (e.g., the switching component 113, etc.).

[0045] In some embodiments, the memory device may generate a clock signal in response to a second plurality of clock signals. As described herein, the second plurality of clock signals generated by the switching component 113 may not correspond to a command signal or a request signal. In this way, the switching component 113 may provide an additional clock signal to the memory resource so that the memory resource responds with a corresponding additional clock signal. As described herein, the communication path between the memory device and the switching component 113 may include a plurality of flip-flop circuits and / or a plurality of first-in, first-out (FIFO) devices. In some embodiments, a plurality of flip-flop circuits may be used to sample a command data signal received by the memory device.

[0046] As reference Figure 2 As further described, the communication path may include: a first flip-flop circuit for receiving command data from a command data processing circuit of a memory device; a second flip-flop circuit for receiving a clock signal from a clock processing circuit of the memory device; a first first-in-first-out (FIFO) device for receiving output command data from the first flip-flop circuit; and a second FIFO device for receiving output clock data from the second flip-flop circuit. In these embodiments, the first FIFO device and / or the second FIFO device may store a plurality of bits and subsequently release the bits in the order in which they were received. In these embodiments, bits may be captured within the FIFO devices when additional signals are not provided to the FIFO devices.

[0047] In some embodiments, the first flip-flop circuit and the second flip-flop circuit are located on a physical layer of the device, and the first FIFO device and the second FIFO device are located outside the physical layer of the device. In some embodiments, the first flip-flop circuit is coupled to the first FIFO device through a first plurality of pipeline stages, and the second flip-flop circuit is coupled to the second FIFO device through a second plurality of pipeline stages.

[0048] In some embodiments, a second plurality of clock signals may be provided to the memory device to generate a response clock signal from the memory device to push data out of the first FIFO device and / or the second FIFO device. In these embodiments, the second plurality of clock signals may be generated based on the number of bits stored by the first FIFO device and / or the second FIFO device so that the command data signal provided by the memory device is pushed through the first FIFO device and / or the second FIFO device so that the command data signal is not captured within the first FIFO device and / or the second FIFO device.

[0049] In some embodiments, the switching component 113 can be configured to calculate the number of the second plurality of clock signals based on the number of bits utilized by the first FIFO device and the second FIFO device. As described herein, the number of the second plurality of clock signals can be used to push data through the first FIFO device and / or the second FIFO device. In this way, the switching component 113 can calculate the number of the second plurality of clock signals so that a command data signal corresponding to a command signal provided to the memory device is pushed through the first FIFO device and / or the second FIFO device.

[0050] In some embodiments, the switching component 113 and / or the local media controller 135 may be configured to count a second plurality of clock signals exceeding the number of the plurality of command signals. In some embodiments, the memory device may include a counter device for counting the number of clock signals exceeding the number of command signals received from the switching component 113. In some embodiments, the switching component 113 and / or the local media controller 135 may be configured to mark the data associated with the second plurality of clock signals to the clock processing circuit as junk data. In this way, the memory device can respond with the corresponding clock signal and junk data based on the second plurality of clock signals. As used herein, junk data refers to a data signal that does not correspond to a data bit stored at the memory device. In this way, the junk data does not represent the stored data of the memory device.

[0051] In some embodiments, the switching component 113 and / or the local media controller 135 may be configured to perform a clock reset in response to receiving a final clock signal from the second plurality of clock signals. As used herein, a clock reset may be performed by a memory device to change a state of the memory device to receive a signal from a host. In some embodiments, the clock reset may be an indication that the SCA mode has ended.

[0052] In some embodiments, the plurality of command signals include a command output header signal and a command deassertion signal. In some embodiments, the command output header signal may start the SCA mode, and the command deassertion signal may stop the SCA mode. In these embodiments, the host or switching component 113 may send any number of clock pulses between the command output header and the command deassertion signal. As used herein, the command deassertion signal may be when the command signal becomes a high signal.

[0053] In some embodiments, the switching component 113 can be configured to generate a first plurality of clock signals corresponding to a first plurality of command signals and a second plurality of clock signals, provide the first plurality of clock signals, the second plurality of clock signals, and the plurality of command signals to a non-volatile memory device, receive a second plurality of command signals corresponding to the first plurality of command signals and a third plurality of clock signals corresponding to the first plurality of clock signals at a first-in-first-out (FIFO) device, receive a third plurality of command signals and a fourth plurality of clock signals corresponding to the second plurality of clock signals at the FIFO device, identify a first set of output values ​​based on the second plurality of command signals and the third plurality of clock signals received within the FIFO device, and ignore the second set of output values ​​based on the third plurality of command signals and the fourth plurality of clock signals.

[0054] In some embodiments, the switching component 113 may be configured to calculate the number of the second plurality of clock signals based on the number of bits associated with the FIFO device. As described herein, the second plurality of clock signals may be based on the number of bits associated with the FIFO device so that command data corresponding to data stored at the memory device is pushed through the FIFO device. In some embodiments, the fourth plurality of clock signals pushes the first set of output values ​​out of the FIFO device. In some embodiments, the switching component 113 may be configured to send a command deassertion signal to the non-volatile memory device after the fourth plurality of clock signals.

[0055] Figure 2 FIG. 2 shows a system 221 for clock switching of command signals by a controller 222 according to some embodiments of the present disclosure. In some embodiments, the system 221 may include Figure 1 Components or elements similar to the memory system 110 of FIG. In some embodiments, the controller 222 may be Figure 1At least a portion of the switching component 113.

[0056] The system 221 may include a PHY voltage domain 224 and an application specific integrated circuit (ASIC) core voltage domain 223. As described herein, the PHY voltage domain 224 may be a physical layer of the circuit of the system 221. In these embodiments, the ASIC core voltage domain 223 may include an integrated circuit customized for a specific purpose. In these embodiments, the system 221 may include a first FIFO device 233 and a second FIFO device 234 located (e.g., deployed) within the ASIC core voltage domain 223. In these embodiments, the system 221 includes a first flip-flop circuit 231 and a second flip-flop circuit 232 located on the PHY voltage domain 224. As described herein, the previous method may locate the first FIFO device 233 and the second FIFO device 234 within the PHY voltage domain. In this way, the present disclosure moves the first FIFO device 233 and the second FIFO device 234 from the PHY voltage domain 224 to the ASIC core voltage domain 223.

[0057] The system 221 may include a command data processing circuit 225 for providing a command data signal from a NAND or other type of memory device. The command data processing circuit 225 may include various hardware circuit systems that may be configured to provide the command data signal to the delay line 227. The delay line 227 may be an arbitrator or similar circuit system to ensure that the signals are not provided to the devices at the same time or substantially at the same time. The command signal may be provided to the first flip-flop circuit 231 and / or the second flip-flop circuit 232. In some embodiments, the first flip-flop circuit 231 may store a first value corresponding to the first command data signal received from the delay line 227. In these embodiments, the first flip-flop circuit 231 may provide the first value to the first FIFO device 233 after receiving the second command data signal received from the delay line 227. In this embodiment, the first flip-flop circuit 231 may store a second value corresponding to the second command data signal, and store the second value until the first flip-flop circuit 231 receives a subsequent command data signal.

[0058] In a similar manner, the system 221 may include a clock processing circuit 226 for providing a clock signal from a memory device in response to a clock signal provided to the memory device by the controller 222. The clock processing circuit 226 may include various hardware circuit systems that may be configured to provide a clock signal to a delay line 228. The delay line 228 may be an arbitrator or similar circuit system to ensure that signals are not provided to the devices at the same time or substantially at the same time. In some embodiments, the clock signal from the delay line 228 is provided to a NAND gate 229 that may receive the clock signal from the clock processing circuit 226. In some embodiments, the command data processing circuit 225 may command a data signal from the memory device in response to a command data signal provided to the memory device.

[0059] As described herein, the clock processing circuit 226 can include hardware for sending clock signals to the memory device and / or receiving clock signals from the memory device. For example, the controller 222 can provide the first plurality of clock signals to the clock processing circuit 226 for providing to the memory device. In this example, the clock processing circuit 226 can provide the clock signals from the memory device to the delay line 228.

[0060] The clock signal may be provided to the second flip-flop circuit 232 and / or the first flip-flop circuit 231. In some embodiments, the second flip-flop circuit 232 may store a first value of the first clock signal received from the NAND gate 229. In these embodiments, the second flip-flop circuit 232 may provide the first value to the second FIFO device 234 after receiving the second clock signal received from the NAND gate 229. In this embodiment, the second flip-flop circuit 232 may store a second value corresponding to the second clock signal and store the second value until the second flip-flop circuit 232 receives a subsequent clock signal.

[0061] In some embodiments, the first FIFO device 233 and the second FIFO device 234 may include several stages so that the data received at the input is transmitted through each of the stages before being transmitted from the corresponding FIFO device to the controller 222. For example, the first FIFO device 233 may include four stages. Although four stages are described, any number of stages may be utilized in a similar manner. In this example, the first FIFO device 233 may receive a first value (e.g., state) or a first command data signal from the first flip-flop circuit 231. The first value may be stored at the first stage of the first FIFO device 233. In this example, the first FIFO device may receive a second value (e.g., state) or a second command data signal from the first flip-flop circuit 231. The first FIFO device 233 may push the first value to the second stage and store the second value at the first stage. For each value received at the first FIFO device 233, the received value may be stored at the first stage, and other values ​​may be pushed to the next stage until the received value is pushed out of the fourth stage and pushed to the controller 222. The second FIFO device 234 may operate in a similar manner to the first FIFO device 233 when receiving the clock signal from the NAND gate 229 .

[0062] In some embodiments, the controller 222 may be configured to identify output values ​​based on a plurality of command data signals and a plurality of clock signals applied to the FIFO device. In some embodiments, the output value may be a value that is stagnant or captured within the FIFO device. The controller 222 is capable of identifying the captured output value within the FIFO device based on the number of command data signals and clock signals provided to the command data processing circuit 225 and the clock processing circuit 226, respectively. For example, the number of command data signals and / or clock signals may be a number that causes the output data to be captured at a particular level of the system 221. In some embodiments, the controller 222 may be configured to calculate the number of additional clock signals based on the number of bits to be provided to the memory device and the number of bits utilized by the first FIFO device 233 and the second FIFO device 234.

[0063] As described herein, the size of the FIFO device can correspond to the maximum number of stored locations of the FIFO device and / or the number of stages associated with the FIFO device. In this way, the controller 222 can determine the number of additional clock signals and data signals required to push the captured data within the FIFO device out of the FIFO device. In this way, the controller 222 can generate a second plurality of clock signals to provide to the clock processing circuit 226 and thus to the memory device. In this example, the clock processing circuit 226 can receive the corresponding clock signal from the memory device and provide the corresponding clock signal to the delay line 228.

[0064] In some embodiments, the memory device may provide command data to command data processing circuit 225 for each of the additional clock signals generated by controller 222. As described herein, the command data corresponding to the additional clock signals may be junk data, which may be flagged or ignored by controller 222.

[0065] As described herein, the process of pushing the command data signal through the first flip-flop circuit 231 and the first FIFO device 233 to the controller 222 and pushing the clock signal through the second flip-flop circuit 232 and the second FIFO device 234 may traditionally cause data to stagnate within one or more of the first flip-flop circuit 231, the first FIFO device 233, the second flip-flop circuit, and / or the second FIFO device 234. For this reason, the present disclosure may utilize the controller 222 to provide an additional clock signal to the clock processing circuit 226 through the connection 235. In these embodiments, the additional clock signal from the controller 222 to the memory device may correspond to data to be ignored or identified as junk data. The additional clock signal from the controller 222 through the connection 235 can be used to push the stagnant data through the second flip-flop circuit 232 and / or the second FIFO device 234.

[0066] In some embodiments, the controller 222 may determine the number of additional clock signals to provide based on the amount of data stalled within the second flip-flop circuit 232 and / or the second FIFO device 234. That is, the controller 222 may determine the number of additional clock signals required to push the last received clock signal from the clock processing circuit 226 through the second flip-flop circuit 232 and / or the second FIFO device 234. In some embodiments, the additional clock signals may be marked or flagged by the controller 222 as unusable signals or signals to be ignored.

[0067] Figure 3 341 is a flow chart corresponding to a method 341 for command signal clock switching according to some embodiments of the present disclosure. The method 341 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 341 is performed by Figure 1 The switching component 113 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0068] At operation 342, method 341 may be performed to provide, by the controller, a plurality of control signals and a first plurality of clock signals to the memory device. In these embodiments, the first plurality of clock signals is greater than the plurality of control signals. In some embodiments, the control signal may be a command signal generated by the controller during the SCA mode of operation. As described herein, the command signal may be used to determine a condition or state of the memory device. The plurality of control signals may include a command output header.

[0069] At operation 343, method 341 may be performed to receive, at a controller, from a memory device a first plurality of data signals corresponding to a plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals. As described herein, the first plurality of data signals may be sampled by the controller to determine a response to a control signal generated by the controller. In some embodiments, the second plurality of clock signals may correspond to a clock signal corresponding to the control signal. In this manner, the first portion of the first plurality of clock signals may correspond to the control signal.

[0070] At operation 344, method 341 may be performed to receive, at the controller, from the memory device a second plurality of data signals and a third plurality of clock signals corresponding to a second portion of the first plurality of clock signals. As described herein, the second plurality of data signals may be generated by the memory device in response to receiving additional clock signals exceeding the number of control signals. For example, the second plurality of data signals may be junk data that does not correspond to data stored by the memory device. In these embodiments, the second plurality of data signals and the third plurality of clock signals may be used to push the first plurality of data signals through the FIFO device.

[0071] In some embodiments, method 341 may be performed to determine at the memory device the number of control signals received from the controller. In some embodiments, the memory device may identify the command output header received from the controller. In these embodiments, the number of control signals may be determined to identify the number of the second plurality of clock signals. In this manner, the memory device may respond to the second plurality of clock signals with the clock signal and junk data to push the command data signal through the FIFO device.

[0072] In some embodiments, method 341 may be performed to generate a first portion of a first plurality of clock signals at a controller based on the number of the plurality of control signals, and to generate a second portion of the first plurality of clock signals based on a path between the controller and a memory device. As described herein, the path between the controller and the memory device may include a plurality of flip-flop circuits and / or FIFO devices. In this manner, the controller may provide excess clock signals to the memory device such that the memory device will provide junk data and clock signals to push the signals through the flip-flop circuits and / or FIFO devices.

[0073] In some embodiments, a first plurality of data signals corresponding to the plurality of control signals correspond to values ​​stored by the memory device. As described herein, the first plurality of data signals may be response data to the control signals stored by the memory device. In this manner, control signals may be sent to the memory device to determine the state of the memory device. In these embodiments, the first plurality of data signals may represent the state of the memory device.

[0074] In some embodiments, the second plurality of data signals corresponding to the second portion of the first plurality of clock signals do not correspond to values ​​stored by the memory device. As described herein, the second plurality of data signals may be junk data generated without corresponding data stored by the memory device. In these embodiments, the memory device may generate the second plurality of data signals to correspond to the third plurality of clock signals.

[0075] In some embodiments, method 341 may be performed to generate, by the controller, a number of second portions of the first plurality of clock signals based on a first-in, first-out (FIFO) device positioned between the controller and the memory device. In these embodiments, the second plurality of data signals and the third plurality of clock signals move the first plurality of data signals to the controller through the FIFO device.

[0076] Figure 4 4 is a block diagram of an example computer system 400 in which embodiments of the present disclosure may operate. For example, Figure 4 An example machine of a computer system 400 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 400 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120), or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0077] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also include any collection of machines that individually or collectively execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0078] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0079] The processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 402 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 may further include a network interface device 408 to communicate via a network 420.

[0080] The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and / or within the processing device 402 during execution by the computer system 400, with the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0081] In one embodiment, instructions 426 include instructions for implementing instructions corresponding to a switching component (e.g., Figure 1The term "machine-readable storage medium" may be a storage medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" may be a storage medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure.

[0082] Algorithms and symbolic representations of operations on data bits within a computer memory present some portions of the previous detailed description. These algorithmic descriptions and representations are used by those skilled in the art of data processing to most effectively convey the substance of their work to other technicians in the field. An algorithm is here and generally considered to be a self-consistent sequence of operations that produce a desired result. The operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0083] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform them into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0084] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0085] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with the program according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. Structures for a variety of these systems will be presented as shown in the following description. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0086] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer).

[0087] In some embodiments, machine-readable (e.g., computer-readable) media include machine (e.g., computer) readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc. In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method (341) for command signal clock switching, comprising: providing, by a controller (115, 222, 402), a plurality of control signals and a first plurality of clock signals to a memory device (130, 140), wherein the first plurality of clock signals is greater than the plurality of control signals; receiving, at the controller (115, 222, 402), from the memory device (130, 140), a first plurality of data signals corresponding to the plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals; as well as A second plurality of data signals and a third plurality of clock signals corresponding to a second portion of the first plurality of clock signals are received at the controller (115, 222, 402) from the memory device (130, 140).

2. The method according to claim 1, further comprising: determining, at the memory device, a number of control signals received from the controller; as well as The first portion of the first plurality of clock signals is generated at the controller based on the number of the plurality of control signals, and the second portion of the first plurality of clock signals is generated based on a path between the controller and the memory device.

3. The method of claim 1 , wherein the first plurality of data signals corresponding to the plurality of control signals correspond to values ​​stored by the memory device, and wherein the second plurality of data signals includes junk data that does not correspond to values ​​stored by the memory device.

4. The method of claim 1 , further comprising generating, by the controller, the number of the second portion of the first plurality of clock signals based on a first-in-first-out (FIFO) device positioned between the controller and the memory device, wherein the second plurality of data signals and the third plurality of clock signals move the first plurality of data signals to the controller through the FIFO device.

5. A device for command signal clock switching, comprising: A memory device interface comprising: a first flip-flop circuit (231) for receiving command data from a command data processing circuit (225) of a memory device (130, 140); a second flip-flop circuit (232) for receiving a clock signal from a clock processing circuit (226) of the memory device (130, 140); a first FIFO device (233) for receiving output command data from the first flip-flop circuit (231); and a second FIFO device (234) for receiving output clock data from the second flip-flop circuit (232); and A controller (115, 222, 402) configured to: generating a plurality of command signals to be provided to a memory device (130, 140) to generate command data in response to the plurality of command signals; generating a first plurality of clock signals corresponding to the plurality of command signals to be provided to the memory device (130, 140); and generating a second plurality of clock signals that exceeds the number of the plurality of command signals to be provided to the memory device (130, 140), wherein the memory device (130, 140) generates clock signals in response to the first plurality of clock signals and the second plurality of clock signals to be provided to the second flip-flop circuit (232). 6 . The apparatus of claim 5 , wherein the controller is further configured to calculate the number of the second plurality of clock signals based on the number of bits utilized by the first FIFO device and the second FIFO device.

7. The apparatus of claim 5, wherein the memory device is further configured to count the second plurality of clock signals exceeding the number of the plurality of command signals and to perform a clock reset in response to receiving a final clock signal from the second plurality of clock signals.

8. The apparatus of claim 5, wherein the first flip-flop circuit and the second flip-flop circuit are located on a physical layer of the apparatus, and the first FIFO device and the second FIFO device are located outside the physical layer of the apparatus.

9. The apparatus of claim 5, wherein the first flip-flop circuit is coupled to the first FIFO device through a first plurality of pipeline stages, and the second flip-flop circuit is coupled to the second FIFO device through a second plurality of pipeline stages.

10. The apparatus of claim 5, wherein the plurality of command signals comprises a command output header signal and a command deassertion signal.

11. The apparatus of claim 5, wherein the memory device is configured to mark data associated with the second plurality of clock signals to the clock processing circuit as junk data.

12. A system (221) for command signal clock switching, comprising: A memory subsystem (110) comprising a non-volatile memory device (130, 140); as well as A processing device (117, 402) coupled to the memory subsystem (110), wherein the processing device (117, 402) is configured to: generating a first plurality of clock signals corresponding to the first plurality of command signals and a second plurality of clock signals; providing the first plurality of clock signals, the second plurality of clock signals, and the plurality of command signals to the nonvolatile memory device (130, 140); receiving, at a first-in-first-out (FIFO) device (233, 234), a second plurality of command signals corresponding to the first plurality of command signals and a third plurality of clock signals corresponding to the first plurality of clock signals; receiving at the FIFO device (233, 234) a third plurality of command signals and a fourth plurality of clock signals corresponding to the second plurality of clock signals; identifying a first set of output values ​​based on a second plurality of command signals and the third plurality of clock signals received within the FIFO device (233, 234); as well as A second set of output values ​​is ignored based on the third plurality of command signals and the fourth plurality of clock signals.

13. The system of claim 12, wherein the processing device is further configured to calculate the number of the second plurality of clock signals based on the number of bits associated with the FIFO device.

14. The system of claim 12, wherein the fourth plurality of clock signals pushes the first set of output values ​​out of the FIFO device.

15. The system of claim 12, wherein the processing device is further configured to send a command de-assertion signal to the non-volatile memory device after the fourth plurality of clock signals.

Images