Thin film structure and preparation method thereof

Abstract

According to the thin film structure preparation method and the thin film structure provided by the invention, the graphene oxide adhesion layer is formed between the two material layers, so that the adhesion between the two material layers can be effectively improved, the stress between the two material layers can be relieved, and the risk of thin film stripping and cracking of the two material layers can be reduced. The graphene oxide material is rich in oxygen functional groups, and strong chemical bonds are easily formed between the graphene oxide material and other materials, so that the adhesion between the graphene oxide and the material layer in contact with the graphene oxide material is remarkably improved, and the graphene oxide material can be used as an adhesion connecting layer between the two material layers; in addition, the graphene oxide material also has excellent mechanical properties, can effectively buffer the stress generated in the deposition and treatment process of the film structure, and reduces the risk of film stripping and cracking.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a thin film structure and a preparation method thereof. Background Art

[0002] As the size and performance of silicon transistors approach their physical limits, alternative materials need to be found to support more emerging technologies, and one of the promising materials is graphene. Graphene has the best potential to become a field effect transistor channel material due to its excellent electrical, mechanical and thermal properties.

[0003] Electronic devices are usually constructed from basic structures such as conductors, semiconductors, and insulators. For graphene devices, the construction of its insulating layer is crucial. Taking graphene transistors (GFETs) as an example, when making the top gate, an insulating oxide layer is often deposited on the graphene as a gate dielectric layer. The preparation techniques include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD) and other deposition processes. As semiconductor technology nodes continue to develop towards smaller sizes, such as 7nm, 5nm and even below 3nm, ALD has become the first choice for applications in advanced processes.

[0004] ALD is a deposition technology that precisely controls the thickness and composition of thin films. It is a special form of CVD that grows thin films layer by layer on the substrate surface through step-by-step reactions. The ALD process usually involves alternating exposure of two or more precursors, followed by purging with an inert gas after each exposure. Since each reaction step is self-limiting, the deposit reacts only on the substrate surface, thus ensuring growth control at the single-atom level.

[0005] However, during the ALD deposition process, film adhesion issues can affect film quality and device reliability. The main limiting factors include insufficient substrate surface chemistry, poor precursor reactivity, inappropriate deposition temperature, poor intrinsic material adhesion, differences in stress and thermal expansion coefficients, and the formation of interfacial layers. These issues can lead to poor film adhesion, interface defects, and peeling.

[0006] The current methods to alleviate the adhesion problem of atomic layer deposition (ALD) are: 1. Surface pretreatment, such as cleaning, functionalization or plasma treatment, to improve the surface reactivity of the substrate. This method adds additional processing steps and may require multiple equipment and chemical reagents, increasing the process complexity. At the same time, there may be a risk of surface damage. For example, plasma treatment may cause damage to the substrate surface, affecting the quality of subsequent films. The cleaning effect is also limited. Some contaminants may be difficult to completely remove and may still affect the adhesion of the film. 2. Optimize precursors and deposition conditions, select more suitable precursors and temperatures, and improve film quality. However, the types of precursors currently available are limited, and some highly reactive precursors may be costly or difficult to handle. The deposition temperature window is narrow. In order to avoid film quality problems, the adjustment range of deposition temperature is limited, which limits process flexibility, and not all materials can solve adhesion problems through simple process optimization. 3. Multi-layer or gradient layer deposition improves interface stability and adhesion. The deposition process of multi-layer structures or gradient layers is more complicated, the difficulty of process control is increased, and thickness control is difficult. It is difficult to maintain the uniformity and accuracy of the thickness of each layer, which may affect the overall performance of the film. There is also a stress accumulation problem. Despite the use of a multi-layer structure, film stress problems may still exist, and even stress accumulation may occur due to multi-layer stacking. 4. Adjust process conditions to reduce film stress. Therefore, while solving adhesion problems, these methods currently used may increase process complexity, increase costs, and other limitations on film performance.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a thin film structure and a preparation method thereof, which is used to solve the problem of peeling, flaking and cracking caused by poor adhesion and thermal mismatch during the deposition of thin film layers of different materials in the prior art, thereby affecting the performance of the thin film structure.

[0009] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a thin film structure, the preparation method comprising:

[0010] Providing a substrate, wherein a first material layer is formed on the surface of the substrate;

[0011] Depositing a first graphene oxide adhesion layer on the surface of the first material layer;

[0012] A second material layer is deposited on the surface of the first graphene oxide adhesion layer.

[0013] Optionally, the first material layer is a silicon oxide layer, and the second material layer is a graphene layer; or the first material layer is a graphene layer, and the second material layer is a high-k dielectric layer; or the first material layer is a high-k dielectric layer, and the second material layer is a metal layer.

[0014] Optionally, the thin film structure is a top-gate GFET thin film structure, the substrate is a silicon substrate, the first material layer is a silicon oxide layer, the second material layer is a graphene channel layer, and the preparation method further comprises:

[0015] Depositing a second graphene oxide adhesion layer on the surface of the second material layer;

[0016] Depositing a high-k gate dielectric layer on the surface of the second graphene oxide adhesion layer;

[0017] Depositing a third graphene oxide adhesion layer on the surface of the high-k gate dielectric layer;

[0018] A gate metal layer is deposited on the surface of the third graphene oxide adhesion layer.

[0019] Optionally, the thin film structure is a back-gate GFET thin film structure, the substrate is a silicon substrate, the first material layer is a silicon oxide layer, the second material layer is a graphene channel layer, and the preparation method further comprises:

[0020] depositing a fourth graphene oxide adhesion layer on the back side of the substrate;

[0021] A back gate metal layer is deposited on the surface of the fourth graphene oxide adhesion layer.

[0022] Optionally, the thin film structure is a full-gate GFET thin film structure, the substrate is a silicon substrate, the first material layer is a silicon oxide layer, the second material layer is a graphene channel layer, and the preparation method further includes:

[0023] Depositing a second graphene oxide adhesion layer on the surface of the second material layer;

[0024] Depositing a high-k gate dielectric layer on the surface of the second graphene oxide adhesion layer;

[0025] Depositing a third graphene oxide adhesion layer on the surface of the high-k gate dielectric layer;

[0026] Depositing a gate metal layer on the surface of the third graphene oxide adhesion layer;

[0027] depositing a fourth graphene oxide adhesion layer on the back side of the substrate;

[0028] A back gate metal layer is deposited on the surface of the fourth graphene oxide adhesion layer.

[0029] Furthermore, the content of the C element in the graphene oxide adhesion layer in contact with the second material layer is adjusted to achieve the required conductivity of the corresponding graphene adhesion layer. The principle is that the more the C element content, the better the conductivity.

[0030] Furthermore, the corresponding graphene oxide adhesion layer is deposited by ALD process.

[0031] Furthermore, the parameters for depositing the corresponding graphene oxide adhesion layer using the ALD process are: temperature of 50°C to 200°C; precursor pulse time of 0.1s to 1s; pumping time of 5s to 30s; inert gas flow rate of 10sccm to 200sccm; and reaction chamber pressure of 0.1torr to 1torr.

[0032] Optionally, the thickness of the corresponding graphene oxide adhesion layer is 2 nm to 5 nm.

[0033] Optionally, after forming the thin film structure, a low temperature annealing step at 200° C. to 300° C. is further included.

[0034] The present invention also provides a thin film structure, which is prepared by using any one of the above methods for preparing a thin film structure.

[0035] As described above, the thin film structure preparation method and thin film structure of the present invention can effectively improve the adhesion between the two material layers and relieve the stress between the two material layers by forming a graphene oxide adhesion layer (i.e., the first graphene oxide adhesion layer) between the two material layers, thereby reducing the risk of film peeling and cracking of the two material layers. The graphene oxide material is rich in oxygen functional groups and is easy to form strong chemical bonds with other materials, thereby significantly increasing the adhesion between the graphene oxide and the contact material layer. Therefore, the graphene oxide material can be used as an adhesion connection layer between the two material layers, especially when the intrinsic adhesion of at least one of the two material layers is poor, the adhesion performance of the graphene oxide material is particularly obvious in improving the adhesion performance between the two material layers; in addition, the graphene oxide material also has excellent mechanical properties, which can effectively buffer the stress generated during the deposition and processing of the thin film structure, and reduce the risk of film peeling and cracking. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0037] Figures 1 to 4 Shown are schematic cross-sectional views of thin film structures of four examples of the present invention.

[0038] Figure 5 Shown is an atomic map of graphene oxide material.

[0039] Figure 6 Shown is a diagram of the chemical formula of graphene oxide material.

[0040] Component number description

[0041] 100 Base

[0042] 101 First Material Layer

[0043] 102 First graphene oxide adhesion layer

[0044] 103 Second material layer

[0045] 104 Second graphene oxide adhesion layer

[0046] 105 High-k gate dielectric layer

[0047] 106 third graphene oxide adhesion layer

[0048] 107 Gate metal layer

[0049] 108 fourth graphene oxide adhesion layer

[0050] 109 back gate metal layer DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] It should be emphasized that the term “include / comprises” when used herein refers to the existence of features, integers, steps or components, but does not exclude the existence or addition of one or more other features, integers, steps or components.

[0053] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0054] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0055] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" may be used herein to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation, in addition to the orientations depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0056] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include an embodiment where the first and second features are formed in direct contact, and may also include an embodiment where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0057] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0058] As Figure 1 shown, this embodiment provides a method for preparing a thin film structure, and the preparation method includes the following steps:

[0059] Provide a substrate 100, on the surface of which a first material layer 101 is formed;

[0060] Deposit a first graphene oxide adhesion layer 102 on the surface of the first material layer 101;

[0061] Deposit a second material layer 103 on the surface of the first graphene oxide adhesion layer 102.

[0062] In the method for preparing the thin film structure of this embodiment, by forming a graphene oxide adhesion layer (i.e., the first graphene oxide adhesion layer) between two material layers, the adhesion between the two material layers can be effectively improved, the stress between the two material layers can be relieved, and the risk of film peeling and cracking of the two material layers can be reduced. As Figure 5 and Figure 6As shown in the figure, the graphene oxide material is rich in oxygen functional groups and is easy to form strong chemical bonds with other materials, thereby significantly increasing the adhesion between the graphene oxide and the contact material layer. Therefore, the graphene oxide material can be used as an adhesion connection layer between two material layers. Especially when at least one of the two material layers has poor intrinsic adhesion, the adhesion performance of the graphene oxide material can significantly improve the adhesion performance between the two material layers. For example, adding a graphene oxide adhesion layer between the graphene material layer and the high-K dielectric material layer can increase the adhesion energy of the interface from about 20 mJ / m 2 ~100mJ / m 2 , increased to about 200mJ / m 2 ~400mJ / m 2 , which can increase the adhesion energy by 2 to 5 times; in addition, graphene oxide materials also have excellent mechanical properties, which can effectively buffer the stress generated during the deposition and processing of thin film structures and reduce the risk of film peeling and cracking.

[0063] The method for preparing the thin film structure of this embodiment is applicable to the preparation of any suitable thin film structure in the process of preparing electronic devices, so as to improve the adhesion between two adjacent thin films and relieve the stress between the two thin films. Therefore, the preparation method may be used in the deposition of two adjacent thin films multiple times in the preparation process of the same thin film structure of the same electronic device. Therefore, according to different situations, the substrate 100 can be a single-layer structure of a single material, or a multi-layer stacked structure of multiple materials. The material of the substrate 100 is not overly limited, and can be a semiconductor material, an insulator material, or a conductor material, which is selected according to actual needs.

[0064] The materials of the first material layer 101 and the second material layer 103 can be semiconductor materials, insulator materials or conductor materials, as long as the materials have poor adhesion during the deposition process. As a preferred example, the first material layer 101 can be a silicon oxide layer, and the second material layer 103 can be a graphene layer; or the first material layer 101 can be a graphene layer, and the second material layer 103 can be a high-k dielectric layer; or the first material layer 101 can be a high-k dielectric layer, and the second material layer 103 can be a metal layer.

[0065] The thickness of the first material layer 101 and the second material layer 103 are selected according to device requirements and are not excessively limited herein.

[0066] As a preferred example, the first graphene oxide adhesion layer 102 is deposited using the ALD process. Since the ALD process is a deposition method controlled by single-atom-level growth, the defects on the surface of the front layer (i.e., the first material layer) can be effectively smoothed during the ALD deposition of the first graphene oxide adhesion layer 102, thereby improving the interface quality. In addition, the first graphene oxide adhesion layer 102 formed by the ALD process has a smooth surface and few defects, and can also effectively improve the interface quality with the second material layer.

[0067] As a preferred example, the parameters for ALD preparation of the first graphene oxide adhesion layer 102 are selected as follows: the deposition temperature is 50°C to 200°C, and this deposition temperature range can effectively avoid thermal degradation of the deposited graphene oxide during the deposition process, thereby improving the surface uniformity of the film layer finally formed; the precursor pulse time is 0.1s to 1s to control the reaction rate of the precursor used; the pumping time is 5s to 30s to ensure the effective removal of the reaction gas; the inert gas flow rate is 10sccm to 200sccm to ensure the mixing and dilution of the precursor gas; the reaction chamber pressure is 0.1torr to 1torr to ensure the requirements of low-pressure ALD.

[0068] As another preferred example, the thickness of the first graphene oxide adhesion layer 102 is 2 nm to 5 nm, and may be 2 nm, 3 nm, 3.8 nm, 4.3 nm, or 5 nm.

[0069] In a specific example, after forming the desired thin film structure, the formed thin film structure can also be subjected to a low temperature annealing process. The low temperature annealing can help remove some oxidized functional groups (such as carboxyl, hydroxyl and epoxy groups) in the graphene oxide, improve its conductivity, but will not completely remove the oxygen in the graphene oxide, while maintaining its partial oxidation characteristics. In addition, some harmful organic matter and moisture can be removed, and the interlayer interface bonding between the film layers in the thin film structure can be improved, and the interface defect density can be reduced. Preferably, the low temperature annealing temperature is selected to be 200°C to 300°C.

[0070] The method for preparing the thin film structure of this embodiment can be preferably applied in the process of preparing the thin film structure of GFET (graphene field effect transistor).

[0071] like Figure 2 As shown, it is a top-gate GFET thin film structure, wherein the substrate 100 is a silicon substrate, the first material layer 101 is a silicon oxide layer, and the second material layer 103 is a graphene channel layer. As a specific example, the method for preparing the top-gate GFET thin film structure includes:

[0072] First, step S10 is performed to select a substrate 100 made of silicon, on the surface of which a first material layer 101 made of silicon oxide is formed.

[0073] The first material layer 101 may be formed by a thermal oxidation process or a deposition process. The thickness of the first material layer 101 is selected according to insulation and electric field shielding requirements, and is typically 90 nm to 300 nm.

[0074] After forming the first material layer 101 and before performing subsequent steps, the substrate 100 formed with the first material layer 101 may be cleaned to remove surface impurities and improve the adhesion of subsequent deposited layers.

[0075] Then, step S11 is performed to deposit a first graphene oxide adhesion layer 102 on the surface of the first material layer 101 .

[0076] The deposition method of the first graphene oxide adhesion layer 102 is not excessively limited, and a CVD process, an ALD process, etc. may be used. Preferably, the first graphene oxide adhesion layer 102 is prepared by an ALD process. A graphene oxide precursor and an appropriate oxidant, such as O 2 or H 2 O, perform alternating pulse deposition, control the ALD cycle number and temperature to ensure the thickness and uniformity of the film layer. As mentioned above, the ALD deposition parameters are selected as follows: deposition temperature is 50°C to 200°C; precursor pulse time is 0.1s to 1s; pumping time is 5s to 30s; inert gas flow rate is 10sccm to 200sccm; reaction chamber pressure is 0.1torr to 1torr.

[0077] The thickness of the first graphene oxide adhesion layer 102 is selected to be in the range of 2 nm to 5 nm.

[0078] In addition, the content of C element in the film layer can be adjusted during the deposition process of the first graphene oxide adhesion layer 102. The higher the content of C element, the better the conductivity. Therefore, the conductivity of the first graphene oxide adhesion layer 102 can be controlled by controlling the C content. Therefore, the first graphene oxide adhesion layer 102 can be used as an adhesion layer and a stress buffer layer, and the conductivity of the subsequent graphene channel layer can be regulated by controlling its conductivity, thereby finally meeting the needs of different electronic devices.

[0079] Then, step S12 is performed to deposit a second material layer 103 of graphene material on the surface of the first graphene oxide adhesion layer 102. At this time, the second material layer 103 is used as a channel layer of the GFET.

[0080] Graphene has extremely high electron mobility (more than 200,000 cm2 / V·s), good thermal conductivity and mechanical strength, and can provide excellent electrical performance. A single layer of graphene is usually 0.34 nm, and a double layer of graphene can provide higher conductivity, but it may affect the switching ratio of the channel. Therefore, the conductive performance of the second material layer 103 can be achieved by controlling the conductivity of the upper first graphene oxide adhesion layer 102.

[0081] The second material layer 103 of the graphene material can be prepared by existing conventional processes. In this embodiment, the second material layer 103 is prepared by a CVD process, using a carbon source gas (such as methane or ethylene) and hydrogen, and performing CVD deposition under appropriate temperature and atmosphere conditions to grow graphene directly on the first graphene oxide adhesion layer 102. The thickness and quality of the second material layer 103 of the graphene material are controlled by optimizing the CVD process parameters.

[0082] Then, step S13 is performed to deposit a second graphene oxide adhesion layer 104 on the surface of the second material layer 103 .

[0083] The deposition method and corresponding thickness and other parameters of the second graphene oxide adhesion layer 104 are the same as the preparation method and corresponding thickness and other parameters of the first graphene oxide adhesion layer 102, and are not described in detail here. In addition, the content of C element in the film layer can also be adjusted during the deposition process of the second graphene oxide adhesion layer 104, so that the conductivity of the second graphene oxide adhesion layer 104 can be controlled by controlling the C content, so that the second graphene oxide adhesion layer 104 can also be used as an adhesion layer and a stress buffer layer. At the same time, it can also control the conductivity of the front graphene channel layer by controlling its conductivity, and finally meet the needs of different electronic devices. It should be noted here that the C content in the first graphene oxide adhesion layer 102 and / or the second graphene oxide adhesion layer 104 can be controlled separately according to actual needs to achieve the control of the corresponding conductive properties, so as to finally coordinately regulate the conductive properties of the graphene channel layer to meet the needs of different electronic devices.

[0084] Both graphene materials and graphene oxide materials are two-dimensional materials, and the interlayer interaction mainly relies on van der Waals forces, so they have excellent compatibility in thickness and arrangement.

[0085] Then, step S14 is performed to deposit a high-k gate dielectric layer 105 on the surface of the second graphene oxide adhesion layer 104 .

[0086] The second graphene oxide adhesion layer 104 also serves as an adhesion layer for the high-k gate dielectric layer 105 .

[0087] The high-k gate dielectric layer 105 is made of a material with a high dielectric constant, such as hafnium oxide or aluminum oxide. The formation method of the high-k gate dielectric layer 105 is not excessively limited. As a typical example, the high-k gate dielectric layer 105 is prepared by an ALD process, and a metal precursor, such as HfCl, is alternately injected. 4 or Al(CH 3 ) 3 and oxidants such as H 2 O, depositing a uniform high-k gate dielectric layer 105 at low temperature, and ensuring the required gate capacitance characteristics by controlling the thickness of the high-k gate dielectric layer 105, generally the thickness is selected to be 5nm to 15nm.

[0088] Then, step S15 is performed to deposit a third graphene oxide adhesion layer 106 on the surface of the high-k gate dielectric layer 105 .

[0089] The deposition method and corresponding thickness and other parameters of the third graphene oxide adhesion layer 106 are the same as the preparation method and corresponding thickness and other parameters of the first graphene oxide adhesion layer 102, and are not described in detail here. In addition, the content of the C element in the film layer can also be adjusted during the deposition process of the third graphene oxide adhesion layer 106, so that the conductive properties of the third graphene oxide adhesion layer 106 can be controlled by controlling the C content.

[0090] The third graphene oxide adhesion layer 106 serves as an adhesion layer between the high-k gate dielectric layer 105 and the subsequent gate metal layer 107 .

[0091] Then, step S16 is performed to deposit a gate metal layer 107 on the surface of the third graphene oxide adhesion layer 106 .

[0092] The material of the gate metal layer 107 is selected to be a material suitable for the gate metal, such as an aluminum material or a titanium material. The gate metal layer 107 can be prepared by a PVD process or an electron beam evaporation process. The thickness of the gate metal layer 107 depends on the conductivity and coverage uniformity requirements of the gate, and the general thickness is selected to be 50nm to 100nm.

[0093] Finally, step S17 is performed to perform low temperature annealing at 200° C. to 300° C. on the thin film structure formed above to improve the interlayer interface bonding and reduce the interface defect density.

[0094] At this point, the preparation of the top-gate GFET thin film structure is completed.

[0095] like Figure 3 The back-gate GFET thin film structure is shown, wherein the substrate 100 is a silicon substrate, the first material layer 101 is a silicon oxide layer, and the second material layer 103 is a graphene channel layer. As a specific example, the method for preparing the back-gate GFET thin film structure includes:

[0096] First, step S20 is performed, and the first material layer 101, the first graphene oxide adhesion layer 102 and the second material layer 103 are prepared with reference to steps S10 to S12 in the top-gate GFET thin film structure preparation method. The corresponding parameters such as thickness also refer to the selection principles in the top-gate GFET thin film structure preparation method, which will not be repeated here.

[0097] Then, step S21 is performed to deposit a fourth graphene oxide adhesion layer 108 on the back side of the substrate 100 .

[0098] The deposition method and corresponding thickness and other parameters of the fourth graphene oxide adhesion layer 108 are the same as the preparation method and corresponding thickness and other parameters of the first graphene oxide adhesion layer 102, and are not described in detail here. In addition, the content of the C element in the film layer can also be adjusted during the deposition process of the fourth graphene oxide adhesion layer 108, so that the conductive properties of the fourth graphene oxide adhesion layer 108 can be controlled by controlling the C content.

[0099] The fourth graphene oxide adhesion layer 108 serves as an adhesion layer between the substrate 100 and a back gate metal layer 109 formed subsequently.

[0100] Then, step S22 is performed to deposit a back gate metal layer 109 on the surface of the fourth graphene oxide adhesion layer 108 .

[0101] The material of the back gate metal layer 109 is selected to be suitable for the back gate metal, such as aluminum material or titanium material. The back gate metal layer 109 can be prepared by PVD process or electron beam evaporation process. The thickness of the back gate metal layer 109 depends on the conductivity and coverage uniformity requirements of the back gate, and the general thickness is selected to be 50nm to 100nm.

[0102] Finally, step S23 is performed to perform low-temperature annealing at 200° C. to 300° C. on the thin film structure formed above to improve the interlayer interface bonding and reduce the interface defect density.

[0103] At this point, the preparation of the back-gate GFET thin film structure is completed.

[0104] like Figure 4 The figure shows a full-gate GFET thin film structure, wherein the substrate 100 is a silicon substrate, the first material layer 101 is a silicon oxide layer, and the second material layer 103 is a graphene channel layer. As a specific example, the method for preparing a full back-gate GFET thin film structure includes:

[0105] First, step S30 is performed, referring to the corresponding film layers prepared in steps S10 to S16 in the top-gate GFET thin film structure preparation method, and the corresponding thickness and other parameters also refer to the selection principles in the top-gate GFET thin film structure preparation method, which will not be repeated here.

[0106] Then, step S31 is performed, and the fourth graphene oxide adhesion layer 108 and the back gate metal layer 109 are prepared with reference to steps S21 and S22 in the back-gate GFET thin film structure preparation method, and the corresponding thickness and other parameters also refer to the selection principles in the back-gate GFET thin film structure preparation method, which will not be repeated here.

[0107] Finally, step S32 is performed to perform low-temperature annealing at 200° C. to 300° C. on the thin film structure formed above to improve the interlayer interface bonding and reduce the interface defect density.

[0108] At this point, the preparation of the full-gate GFET thin film structure is achieved.

[0109] This embodiment also provides a thin film structure, which is prepared by using the above-mentioned thin film structure preparation method.

[0110] In summary, the thin film structure preparation method and thin film structure of the present invention can effectively improve the adhesion between the two material layers and relieve the stress between the two material layers by forming a graphene oxide adhesion layer (i.e., the first graphene oxide adhesion layer) between the two material layers, thereby reducing the risk of film peeling and cracking of the two material layers. The graphene oxide material is rich in oxygen functional groups and is easy to form strong chemical bonds with other materials, thereby significantly increasing the adhesion between the graphene oxide and the contact material layer. Therefore, the graphene oxide material can be used as an adhesion connection layer between the two material layers, especially when at least one of the two material layers has poor intrinsic adhesion, the adhesion performance of the graphene oxide material is particularly obvious in improving the adhesion performance between the two material layers; in addition, the graphene oxide material also has excellent mechanical properties, which can effectively buffer the stress generated during the deposition and processing of the thin film structure, and reduce the risk of film peeling and cracking. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a thin film structure, characterized in that: The preparation method comprises: Providing a substrate, wherein a first material layer is formed on the surface of the substrate; Depositing a first graphene oxide adhesion layer on the surface of the first material layer; A second material layer is deposited on the surface of the first graphene oxide adhesion layer.

2. The method for preparing a thin film structure according to claim 1, characterized in that: The first material layer is a silicon oxide layer, and the second material layer is a graphene layer; or the first material layer is a graphene layer, and the second material layer is a high-k dielectric layer; or the first material layer is a high-k dielectric layer, and the second material layer is a metal layer.

3. The method for preparing a thin film structure according to claim 1, characterized in that: The thin film structure is a top-gate GFET thin film structure, the substrate is a silicon substrate, the first material layer is a silicon oxide layer, the second material layer is a graphene channel layer, and the preparation method further includes: Depositing a second graphene oxide adhesion layer on the surface of the second material layer; Depositing a high-k gate dielectric layer on the surface of the second graphene oxide adhesion layer; Depositing a third graphene oxide adhesion layer on the surface of the high-k gate dielectric layer; A gate metal layer is deposited on the surface of the third graphene oxide adhesion layer.

4. The method for preparing a thin film structure according to claim 1, characterized in that: The thin film structure is a back-gate GFET thin film structure, the substrate is a silicon substrate, the first material layer is a silicon oxide layer, the second material layer is a graphene channel layer, and the preparation method further includes: depositing a fourth graphene oxide adhesion layer on the back side of the substrate; A back gate metal layer is deposited on the surface of the fourth graphene oxide adhesion layer.

5. The method for preparing a thin film structure according to claim 1, characterized in that: The thin film structure is a full-gate GFET thin film structure, the substrate is a silicon substrate, the first material layer is a silicon oxide layer, the second material layer is a graphene channel layer, and the preparation method further includes: Depositing a second graphene oxide adhesion layer on the surface of the second material layer; Depositing a high-k gate dielectric layer on the surface of the second graphene oxide adhesion layer; Depositing a third graphene oxide adhesion layer on the surface of the high-k gate dielectric layer; Depositing a gate metal layer on the surface of the third graphene oxide adhesion layer; depositing a fourth graphene oxide adhesion layer on the back side of the substrate; A back gate metal layer is deposited on the surface of the fourth graphene oxide adhesion layer.

6. The method for preparing a thin film structure according to any one of claims 3 to 5, characterized in that: The content of the C element in the graphene oxide adhesion layer in contact with the second material layer is adjusted to achieve the required conductivity of the corresponding graphene adhesion layer. The principle is that the more the C element content, the better the conductivity.

7. The method for preparing a thin film structure according to any one of claims 1 to 5, characterized in that: The corresponding graphene oxide adhesion layer is deposited using an ALD process.

8. The method for preparing a thin film structure according to claim 7, characterized in that: The parameters for depositing the corresponding graphene oxide adhesion layer using the ALD process are: temperature of 50°C to 200°C; precursor pulse time of 0.1s to 1s; pumping time of 5s to 30s; inert gas flow rate of 10sccm to 200sccm; and reaction chamber pressure of 0.1torr to 1torr.

9. The method for preparing a thin film structure according to any one of claims 1 to 5, characterized in that: The thickness of the corresponding graphene oxide adhesion layer is 2nm to 5nm.

10. The method for preparing a thin film structure according to claim 1, characterized in that: After the thin film structure is formed, a low temperature annealing step at 200° C. to 300° C. is also included.

11. A thin film structure, characterized in that: The thin film structure is prepared by the method for preparing the thin film structure as described in any one of claims 1 to 10.

Images